| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2020 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_DCORE0_MME_CTRL_LO_MME_AXUSER_REGS_H_ |
| #define ASIC_REG_DCORE0_MME_CTRL_LO_MME_AXUSER_REGS_H_ |
| |
| /* |
| ***************************************** |
| * DCORE0_MME_CTRL_LO_MME_AXUSER |
| * (Prototype: AXUSER) |
| ***************************************** |
| */ |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_ASID 0x40CBE00 |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_MMU_BP 0x40CBE04 |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_STRONG_ORDER 0x40CBE08 |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_NO_SNOOP 0x40CBE0C |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_WR_REDUCTION 0x40CBE10 |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_RD_ATOMIC 0x40CBE14 |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_QOS 0x40CBE18 |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_RSVD 0x40CBE1C |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_EMEM_CPAGE 0x40CBE20 |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_CORE 0x40CBE24 |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_E2E_COORD 0x40CBE28 |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_WR_OVRD_LO 0x40CBE30 |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_WR_OVRD_HI 0x40CBE34 |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_RD_OVRD_LO 0x40CBE38 |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_RD_OVRD_HI 0x40CBE3C |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_LB_COORD 0x40CBE40 |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_LB_LOCK 0x40CBE44 |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_LB_RSVD 0x40CBE48 |
| |
| #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_LB_OVRD 0x40CBE4C |
| |
| #endif /* ASIC_REG_DCORE0_MME_CTRL_LO_MME_AXUSER_REGS_H_ */ |
