| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2020 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_DCORE0_MME_QM_ARC_ACP_ENG_REGS_H_ |
| #define ASIC_REG_DCORE0_MME_QM_ARC_ACP_ENG_REGS_H_ |
| |
| /* |
| ***************************************** |
| * DCORE0_MME_QM_ARC_ACP_ENG |
| * (Prototype: ARC_ACP_ENG) |
| ***************************************** |
| */ |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_0 0x40CF000 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_1 0x40CF004 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_2 0x40CF008 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_3 0x40CF00C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_4 0x40CF010 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_5 0x40CF014 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_6 0x40CF018 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_7 0x40CF01C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_8 0x40CF020 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_9 0x40CF024 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_10 0x40CF028 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_11 0x40CF02C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_12 0x40CF030 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_13 0x40CF034 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_14 0x40CF038 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_15 0x40CF03C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_16 0x40CF040 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_17 0x40CF044 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_18 0x40CF048 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_19 0x40CF04C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_20 0x40CF050 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_21 0x40CF054 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_22 0x40CF058 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_23 0x40CF05C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_24 0x40CF060 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_25 0x40CF064 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_26 0x40CF068 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_27 0x40CF06C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_28 0x40CF070 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_29 0x40CF074 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_30 0x40CF078 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_31 0x40CF07C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_32 0x40CF080 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_33 0x40CF084 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_34 0x40CF088 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_35 0x40CF08C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_36 0x40CF090 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_37 0x40CF094 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_38 0x40CF098 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_39 0x40CF09C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_40 0x40CF0A0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_41 0x40CF0A4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_42 0x40CF0A8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_43 0x40CF0AC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_44 0x40CF0B0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_45 0x40CF0B4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_46 0x40CF0B8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_47 0x40CF0BC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_48 0x40CF0C0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_49 0x40CF0C4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_50 0x40CF0C8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_51 0x40CF0CC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_52 0x40CF0D0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_53 0x40CF0D4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_54 0x40CF0D8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_55 0x40CF0DC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_56 0x40CF0E0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_57 0x40CF0E4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_58 0x40CF0E8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_59 0x40CF0EC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_60 0x40CF0F0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_61 0x40CF0F4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_62 0x40CF0F8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_63 0x40CF0FC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_0 0x40CF100 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_1 0x40CF104 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_2 0x40CF108 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_3 0x40CF10C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_4 0x40CF110 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_5 0x40CF114 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_6 0x40CF118 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_7 0x40CF11C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_8 0x40CF120 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_9 0x40CF124 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_10 0x40CF128 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_11 0x40CF12C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_12 0x40CF130 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_13 0x40CF134 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_14 0x40CF138 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_15 0x40CF13C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_16 0x40CF140 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_17 0x40CF144 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_18 0x40CF148 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_19 0x40CF14C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_20 0x40CF150 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_21 0x40CF154 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_22 0x40CF158 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_23 0x40CF15C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_24 0x40CF160 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_25 0x40CF164 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_26 0x40CF168 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_27 0x40CF16C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_28 0x40CF170 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_29 0x40CF174 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_30 0x40CF178 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_31 0x40CF17C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_32 0x40CF180 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_33 0x40CF184 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_34 0x40CF188 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_35 0x40CF18C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_36 0x40CF190 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_37 0x40CF194 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_38 0x40CF198 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_39 0x40CF19C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_40 0x40CF1A0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_41 0x40CF1A4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_42 0x40CF1A8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_43 0x40CF1AC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_44 0x40CF1B0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_45 0x40CF1B4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_46 0x40CF1B8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_47 0x40CF1BC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_48 0x40CF1C0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_49 0x40CF1C4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_50 0x40CF1C8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_51 0x40CF1CC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_52 0x40CF1D0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_53 0x40CF1D4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_54 0x40CF1D8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_55 0x40CF1DC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_56 0x40CF1E0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_57 0x40CF1E4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_58 0x40CF1E8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_59 0x40CF1EC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_60 0x40CF1F0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_61 0x40CF1F4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_62 0x40CF1F8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_63 0x40CF1FC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_0 0x40CF200 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_1 0x40CF204 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_2 0x40CF208 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_3 0x40CF20C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_4 0x40CF210 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_5 0x40CF214 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_6 0x40CF218 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_7 0x40CF21C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_8 0x40CF220 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_9 0x40CF224 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_10 0x40CF228 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_11 0x40CF22C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_12 0x40CF230 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_13 0x40CF234 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_14 0x40CF238 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_15 0x40CF23C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_16 0x40CF240 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_17 0x40CF244 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_18 0x40CF248 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_19 0x40CF24C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_20 0x40CF250 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_21 0x40CF254 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_22 0x40CF258 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_23 0x40CF25C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_24 0x40CF260 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_25 0x40CF264 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_26 0x40CF268 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_27 0x40CF26C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_28 0x40CF270 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_29 0x40CF274 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_30 0x40CF278 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_31 0x40CF27C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_32 0x40CF280 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_33 0x40CF284 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_34 0x40CF288 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_35 0x40CF28C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_36 0x40CF290 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_37 0x40CF294 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_38 0x40CF298 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_39 0x40CF29C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_40 0x40CF2A0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_41 0x40CF2A4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_42 0x40CF2A8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_43 0x40CF2AC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_44 0x40CF2B0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_45 0x40CF2B4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_46 0x40CF2B8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_47 0x40CF2BC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_48 0x40CF2C0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_49 0x40CF2C4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_50 0x40CF2C8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_51 0x40CF2CC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_52 0x40CF2D0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_53 0x40CF2D4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_54 0x40CF2D8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_55 0x40CF2DC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_56 0x40CF2E0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_57 0x40CF2E4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_58 0x40CF2E8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_59 0x40CF2EC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_60 0x40CF2F0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_61 0x40CF2F4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_62 0x40CF2F8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_63 0x40CF2FC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_0 0x40CF300 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_1 0x40CF304 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_2 0x40CF308 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_3 0x40CF30C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_4 0x40CF310 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_5 0x40CF314 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_6 0x40CF318 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_7 0x40CF31C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_8 0x40CF320 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_9 0x40CF324 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_10 0x40CF328 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_11 0x40CF32C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_12 0x40CF330 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_13 0x40CF334 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_14 0x40CF338 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_15 0x40CF33C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_16 0x40CF340 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_17 0x40CF344 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_18 0x40CF348 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_19 0x40CF34C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_20 0x40CF350 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_21 0x40CF354 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_22 0x40CF358 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_23 0x40CF35C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_24 0x40CF360 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_25 0x40CF364 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_26 0x40CF368 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_27 0x40CF36C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_28 0x40CF370 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_29 0x40CF374 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_30 0x40CF378 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_31 0x40CF37C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_32 0x40CF380 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_33 0x40CF384 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_34 0x40CF388 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_35 0x40CF38C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_36 0x40CF390 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_37 0x40CF394 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_38 0x40CF398 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_39 0x40CF39C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_40 0x40CF3A0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_41 0x40CF3A4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_42 0x40CF3A8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_43 0x40CF3AC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_44 0x40CF3B0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_45 0x40CF3B4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_46 0x40CF3B8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_47 0x40CF3BC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_48 0x40CF3C0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_49 0x40CF3C4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_50 0x40CF3C8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_51 0x40CF3CC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_52 0x40CF3D0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_53 0x40CF3D4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_54 0x40CF3D8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_55 0x40CF3DC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_56 0x40CF3E0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_57 0x40CF3E4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_58 0x40CF3E8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_59 0x40CF3EC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_60 0x40CF3F0 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_61 0x40CF3F4 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_62 0x40CF3F8 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_63 0x40CF3FC |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_SELECTED_QUEUE_ID 0x40CF400 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_0 0x40CF404 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_1 0x40CF408 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_2 0x40CF40C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_0 0x40CF410 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_1 0x40CF414 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_2 0x40CF418 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_0 0x40CF41C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_1 0x40CF420 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_2 0x40CF424 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_3 0x40CF428 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_0 0x40CF42C |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_1 0x40CF430 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_2 0x40CF434 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_3 0x40CF438 |
| |
| #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_REG 0x40CF43C |
| |
| #endif /* ASIC_REG_DCORE0_MME_QM_ARC_ACP_ENG_REGS_H_ */ |