drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_regs.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_DCORE0_TPC0_CFG_REGS_H_
#define ASIC_REG_DCORE0_TPC0_CFG_REGS_H_

/*
 *****************************************
 *   DCORE0_TPC0_CFG
 *   (Prototype: TPC)
 *****************************************
 */

#define mmDCORE0_TPC0_CFG_TPC_COUNT 0x400BC18

#define mmDCORE0_TPC0_CFG_TPC_ID 0x400BC1C

#define mmDCORE0_TPC0_CFG_STALL_ON_ERR 0x400BC20

#define mmDCORE0_TPC0_CFG_CLK_EN 0x400BC24

#define mmDCORE0_TPC0_CFG_IQ_RL_EN 0x400BC28

#define mmDCORE0_TPC0_CFG_IQ_RL_SAT 0x400BC2C

#define mmDCORE0_TPC0_CFG_IQ_RL_RST_TOKEN 0x400BC30

#define mmDCORE0_TPC0_CFG_IQ_RL_TIMEOUT 0x400BC34

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_0 0x400BC38

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_1 0x400BC3C

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_2 0x400BC40

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_3 0x400BC44

#define mmDCORE0_TPC0_CFG_IQ_LBW_CLK_EN 0x400BC48

#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0 0x400BC4C

#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_1 0x400BC50

#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_2 0x400BC54

#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_3 0x400BC58

#define mmDCORE0_TPC0_CFG_TPC_LOCK_0 0x400BC5C

#define mmDCORE0_TPC0_CFG_TPC_LOCK_1 0x400BC60

#define mmDCORE0_TPC0_CFG_TPC_LOCK_2 0x400BC64

#define mmDCORE0_TPC0_CFG_TPC_LOCK_3 0x400BC68

#define mmDCORE0_TPC0_CFG_CGU_SB 0x400BC6C

#define mmDCORE0_TPC0_CFG_CGU_CNT 0x400BC70

#define mmDCORE0_TPC0_CFG_CGU_CPE_0 0x400BC74

#define mmDCORE0_TPC0_CFG_CGU_CPE_1 0x400BC78

#define mmDCORE0_TPC0_CFG_CGU_CPE_2 0x400BC7C

#define mmDCORE0_TPC0_CFG_CGU_CPE_3 0x400BC80

#define mmDCORE0_TPC0_CFG_CGU_CPE_4 0x400BC84

#define mmDCORE0_TPC0_CFG_CGU_CPE_5 0x400BC88

#define mmDCORE0_TPC0_CFG_CGU_CPE_6 0x400BC8C

#define mmDCORE0_TPC0_CFG_CGU_CPE_7 0x400BC90

#define mmDCORE0_TPC0_CFG_FP16_FTZ_IN 0x400BC94

#define mmDCORE0_TPC0_CFG_DCACHE_CFG 0x400BC98

#define mmDCORE0_TPC0_CFG_E2E_CRDT_TOP 0x400BC9C

#define mmDCORE0_TPC0_CFG_TPC_DCACHE_L0CD 0x400BCA0

#define mmDCORE0_TPC0_CFG_TPC_SB_L0CD 0x400BCA4

#define mmDCORE0_TPC0_CFG_CONV_ROUND_CSR 0x400BCA8

#define mmDCORE0_TPC0_CFG_TSB_OCCUPANCY 0x400BCAC

#define mmDCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT 0x400BCB0

#define mmDCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT 0x400BCB4

#define mmDCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT 0x400BCB8

#define mmDCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT 0x400BCBC

#define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO 0x400BCC0

#define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI 0x400BCC4

#define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO 0x400BCC8

#define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI 0x400BCCC

#define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO 0x400BCD0

#define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI 0x400BCD4

#define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO 0x400BCD8

#define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI 0x400BCDC

#define mmDCORE0_TPC0_CFG_SPE_LFSR_POLYNOM 0x400BCE0

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL 0x400BCE4

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_0 0x400BCE8

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_1 0x400BCEC

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2 0x400BCF0

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_3 0x400BCF4

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_0 0x400BCF8

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_1 0x400BCFC

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_2 0x400BD00

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_3 0x400BD04

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_0 0x400BD08

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_1 0x400BD0C

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_2 0x400BD10

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_3 0x400BD14

#define mmDCORE0_TPC0_CFG_FP8_143_BIAS 0x400BD64

#define mmDCORE0_TPC0_CFG_ROUND_CSR 0x400BD68

#define mmDCORE0_TPC0_CFG_HB_PROT 0x400BD6C

#define mmDCORE0_TPC0_CFG_LB_PROT 0x400BD70

#define mmDCORE0_TPC0_CFG_SEMAPHORE 0x400BD74

#define mmDCORE0_TPC0_CFG_VFLAGS 0x400BD78

#define mmDCORE0_TPC0_CFG_SFLAGS 0x400BD7C

#define mmDCORE0_TPC0_CFG_LFSR_POLYNOM 0x400BD80

#define mmDCORE0_TPC0_CFG_STATUS 0x400BD84

#define mmDCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH 0x400BD88

#define mmDCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE 0x400BD8C

#define mmDCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH 0x400BD90

#define mmDCORE0_TPC0_CFG_TPC_CMD 0x400BD94

#define mmDCORE0_TPC0_CFG_TPC_EXECUTE 0x400BD98

#define mmDCORE0_TPC0_CFG_TPC_STALL 0x400BD9C

#define mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW 0x400BDA0

#define mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH 0x400BDA4

#define mmDCORE0_TPC0_CFG_RD_RATE_LIMIT 0x400BDA8

#define mmDCORE0_TPC0_CFG_WR_RATE_LIMIT 0x400BDAC

#define mmDCORE0_TPC0_CFG_MSS_CONFIG 0x400BDB0

#define mmDCORE0_TPC0_CFG_TPC_INTR_CAUSE 0x400BDB4

#define mmDCORE0_TPC0_CFG_TPC_INTR_MASK 0x400BDB8

#define mmDCORE0_TPC0_CFG_WQ_CREDITS 0x400BDBC

#define mmDCORE0_TPC0_CFG_OPCODE_EXEC 0x400BDC0

#define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO 0x400BDC4

#define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI 0x400BDC8

#define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO 0x400BDCC

#define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI 0x400BDD0

#define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO 0x400BDD4

#define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI 0x400BDD8

#define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO 0x400BDDC

#define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI 0x400BDE0

#define mmDCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE 0x400BDE4

#define mmDCORE0_TPC0_CFG_TSB_CFG 0x400BDE8

#define mmDCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR 0x400BDEC

#define mmDCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR 0x400BDF0

#define mmDCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR 0x400BDF4

#define mmDCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR 0x400BDF8

#define mmDCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR 0x400BDFC

#endif /* ASIC_REG_DCORE0_TPC0_CFG_REGS_H_ */