| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2020 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ |
| #define ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ |
| |
| /* |
| ***************************************** |
| * DCORE0_TPC0_QM_ARC_AUX |
| * (Prototype: QMAN_ARC_AUX) |
| ***************************************** |
| */ |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_REQ 0x4008100 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_ACK 0x4008104 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_RST_VEC_ADDR 0x4008108 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DBG_MODE 0x400810C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CLUSTER_NUM 0x4008110 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_NUM 0x4008114 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_WAKE_UP_EVENT 0x4008118 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x400811C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CTI_AP_STS 0x4008120 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x4008124 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST 0x4008128 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST_REQ 0x400812C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SRAM_LSB_ADDR 0x4008130 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SRAM_MSB_ADDR 0x4008134 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_PCIE_LSB_ADDR 0x4008138 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_PCIE_MSB_ADDR 0x400813C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LSB_ADDR 0x4008140 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_MSB_ADDR 0x4008144 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_LSB_ADDR 0x4008150 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_MSB_ADDR 0x4008154 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_LSB_ADDR 0x4008158 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_MSB_ADDR 0x400815C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_LSB_ADDR 0x4008160 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_MSB_ADDR 0x4008164 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_LSB_ADDR 0x4008168 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_MSB_ADDR 0x400816C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_OFFSET 0x4008170 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_OFFSET 0x4008174 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_OFFSET 0x4008178 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_OFFSET 0x400817C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4008180 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4008184 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4008188 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x400818C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4008190 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4008194 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4008198 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x400819C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x40081A0 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x40081A4 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x40081A8 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x40081AC |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x40081B0 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x40081B4 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x40081B8 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x40081BC |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_0 0x40081C0 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_1 0x40081C4 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_2 0x40081C8 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_3 0x40081CC |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_4 0x40081D0 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_5 0x40081D4 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_6 0x40081D8 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_7 0x40081DC |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_0 0x40081E0 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_1 0x40081E4 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_2 0x40081E8 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_3 0x40081EC |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_4 0x40081F0 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_5 0x40081F4 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_6 0x40081F8 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_7 0x40081FC |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_0 0x4008200 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_1 0x4008204 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_2 0x4008208 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_3 0x400820C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_4 0x4008210 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_5 0x4008214 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_6 0x4008218 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_7 0x400821C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_8 0x4008220 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_9 0x4008224 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_10 0x4008228 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_11 0x400822C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_12 0x4008230 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_13 0x4008234 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_14 0x4008238 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_15 0x400823C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x4008280 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x4008284 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x4008290 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x4008294 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x4008298 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x400829C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x40082A0 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x40082A4 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x40082A8 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_STS 0x40082B0 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x40082B4 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x40082B8 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x40082BC |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x40082C0 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x40082C4 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x40082C8 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x40082CC |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x40082D0 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x40082E0 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x40082E4 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x40082E8 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x40082EC |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x40082F0 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x40082F4 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_0 0x4008300 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_1 0x4008304 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_2 0x4008308 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_3 0x400830C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_4 0x4008310 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_5 0x4008314 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_6 0x4008318 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_7 0x400831C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x4008320 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x4008324 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x4008328 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x400832C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x4008330 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x4008334 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x4008338 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x400833C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_OVR 0x4008350 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x4008354 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_OVR 0x4008358 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x400835C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x4008360 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x4008364 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x4008368 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x400836C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x4008370 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_LOCK_OVR 0x4008374 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_PROT_OVR 0x4008378 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x400837C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x4008380 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x4008384 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x400838C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x4008390 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_ARUSER_OVR 0x4008400 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x4008404 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AWUSER_OVR 0x4008408 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x400840C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x4008420 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_LOCK_OVR 0x4008424 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_PROT_OVR 0x4008428 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x400842C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x4008430 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x4008434 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x400843C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x4008440 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4008500 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4008504 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4008508 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x400850C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4008510 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4008514 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4008518 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x400851C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x4008520 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x4008524 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x4008528 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x400852C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x4008530 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x4008534 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x4008538 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x400853C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x4008540 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x4008544 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x4008548 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x400854C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x4008550 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x4008554 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x4008558 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x400855C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x4008560 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x4008564 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x4008568 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x400856C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x4008570 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x4008574 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x4008578 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x400857C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x4008580 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x4008584 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x4008588 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x400858C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x4008590 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x4008594 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x4008598 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x400859C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x40085A0 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x40085A4 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x40085A8 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x40085AC |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x40085B0 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x40085B4 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x40085B8 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x40085BC |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x40085C0 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x40085C4 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x40085C8 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x40085CC |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x40085D0 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x40085D4 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x40085D8 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x40085DC |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x40085E0 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x40085E4 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x4008620 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x4008624 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x4008628 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x4008630 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x4008634 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x4008638 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x400863C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x4008640 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x4008644 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4008648 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x400864C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4008650 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4008654 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x4008658 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x400865C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_AUX2APB_PROT 0x4008700 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x4008704 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4008708 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x400870C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4008710 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4008714 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4008718 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x400871C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4008720 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4008724 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x4008728 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x400872C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4008730 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4008734 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4008738 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x400873C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x4008740 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4008750 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4008754 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4008758 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x400875C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4008760 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4008764 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4008768 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x400876C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4008770 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4008774 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4008778 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x400877C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4008780 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4008784 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4008788 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x400878C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x4008790 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x4008794 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x4008798 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x400879C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_0 0x4008800 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_1 0x4008804 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_2 0x4008808 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_3 0x400880C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_4 0x4008810 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_5 0x4008814 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_6 0x4008818 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_7 0x400881C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_8 0x4008820 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_9 0x4008824 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_10 0x4008828 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_11 0x400882C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_12 0x4008830 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_13 0x4008834 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_14 0x4008838 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_15 0x400883C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4008840 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4008844 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x4008848 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x400884C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x4008850 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x4008854 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4008900 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x4008904 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4008908 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x400890C |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x4008910 |
| |
| #define mmDCORE0_TPC0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x4008920 |
| |
| #endif /* ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ */ |