| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2020 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_ |
| #define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_ |
| |
| /* |
| ***************************************** |
| * PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC |
| * (Prototype: AXUSER) |
| ***************************************** |
| */ |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_ASID 0x4F03C00 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_MMU_BP 0x4F03C04 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_STRONG_ORDER 0x4F03C08 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_NO_SNOOP 0x4F03C0C |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_REDUCTION 0x4F03C10 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_ATOMIC 0x4F03C14 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_QOS 0x4F03C18 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RSVD 0x4F03C1C |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_EMEM_CPAGE 0x4F03C20 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_CORE 0x4F03C24 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_E2E_COORD 0x4F03C28 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_OVRD_LO 0x4F03C30 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_OVRD_HI 0x4F03C34 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_OVRD_LO 0x4F03C38 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_OVRD_HI 0x4F03C3C |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_COORD 0x4F03C40 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_LOCK 0x4F03C44 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_RSVD 0x4F03C48 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_OVRD 0x4F03C4C |
| |
| #endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_ */ |
