| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2020 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_ |
| #define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_ |
| |
| /* |
| ***************************************** |
| * PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD |
| * (Prototype: AXUSER) |
| ***************************************** |
| */ |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_ASID 0x4F03800 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_MMU_BP 0x4F03804 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_STRONG_ORDER 0x4F03808 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_NO_SNOOP 0x4F0380C |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_REDUCTION 0x4F03810 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_ATOMIC 0x4F03814 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_QOS 0x4F03818 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RSVD 0x4F0381C |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_EMEM_CPAGE 0x4F03820 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_CORE 0x4F03824 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_E2E_COORD 0x4F03828 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_OVRD_LO 0x4F03830 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_OVRD_HI 0x4F03834 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_OVRD_LO 0x4F03838 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_OVRD_HI 0x4F0383C |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_COORD 0x4F03840 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_LOCK 0x4F03844 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_RSVD 0x4F03848 |
| |
| #define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_OVRD 0x4F0384C |
| |
| #endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_ */ |