| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2020 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_PSOC_RESET_CONF_REGS_H_ |
| #define ASIC_REG_PSOC_RESET_CONF_REGS_H_ |
| |
| /* |
| ***************************************** |
| * PSOC_RESET_CONF |
| * (Prototype: PSOC_RESET_CONF) |
| ***************************************** |
| */ |
| |
| #define mmPSOC_RESET_CONF_PSOC_PRSTN_RST_CFG 0x4C74000 |
| |
| #define mmPSOC_RESET_CONF_PSOC_SOFT_RST_CFG 0x4C74004 |
| |
| #define mmPSOC_RESET_CONF_PSOC_FW_RST_CFG 0x4C74008 |
| |
| #define mmPSOC_RESET_CONF_PSOC_WD_RST_CFG 0x4C7400C |
| |
| #define mmPSOC_RESET_CONF_PSOC_MNL_RST_CFG 0x4C74010 |
| |
| #define mmPSOC_RESET_CONF_PSOC_FLR_RST_CFG 0x4C74014 |
| |
| #define mmPSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG 0x4C74018 |
| |
| #define mmPSOC_RESET_CONF_PSOC_SW_RST_CFG 0x4C7401C |
| |
| #define mmPSOC_RESET_CONF_CPU_PRSTN_RST_CFG 0x4C74020 |
| |
| #define mmPSOC_RESET_CONF_CPU_SOFT_RST_CFG 0x4C74024 |
| |
| #define mmPSOC_RESET_CONF_CPU_FW_RST_CFG 0x4C74028 |
| |
| #define mmPSOC_RESET_CONF_CPU_WD_RST_CFG 0x4C7402C |
| |
| #define mmPSOC_RESET_CONF_CPU_MNL_RST_CFG 0x4C74030 |
| |
| #define mmPSOC_RESET_CONF_CPU_FLR_RST_CFG 0x4C74034 |
| |
| #define mmPSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG 0x4C74038 |
| |
| #define mmPSOC_RESET_CONF_CPU_SW_RST_CFG 0x4C7403C |
| |
| #define mmPSOC_RESET_CONF_ARC_PRSTN_RST_CFG 0x4C74040 |
| |
| #define mmPSOC_RESET_CONF_ARC_SOFT_RST_CFG 0x4C74044 |
| |
| #define mmPSOC_RESET_CONF_ARC_FW_RST_CFG 0x4C74048 |
| |
| #define mmPSOC_RESET_CONF_ARC_WD_RST_CFG 0x4C7404C |
| |
| #define mmPSOC_RESET_CONF_ARC_MNL_RST_CFG 0x4C74050 |
| |
| #define mmPSOC_RESET_CONF_ARC_FLR_RST_CFG 0x4C74054 |
| |
| #define mmPSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG 0x4C74058 |
| |
| #define mmPSOC_RESET_CONF_ARC_SW_RST_CFG 0x4C7405C |
| |
| #define mmPSOC_RESET_CONF_SIF_PRSTN_RST_CFG 0x4C74060 |
| |
| #define mmPSOC_RESET_CONF_SIF_SOFT_RST_CFG 0x4C74064 |
| |
| #define mmPSOC_RESET_CONF_SIF_FW_RST_CFG 0x4C74068 |
| |
| #define mmPSOC_RESET_CONF_SIF_WD_RST_CFG 0x4C7406C |
| |
| #define mmPSOC_RESET_CONF_SIF_MNL_RST_CFG 0x4C74070 |
| |
| #define mmPSOC_RESET_CONF_SIF_FLR_RST_CFG 0x4C74074 |
| |
| #define mmPSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG 0x4C74078 |
| |
| #define mmPSOC_RESET_CONF_SIF_SW_RST_CFG 0x4C7407C |
| |
| #define mmPSOC_RESET_CONF_SRAM_PRSTN_RST_CFG 0x4C74080 |
| |
| #define mmPSOC_RESET_CONF_SRAM_SOFT_RST_CFG 0x4C74084 |
| |
| #define mmPSOC_RESET_CONF_SRAM_FW_RST_CFG 0x4C74088 |
| |
| #define mmPSOC_RESET_CONF_SRAM_WD_RST_CFG 0x4C7408C |
| |
| #define mmPSOC_RESET_CONF_SRAM_MNL_RST_CFG 0x4C74090 |
| |
| #define mmPSOC_RESET_CONF_SRAM_FLR_RST_CFG 0x4C74094 |
| |
| #define mmPSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG 0x4C74098 |
| |
| #define mmPSOC_RESET_CONF_SRAM_SW_RST_CFG 0x4C7409C |
| |
| #define mmPSOC_RESET_CONF_PCIE_CTRL_PRSTN_RST_CFG 0x4C740A0 |
| |
| #define mmPSOC_RESET_CONF_PCIE_CTRL_SOFT_RST_CFG 0x4C740A4 |
| |
| #define mmPSOC_RESET_CONF_PCIE_CTRL_FW_RST_CFG 0x4C740A8 |
| |
| #define mmPSOC_RESET_CONF_PCIE_CTRL_WD_RST_CFG 0x4C740AC |
| |
| #define mmPSOC_RESET_CONF_PCIE_CTRL_MNL_RST_CFG 0x4C740B0 |
| |
| #define mmPSOC_RESET_CONF_PCIE_CTRL_FLR_RST_CFG 0x4C740B4 |
| |
| #define mmPSOC_RESET_CONF_PCIE_CTRL_ECC_DERR_RST_CFG 0x4C740B8 |
| |
| #define mmPSOC_RESET_CONF_PCIE_CTRL_SW_RST_CFG 0x4C740BC |
| |
| #define mmPSOC_RESET_CONF_PCIE_PHY_CFG_PRSTN_RST_CFG 0x4C740C0 |
| |
| #define mmPSOC_RESET_CONF_PCIE_PHY_CFG_SOFT_RST_CFG 0x4C740C4 |
| |
| #define mmPSOC_RESET_CONF_PCIE_PHY_CFG_FW_RST_CFG 0x4C740C8 |
| |
| #define mmPSOC_RESET_CONF_PCIE_PHY_CFG_WD_RST_CFG 0x4C740CC |
| |
| #define mmPSOC_RESET_CONF_PCIE_PHY_CFG_MNL_RST_CFG 0x4C740D0 |
| |
| #define mmPSOC_RESET_CONF_PCIE_PHY_CFG_FLR_RST_CFG 0x4C740D4 |
| |
| #define mmPSOC_RESET_CONF_PCIE_PHY_CFG_ECC_DERR_RST_CFG 0x4C740D8 |
| |
| #define mmPSOC_RESET_CONF_PCIE_PHY_CFG_SW_RST_CFG 0x4C740DC |
| |
| #define mmPSOC_RESET_CONF_PCIE_IF_PRSTN_RST_CFG 0x4C740E0 |
| |
| #define mmPSOC_RESET_CONF_PCIE_IF_SOFT_RST_CFG 0x4C740E4 |
| |
| #define mmPSOC_RESET_CONF_PCIE_IF_FW_RST_CFG 0x4C740E8 |
| |
| #define mmPSOC_RESET_CONF_PCIE_IF_WD_RST_CFG 0x4C740EC |
| |
| #define mmPSOC_RESET_CONF_PCIE_IF_MNL_RST_CFG 0x4C740F0 |
| |
| #define mmPSOC_RESET_CONF_PCIE_IF_FLR_RST_CFG 0x4C740F4 |
| |
| #define mmPSOC_RESET_CONF_PCIE_IF_ECC_DERR_RST_CFG 0x4C740F8 |
| |
| #define mmPSOC_RESET_CONF_PCIE_IF_SW_RST_CFG 0x4C740FC |
| |
| #define mmPSOC_RESET_CONF_TPC_DIV_PRSTN_RST_CFG 0x4C74100 |
| |
| #define mmPSOC_RESET_CONF_TPC_DIV_SOFT_RST_CFG 0x4C74104 |
| |
| #define mmPSOC_RESET_CONF_TPC_DIV_FW_RST_CFG 0x4C74108 |
| |
| #define mmPSOC_RESET_CONF_TPC_DIV_WD_RST_CFG 0x4C7410C |
| |
| #define mmPSOC_RESET_CONF_TPC_DIV_MNL_RST_CFG 0x4C74110 |
| |
| #define mmPSOC_RESET_CONF_TPC_DIV_FLR_RST_CFG 0x4C74114 |
| |
| #define mmPSOC_RESET_CONF_TPC_DIV_ECC_DERR_RST_CFG 0x4C74118 |
| |
| #define mmPSOC_RESET_CONF_TPC_DIV_SW_RST_CFG 0x4C7411C |
| |
| #define mmPSOC_RESET_CONF_HBM_DIV_PRSTN_RST_CFG 0x4C74120 |
| |
| #define mmPSOC_RESET_CONF_HBM_DIV_SOFT_RST_CFG 0x4C74124 |
| |
| #define mmPSOC_RESET_CONF_HBM_DIV_FW_RST_CFG 0x4C74128 |
| |
| #define mmPSOC_RESET_CONF_HBM_DIV_WD_RST_CFG 0x4C7412C |
| |
| #define mmPSOC_RESET_CONF_HBM_DIV_MNL_RST_CFG 0x4C74130 |
| |
| #define mmPSOC_RESET_CONF_HBM_DIV_FLR_RST_CFG 0x4C74134 |
| |
| #define mmPSOC_RESET_CONF_HBM_DIV_ECC_DERR_RST_CFG 0x4C74138 |
| |
| #define mmPSOC_RESET_CONF_HBM_DIV_SW_RST_CFG 0x4C7413C |
| |
| #define mmPSOC_RESET_CONF_PMMU_PRSTN_RST_CFG 0x4C74140 |
| |
| #define mmPSOC_RESET_CONF_PMMU_SOFT_RST_CFG 0x4C74144 |
| |
| #define mmPSOC_RESET_CONF_PMMU_FW_RST_CFG 0x4C74148 |
| |
| #define mmPSOC_RESET_CONF_PMMU_WD_RST_CFG 0x4C7414C |
| |
| #define mmPSOC_RESET_CONF_PMMU_MNL_RST_CFG 0x4C74150 |
| |
| #define mmPSOC_RESET_CONF_PMMU_FLR_RST_CFG 0x4C74154 |
| |
| #define mmPSOC_RESET_CONF_PMMU_ECC_DERR_RST_CFG 0x4C74158 |
| |
| #define mmPSOC_RESET_CONF_PMMU_SW_RST_CFG 0x4C7415C |
| |
| #define mmPSOC_RESET_CONF_PM_PRSTN_RST_CFG 0x4C74160 |
| |
| #define mmPSOC_RESET_CONF_PM_SOFT_RST_CFG 0x4C74164 |
| |
| #define mmPSOC_RESET_CONF_PM_FW_RST_CFG 0x4C74168 |
| |
| #define mmPSOC_RESET_CONF_PM_WD_RST_CFG 0x4C7416C |
| |
| #define mmPSOC_RESET_CONF_PM_MNL_RST_CFG 0x4C74170 |
| |
| #define mmPSOC_RESET_CONF_PM_FLR_RST_CFG 0x4C74174 |
| |
| #define mmPSOC_RESET_CONF_PM_ECC_DERR_RST_CFG 0x4C74178 |
| |
| #define mmPSOC_RESET_CONF_PM_SW_RST_CFG 0x4C7417C |
| |
| #define mmPSOC_RESET_CONF_TS_PRSTN_RST_CFG 0x4C74180 |
| |
| #define mmPSOC_RESET_CONF_TS_SOFT_RST_CFG 0x4C74184 |
| |
| #define mmPSOC_RESET_CONF_TS_FW_RST_CFG 0x4C74188 |
| |
| #define mmPSOC_RESET_CONF_TS_WD_RST_CFG 0x4C7418C |
| |
| #define mmPSOC_RESET_CONF_TS_MNL_RST_CFG 0x4C74190 |
| |
| #define mmPSOC_RESET_CONF_TS_FLR_RST_CFG 0x4C74194 |
| |
| #define mmPSOC_RESET_CONF_TS_ECC_DERR_RST_CFG 0x4C74198 |
| |
| #define mmPSOC_RESET_CONF_TS_SW_RST_CFG 0x4C7419C |
| |
| #define mmPSOC_RESET_CONF_TS_IF_PRSTN_RST_CFG 0x4C741A0 |
| |
| #define mmPSOC_RESET_CONF_TS_IF_SOFT_RST_CFG 0x4C741A4 |
| |
| #define mmPSOC_RESET_CONF_TS_IF_FW_RST_CFG 0x4C741A8 |
| |
| #define mmPSOC_RESET_CONF_TS_IF_WD_RST_CFG 0x4C741AC |
| |
| #define mmPSOC_RESET_CONF_TS_IF_MNL_RST_CFG 0x4C741B0 |
| |
| #define mmPSOC_RESET_CONF_TS_IF_FLR_RST_CFG 0x4C741B4 |
| |
| #define mmPSOC_RESET_CONF_TS_IF_ECC_DERR_RST_CFG 0x4C741B8 |
| |
| #define mmPSOC_RESET_CONF_TS_IF_SW_RST_CFG 0x4C741BC |
| |
| #define mmPSOC_RESET_CONF_PLL_L_PRSTN_RST_CFG 0x4C741C0 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_SOFT_RST_CFG 0x4C741C4 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_FW_RST_CFG 0x4C741C8 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_WD_RST_CFG 0x4C741CC |
| |
| #define mmPSOC_RESET_CONF_PLL_L_MNL_RST_CFG 0x4C741D0 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_FLR_RST_CFG 0x4C741D4 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_ECC_DERR_RST_CFG 0x4C741D8 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_SW_RST_CFG 0x4C741DC |
| |
| #define mmPSOC_RESET_CONF_PLL_H_PRSTN_RST_CFG 0x4C741E0 |
| |
| #define mmPSOC_RESET_CONF_PLL_H_SOFT_RST_CFG 0x4C741E4 |
| |
| #define mmPSOC_RESET_CONF_PLL_H_FW_RST_CFG 0x4C741E8 |
| |
| #define mmPSOC_RESET_CONF_PLL_H_WD_RST_CFG 0x4C741EC |
| |
| #define mmPSOC_RESET_CONF_PLL_H_MNL_RST_CFG 0x4C741F0 |
| |
| #define mmPSOC_RESET_CONF_PLL_H_FLR_RST_CFG 0x4C741F4 |
| |
| #define mmPSOC_RESET_CONF_PLL_H_ECC_DERR_RST_CFG 0x4C741F8 |
| |
| #define mmPSOC_RESET_CONF_PLL_H_SW_RST_CFG 0x4C741FC |
| |
| #define mmPSOC_RESET_CONF_MME_EUS_PRSTN_RST_CFG 0x4C74200 |
| |
| #define mmPSOC_RESET_CONF_MME_EUS_SOFT_RST_CFG 0x4C74204 |
| |
| #define mmPSOC_RESET_CONF_MME_EUS_FW_RST_CFG 0x4C74208 |
| |
| #define mmPSOC_RESET_CONF_MME_EUS_WD_RST_CFG 0x4C7420C |
| |
| #define mmPSOC_RESET_CONF_MME_EUS_MNL_RST_CFG 0x4C74210 |
| |
| #define mmPSOC_RESET_CONF_MME_EUS_FLR_RST_CFG 0x4C74214 |
| |
| #define mmPSOC_RESET_CONF_MME_EUS_ECC_DERR_RST_CFG 0x4C74218 |
| |
| #define mmPSOC_RESET_CONF_MME_EUS_SW_RST_CFG 0x4C7421C |
| |
| #define mmPSOC_RESET_CONF_MSS_CLS_PRSTN_RST_CFG 0x4C74220 |
| |
| #define mmPSOC_RESET_CONF_MSS_CLS_SOFT_RST_CFG 0x4C74224 |
| |
| #define mmPSOC_RESET_CONF_MSS_CLS_FW_RST_CFG 0x4C74228 |
| |
| #define mmPSOC_RESET_CONF_MSS_CLS_WD_RST_CFG 0x4C7422C |
| |
| #define mmPSOC_RESET_CONF_MSS_CLS_MNL_RST_CFG 0x4C74230 |
| |
| #define mmPSOC_RESET_CONF_MSS_CLS_FLR_RST_CFG 0x4C74234 |
| |
| #define mmPSOC_RESET_CONF_MSS_CLS_ECC_DERR_RST_CFG 0x4C74238 |
| |
| #define mmPSOC_RESET_CONF_MSS_CLS_SW_RST_CFG 0x4C7423C |
| |
| #define mmPSOC_RESET_CONF_TPC_PRSTN_RST_CFG 0x4C74240 |
| |
| #define mmPSOC_RESET_CONF_TPC_SOFT_RST_CFG 0x4C74244 |
| |
| #define mmPSOC_RESET_CONF_TPC_FW_RST_CFG 0x4C74248 |
| |
| #define mmPSOC_RESET_CONF_TPC_WD_RST_CFG 0x4C7424C |
| |
| #define mmPSOC_RESET_CONF_TPC_MNL_RST_CFG 0x4C74250 |
| |
| #define mmPSOC_RESET_CONF_TPC_FLR_RST_CFG 0x4C74254 |
| |
| #define mmPSOC_RESET_CONF_TPC_ECC_DERR_RST_CFG 0x4C74258 |
| |
| #define mmPSOC_RESET_CONF_TPC_SW_RST_CFG 0x4C7425C |
| |
| #define mmPSOC_RESET_CONF_HIF_HMMU_PRSTN_RST_CFG 0x4C74260 |
| |
| #define mmPSOC_RESET_CONF_HIF_HMMU_SOFT_RST_CFG 0x4C74264 |
| |
| #define mmPSOC_RESET_CONF_HIF_HMMU_FW_RST_CFG 0x4C74268 |
| |
| #define mmPSOC_RESET_CONF_HIF_HMMU_WD_RST_CFG 0x4C7426C |
| |
| #define mmPSOC_RESET_CONF_HIF_HMMU_MNL_RST_CFG 0x4C74270 |
| |
| #define mmPSOC_RESET_CONF_HIF_HMMU_FLR_RST_CFG 0x4C74274 |
| |
| #define mmPSOC_RESET_CONF_HIF_HMMU_ECC_DERR_RST_CFG 0x4C74278 |
| |
| #define mmPSOC_RESET_CONF_HIF_HMMU_SW_RST_CFG 0x4C7427C |
| |
| #define mmPSOC_RESET_CONF_XBAR_PRSTN_RST_CFG 0x4C74280 |
| |
| #define mmPSOC_RESET_CONF_XBAR_SOFT_RST_CFG 0x4C74284 |
| |
| #define mmPSOC_RESET_CONF_XBAR_FW_RST_CFG 0x4C74288 |
| |
| #define mmPSOC_RESET_CONF_XBAR_WD_RST_CFG 0x4C7428C |
| |
| #define mmPSOC_RESET_CONF_XBAR_MNL_RST_CFG 0x4C74290 |
| |
| #define mmPSOC_RESET_CONF_XBAR_FLR_RST_CFG 0x4C74294 |
| |
| #define mmPSOC_RESET_CONF_XBAR_ECC_DERR_RST_CFG 0x4C74298 |
| |
| #define mmPSOC_RESET_CONF_XBAR_SW_RST_CFG 0x4C7429C |
| |
| #define mmPSOC_RESET_CONF_SFT_XFT_TFT_PRSTN_RST_CFG 0x4C742A0 |
| |
| #define mmPSOC_RESET_CONF_SFT_XFT_TFT_SOFT_RST_CFG 0x4C742A4 |
| |
| #define mmPSOC_RESET_CONF_SFT_XFT_TFT_FW_RST_CFG 0x4C742A8 |
| |
| #define mmPSOC_RESET_CONF_SFT_XFT_TFT_WD_RST_CFG 0x4C742AC |
| |
| #define mmPSOC_RESET_CONF_SFT_XFT_TFT_MNL_RST_CFG 0x4C742B0 |
| |
| #define mmPSOC_RESET_CONF_SFT_XFT_TFT_FLR_RST_CFG 0x4C742B4 |
| |
| #define mmPSOC_RESET_CONF_SFT_XFT_TFT_ECC_DERR_RST_CFG 0x4C742B8 |
| |
| #define mmPSOC_RESET_CONF_SFT_XFT_TFT_SW_RST_CFG 0x4C742BC |
| |
| #define mmPSOC_RESET_CONF_DDMA_PRSTN_RST_CFG 0x4C742C0 |
| |
| #define mmPSOC_RESET_CONF_DDMA_SOFT_RST_CFG 0x4C742C4 |
| |
| #define mmPSOC_RESET_CONF_DDMA_FW_RST_CFG 0x4C742C8 |
| |
| #define mmPSOC_RESET_CONF_DDMA_WD_RST_CFG 0x4C742CC |
| |
| #define mmPSOC_RESET_CONF_DDMA_MNL_RST_CFG 0x4C742D0 |
| |
| #define mmPSOC_RESET_CONF_DDMA_FLR_RST_CFG 0x4C742D4 |
| |
| #define mmPSOC_RESET_CONF_DDMA_ECC_DERR_RST_CFG 0x4C742D8 |
| |
| #define mmPSOC_RESET_CONF_DDMA_SW_RST_CFG 0x4C742DC |
| |
| #define mmPSOC_RESET_CONF_KDMA_PRSTN_RST_CFG 0x4C742E0 |
| |
| #define mmPSOC_RESET_CONF_KDMA_SOFT_RST_CFG 0x4C742E4 |
| |
| #define mmPSOC_RESET_CONF_KDMA_FW_RST_CFG 0x4C742E8 |
| |
| #define mmPSOC_RESET_CONF_KDMA_WD_RST_CFG 0x4C742EC |
| |
| #define mmPSOC_RESET_CONF_KDMA_MNL_RST_CFG 0x4C742F0 |
| |
| #define mmPSOC_RESET_CONF_KDMA_FLR_RST_CFG 0x4C742F4 |
| |
| #define mmPSOC_RESET_CONF_KDMA_ECC_DERR_RST_CFG 0x4C742F8 |
| |
| #define mmPSOC_RESET_CONF_KDMA_SW_RST_CFG 0x4C742FC |
| |
| #define mmPSOC_RESET_CONF_PDMA_PRSTN_RST_CFG 0x4C74300 |
| |
| #define mmPSOC_RESET_CONF_PDMA_SOFT_RST_CFG 0x4C74304 |
| |
| #define mmPSOC_RESET_CONF_PDMA_FW_RST_CFG 0x4C74308 |
| |
| #define mmPSOC_RESET_CONF_PDMA_WD_RST_CFG 0x4C7430C |
| |
| #define mmPSOC_RESET_CONF_PDMA_MNL_RST_CFG 0x4C74310 |
| |
| #define mmPSOC_RESET_CONF_PDMA_FLR_RST_CFG 0x4C74314 |
| |
| #define mmPSOC_RESET_CONF_PDMA_ECC_DERR_RST_CFG 0x4C74318 |
| |
| #define mmPSOC_RESET_CONF_PDMA_SW_RST_CFG 0x4C7431C |
| |
| #define mmPSOC_RESET_CONF_ARC_SS_PRSTN_RST_CFG 0x4C74320 |
| |
| #define mmPSOC_RESET_CONF_ARC_SS_SOFT_RST_CFG 0x4C74324 |
| |
| #define mmPSOC_RESET_CONF_ARC_SS_FW_RST_CFG 0x4C74328 |
| |
| #define mmPSOC_RESET_CONF_ARC_SS_WD_RST_CFG 0x4C7432C |
| |
| #define mmPSOC_RESET_CONF_ARC_SS_MNL_RST_CFG 0x4C74330 |
| |
| #define mmPSOC_RESET_CONF_ARC_SS_FLR_RST_CFG 0x4C74334 |
| |
| #define mmPSOC_RESET_CONF_ARC_SS_ECC_DERR_RST_CFG 0x4C74338 |
| |
| #define mmPSOC_RESET_CONF_ARC_SS_SW_RST_CFG 0x4C7433C |
| |
| #define mmPSOC_RESET_CONF_ROTATOR_PRSTN_RST_CFG 0x4C74340 |
| |
| #define mmPSOC_RESET_CONF_ROTATOR_SOFT_RST_CFG 0x4C74344 |
| |
| #define mmPSOC_RESET_CONF_ROTATOR_FW_RST_CFG 0x4C74348 |
| |
| #define mmPSOC_RESET_CONF_ROTATOR_WD_RST_CFG 0x4C7434C |
| |
| #define mmPSOC_RESET_CONF_ROTATOR_MNL_RST_CFG 0x4C74350 |
| |
| #define mmPSOC_RESET_CONF_ROTATOR_FLR_RST_CFG 0x4C74354 |
| |
| #define mmPSOC_RESET_CONF_ROTATOR_ECC_DERR_RST_CFG 0x4C74358 |
| |
| #define mmPSOC_RESET_CONF_ROTATOR_SW_RST_CFG 0x4C7435C |
| |
| #define mmPSOC_RESET_CONF_SM_PRSTN_RST_CFG 0x4C74360 |
| |
| #define mmPSOC_RESET_CONF_SM_SOFT_RST_CFG 0x4C74364 |
| |
| #define mmPSOC_RESET_CONF_SM_FW_RST_CFG 0x4C74368 |
| |
| #define mmPSOC_RESET_CONF_SM_WD_RST_CFG 0x4C7436C |
| |
| #define mmPSOC_RESET_CONF_SM_MNL_RST_CFG 0x4C74370 |
| |
| #define mmPSOC_RESET_CONF_SM_FLR_RST_CFG 0x4C74374 |
| |
| #define mmPSOC_RESET_CONF_SM_ECC_DERR_RST_CFG 0x4C74378 |
| |
| #define mmPSOC_RESET_CONF_SM_SW_RST_CFG 0x4C7437C |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_PRSTN_RST_CFG 0x4C74380 |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_SOFT_RST_CFG 0x4C74384 |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_FW_RST_CFG 0x4C74388 |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_WD_RST_CFG 0x4C7438C |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_MNL_RST_CFG 0x4C74390 |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_FLR_RST_CFG 0x4C74394 |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_ECC_DERR_RST_CFG 0x4C74398 |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_SW_RST_CFG 0x4C7439C |
| |
| #define mmPSOC_RESET_CONF_HBM_MC_PRSTN_RST_CFG 0x4C743A0 |
| |
| #define mmPSOC_RESET_CONF_HBM_MC_SOFT_RST_CFG 0x4C743A4 |
| |
| #define mmPSOC_RESET_CONF_HBM_MC_FW_RST_CFG 0x4C743A8 |
| |
| #define mmPSOC_RESET_CONF_HBM_MC_WD_RST_CFG 0x4C743AC |
| |
| #define mmPSOC_RESET_CONF_HBM_MC_MNL_RST_CFG 0x4C743B0 |
| |
| #define mmPSOC_RESET_CONF_HBM_MC_FLR_RST_CFG 0x4C743B4 |
| |
| #define mmPSOC_RESET_CONF_HBM_MC_ECC_DERR_RST_CFG 0x4C743B8 |
| |
| #define mmPSOC_RESET_CONF_HBM_MC_SW_RST_CFG 0x4C743BC |
| |
| #define mmPSOC_RESET_CONF_NIC_PRSTN_RST_CFG 0x4C743C0 |
| |
| #define mmPSOC_RESET_CONF_NIC_SOFT_RST_CFG 0x4C743C4 |
| |
| #define mmPSOC_RESET_CONF_NIC_FW_RST_CFG 0x4C743C8 |
| |
| #define mmPSOC_RESET_CONF_NIC_WD_RST_CFG 0x4C743CC |
| |
| #define mmPSOC_RESET_CONF_NIC_MNL_RST_CFG 0x4C743D0 |
| |
| #define mmPSOC_RESET_CONF_NIC_FLR_RST_CFG 0x4C743D4 |
| |
| #define mmPSOC_RESET_CONF_NIC_ECC_DERR_RST_CFG 0x4C743D8 |
| |
| #define mmPSOC_RESET_CONF_NIC_SW_RST_CFG 0x4C743DC |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_PRSTN_RST_CFG 0x4C743E0 |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_SOFT_RST_CFG 0x4C743E4 |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_FW_RST_CFG 0x4C743E8 |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_WD_RST_CFG 0x4C743EC |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_MNL_RST_CFG 0x4C743F0 |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_FLR_RST_CFG 0x4C743F4 |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_ECC_DERR_RST_CFG 0x4C743F8 |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_SW_RST_CFG 0x4C743FC |
| |
| #define mmPSOC_RESET_CONF_NIC_CH_PRSTN_RST_CFG 0x4C74400 |
| |
| #define mmPSOC_RESET_CONF_NIC_CH_SOFT_RST_CFG 0x4C74404 |
| |
| #define mmPSOC_RESET_CONF_NIC_CH_FW_RST_CFG 0x4C74408 |
| |
| #define mmPSOC_RESET_CONF_NIC_CH_WD_RST_CFG 0x4C7440C |
| |
| #define mmPSOC_RESET_CONF_NIC_CH_MNL_RST_CFG 0x4C74410 |
| |
| #define mmPSOC_RESET_CONF_NIC_CH_FLR_RST_CFG 0x4C74414 |
| |
| #define mmPSOC_RESET_CONF_NIC_CH_ECC_DERR_RST_CFG 0x4C74418 |
| |
| #define mmPSOC_RESET_CONF_NIC_CH_SW_RST_CFG 0x4C7441C |
| |
| #define mmPSOC_RESET_CONF_SOFT_RST 0x4C74800 |
| |
| #define mmPSOC_RESET_CONF_SW_ALL_RST 0x4C74804 |
| |
| #define mmPSOC_RESET_CONF_UNIT_RST_N 0x4C74808 |
| |
| #define mmPSOC_RESET_CONF_PSOC_UNIT_RST 0x4C7480C |
| |
| #define mmPSOC_RESET_CONF_CPU_UNIT_RST 0x4C74810 |
| |
| #define mmPSOC_RESET_CONF_ARC_UNIT_RST 0x4C74814 |
| |
| #define mmPSOC_RESET_CONF_SIF_UNIT_RST 0x4C74818 |
| |
| #define mmPSOC_RESET_CONF_SRAM_UNIT_RST 0x4C7481C |
| |
| #define mmPSOC_RESET_CONF_PCIE_CTRL_UNIT_RST 0x4C74820 |
| |
| #define mmPSOC_RESET_CONF_PCIE_PHY_CFG_UNIT_RST 0x4C74824 |
| |
| #define mmPSOC_RESET_CONF_PCIE_IF_UNIT_RST 0x4C74828 |
| |
| #define mmPSOC_RESET_CONF_TPC_DIV_UNIT_RST 0x4C7482C |
| |
| #define mmPSOC_RESET_CONF_HBM_DIV_UNIT_RST 0x4C74830 |
| |
| #define mmPSOC_RESET_CONF_PMMU_UNIT_RST 0x4C74834 |
| |
| #define mmPSOC_RESET_CONF_PM_UNIT_RST 0x4C74838 |
| |
| #define mmPSOC_RESET_CONF_TS_UNIT_RST 0x4C7483C |
| |
| #define mmPSOC_RESET_CONF_TS_IF_UNIT_RST 0x4C74840 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_UNIT_RST 0x4C74844 |
| |
| #define mmPSOC_RESET_CONF_PLL_H_UNIT_RST 0x4C74848 |
| |
| #define mmPSOC_RESET_CONF_MME_EUS_UNIT_RST 0x4C7484C |
| |
| #define mmPSOC_RESET_CONF_MSS_CLS_UNIT_RST 0x4C74850 |
| |
| #define mmPSOC_RESET_CONF_TPC_UNIT_RST 0x4C74854 |
| |
| #define mmPSOC_RESET_CONF_HIF_HMMU_UNIT_RST 0x4C74858 |
| |
| #define mmPSOC_RESET_CONF_XBAR_UNIT_RST 0x4C7485C |
| |
| #define mmPSOC_RESET_CONF_SFT_XFT_TFT_UNIT_RST 0x4C74860 |
| |
| #define mmPSOC_RESET_CONF_DDMA_UNIT_RST 0x4C74864 |
| |
| #define mmPSOC_RESET_CONF_KDMA_UNIT_RST 0x4C74868 |
| |
| #define mmPSOC_RESET_CONF_PDMA_UNIT_RST 0x4C7486C |
| |
| #define mmPSOC_RESET_CONF_ARC_SS_UNIT_RST 0x4C74870 |
| |
| #define mmPSOC_RESET_CONF_ROTATOR_UNIT_RST 0x4C74874 |
| |
| #define mmPSOC_RESET_CONF_SM_UNIT_RST 0x4C74878 |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_UNIT_RST 0x4C7487C |
| |
| #define mmPSOC_RESET_CONF_HBM_MC_UNIT_RST 0x4C74880 |
| |
| #define mmPSOC_RESET_CONF_NIC_UNIT_RST 0x4C74884 |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_UNIT_RST 0x4C74888 |
| |
| #define mmPSOC_RESET_CONF_NIC_CH_UNIT_RST 0x4C7488C |
| |
| #define mmPSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL 0x4C74B00 |
| |
| #define mmPSOC_RESET_CONF_CPU_0_CLK_RST_CTRL 0x4C74B04 |
| |
| #define mmPSOC_RESET_CONF_ARC_0_CLK_RST_CTRL 0x4C74B08 |
| |
| #define mmPSOC_RESET_CONF_ARC_1_CLK_RST_CTRL 0x4C74B0C |
| |
| #define mmPSOC_RESET_CONF_SIF_0_CLK_RST_CTRL 0x4C74B10 |
| |
| #define mmPSOC_RESET_CONF_SIF_1_CLK_RST_CTRL 0x4C74B14 |
| |
| #define mmPSOC_RESET_CONF_SIF_2_CLK_RST_CTRL 0x4C74B18 |
| |
| #define mmPSOC_RESET_CONF_SIF_3_CLK_RST_CTRL 0x4C74B1C |
| |
| #define mmPSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL 0x4C74B20 |
| |
| #define mmPSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL 0x4C74B24 |
| |
| #define mmPSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL 0x4C74B28 |
| |
| #define mmPSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL 0x4C74B2C |
| |
| #define mmPSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL 0x4C74B30 |
| |
| #define mmPSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL 0x4C74B34 |
| |
| #define mmPSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL 0x4C74B38 |
| |
| #define mmPSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL 0x4C74B3C |
| |
| #define mmPSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL 0x4C74B40 |
| |
| #define mmPSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL 0x4C74B44 |
| |
| #define mmPSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL 0x4C74B48 |
| |
| #define mmPSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL 0x4C74B4C |
| |
| #define mmPSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL 0x4C74B50 |
| |
| #define mmPSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL 0x4C74B54 |
| |
| #define mmPSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL 0x4C74B58 |
| |
| #define mmPSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL 0x4C74B5C |
| |
| #define mmPSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL 0x4C74B60 |
| |
| #define mmPSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL 0x4C74B64 |
| |
| #define mmPSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL 0x4C74B68 |
| |
| #define mmPSOC_RESET_CONF_PM_0_CLK_RST_CTRL 0x4C74B6C |
| |
| #define mmPSOC_RESET_CONF_PM_1_CLK_RST_CTRL 0x4C74B70 |
| |
| #define mmPSOC_RESET_CONF_PM_2_CLK_RST_CTRL 0x4C74B74 |
| |
| #define mmPSOC_RESET_CONF_PM_3_CLK_RST_CTRL 0x4C74B78 |
| |
| #define mmPSOC_RESET_CONF_TS_0_CLK_RST_CTRL 0x4C74B7C |
| |
| #define mmPSOC_RESET_CONF_TS_1_CLK_RST_CTRL 0x4C74B80 |
| |
| #define mmPSOC_RESET_CONF_TS_2_CLK_RST_CTRL 0x4C74B84 |
| |
| #define mmPSOC_RESET_CONF_TS_3_CLK_RST_CTRL 0x4C74B88 |
| |
| #define mmPSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL 0x4C74B8C |
| |
| #define mmPSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL 0x4C74B90 |
| |
| #define mmPSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL 0x4C74B94 |
| |
| #define mmPSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL 0x4C74B98 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL 0x4C74B9C |
| |
| #define mmPSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL 0x4C74BA0 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL 0x4C74BA4 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL 0x4C74BA8 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL 0x4C74BAC |
| |
| #define mmPSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL 0x4C74BB0 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL 0x4C74BB4 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL 0x4C74BB8 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL 0x4C74BBC |
| |
| #define mmPSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL 0x4C74BC0 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL 0x4C74BC4 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL 0x4C74BC8 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL 0x4C74BCC |
| |
| #define mmPSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL 0x4C74BD0 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL 0x4C74BD4 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL 0x4C74BD8 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL 0x4C74BDC |
| |
| #define mmPSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL 0x4C74BE0 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL 0x4C74BE4 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL 0x4C74BE8 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL 0x4C74BEC |
| |
| #define mmPSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL 0x4C74BF0 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL 0x4C74BF4 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL 0x4C74BF8 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL 0x4C74BFC |
| |
| #define mmPSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL 0x4C74C00 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL 0x4C74C04 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL 0x4C74C08 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL 0x4C74C0C |
| |
| #define mmPSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL 0x4C74C10 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL 0x4C74C14 |
| |
| #define mmPSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL 0x4C74C18 |
| |
| #define mmPSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL 0x4C74C1C |
| |
| #define mmPSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL 0x4C74C20 |
| |
| #define mmPSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL 0x4C74C24 |
| |
| #define mmPSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL 0x4C74C28 |
| |
| #define mmPSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL 0x4C74C2C |
| |
| #define mmPSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL 0x4C74C30 |
| |
| #define mmPSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL 0x4C74C34 |
| |
| #define mmPSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL 0x4C74C38 |
| |
| #define mmPSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL 0x4C74C3C |
| |
| #define mmPSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL 0x4C74C40 |
| |
| #define mmPSOC_RESET_CONF_TPC_0_CLK_RST_CTRL 0x4C74C44 |
| |
| #define mmPSOC_RESET_CONF_TPC_1_CLK_RST_CTRL 0x4C74C48 |
| |
| #define mmPSOC_RESET_CONF_TPC_2_CLK_RST_CTRL 0x4C74C4C |
| |
| #define mmPSOC_RESET_CONF_TPC_3_CLK_RST_CTRL 0x4C74C50 |
| |
| #define mmPSOC_RESET_CONF_TPC_4_CLK_RST_CTRL 0x4C74C54 |
| |
| #define mmPSOC_RESET_CONF_TPC_5_CLK_RST_CTRL 0x4C74C58 |
| |
| #define mmPSOC_RESET_CONF_TPC_6_CLK_RST_CTRL 0x4C74C5C |
| |
| #define mmPSOC_RESET_CONF_TPC_7_CLK_RST_CTRL 0x4C74C60 |
| |
| #define mmPSOC_RESET_CONF_TPC_8_CLK_RST_CTRL 0x4C74C64 |
| |
| #define mmPSOC_RESET_CONF_TPC_9_CLK_RST_CTRL 0x4C74C68 |
| |
| #define mmPSOC_RESET_CONF_TPC_10_CLK_RST_CTRL 0x4C74C6C |
| |
| #define mmPSOC_RESET_CONF_TPC_11_CLK_RST_CTRL 0x4C74C70 |
| |
| #define mmPSOC_RESET_CONF_TPC_12_CLK_RST_CTRL 0x4C74C74 |
| |
| #define mmPSOC_RESET_CONF_TPC_13_CLK_RST_CTRL 0x4C74C78 |
| |
| #define mmPSOC_RESET_CONF_TPC_14_CLK_RST_CTRL 0x4C74C7C |
| |
| #define mmPSOC_RESET_CONF_TPC_15_CLK_RST_CTRL 0x4C74C80 |
| |
| #define mmPSOC_RESET_CONF_TPC_16_CLK_RST_CTRL 0x4C74C84 |
| |
| #define mmPSOC_RESET_CONF_TPC_17_CLK_RST_CTRL 0x4C74C88 |
| |
| #define mmPSOC_RESET_CONF_TPC_18_CLK_RST_CTRL 0x4C74C8C |
| |
| #define mmPSOC_RESET_CONF_TPC_19_CLK_RST_CTRL 0x4C74C90 |
| |
| #define mmPSOC_RESET_CONF_TPC_20_CLK_RST_CTRL 0x4C74C94 |
| |
| #define mmPSOC_RESET_CONF_TPC_21_CLK_RST_CTRL 0x4C74C98 |
| |
| #define mmPSOC_RESET_CONF_TPC_22_CLK_RST_CTRL 0x4C74C9C |
| |
| #define mmPSOC_RESET_CONF_TPC_23_CLK_RST_CTRL 0x4C74CA0 |
| |
| #define mmPSOC_RESET_CONF_TPC_24_CLK_RST_CTRL 0x4C74CA4 |
| |
| #define mmPSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL 0x4C74CA8 |
| |
| #define mmPSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL 0x4C74CAC |
| |
| #define mmPSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL 0x4C74CB0 |
| |
| #define mmPSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL 0x4C74CB4 |
| |
| #define mmPSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL 0x4C74CB8 |
| |
| #define mmPSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL 0x4C74CBC |
| |
| #define mmPSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL 0x4C74CC0 |
| |
| #define mmPSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL 0x4C74CC4 |
| |
| #define mmPSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL 0x4C74CC8 |
| |
| #define mmPSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL 0x4C74CCC |
| |
| #define mmPSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL 0x4C74CD0 |
| |
| #define mmPSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL 0x4C74CD4 |
| |
| #define mmPSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL 0x4C74CD8 |
| |
| #define mmPSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL 0x4C74CDC |
| |
| #define mmPSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL 0x4C74CE0 |
| |
| #define mmPSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL 0x4C74CE4 |
| |
| #define mmPSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL 0x4C74CE8 |
| |
| #define mmPSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL 0x4C74CEC |
| |
| #define mmPSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL 0x4C74CF0 |
| |
| #define mmPSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL 0x4C74CF4 |
| |
| #define mmPSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL 0x4C74CF8 |
| |
| #define mmPSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL 0x4C74CFC |
| |
| #define mmPSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL 0x4C74D00 |
| |
| #define mmPSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL 0x4C74D04 |
| |
| #define mmPSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL 0x4C74D08 |
| |
| #define mmPSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL 0x4C74D0C |
| |
| #define mmPSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL 0x4C74D10 |
| |
| #define mmPSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL 0x4C74D14 |
| |
| #define mmPSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL 0x4C74D18 |
| |
| #define mmPSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL 0x4C74D1C |
| |
| #define mmPSOC_RESET_CONF_SM_0_CLK_RST_CTRL 0x4C74D20 |
| |
| #define mmPSOC_RESET_CONF_SM_1_CLK_RST_CTRL 0x4C74D24 |
| |
| #define mmPSOC_RESET_CONF_SM_2_CLK_RST_CTRL 0x4C74D28 |
| |
| #define mmPSOC_RESET_CONF_SM_3_CLK_RST_CTRL 0x4C74D2C |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL 0x4C74D30 |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL 0x4C74D34 |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL 0x4C74D38 |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL 0x4C74D3C |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL 0x4C74D40 |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL 0x4C74D44 |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL 0x4C74D48 |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL 0x4C74D4C |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL 0x4C74D50 |
| |
| #define mmPSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL 0x4C74D54 |
| |
| #define mmPSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL 0x4C74D58 |
| |
| #define mmPSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL 0x4C74D5C |
| |
| #define mmPSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL 0x4C74D60 |
| |
| #define mmPSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL 0x4C74D64 |
| |
| #define mmPSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL 0x4C74D68 |
| |
| #define mmPSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL 0x4C74D6C |
| |
| #define mmPSOC_RESET_CONF_NIC_0_CLK_RST_CTRL 0x4C74D70 |
| |
| #define mmPSOC_RESET_CONF_NIC_1_CLK_RST_CTRL 0x4C74D74 |
| |
| #define mmPSOC_RESET_CONF_NIC_2_CLK_RST_CTRL 0x4C74D78 |
| |
| #define mmPSOC_RESET_CONF_NIC_3_CLK_RST_CTRL 0x4C74D7C |
| |
| #define mmPSOC_RESET_CONF_NIC_4_CLK_RST_CTRL 0x4C74D80 |
| |
| #define mmPSOC_RESET_CONF_NIC_5_CLK_RST_CTRL 0x4C74D84 |
| |
| #define mmPSOC_RESET_CONF_NIC_6_CLK_RST_CTRL 0x4C74D88 |
| |
| #define mmPSOC_RESET_CONF_NIC_7_CLK_RST_CTRL 0x4C74D8C |
| |
| #define mmPSOC_RESET_CONF_NIC_8_CLK_RST_CTRL 0x4C74D90 |
| |
| #define mmPSOC_RESET_CONF_NIC_9_CLK_RST_CTRL 0x4C74D94 |
| |
| #define mmPSOC_RESET_CONF_NIC_10_CLK_RST_CTRL 0x4C74D98 |
| |
| #define mmPSOC_RESET_CONF_NIC_11_CLK_RST_CTRL 0x4C74D9C |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL 0x4C74DA0 |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL 0x4C74DA4 |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL 0x4C74DA8 |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL 0x4C74DAC |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL 0x4C74DB0 |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL 0x4C74DB4 |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL 0x4C74DB8 |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL 0x4C74DBC |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL 0x4C74DC0 |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL 0x4C74DC4 |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL 0x4C74DC8 |
| |
| #define mmPSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL 0x4C74DCC |
| |
| #define mmPSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL 0x4C74DD0 |
| |
| #define mmPSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL 0x4C74DD4 |
| |
| #define mmPSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL 0x4C74DD8 |
| |
| #endif /* ASIC_REG_PSOC_RESET_CONF_REGS_H_ */ |
