drivers/accel/habanalabs/include/gaudi2/asic_reg/xbar_mid_0_regs.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_XBAR_MID_0_REGS_H_
#define ASIC_REG_XBAR_MID_0_REGS_H_

/*
 *****************************************
 *   XBAR_MID_0
 *   (Prototype: XBAR)
 *****************************************
 */

#define mmXBAR_MID_0_LBW_HIF0_BASE_ADDR 0x4D40000

#define mmXBAR_MID_0_LBW_HIF0_ADDR_MASK 0x4D40004

#define mmXBAR_MID_0_LBW_HIF1_BASE_ADDR 0x4D40008

#define mmXBAR_MID_0_LBW_HIF1_ADDR_MASK 0x4D4000C

#define mmXBAR_MID_0_LBW_HMMU0_BASE_ADDR 0x4D40010

#define mmXBAR_MID_0_LBW_HMMU0_ADDR_MASK 0x4D40014

#define mmXBAR_MID_0_LBW_HMMU1_BASE_ADDR 0x4D40018

#define mmXBAR_MID_0_LBW_HMMU1_ADDR_MASK 0x4D4001C

#define mmXBAR_MID_0_LBW_EDMA_BASE_ADDR0 0x4D40020

#define mmXBAR_MID_0_LBW_EDMA_ADDR_MASK0 0x4D40024

#define mmXBAR_MID_0_LBW_EDMA_BASE_ADDR1 0x4D40028

#define mmXBAR_MID_0_LBW_EDMA_ADDR_MASK1 0x4D4002C

#define mmXBAR_MID_0_LBW_HBM_BASE_ADDR0 0x4D40030

#define mmXBAR_MID_0_LBW_HBM_ADDR_MASK0 0x4D40034

#define mmXBAR_MID_0_LBW_HBM_BASE_ADDR1 0x4D40038

#define mmXBAR_MID_0_LBW_HBM_ADDR_MASK1 0x4D4003C

#define mmXBAR_MID_0_LBW_XBAR_BASE_ADDR0 0x4D40040

#define mmXBAR_MID_0_LBW_XBAR_ADDR_MASK0 0x4D40044

#define mmXBAR_MID_0_LBW_XBAR_BASE_ADDR1 0x4D40048

#define mmXBAR_MID_0_LBW_XBAR_ADDR_MASK1 0x4D4004C

#define mmXBAR_MID_0_DBG_HIF0_BASE_ADDR 0x4D40080

#define mmXBAR_MID_0_DBG_HIF0_ADDR_MASK 0x4D40084

#define mmXBAR_MID_0_DBG_HIF1_BASE_ADDR 0x4D40088

#define mmXBAR_MID_0_DBG_HIF1_ADDR_MASK 0x4D4008C

#define mmXBAR_MID_0_DBG_HMMU0_BASE_ADDR 0x4D40090

#define mmXBAR_MID_0_DBG_HMMU0_ADDR_MASK 0x4D40094

#define mmXBAR_MID_0_DBG_HMMU1_BASE_ADDR 0x4D40098

#define mmXBAR_MID_0_DBG_HMMU1_ADDR_MASK 0x4D4009C

#define mmXBAR_MID_0_DBG_EDMA_BASE_ADDR0 0x4D400A0

#define mmXBAR_MID_0_DBG_EDMA_ADDR_MASK0 0x4D400A4

#define mmXBAR_MID_0_DBG_EDMA_BASE_ADDR1 0x4D400A8

#define mmXBAR_MID_0_DBG_EDMA_ADDR_MASK1 0x4D400AC

#define mmXBAR_MID_0_DBG_HBM_BASE_ADDR0 0x4D400B0

#define mmXBAR_MID_0_DBG_HBM_ADDR_MASK0 0x4D400B4

#define mmXBAR_MID_0_DBG_HBM_BASE_ADDR1 0x4D400B8

#define mmXBAR_MID_0_DBG_HBM_ADDR_MASK1 0x4D400BC

#define mmXBAR_MID_0_DBG_XBAR_BASE_ADDR0 0x4D400C0

#define mmXBAR_MID_0_DBG_XBAR_ADDR_MASK0 0x4D400C4

#define mmXBAR_MID_0_DBG_XBAR_BASE_ADDR1 0x4D400C8

#define mmXBAR_MID_0_DBG_XBAR_ADDR_MASK1 0x4D400CC

#define mmXBAR_MID_0_LBW_INTERNAL_ADDR_RGF 0x4D400D0

#define mmXBAR_MID_0_DBG_INTERNAL_ADDR_FUN 0x4D400D4

#define mmXBAR_MID_0_EMEM_HBM_BIT_LOCATION 0x4D40100

#define mmXBAR_MID_0_EMEM_PC_BIT_LOCATION 0x4D40104

#define mmXBAR_MID_0_HIF_WR_RS_CH_LOCATION 0x4D40108

#define mmXBAR_MID_0_HBW_MST_ARB_WEIGHT 0x4D4010C

#define mmXBAR_MID_0_MMU_PC_IDX_MAP_0 0x4D40110

#define mmXBAR_MID_0_MMU_PC_IDX_MAP_1 0x4D40114

#define mmXBAR_MID_0_MMU_RD_LL_ARB_0 0x4D40120

#define mmXBAR_MID_0_MMU_RD_LL_ARB_1 0x4D40124

#define mmXBAR_MID_0_MMU_WR_LL_ARB_0 0x4D40128

#define mmXBAR_MID_0_MMU_WR_LL_ARB_1 0x4D4012C

#define mmXBAR_MID_0_HBM_USER_RESP_OVR_0 0x4D40130

#define mmXBAR_MID_0_HBM_USER_RESP_OVR_1 0x4D40134

#define mmXBAR_MID_0_RL_RD_0 0x4D40140

#define mmXBAR_MID_0_RL_RD_1 0x4D40144

#define mmXBAR_MID_0_RL_RD_2 0x4D40148

#define mmXBAR_MID_0_RL_RD_3 0x4D4014C

#define mmXBAR_MID_0_RL_RD_4 0x4D40150

#define mmXBAR_MID_0_RL_RD_5 0x4D40154

#define mmXBAR_MID_0_RL_RD_6 0x4D40158

#define mmXBAR_MID_0_RL_RD_7 0x4D4015C

#define mmXBAR_MID_0_RL_RD_8 0x4D40160

#define mmXBAR_MID_0_RL_RD_9 0x4D40164

#define mmXBAR_MID_0_RL_RD_10 0x4D40168

#define mmXBAR_MID_0_RL_RD_11 0x4D4016C

#define mmXBAR_MID_0_RL_WR_0 0x4D40180

#define mmXBAR_MID_0_RL_WR_1 0x4D40184

#define mmXBAR_MID_0_RL_WR_2 0x4D40188

#define mmXBAR_MID_0_RL_WR_3 0x4D4018C

#define mmXBAR_MID_0_RL_WR_4 0x4D40190

#define mmXBAR_MID_0_RL_WR_5 0x4D40194

#define mmXBAR_MID_0_RL_WR_6 0x4D40198

#define mmXBAR_MID_0_RL_WR_7 0x4D4019C

#define mmXBAR_MID_0_RL_WR_8 0x4D401A0

#define mmXBAR_MID_0_RL_WR_9 0x4D401A4

#define mmXBAR_MID_0_RL_WR_10 0x4D401A8

#define mmXBAR_MID_0_RL_WR_11 0x4D401AC

#define mmXBAR_MID_0_E2E_CRDT_SLV_0 0x4D401B0

#define mmXBAR_MID_0_E2E_CRDT_SLV_1 0x4D401B4

#define mmXBAR_MID_0_E2E_CRDT_SLV_2 0x4D401B8

#define mmXBAR_MID_0_E2E_CRDT_DEBUG 0x4D401BC

#define mmXBAR_MID_0_UPSCALE 0x4D401C0

#define mmXBAR_MID_0_DOWN_CONV 0x4D401C4

#define mmXBAR_MID_0_DOWN_CONV_LFSR_EN 0x4D401D0

#define mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VLD 0x4D401D4

#define mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VALUE 0x4D401D8

#define mmXBAR_MID_0_DOWN_CONV_LFSR_CFG_POLY 0x4D401DC

#endif /* ASIC_REG_XBAR_MID_0_REGS_H_ */