Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/ti,j721e-csi2rx-shim.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI J721E CSI2RX Shim

description: |
  The TI J721E CSI2RX Shim is a wrapper around Cadence CSI2RX bridge that
  enables sending captured frames to memory over PSI-L DMA. In the J721E
  Technical Reference Manual (SPRUIL1B) it is referred to as "SHIM" under the
  CSI_RX_IF section.

maintainers:
  - Jai Luthra <j-luthra@ti.com>

properties:
  compatible:
    const: ti,j721e-csi2rx-shim

  dmas:
    maxItems: 1

  dma-names:
    items:
      - const: rx0

  reg:
    maxItems: 1

  power-domains:
    maxItems: 1

  ranges: true

  "#address-cells": true

  "#size-cells": true

patternProperties:
  "^csi-bridge@":
    type: object
    description: CSI2 bridge node.
    $ref: cdns,csi2rx.yaml#

required:
  - compatible
  - reg
  - dmas
  - dma-names
  - power-domains
  - ranges
  - "#address-cells"
  - "#size-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/soc/ti,sci_pm_domain.h>

    ti_csi2rx0: ticsi2rx@4500000 {
        compatible = "ti,j721e-csi2rx-shim";
        dmas = <&main_udmap 0x4940>;
        dma-names = "rx0";
        reg = <0x4500000 0x1000>;
        power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        cdns_csi2rx: csi-bridge@4504000 {
            compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
            reg = <0x4504000 0x1000>;
            clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
              <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;
            clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
              "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
            phys = <&dphy0>;
            phy-names = "dphy";

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                csi2_0: port@0 {

                    reg = <0>;

                    csi2rx0_in_sensor: endpoint {
                        remote-endpoint = <&csi2_cam0>;
                        bus-type = <4>; /* CSI2 DPHY. */
                        clock-lanes = <0>;
                        data-lanes = <1 2>;
                    };
                };
            };
        };
    };