Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Freescale SEC (talitos) device register and descriptor header defines |
| 3 | * |
Kim Phillips | ad42d5f | 2011-11-21 16:13:27 +0800 | [diff] [blame] | 4 | * Copyright (c) 2006-2011 Freescale Semiconductor, Inc. |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * 3. The name of the author may not be used to endorse or promote products |
| 16 | * derived from this software without specific prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | * |
| 29 | */ |
| 30 | |
Horia Geanta | d1a0eb9 | 2012-07-03 19:16:51 +0300 | [diff] [blame] | 31 | #define TALITOS_TIMEOUT 100000 |
LEROY Christophe | 6f65f6a | 2015-04-17 16:32:15 +0200 | [diff] [blame] | 32 | #define TALITOS1_MAX_DATA_LEN 32768 |
| 33 | #define TALITOS2_MAX_DATA_LEN 65535 |
Horia Geanta | d1a0eb9 | 2012-07-03 19:16:51 +0300 | [diff] [blame] | 34 | |
| 35 | #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f) |
| 36 | #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf) |
| 37 | #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf) |
| 38 | |
| 39 | /* descriptor pointer entry */ |
| 40 | struct talitos_ptr { |
LEROY Christophe | 9049075 | 2015-04-17 16:32:01 +0200 | [diff] [blame] | 41 | union { |
| 42 | struct { /* SEC2 format */ |
| 43 | __be16 len; /* length */ |
| 44 | u8 j_extent; /* jump to sg link table and/or extent*/ |
| 45 | u8 eptr; /* extended address */ |
| 46 | }; |
| 47 | struct { /* SEC1 format */ |
| 48 | __be16 res; |
| 49 | __be16 len1; /* length */ |
| 50 | }; |
| 51 | }; |
Horia Geanta | d1a0eb9 | 2012-07-03 19:16:51 +0300 | [diff] [blame] | 52 | __be32 ptr; /* address */ |
| 53 | }; |
| 54 | |
Aaron Sierra | 76bea64 | 2015-08-03 18:56:21 -0500 | [diff] [blame] | 55 | static const struct talitos_ptr zero_entry; |
Horia Geanta | d1a0eb9 | 2012-07-03 19:16:51 +0300 | [diff] [blame] | 56 | |
| 57 | /* descriptor */ |
| 58 | struct talitos_desc { |
| 59 | __be32 hdr; /* header high bits */ |
LEROY Christophe | 9049075 | 2015-04-17 16:32:01 +0200 | [diff] [blame] | 60 | union { |
| 61 | __be32 hdr_lo; /* header low bits */ |
| 62 | __be32 hdr1; /* header for SEC1 */ |
| 63 | }; |
Horia Geanta | d1a0eb9 | 2012-07-03 19:16:51 +0300 | [diff] [blame] | 64 | struct talitos_ptr ptr[7]; /* ptr/len pair array */ |
LEROY Christophe | 9049075 | 2015-04-17 16:32:01 +0200 | [diff] [blame] | 65 | __be32 next_desc; /* next descriptor (SEC1) */ |
Horia Geanta | d1a0eb9 | 2012-07-03 19:16:51 +0300 | [diff] [blame] | 66 | }; |
| 67 | |
LEROY Christophe | 7d607c6a | 2015-04-17 16:32:09 +0200 | [diff] [blame] | 68 | #define TALITOS_DESC_SIZE (sizeof(struct talitos_desc) - sizeof(__be32)) |
| 69 | |
Horia Geanta | d1a0eb9 | 2012-07-03 19:16:51 +0300 | [diff] [blame] | 70 | /** |
| 71 | * talitos_request - descriptor submission request |
| 72 | * @desc: descriptor pointer (kernel virtual) |
| 73 | * @dma_desc: descriptor's physical bus address |
| 74 | * @callback: whom to call when descriptor processing is done |
| 75 | * @context: caller context (optional) |
| 76 | */ |
| 77 | struct talitos_request { |
| 78 | struct talitos_desc *desc; |
| 79 | dma_addr_t dma_desc; |
| 80 | void (*callback) (struct device *dev, struct talitos_desc *desc, |
| 81 | void *context, int error); |
| 82 | void *context; |
| 83 | }; |
| 84 | |
| 85 | /* per-channel fifo management */ |
| 86 | struct talitos_channel { |
| 87 | void __iomem *reg; |
| 88 | |
| 89 | /* request fifo */ |
| 90 | struct talitos_request *fifo; |
| 91 | |
| 92 | /* number of requests pending in channel h/w fifo */ |
| 93 | atomic_t submit_count ____cacheline_aligned; |
| 94 | |
| 95 | /* request submission (head) lock */ |
| 96 | spinlock_t head_lock ____cacheline_aligned; |
| 97 | /* index to next free descriptor request */ |
| 98 | int head; |
| 99 | |
| 100 | /* request release (tail) lock */ |
| 101 | spinlock_t tail_lock ____cacheline_aligned; |
| 102 | /* index to next in-progress/done descriptor request */ |
| 103 | int tail; |
| 104 | }; |
| 105 | |
| 106 | struct talitos_private { |
| 107 | struct device *dev; |
| 108 | struct platform_device *ofdev; |
| 109 | void __iomem *reg; |
LEROY Christophe | 5fa7fa1 | 2015-04-17 16:32:11 +0200 | [diff] [blame] | 110 | void __iomem *reg_deu; |
| 111 | void __iomem *reg_aesu; |
| 112 | void __iomem *reg_mdeu; |
| 113 | void __iomem *reg_afeu; |
| 114 | void __iomem *reg_rngu; |
| 115 | void __iomem *reg_pkeu; |
| 116 | void __iomem *reg_keu; |
| 117 | void __iomem *reg_crcu; |
Horia Geanta | d1a0eb9 | 2012-07-03 19:16:51 +0300 | [diff] [blame] | 118 | int irq[2]; |
| 119 | |
| 120 | /* SEC global registers lock */ |
| 121 | spinlock_t reg_lock ____cacheline_aligned; |
| 122 | |
| 123 | /* SEC version geometry (from device tree node) */ |
| 124 | unsigned int num_channels; |
| 125 | unsigned int chfifo_len; |
| 126 | unsigned int exec_units; |
| 127 | unsigned int desc_types; |
| 128 | |
| 129 | /* SEC Compatibility info */ |
| 130 | unsigned long features; |
| 131 | |
| 132 | /* |
| 133 | * length of the request fifo |
| 134 | * fifo_len is chfifo_len rounded up to next power of 2 |
| 135 | * so we can use bitwise ops to wrap |
| 136 | */ |
| 137 | unsigned int fifo_len; |
| 138 | |
| 139 | struct talitos_channel *chan; |
| 140 | |
| 141 | /* next channel to be assigned next incoming descriptor */ |
| 142 | atomic_t last_chan ____cacheline_aligned; |
| 143 | |
| 144 | /* request callback tasklet */ |
| 145 | struct tasklet_struct done_task[2]; |
| 146 | |
| 147 | /* list of registered algorithms */ |
| 148 | struct list_head alg_list; |
| 149 | |
| 150 | /* hwrng device */ |
| 151 | struct hwrng rng; |
Aaron Sierra | 35a3bb3 | 2015-08-05 16:52:08 -0500 | [diff] [blame] | 152 | bool rng_registered; |
Horia Geanta | d1a0eb9 | 2012-07-03 19:16:51 +0300 | [diff] [blame] | 153 | }; |
| 154 | |
Horia Geanta | 865d506 | 2012-07-03 19:16:52 +0300 | [diff] [blame] | 155 | extern int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc, |
| 156 | void (*callback)(struct device *dev, |
| 157 | struct talitos_desc *desc, |
| 158 | void *context, int error), |
| 159 | void *context); |
| 160 | |
Horia Geanta | d1a0eb9 | 2012-07-03 19:16:51 +0300 | [diff] [blame] | 161 | /* .features flag */ |
| 162 | #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001 |
| 163 | #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002 |
| 164 | #define TALITOS_FTR_SHA224_HWINIT 0x00000004 |
| 165 | #define TALITOS_FTR_HMAC_OK 0x00000008 |
LEROY Christophe | 2159088 | 2015-04-17 16:32:05 +0200 | [diff] [blame] | 166 | #define TALITOS_FTR_SEC1 0x00000010 |
| 167 | |
| 168 | /* |
| 169 | * If both CONFIG_CRYPTO_DEV_TALITOS1 and CONFIG_CRYPTO_DEV_TALITOS2 are |
| 170 | * defined, we check the features which are set according to the device tree. |
| 171 | * Otherwise, we answer true or false directly |
| 172 | */ |
| 173 | static inline bool has_ftr_sec1(struct talitos_private *priv) |
| 174 | { |
| 175 | #if defined(CONFIG_CRYPTO_DEV_TALITOS1) && defined(CONFIG_CRYPTO_DEV_TALITOS2) |
| 176 | return priv->features & TALITOS_FTR_SEC1 ? true : false; |
| 177 | #elif defined(CONFIG_CRYPTO_DEV_TALITOS1) |
| 178 | return true; |
| 179 | #else |
| 180 | return false; |
| 181 | #endif |
| 182 | } |
Horia Geanta | d1a0eb9 | 2012-07-03 19:16:51 +0300 | [diff] [blame] | 183 | |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 184 | /* |
| 185 | * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register |
| 186 | */ |
| 187 | |
LEROY Christophe | dd3c098 | 2015-04-17 16:32:13 +0200 | [diff] [blame] | 188 | #define ISR1_FORMAT(x) (((x) << 28) | ((x) << 16)) |
| 189 | #define ISR2_FORMAT(x) (((x) << 4) | (x)) |
| 190 | |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 191 | /* global register offset addresses */ |
| 192 | #define TALITOS_MCR 0x1030 /* master control register */ |
Kim Phillips | c3e337f | 2011-11-21 16:13:27 +0800 | [diff] [blame] | 193 | #define TALITOS_MCR_RCA0 (1 << 15) /* remap channel 0 */ |
| 194 | #define TALITOS_MCR_RCA1 (1 << 14) /* remap channel 1 */ |
| 195 | #define TALITOS_MCR_RCA2 (1 << 13) /* remap channel 2 */ |
| 196 | #define TALITOS_MCR_RCA3 (1 << 12) /* remap channel 3 */ |
LEROY Christophe | dd3c098 | 2015-04-17 16:32:13 +0200 | [diff] [blame] | 197 | #define TALITOS1_MCR_SWR 0x1000000 /* s/w reset */ |
| 198 | #define TALITOS2_MCR_SWR 0x1 /* s/w reset */ |
Kim Phillips | c3e337f | 2011-11-21 16:13:27 +0800 | [diff] [blame] | 199 | #define TALITOS_MCR_LO 0x1034 |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 200 | #define TALITOS_IMR 0x1008 /* interrupt mask register */ |
LEROY Christophe | dd3c098 | 2015-04-17 16:32:13 +0200 | [diff] [blame] | 201 | /* enable channel IRQs */ |
| 202 | #define TALITOS1_IMR_INIT ISR1_FORMAT(0xf) |
| 203 | #define TALITOS1_IMR_DONE ISR1_FORMAT(0x5) /* done IRQs */ |
| 204 | /* enable channel IRQs */ |
| 205 | #define TALITOS2_IMR_INIT (ISR2_FORMAT(0xf) | 0x10000) |
| 206 | #define TALITOS2_IMR_DONE ISR1_FORMAT(0x5) /* done IRQs */ |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 207 | #define TALITOS_IMR_LO 0x100C |
LEROY Christophe | dd3c098 | 2015-04-17 16:32:13 +0200 | [diff] [blame] | 208 | #define TALITOS1_IMR_LO_INIT 0x2000000 /* allow RNGU error IRQs */ |
| 209 | #define TALITOS2_IMR_LO_INIT 0x20000 /* allow RNGU error IRQs */ |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 210 | #define TALITOS_ISR 0x1010 /* interrupt status register */ |
LEROY Christophe | dd3c098 | 2015-04-17 16:32:13 +0200 | [diff] [blame] | 211 | #define TALITOS1_ISR_4CHERR ISR1_FORMAT(0xa) /* 4 ch errors mask */ |
| 212 | #define TALITOS1_ISR_4CHDONE ISR1_FORMAT(0x5) /* 4 ch done mask */ |
| 213 | #define TALITOS1_ISR_TEA_ERR 0x00000040 |
| 214 | #define TALITOS2_ISR_4CHERR ISR2_FORMAT(0xa) /* 4 ch errors mask */ |
| 215 | #define TALITOS2_ISR_4CHDONE ISR2_FORMAT(0x5) /* 4 ch done mask */ |
| 216 | #define TALITOS2_ISR_CH_0_2_ERR ISR2_FORMAT(0x2) /* ch 0, 2 err mask */ |
| 217 | #define TALITOS2_ISR_CH_0_2_DONE ISR2_FORMAT(0x1) /* ch 0, 2 done mask */ |
| 218 | #define TALITOS2_ISR_CH_1_3_ERR ISR2_FORMAT(0x8) /* ch 1, 3 err mask */ |
| 219 | #define TALITOS2_ISR_CH_1_3_DONE ISR2_FORMAT(0x4) /* ch 1, 3 done mask */ |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 220 | #define TALITOS_ISR_LO 0x1014 |
| 221 | #define TALITOS_ICR 0x1018 /* interrupt clear register */ |
| 222 | #define TALITOS_ICR_LO 0x101C |
| 223 | |
| 224 | /* channel register address stride */ |
Kim Phillips | ad42d5f | 2011-11-21 16:13:27 +0800 | [diff] [blame] | 225 | #define TALITOS_CH_BASE_OFFSET 0x1000 /* default channel map base */ |
LEROY Christophe | 5fa7fa1 | 2015-04-17 16:32:11 +0200 | [diff] [blame] | 226 | #define TALITOS1_CH_STRIDE 0x1000 |
| 227 | #define TALITOS2_CH_STRIDE 0x100 |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 228 | |
| 229 | /* channel configuration register */ |
Kim Phillips | ad42d5f | 2011-11-21 16:13:27 +0800 | [diff] [blame] | 230 | #define TALITOS_CCCR 0x8 |
LEROY Christophe | dd3c098 | 2015-04-17 16:32:13 +0200 | [diff] [blame] | 231 | #define TALITOS2_CCCR_CONT 0x2 /* channel continue on SEC2 */ |
| 232 | #define TALITOS2_CCCR_RESET 0x1 /* channel reset on SEC2 */ |
Kim Phillips | ad42d5f | 2011-11-21 16:13:27 +0800 | [diff] [blame] | 233 | #define TALITOS_CCCR_LO 0xc |
Kim Phillips | fe5720e | 2008-10-12 20:33:14 +0800 | [diff] [blame] | 234 | #define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */ |
Kim Phillips | 81eb024 | 2009-08-13 11:51:51 +1000 | [diff] [blame] | 235 | #define TALITOS_CCCR_LO_EAE 0x20 /* extended address enable */ |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 236 | #define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */ |
| 237 | #define TALITOS_CCCR_LO_NT 0x4 /* notification type */ |
| 238 | #define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */ |
LEROY Christophe | dd3c098 | 2015-04-17 16:32:13 +0200 | [diff] [blame] | 239 | #define TALITOS1_CCCR_LO_RESET 0x1 /* channel reset on SEC1 */ |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 240 | |
| 241 | /* CCPSR: channel pointer status register */ |
Kim Phillips | ad42d5f | 2011-11-21 16:13:27 +0800 | [diff] [blame] | 242 | #define TALITOS_CCPSR 0x10 |
| 243 | #define TALITOS_CCPSR_LO 0x14 |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 244 | #define TALITOS_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */ |
| 245 | #define TALITOS_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */ |
| 246 | #define TALITOS_CCPSR_LO_MDTE 0x2000 /* master data transfer error */ |
| 247 | #define TALITOS_CCPSR_LO_SGDLZ 0x1000 /* s/g data len zero error */ |
| 248 | #define TALITOS_CCPSR_LO_FPZ 0x0800 /* fetch ptr zero error */ |
| 249 | #define TALITOS_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */ |
| 250 | #define TALITOS_CCPSR_LO_IEU 0x0200 /* invalid EU error */ |
| 251 | #define TALITOS_CCPSR_LO_EU 0x0100 /* EU error detected */ |
| 252 | #define TALITOS_CCPSR_LO_GB 0x0080 /* gather boundary error */ |
| 253 | #define TALITOS_CCPSR_LO_GRL 0x0040 /* gather return/length error */ |
| 254 | #define TALITOS_CCPSR_LO_SB 0x0020 /* scatter boundary error */ |
| 255 | #define TALITOS_CCPSR_LO_SRL 0x0010 /* scatter return/length error */ |
| 256 | |
| 257 | /* channel fetch fifo register */ |
Kim Phillips | ad42d5f | 2011-11-21 16:13:27 +0800 | [diff] [blame] | 258 | #define TALITOS_FF 0x48 |
| 259 | #define TALITOS_FF_LO 0x4c |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 260 | |
| 261 | /* current descriptor pointer register */ |
Kim Phillips | ad42d5f | 2011-11-21 16:13:27 +0800 | [diff] [blame] | 262 | #define TALITOS_CDPR 0x40 |
| 263 | #define TALITOS_CDPR_LO 0x44 |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 264 | |
| 265 | /* descriptor buffer register */ |
Kim Phillips | ad42d5f | 2011-11-21 16:13:27 +0800 | [diff] [blame] | 266 | #define TALITOS_DESCBUF 0x80 |
| 267 | #define TALITOS_DESCBUF_LO 0x84 |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 268 | |
| 269 | /* gather link table */ |
Kim Phillips | ad42d5f | 2011-11-21 16:13:27 +0800 | [diff] [blame] | 270 | #define TALITOS_GATHER 0xc0 |
| 271 | #define TALITOS_GATHER_LO 0xc4 |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 272 | |
| 273 | /* scatter link table */ |
Kim Phillips | ad42d5f | 2011-11-21 16:13:27 +0800 | [diff] [blame] | 274 | #define TALITOS_SCATTER 0xe0 |
| 275 | #define TALITOS_SCATTER_LO 0xe4 |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 276 | |
LEROY Christophe | 5fa7fa1 | 2015-04-17 16:32:11 +0200 | [diff] [blame] | 277 | /* execution unit registers base */ |
| 278 | #define TALITOS2_DEU 0x2000 |
| 279 | #define TALITOS2_AESU 0x4000 |
| 280 | #define TALITOS2_MDEU 0x6000 |
| 281 | #define TALITOS2_AFEU 0x8000 |
| 282 | #define TALITOS2_RNGU 0xa000 |
| 283 | #define TALITOS2_PKEU 0xc000 |
| 284 | #define TALITOS2_KEU 0xe000 |
| 285 | #define TALITOS2_CRCU 0xf000 |
| 286 | |
| 287 | #define TALITOS12_AESU 0x4000 |
| 288 | #define TALITOS12_DEU 0x5000 |
| 289 | #define TALITOS12_MDEU 0x6000 |
| 290 | |
| 291 | #define TALITOS10_AFEU 0x8000 |
| 292 | #define TALITOS10_DEU 0xa000 |
| 293 | #define TALITOS10_MDEU 0xc000 |
| 294 | #define TALITOS10_RNGU 0xe000 |
| 295 | #define TALITOS10_PKEU 0x10000 |
| 296 | #define TALITOS10_AESU 0x12000 |
| 297 | |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 298 | /* execution unit interrupt status registers */ |
LEROY Christophe | 5fa7fa1 | 2015-04-17 16:32:11 +0200 | [diff] [blame] | 299 | #define TALITOS_EUDSR 0x10 /* data size */ |
| 300 | #define TALITOS_EUDSR_LO 0x14 |
| 301 | #define TALITOS_EURCR 0x18 /* reset control*/ |
| 302 | #define TALITOS_EURCR_LO 0x1c |
| 303 | #define TALITOS_EUSR 0x28 /* rng status */ |
| 304 | #define TALITOS_EUSR_LO 0x2c |
| 305 | #define TALITOS_EUISR 0x30 |
| 306 | #define TALITOS_EUISR_LO 0x34 |
| 307 | #define TALITOS_EUICR 0x38 /* int. control */ |
| 308 | #define TALITOS_EUICR_LO 0x3c |
| 309 | #define TALITOS_EU_FIFO 0x800 /* output FIFO */ |
| 310 | #define TALITOS_EU_FIFO_LO 0x804 /* output FIFO */ |
LEROY Christophe | dd3c098 | 2015-04-17 16:32:13 +0200 | [diff] [blame] | 311 | /* DES unit */ |
| 312 | #define TALITOS1_DEUICR_KPE 0x00200000 /* Key Parity Error */ |
LEROY Christophe | 5fa7fa1 | 2015-04-17 16:32:11 +0200 | [diff] [blame] | 313 | /* message digest unit */ |
Kim Phillips | fe5720e | 2008-10-12 20:33:14 +0800 | [diff] [blame] | 314 | #define TALITOS_MDEUICR_LO_ICE 0x4000 /* integrity check IRQ enable */ |
LEROY Christophe | 5fa7fa1 | 2015-04-17 16:32:11 +0200 | [diff] [blame] | 315 | /* random number unit */ |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 316 | #define TALITOS_RNGUSR_LO_RD 0x1 /* reset done */ |
| 317 | #define TALITOS_RNGUSR_LO_OFL 0xff0000/* output FIFO length */ |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 318 | #define TALITOS_RNGURCR_LO_SR 0x1 /* software reset */ |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 319 | |
Lee Nipper | 497f2e6 | 2010-05-19 19:20:36 +1000 | [diff] [blame] | 320 | #define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 0x28 |
| 321 | #define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512 0x48 |
| 322 | |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 323 | /* |
| 324 | * talitos descriptor header (hdr) bits |
| 325 | */ |
| 326 | |
| 327 | /* written back when done */ |
Harvey Harrison | dad3df2 | 2008-11-28 20:49:19 +0800 | [diff] [blame] | 328 | #define DESC_HDR_DONE cpu_to_be32(0xff000000) |
| 329 | #define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000) |
| 330 | #define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000) |
| 331 | #define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000) |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 332 | |
| 333 | /* primary execution unit select */ |
Harvey Harrison | dad3df2 | 2008-11-28 20:49:19 +0800 | [diff] [blame] | 334 | #define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000) |
| 335 | #define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000) |
| 336 | #define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000) |
| 337 | #define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000) |
| 338 | #define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000) |
| 339 | #define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000) |
| 340 | #define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000) |
| 341 | #define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000) |
| 342 | #define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000) |
| 343 | #define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000) |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 344 | |
| 345 | /* primary execution unit mode (MODE0) and derivatives */ |
Harvey Harrison | dad3df2 | 2008-11-28 20:49:19 +0800 | [diff] [blame] | 346 | #define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000) |
| 347 | #define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000) |
| 348 | #define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000) |
| 349 | #define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000) |
Lee Nipper | 497f2e6 | 2010-05-19 19:20:36 +1000 | [diff] [blame] | 350 | #define DESC_HDR_MODE0_MDEU_CONT cpu_to_be32(0x08000000) |
Harvey Harrison | dad3df2 | 2008-11-28 20:49:19 +0800 | [diff] [blame] | 351 | #define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000) |
| 352 | #define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000) |
| 353 | #define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000) |
Kim Phillips | 60f208d7 | 2010-05-19 19:21:53 +1000 | [diff] [blame] | 354 | #define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000) |
Harvey Harrison | dad3df2 | 2008-11-28 20:49:19 +0800 | [diff] [blame] | 355 | #define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000) |
| 356 | #define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000) |
| 357 | #define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000) |
Lee Nipper | 497f2e6 | 2010-05-19 19:20:36 +1000 | [diff] [blame] | 358 | #define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000) |
| 359 | #define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000) |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 360 | #define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \ |
| 361 | DESC_HDR_MODE0_MDEU_HMAC) |
| 362 | #define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \ |
| 363 | DESC_HDR_MODE0_MDEU_HMAC) |
| 364 | #define DESC_HDR_MODE0_MDEU_SHA1_HMAC (DESC_HDR_MODE0_MDEU_SHA1 | \ |
| 365 | DESC_HDR_MODE0_MDEU_HMAC) |
| 366 | |
| 367 | /* secondary execution unit select (SEL1) */ |
Harvey Harrison | dad3df2 | 2008-11-28 20:49:19 +0800 | [diff] [blame] | 368 | #define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000) |
| 369 | #define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000) |
| 370 | #define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000) |
| 371 | #define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000) |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 372 | |
| 373 | /* secondary execution unit mode (MODE1) and derivatives */ |
Harvey Harrison | dad3df2 | 2008-11-28 20:49:19 +0800 | [diff] [blame] | 374 | #define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000) |
| 375 | #define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000) |
| 376 | #define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800) |
| 377 | #define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400) |
Kim Phillips | 60f208d7 | 2010-05-19 19:21:53 +1000 | [diff] [blame] | 378 | #define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300) |
Harvey Harrison | dad3df2 | 2008-11-28 20:49:19 +0800 | [diff] [blame] | 379 | #define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200) |
| 380 | #define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100) |
| 381 | #define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000) |
Lee Nipper | 497f2e6 | 2010-05-19 19:20:36 +1000 | [diff] [blame] | 382 | #define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000) |
| 383 | #define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200) |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 384 | #define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \ |
| 385 | DESC_HDR_MODE1_MDEU_HMAC) |
| 386 | #define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \ |
| 387 | DESC_HDR_MODE1_MDEU_HMAC) |
| 388 | #define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 | \ |
| 389 | DESC_HDR_MODE1_MDEU_HMAC) |
Horia Geanta | 357fb60 | 2012-07-03 19:16:53 +0300 | [diff] [blame] | 390 | #define DESC_HDR_MODE1_MDEU_SHA224_HMAC (DESC_HDR_MODE1_MDEU_SHA224 | \ |
| 391 | DESC_HDR_MODE1_MDEU_HMAC) |
| 392 | #define DESC_HDR_MODE1_MDEUB_SHA384_HMAC (DESC_HDR_MODE1_MDEUB_SHA384 | \ |
| 393 | DESC_HDR_MODE1_MDEU_HMAC) |
| 394 | #define DESC_HDR_MODE1_MDEUB_SHA512_HMAC (DESC_HDR_MODE1_MDEUB_SHA512 | \ |
| 395 | DESC_HDR_MODE1_MDEU_HMAC) |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 396 | |
| 397 | /* direction of overall data flow (DIR) */ |
Harvey Harrison | dad3df2 | 2008-11-28 20:49:19 +0800 | [diff] [blame] | 398 | #define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002) |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 399 | |
| 400 | /* request done notification (DN) */ |
Harvey Harrison | dad3df2 | 2008-11-28 20:49:19 +0800 | [diff] [blame] | 401 | #define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001) |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 402 | |
| 403 | /* descriptor types */ |
Harvey Harrison | dad3df2 | 2008-11-28 20:49:19 +0800 | [diff] [blame] | 404 | #define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3) |
| 405 | #define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3) |
| 406 | #define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3) |
| 407 | #define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3) |
Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame] | 408 | |
| 409 | /* link table extent field bits */ |
| 410 | #define DESC_PTR_LNKTBL_JUMP 0x80 |
| 411 | #define DESC_PTR_LNKTBL_RETURN 0x02 |
| 412 | #define DESC_PTR_LNKTBL_NEXT 0x01 |