Thomas Gleixner | 0376148 | 2019-05-28 09:57:24 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2 | /* |
Paul Gortmaker | adef9cf | 2019-01-13 13:36:35 -0500 | [diff] [blame] | 3 | * DB8500 PRCM Unit driver |
| 4 | * |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 5 | * Copyright (C) STMicroelectronics 2009 |
| 6 | * Copyright (C) ST-Ericsson SA 2010 |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 7 | * |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 8 | * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> |
| 9 | * Author: Sundar Iyer <sundar.iyer@stericsson.com> |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 10 | * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> |
| 11 | * |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 12 | * U8500 PRCM Unit interface driver |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 13 | */ |
Paul Gortmaker | adef9cf | 2019-01-13 13:36:35 -0500 | [diff] [blame] | 14 | #include <linux/init.h> |
| 15 | #include <linux/export.h> |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 16 | #include <linux/kernel.h> |
| 17 | #include <linux/delay.h> |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 18 | #include <linux/errno.h> |
| 19 | #include <linux/err.h> |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 20 | #include <linux/spinlock.h> |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 21 | #include <linux/io.h> |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 22 | #include <linux/slab.h> |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 23 | #include <linux/mutex.h> |
| 24 | #include <linux/completion.h> |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 25 | #include <linux/irq.h> |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 26 | #include <linux/jiffies.h> |
| 27 | #include <linux/bitops.h> |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 28 | #include <linux/fs.h> |
Lee Jones | d98a538 | 2013-04-09 20:52:58 +0100 | [diff] [blame] | 29 | #include <linux/of.h> |
Linus Walleij | 22fb3ad | 2019-10-26 23:47:32 +0200 | [diff] [blame] | 30 | #include <linux/of_address.h> |
Linus Walleij | f864c46 | 2014-02-04 00:35:56 +0100 | [diff] [blame] | 31 | #include <linux/of_irq.h> |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 32 | #include <linux/platform_device.h> |
| 33 | #include <linux/uaccess.h> |
| 34 | #include <linux/mfd/core.h> |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 35 | #include <linux/mfd/dbx500-prcmu.h> |
Lee Jones | 3a8e39c | 2012-07-06 12:46:23 +0200 | [diff] [blame] | 36 | #include <linux/mfd/abx500/ab8500.h> |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 37 | #include <linux/regulator/db8500-prcmu.h> |
| 38 | #include <linux/regulator/machine.h> |
Fabio Baltieri | b3aac62 | 2013-01-18 12:40:14 +0100 | [diff] [blame] | 39 | #include <linux/platform_data/ux500_wdt.h> |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 40 | #include "dbx500-prcmu-regs.h" |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 41 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 42 | /* Index of different voltages to be used when accessing AVSData */ |
| 43 | #define PRCM_AVS_BASE 0x2FC |
| 44 | #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0) |
| 45 | #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1) |
| 46 | #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2) |
| 47 | #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3) |
| 48 | #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4) |
| 49 | #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5) |
| 50 | #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6) |
| 51 | #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7) |
| 52 | #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8) |
| 53 | #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9) |
| 54 | #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA) |
| 55 | #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB) |
| 56 | #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC) |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 57 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 58 | #define PRCM_AVS_VOLTAGE 0 |
| 59 | #define PRCM_AVS_VOLTAGE_MASK 0x3f |
| 60 | #define PRCM_AVS_ISSLOWSTARTUP 6 |
| 61 | #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP) |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 62 | #define PRCM_AVS_ISMODEENABLE 7 |
| 63 | #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) |
| 64 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 65 | #define PRCM_BOOT_STATUS 0xFFF |
| 66 | #define PRCM_ROMCODE_A2P 0xFFE |
| 67 | #define PRCM_ROMCODE_P2A 0xFFD |
| 68 | #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */ |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 69 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 70 | #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */ |
| 71 | |
| 72 | #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */ |
| 73 | #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) |
| 74 | #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) |
| 75 | #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) |
| 76 | #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) |
| 77 | #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) |
| 78 | #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) |
| 79 | #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) |
| 80 | |
| 81 | /* Req Mailboxes */ |
| 82 | #define PRCM_REQ_MB0 0xFDC /* 12 bytes */ |
| 83 | #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */ |
| 84 | #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */ |
| 85 | #define PRCM_REQ_MB3 0xE4C /* 372 bytes */ |
| 86 | #define PRCM_REQ_MB4 0xE48 /* 4 bytes */ |
| 87 | #define PRCM_REQ_MB5 0xE44 /* 4 bytes */ |
| 88 | |
| 89 | /* Ack Mailboxes */ |
| 90 | #define PRCM_ACK_MB0 0xE08 /* 52 bytes */ |
| 91 | #define PRCM_ACK_MB1 0xE04 /* 4 bytes */ |
| 92 | #define PRCM_ACK_MB2 0xE00 /* 4 bytes */ |
| 93 | #define PRCM_ACK_MB3 0xDFC /* 4 bytes */ |
| 94 | #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */ |
| 95 | #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */ |
| 96 | |
| 97 | /* Mailbox 0 headers */ |
| 98 | #define MB0H_POWER_STATE_TRANS 0 |
| 99 | #define MB0H_CONFIG_WAKEUPS_EXE 1 |
| 100 | #define MB0H_READ_WAKEUP_ACK 3 |
| 101 | #define MB0H_CONFIG_WAKEUPS_SLEEP 4 |
| 102 | |
| 103 | #define MB0H_WAKEUP_EXE 2 |
| 104 | #define MB0H_WAKEUP_SLEEP 5 |
| 105 | |
| 106 | /* Mailbox 0 REQs */ |
| 107 | #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0) |
| 108 | #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1) |
| 109 | #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2) |
| 110 | #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3) |
| 111 | #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4) |
| 112 | #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8) |
| 113 | |
| 114 | /* Mailbox 0 ACKs */ |
| 115 | #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0) |
| 116 | #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1) |
| 117 | #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4) |
| 118 | #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8) |
| 119 | #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C) |
| 120 | #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20) |
| 121 | #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 |
| 122 | |
| 123 | /* Mailbox 1 headers */ |
| 124 | #define MB1H_ARM_APE_OPP 0x0 |
| 125 | #define MB1H_RESET_MODEM 0x2 |
| 126 | #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 |
| 127 | #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 |
| 128 | #define MB1H_RELEASE_USB_WAKEUP 0x5 |
Mattias Nilsson | a592c2e | 2011-08-12 10:27:41 +0200 | [diff] [blame] | 129 | #define MB1H_PLL_ON_OFF 0x6 |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 130 | |
| 131 | /* Mailbox 1 Requests */ |
| 132 | #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) |
| 133 | #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) |
Mattias Nilsson | a592c2e | 2011-08-12 10:27:41 +0200 | [diff] [blame] | 134 | #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 135 | #define PLL_SOC0_OFF 0x1 |
| 136 | #define PLL_SOC0_ON 0x2 |
Mattias Nilsson | a592c2e | 2011-08-12 10:27:41 +0200 | [diff] [blame] | 137 | #define PLL_SOC1_OFF 0x4 |
| 138 | #define PLL_SOC1_ON 0x8 |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 139 | |
| 140 | /* Mailbox 1 ACKs */ |
| 141 | #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) |
| 142 | #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1) |
| 143 | #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2) |
| 144 | #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) |
| 145 | |
| 146 | /* Mailbox 2 headers */ |
| 147 | #define MB2H_DPS 0x0 |
| 148 | #define MB2H_AUTO_PWR 0x1 |
| 149 | |
| 150 | /* Mailbox 2 REQs */ |
| 151 | #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0) |
| 152 | #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1) |
| 153 | #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2) |
| 154 | #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3) |
| 155 | #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4) |
| 156 | #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5) |
| 157 | #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6) |
| 158 | #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7) |
| 159 | #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8) |
| 160 | #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC) |
| 161 | |
| 162 | /* Mailbox 2 ACKs */ |
| 163 | #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) |
| 164 | #define HWACC_PWR_ST_OK 0xFE |
| 165 | |
| 166 | /* Mailbox 3 headers */ |
| 167 | #define MB3H_ANC 0x0 |
| 168 | #define MB3H_SIDETONE 0x1 |
| 169 | #define MB3H_SYSCLK 0xE |
| 170 | |
| 171 | /* Mailbox 3 Requests */ |
| 172 | #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0) |
| 173 | #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20) |
| 174 | #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60) |
| 175 | #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64) |
| 176 | #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68) |
| 177 | #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C) |
| 178 | #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C) |
| 179 | |
| 180 | /* Mailbox 4 headers */ |
| 181 | #define MB4H_DDR_INIT 0x0 |
| 182 | #define MB4H_MEM_ST 0x1 |
| 183 | #define MB4H_HOTDOG 0x12 |
| 184 | #define MB4H_HOTMON 0x13 |
| 185 | #define MB4H_HOT_PERIOD 0x14 |
Mattias Nilsson | a592c2e | 2011-08-12 10:27:41 +0200 | [diff] [blame] | 186 | #define MB4H_A9WDOG_CONF 0x16 |
| 187 | #define MB4H_A9WDOG_EN 0x17 |
| 188 | #define MB4H_A9WDOG_DIS 0x18 |
| 189 | #define MB4H_A9WDOG_LOAD 0x19 |
| 190 | #define MB4H_A9WDOG_KICK 0x20 |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 191 | |
| 192 | /* Mailbox 4 Requests */ |
| 193 | #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0) |
| 194 | #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1) |
| 195 | #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3) |
| 196 | #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0) |
| 197 | #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0) |
| 198 | #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1) |
| 199 | #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2) |
| 200 | #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0) |
| 201 | #define HOTMON_CONFIG_LOW BIT(0) |
| 202 | #define HOTMON_CONFIG_HIGH BIT(1) |
Mattias Nilsson | a592c2e | 2011-08-12 10:27:41 +0200 | [diff] [blame] | 203 | #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0) |
| 204 | #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1) |
| 205 | #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2) |
| 206 | #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3) |
| 207 | #define A9WDOG_AUTO_OFF_EN BIT(7) |
| 208 | #define A9WDOG_AUTO_OFF_DIS 0 |
| 209 | #define A9WDOG_ID_MASK 0xf |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 210 | |
| 211 | /* Mailbox 5 Requests */ |
| 212 | #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0) |
| 213 | #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) |
| 214 | #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) |
| 215 | #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) |
Linus Walleij | 7a4f260 | 2012-09-19 19:31:19 +0200 | [diff] [blame] | 216 | #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6)) |
| 217 | #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6)) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 218 | #define PRCMU_I2C_STOP_EN BIT(3) |
| 219 | |
| 220 | /* Mailbox 5 ACKs */ |
| 221 | #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1) |
| 222 | #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3) |
| 223 | #define I2C_WR_OK 0x1 |
| 224 | #define I2C_RD_OK 0x2 |
| 225 | |
| 226 | #define NUM_MB 8 |
| 227 | #define MBOX_BIT BIT |
| 228 | #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1) |
| 229 | |
| 230 | /* |
| 231 | * Wakeups/IRQs |
| 232 | */ |
| 233 | |
| 234 | #define WAKEUP_BIT_RTC BIT(0) |
| 235 | #define WAKEUP_BIT_RTT0 BIT(1) |
| 236 | #define WAKEUP_BIT_RTT1 BIT(2) |
| 237 | #define WAKEUP_BIT_HSI0 BIT(3) |
| 238 | #define WAKEUP_BIT_HSI1 BIT(4) |
| 239 | #define WAKEUP_BIT_CA_WAKE BIT(5) |
| 240 | #define WAKEUP_BIT_USB BIT(6) |
| 241 | #define WAKEUP_BIT_ABB BIT(7) |
| 242 | #define WAKEUP_BIT_ABB_FIFO BIT(8) |
| 243 | #define WAKEUP_BIT_SYSCLK_OK BIT(9) |
| 244 | #define WAKEUP_BIT_CA_SLEEP BIT(10) |
| 245 | #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) |
| 246 | #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) |
| 247 | #define WAKEUP_BIT_ANC_OK BIT(13) |
| 248 | #define WAKEUP_BIT_SW_ERROR BIT(14) |
| 249 | #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) |
| 250 | #define WAKEUP_BIT_ARM BIT(17) |
| 251 | #define WAKEUP_BIT_HOTMON_LOW BIT(18) |
| 252 | #define WAKEUP_BIT_HOTMON_HIGH BIT(19) |
| 253 | #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) |
| 254 | #define WAKEUP_BIT_GPIO0 BIT(23) |
| 255 | #define WAKEUP_BIT_GPIO1 BIT(24) |
| 256 | #define WAKEUP_BIT_GPIO2 BIT(25) |
| 257 | #define WAKEUP_BIT_GPIO3 BIT(26) |
| 258 | #define WAKEUP_BIT_GPIO4 BIT(27) |
| 259 | #define WAKEUP_BIT_GPIO5 BIT(28) |
| 260 | #define WAKEUP_BIT_GPIO6 BIT(29) |
| 261 | #define WAKEUP_BIT_GPIO7 BIT(30) |
| 262 | #define WAKEUP_BIT_GPIO8 BIT(31) |
| 263 | |
Mattias Nilsson | b58d12f | 2012-01-13 16:20:10 +0100 | [diff] [blame] | 264 | static struct { |
| 265 | bool valid; |
| 266 | struct prcmu_fw_version version; |
| 267 | } fw_info; |
| 268 | |
Lee Jones | f3f1f0a | 2012-09-24 09:11:46 +0100 | [diff] [blame] | 269 | static struct irq_domain *db8500_irq_domain; |
| 270 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 271 | /* |
| 272 | * This vector maps irq numbers to the bits in the bit field used in |
| 273 | * communication with the PRCMU firmware. |
| 274 | * |
| 275 | * The reason for having this is to keep the irq numbers contiguous even though |
| 276 | * the bits in the bit field are not. (The bits also have a tendency to move |
| 277 | * around, to further complicate matters.) |
| 278 | */ |
Arnd Bergmann | 55b175d | 2013-03-21 22:51:07 +0100 | [diff] [blame] | 279 | #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name)) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 280 | #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) |
Arnd Bergmann | 55b175d | 2013-03-21 22:51:07 +0100 | [diff] [blame] | 281 | |
| 282 | #define IRQ_PRCMU_RTC 0 |
| 283 | #define IRQ_PRCMU_RTT0 1 |
| 284 | #define IRQ_PRCMU_RTT1 2 |
| 285 | #define IRQ_PRCMU_HSI0 3 |
| 286 | #define IRQ_PRCMU_HSI1 4 |
| 287 | #define IRQ_PRCMU_CA_WAKE 5 |
| 288 | #define IRQ_PRCMU_USB 6 |
| 289 | #define IRQ_PRCMU_ABB 7 |
| 290 | #define IRQ_PRCMU_ABB_FIFO 8 |
| 291 | #define IRQ_PRCMU_ARM 9 |
| 292 | #define IRQ_PRCMU_MODEM_SW_RESET_REQ 10 |
| 293 | #define IRQ_PRCMU_GPIO0 11 |
| 294 | #define IRQ_PRCMU_GPIO1 12 |
| 295 | #define IRQ_PRCMU_GPIO2 13 |
| 296 | #define IRQ_PRCMU_GPIO3 14 |
| 297 | #define IRQ_PRCMU_GPIO4 15 |
| 298 | #define IRQ_PRCMU_GPIO5 16 |
| 299 | #define IRQ_PRCMU_GPIO6 17 |
| 300 | #define IRQ_PRCMU_GPIO7 18 |
| 301 | #define IRQ_PRCMU_GPIO8 19 |
| 302 | #define IRQ_PRCMU_CA_SLEEP 20 |
| 303 | #define IRQ_PRCMU_HOTMON_LOW 21 |
| 304 | #define IRQ_PRCMU_HOTMON_HIGH 22 |
| 305 | #define NUM_PRCMU_WAKEUPS 23 |
| 306 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 307 | static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { |
| 308 | IRQ_ENTRY(RTC), |
| 309 | IRQ_ENTRY(RTT0), |
| 310 | IRQ_ENTRY(RTT1), |
| 311 | IRQ_ENTRY(HSI0), |
| 312 | IRQ_ENTRY(HSI1), |
| 313 | IRQ_ENTRY(CA_WAKE), |
| 314 | IRQ_ENTRY(USB), |
| 315 | IRQ_ENTRY(ABB), |
| 316 | IRQ_ENTRY(ABB_FIFO), |
| 317 | IRQ_ENTRY(CA_SLEEP), |
| 318 | IRQ_ENTRY(ARM), |
| 319 | IRQ_ENTRY(HOTMON_LOW), |
| 320 | IRQ_ENTRY(HOTMON_HIGH), |
| 321 | IRQ_ENTRY(MODEM_SW_RESET_REQ), |
| 322 | IRQ_ENTRY(GPIO0), |
| 323 | IRQ_ENTRY(GPIO1), |
| 324 | IRQ_ENTRY(GPIO2), |
| 325 | IRQ_ENTRY(GPIO3), |
| 326 | IRQ_ENTRY(GPIO4), |
| 327 | IRQ_ENTRY(GPIO5), |
| 328 | IRQ_ENTRY(GPIO6), |
| 329 | IRQ_ENTRY(GPIO7), |
| 330 | IRQ_ENTRY(GPIO8) |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 331 | }; |
| 332 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 333 | #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) |
| 334 | #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name) |
| 335 | static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = { |
| 336 | WAKEUP_ENTRY(RTC), |
| 337 | WAKEUP_ENTRY(RTT0), |
| 338 | WAKEUP_ENTRY(RTT1), |
| 339 | WAKEUP_ENTRY(HSI0), |
| 340 | WAKEUP_ENTRY(HSI1), |
| 341 | WAKEUP_ENTRY(USB), |
| 342 | WAKEUP_ENTRY(ABB), |
| 343 | WAKEUP_ENTRY(ABB_FIFO), |
| 344 | WAKEUP_ENTRY(ARM) |
| 345 | }; |
| 346 | |
| 347 | /* |
| 348 | * mb0_transfer - state needed for mailbox 0 communication. |
| 349 | * @lock: The transaction lock. |
| 350 | * @dbb_events_lock: A lock used to handle concurrent access to (parts of) |
| 351 | * the request data. |
| 352 | * @mask_work: Work structure used for (un)masking wakeup interrupts. |
| 353 | * @req: Request data that need to persist between requests. |
| 354 | */ |
| 355 | static struct { |
| 356 | spinlock_t lock; |
| 357 | spinlock_t dbb_irqs_lock; |
| 358 | struct work_struct mask_work; |
| 359 | struct mutex ac_wake_lock; |
| 360 | struct completion ac_wake_work; |
| 361 | struct { |
| 362 | u32 dbb_irqs; |
| 363 | u32 dbb_wakeups; |
| 364 | u32 abb_events; |
| 365 | } req; |
| 366 | } mb0_transfer; |
| 367 | |
| 368 | /* |
| 369 | * mb1_transfer - state needed for mailbox 1 communication. |
| 370 | * @lock: The transaction lock. |
| 371 | * @work: The transaction completion structure. |
Mattias Nilsson | 4d64d2e | 2012-01-13 16:20:43 +0100 | [diff] [blame] | 372 | * @ape_opp: The current APE OPP. |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 373 | * @ack: Reply ("acknowledge") data. |
| 374 | */ |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 375 | static struct { |
| 376 | struct mutex lock; |
| 377 | struct completion work; |
Mattias Nilsson | 4d64d2e | 2012-01-13 16:20:43 +0100 | [diff] [blame] | 378 | u8 ape_opp; |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 379 | struct { |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 380 | u8 header; |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 381 | u8 arm_opp; |
| 382 | u8 ape_opp; |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 383 | u8 ape_voltage_status; |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 384 | } ack; |
| 385 | } mb1_transfer; |
| 386 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 387 | /* |
| 388 | * mb2_transfer - state needed for mailbox 2 communication. |
| 389 | * @lock: The transaction lock. |
| 390 | * @work: The transaction completion structure. |
| 391 | * @auto_pm_lock: The autonomous power management configuration lock. |
| 392 | * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled. |
| 393 | * @req: Request data that need to persist between requests. |
| 394 | * @ack: Reply ("acknowledge") data. |
| 395 | */ |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 396 | static struct { |
| 397 | struct mutex lock; |
| 398 | struct completion work; |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 399 | spinlock_t auto_pm_lock; |
| 400 | bool auto_pm_enabled; |
| 401 | struct { |
| 402 | u8 status; |
| 403 | } ack; |
| 404 | } mb2_transfer; |
| 405 | |
| 406 | /* |
| 407 | * mb3_transfer - state needed for mailbox 3 communication. |
| 408 | * @lock: The request lock. |
| 409 | * @sysclk_lock: A lock used to handle concurrent sysclk requests. |
| 410 | * @sysclk_work: Work structure used for sysclk requests. |
| 411 | */ |
| 412 | static struct { |
| 413 | spinlock_t lock; |
| 414 | struct mutex sysclk_lock; |
| 415 | struct completion sysclk_work; |
| 416 | } mb3_transfer; |
| 417 | |
| 418 | /* |
| 419 | * mb4_transfer - state needed for mailbox 4 communication. |
| 420 | * @lock: The transaction lock. |
| 421 | * @work: The transaction completion structure. |
| 422 | */ |
| 423 | static struct { |
| 424 | struct mutex lock; |
| 425 | struct completion work; |
| 426 | } mb4_transfer; |
| 427 | |
| 428 | /* |
| 429 | * mb5_transfer - state needed for mailbox 5 communication. |
| 430 | * @lock: The transaction lock. |
| 431 | * @work: The transaction completion structure. |
| 432 | * @ack: Reply ("acknowledge") data. |
| 433 | */ |
| 434 | static struct { |
| 435 | struct mutex lock; |
| 436 | struct completion work; |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 437 | struct { |
| 438 | u8 status; |
| 439 | u8 value; |
| 440 | } ack; |
| 441 | } mb5_transfer; |
| 442 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 443 | static atomic_t ac_wake_req_state = ATOMIC_INIT(0); |
| 444 | |
| 445 | /* Spinlocks */ |
Mattias Nilsson | b4a6dbd | 2012-01-13 16:21:00 +0100 | [diff] [blame] | 446 | static DEFINE_SPINLOCK(prcmu_lock); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 447 | static DEFINE_SPINLOCK(clkout_lock); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 448 | |
| 449 | /* Global var to runtime determine TCDM base for v2 or v1 */ |
| 450 | static __iomem void *tcdm_base; |
Linus Walleij | b047d98 | 2013-03-19 14:21:47 +0100 | [diff] [blame] | 451 | static __iomem void *prcmu_base; |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 452 | |
| 453 | struct clk_mgt { |
Linus Walleij | b047d98 | 2013-03-19 14:21:47 +0100 | [diff] [blame] | 454 | u32 offset; |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 455 | u32 pllsw; |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 456 | int branch; |
| 457 | bool clk38div; |
| 458 | }; |
| 459 | |
| 460 | enum { |
| 461 | PLL_RAW, |
| 462 | PLL_FIX, |
| 463 | PLL_DIV |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 464 | }; |
| 465 | |
| 466 | static DEFINE_SPINLOCK(clk_mgt_lock); |
| 467 | |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 468 | #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \ |
| 469 | { (PRCM_##_name##_MGT), 0 , _branch, _clk38div} |
Sachin Kamat | 6746f23 | 2013-08-23 17:05:20 +0530 | [diff] [blame] | 470 | static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 471 | CLK_MGT_ENTRY(SGACLK, PLL_DIV, false), |
| 472 | CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true), |
| 473 | CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true), |
| 474 | CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true), |
| 475 | CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true), |
| 476 | CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true), |
| 477 | CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true), |
| 478 | CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true), |
| 479 | CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true), |
| 480 | CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true), |
| 481 | CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true), |
| 482 | CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), |
| 483 | CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), |
| 484 | CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), |
| 485 | CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), |
| 486 | CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), |
| 487 | CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), |
| 488 | CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false), |
| 489 | CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true), |
| 490 | CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true), |
| 491 | CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true), |
| 492 | CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true), |
| 493 | CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false), |
| 494 | CLK_MGT_ENTRY(DMACLK, PLL_DIV, true), |
| 495 | CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true), |
| 496 | CLK_MGT_ENTRY(TVCLK, PLL_FIX, true), |
| 497 | CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true), |
| 498 | CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true), |
| 499 | CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false), |
| 500 | }; |
| 501 | |
| 502 | struct dsiclk { |
| 503 | u32 divsel_mask; |
| 504 | u32 divsel_shift; |
| 505 | u32 divsel; |
| 506 | }; |
| 507 | |
| 508 | static struct dsiclk dsiclk[2] = { |
| 509 | { |
| 510 | .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK, |
| 511 | .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT, |
| 512 | .divsel = PRCM_DSI_PLLOUT_SEL_PHI, |
| 513 | }, |
| 514 | { |
| 515 | .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK, |
| 516 | .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT, |
| 517 | .divsel = PRCM_DSI_PLLOUT_SEL_PHI, |
| 518 | } |
| 519 | }; |
| 520 | |
| 521 | struct dsiescclk { |
| 522 | u32 en; |
| 523 | u32 div_mask; |
| 524 | u32 div_shift; |
| 525 | }; |
| 526 | |
| 527 | static struct dsiescclk dsiescclk[3] = { |
| 528 | { |
| 529 | .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN, |
| 530 | .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK, |
| 531 | .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT, |
| 532 | }, |
| 533 | { |
| 534 | .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN, |
| 535 | .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK, |
| 536 | .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT, |
| 537 | }, |
| 538 | { |
| 539 | .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN, |
| 540 | .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK, |
| 541 | .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT, |
| 542 | } |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 543 | }; |
| 544 | |
Mattias Nilsson | b4a6dbd | 2012-01-13 16:21:00 +0100 | [diff] [blame] | 545 | u32 db8500_prcmu_read(unsigned int reg) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 546 | { |
Linus Walleij | b047d98 | 2013-03-19 14:21:47 +0100 | [diff] [blame] | 547 | return readl(prcmu_base + reg); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 548 | } |
| 549 | |
Mattias Nilsson | b4a6dbd | 2012-01-13 16:21:00 +0100 | [diff] [blame] | 550 | void db8500_prcmu_write(unsigned int reg, u32 value) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 551 | { |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 552 | unsigned long flags; |
| 553 | |
Mattias Nilsson | b4a6dbd | 2012-01-13 16:21:00 +0100 | [diff] [blame] | 554 | spin_lock_irqsave(&prcmu_lock, flags); |
Linus Walleij | b047d98 | 2013-03-19 14:21:47 +0100 | [diff] [blame] | 555 | writel(value, (prcmu_base + reg)); |
Mattias Nilsson | b4a6dbd | 2012-01-13 16:21:00 +0100 | [diff] [blame] | 556 | spin_unlock_irqrestore(&prcmu_lock, flags); |
| 557 | } |
| 558 | |
| 559 | void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value) |
| 560 | { |
| 561 | u32 val; |
| 562 | unsigned long flags; |
| 563 | |
| 564 | spin_lock_irqsave(&prcmu_lock, flags); |
Linus Walleij | b047d98 | 2013-03-19 14:21:47 +0100 | [diff] [blame] | 565 | val = readl(prcmu_base + reg); |
Mattias Nilsson | b4a6dbd | 2012-01-13 16:21:00 +0100 | [diff] [blame] | 566 | val = ((val & ~mask) | (value & mask)); |
Linus Walleij | b047d98 | 2013-03-19 14:21:47 +0100 | [diff] [blame] | 567 | writel(val, (prcmu_base + reg)); |
Mattias Nilsson | b4a6dbd | 2012-01-13 16:21:00 +0100 | [diff] [blame] | 568 | spin_unlock_irqrestore(&prcmu_lock, flags); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 569 | } |
| 570 | |
Mattias Nilsson | b58d12f | 2012-01-13 16:20:10 +0100 | [diff] [blame] | 571 | struct prcmu_fw_version *prcmu_get_fw_version(void) |
| 572 | { |
| 573 | return fw_info.valid ? &fw_info.version : NULL; |
| 574 | } |
| 575 | |
Linus Walleij | 22fb3ad | 2019-10-26 23:47:32 +0200 | [diff] [blame] | 576 | static bool prcmu_is_ulppll_disabled(void) |
| 577 | { |
| 578 | struct prcmu_fw_version *ver; |
| 579 | |
| 580 | ver = prcmu_get_fw_version(); |
| 581 | return ver && ver->project == PRCMU_FW_PROJECT_U8420_SYSCLK; |
| 582 | } |
| 583 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 584 | bool prcmu_has_arm_maxopp(void) |
| 585 | { |
| 586 | return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & |
| 587 | PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; |
| 588 | } |
| 589 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 590 | /** |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 591 | * prcmu_set_rc_a2p - This function is used to run few power state sequences |
| 592 | * @val: Value to be set, i.e. transition requested |
| 593 | * Returns: 0 on success, -EINVAL on invalid argument |
| 594 | * |
| 595 | * This function is used to run the following power state sequences - |
| 596 | * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep |
| 597 | */ |
| 598 | int prcmu_set_rc_a2p(enum romcode_write val) |
| 599 | { |
| 600 | if (val < RDY_2_DS || val > RDY_2_XP70_RST) |
| 601 | return -EINVAL; |
| 602 | writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); |
| 603 | return 0; |
| 604 | } |
| 605 | |
| 606 | /** |
| 607 | * prcmu_get_rc_p2a - This function is used to get power state sequences |
| 608 | * Returns: the power transition that has last happened |
| 609 | * |
| 610 | * This function can return the following transitions- |
| 611 | * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep |
| 612 | */ |
| 613 | enum romcode_read prcmu_get_rc_p2a(void) |
| 614 | { |
| 615 | return readb(tcdm_base + PRCM_ROMCODE_P2A); |
| 616 | } |
| 617 | |
| 618 | /** |
| 619 | * prcmu_get_current_mode - Return the current XP70 power mode |
| 620 | * Returns: Returns the current AP(ARM) power mode: init, |
| 621 | * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset |
| 622 | */ |
| 623 | enum ap_pwrst prcmu_get_xp70_current_state(void) |
| 624 | { |
| 625 | return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); |
| 626 | } |
| 627 | |
| 628 | /** |
| 629 | * prcmu_config_clkout - Configure one of the programmable clock outputs. |
| 630 | * @clkout: The CLKOUT number (0 or 1). |
| 631 | * @source: The clock to be used (one of the PRCMU_CLKSRC_*). |
| 632 | * @div: The divider to be applied. |
| 633 | * |
| 634 | * Configures one of the programmable clock outputs (CLKOUTs). |
| 635 | * @div should be in the range [1,63] to request a configuration, or 0 to |
| 636 | * inform that the configuration is no longer requested. |
| 637 | */ |
| 638 | int prcmu_config_clkout(u8 clkout, u8 source, u8 div) |
| 639 | { |
| 640 | static int requests[2]; |
| 641 | int r = 0; |
| 642 | unsigned long flags; |
| 643 | u32 val; |
| 644 | u32 bits; |
| 645 | u32 mask; |
| 646 | u32 div_mask; |
| 647 | |
| 648 | BUG_ON(clkout > 1); |
| 649 | BUG_ON(div > 63); |
| 650 | BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009)); |
| 651 | |
| 652 | if (!div && !requests[clkout]) |
| 653 | return -EINVAL; |
| 654 | |
Arnd Bergmann | a7e4631 | 2016-01-25 17:02:24 +0100 | [diff] [blame] | 655 | if (clkout == 0) { |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 656 | div_mask = PRCM_CLKOCR_CLKODIV0_MASK; |
| 657 | mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); |
| 658 | bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) | |
| 659 | (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); |
Arnd Bergmann | a7e4631 | 2016-01-25 17:02:24 +0100 | [diff] [blame] | 660 | } else { |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 661 | div_mask = PRCM_CLKOCR_CLKODIV1_MASK; |
| 662 | mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | |
| 663 | PRCM_CLKOCR_CLK1TYPE); |
| 664 | bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) | |
| 665 | (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 666 | } |
| 667 | bits &= mask; |
| 668 | |
| 669 | spin_lock_irqsave(&clkout_lock, flags); |
| 670 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 671 | val = readl(PRCM_CLKOCR); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 672 | if (val & div_mask) { |
| 673 | if (div) { |
| 674 | if ((val & mask) != bits) { |
| 675 | r = -EBUSY; |
| 676 | goto unlock_and_return; |
| 677 | } |
| 678 | } else { |
| 679 | if ((val & mask & ~div_mask) != bits) { |
| 680 | r = -EINVAL; |
| 681 | goto unlock_and_return; |
| 682 | } |
| 683 | } |
| 684 | } |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 685 | writel((bits | (val & ~mask)), PRCM_CLKOCR); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 686 | requests[clkout] += (div ? 1 : -1); |
| 687 | |
| 688 | unlock_and_return: |
| 689 | spin_unlock_irqrestore(&clkout_lock, flags); |
| 690 | |
| 691 | return r; |
| 692 | } |
| 693 | |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 694 | int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 695 | { |
| 696 | unsigned long flags; |
| 697 | |
| 698 | BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state)); |
| 699 | |
| 700 | spin_lock_irqsave(&mb0_transfer.lock, flags); |
| 701 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 702 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 703 | cpu_relax(); |
| 704 | |
| 705 | writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); |
| 706 | writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); |
| 707 | writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); |
| 708 | writeb((keep_ulp_clk ? 1 : 0), |
| 709 | (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); |
| 710 | writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 711 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 712 | |
| 713 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); |
| 714 | |
| 715 | return 0; |
| 716 | } |
| 717 | |
Mattias Nilsson | 4d64d2e | 2012-01-13 16:20:43 +0100 | [diff] [blame] | 718 | u8 db8500_prcmu_get_power_state_result(void) |
| 719 | { |
| 720 | return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS); |
| 721 | } |
| 722 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 723 | /* This function should only be called while mb0_transfer.lock is held. */ |
| 724 | static void config_wakeups(void) |
| 725 | { |
| 726 | const u8 header[2] = { |
| 727 | MB0H_CONFIG_WAKEUPS_EXE, |
| 728 | MB0H_CONFIG_WAKEUPS_SLEEP |
| 729 | }; |
| 730 | static u32 last_dbb_events; |
| 731 | static u32 last_abb_events; |
| 732 | u32 dbb_events; |
| 733 | u32 abb_events; |
| 734 | unsigned int i; |
| 735 | |
| 736 | dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups; |
| 737 | dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK); |
| 738 | |
| 739 | abb_events = mb0_transfer.req.abb_events; |
| 740 | |
| 741 | if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events)) |
| 742 | return; |
| 743 | |
| 744 | for (i = 0; i < 2; i++) { |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 745 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 746 | cpu_relax(); |
| 747 | writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); |
| 748 | writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); |
| 749 | writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 750 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 751 | } |
| 752 | last_dbb_events = dbb_events; |
| 753 | last_abb_events = abb_events; |
| 754 | } |
| 755 | |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 756 | void db8500_prcmu_enable_wakeups(u32 wakeups) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 757 | { |
| 758 | unsigned long flags; |
| 759 | u32 bits; |
| 760 | int i; |
| 761 | |
| 762 | BUG_ON(wakeups != (wakeups & VALID_WAKEUPS)); |
| 763 | |
| 764 | for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) { |
| 765 | if (wakeups & BIT(i)) |
| 766 | bits |= prcmu_wakeup_bit[i]; |
| 767 | } |
| 768 | |
| 769 | spin_lock_irqsave(&mb0_transfer.lock, flags); |
| 770 | |
| 771 | mb0_transfer.req.dbb_wakeups = bits; |
| 772 | config_wakeups(); |
| 773 | |
| 774 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); |
| 775 | } |
| 776 | |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 777 | void db8500_prcmu_config_abb_event_readout(u32 abb_events) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 778 | { |
| 779 | unsigned long flags; |
| 780 | |
| 781 | spin_lock_irqsave(&mb0_transfer.lock, flags); |
| 782 | |
| 783 | mb0_transfer.req.abb_events = abb_events; |
| 784 | config_wakeups(); |
| 785 | |
| 786 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); |
| 787 | } |
| 788 | |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 789 | void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 790 | { |
| 791 | if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) |
| 792 | *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); |
| 793 | else |
| 794 | *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); |
| 795 | } |
| 796 | |
| 797 | /** |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 798 | * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 799 | * @opp: The new ARM operating point to which transition is to be made |
| 800 | * Returns: 0 on success, non-zero on failure |
| 801 | * |
| 802 | * This function sets the the operating point of the ARM. |
| 803 | */ |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 804 | int db8500_prcmu_set_arm_opp(u8 opp) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 805 | { |
| 806 | int r; |
| 807 | |
| 808 | if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) |
| 809 | return -EINVAL; |
| 810 | |
| 811 | r = 0; |
| 812 | |
| 813 | mutex_lock(&mb1_transfer.lock); |
| 814 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 815 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 816 | cpu_relax(); |
| 817 | |
| 818 | writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); |
| 819 | writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); |
| 820 | writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); |
| 821 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 822 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 823 | wait_for_completion(&mb1_transfer.work); |
| 824 | |
| 825 | if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || |
| 826 | (mb1_transfer.ack.arm_opp != opp)) |
| 827 | r = -EIO; |
| 828 | |
| 829 | mutex_unlock(&mb1_transfer.lock); |
| 830 | |
| 831 | return r; |
| 832 | } |
| 833 | |
| 834 | /** |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 835 | * db8500_prcmu_get_arm_opp - get the current ARM OPP |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 836 | * |
| 837 | * Returns: the current ARM OPP |
| 838 | */ |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 839 | int db8500_prcmu_get_arm_opp(void) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 840 | { |
| 841 | return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); |
| 842 | } |
| 843 | |
| 844 | /** |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 845 | * db8500_prcmu_get_ddr_opp - get the current DDR OPP |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 846 | * |
| 847 | * Returns: the current DDR OPP |
| 848 | */ |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 849 | int db8500_prcmu_get_ddr_opp(void) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 850 | { |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 851 | return readb(PRCM_DDR_SUBSYS_APE_MINBW); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 852 | } |
| 853 | |
Mattias Nilsson | 4d64d2e | 2012-01-13 16:20:43 +0100 | [diff] [blame] | 854 | /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */ |
| 855 | static void request_even_slower_clocks(bool enable) |
| 856 | { |
Linus Walleij | b047d98 | 2013-03-19 14:21:47 +0100 | [diff] [blame] | 857 | u32 clock_reg[] = { |
Mattias Nilsson | 4d64d2e | 2012-01-13 16:20:43 +0100 | [diff] [blame] | 858 | PRCM_ACLK_MGT, |
| 859 | PRCM_DMACLK_MGT |
| 860 | }; |
| 861 | unsigned long flags; |
| 862 | unsigned int i; |
| 863 | |
| 864 | spin_lock_irqsave(&clk_mgt_lock, flags); |
| 865 | |
| 866 | /* Grab the HW semaphore. */ |
| 867 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
| 868 | cpu_relax(); |
| 869 | |
| 870 | for (i = 0; i < ARRAY_SIZE(clock_reg); i++) { |
| 871 | u32 val; |
| 872 | u32 div; |
| 873 | |
Linus Walleij | b047d98 | 2013-03-19 14:21:47 +0100 | [diff] [blame] | 874 | val = readl(prcmu_base + clock_reg[i]); |
Mattias Nilsson | 4d64d2e | 2012-01-13 16:20:43 +0100 | [diff] [blame] | 875 | div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); |
| 876 | if (enable) { |
| 877 | if ((div <= 1) || (div > 15)) { |
| 878 | pr_err("prcmu: Bad clock divider %d in %s\n", |
| 879 | div, __func__); |
| 880 | goto unlock_and_return; |
| 881 | } |
| 882 | div <<= 1; |
| 883 | } else { |
| 884 | if (div <= 2) |
| 885 | goto unlock_and_return; |
| 886 | div >>= 1; |
| 887 | } |
| 888 | val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) | |
| 889 | (div & PRCM_CLK_MGT_CLKPLLDIV_MASK)); |
Linus Walleij | b047d98 | 2013-03-19 14:21:47 +0100 | [diff] [blame] | 890 | writel(val, prcmu_base + clock_reg[i]); |
Mattias Nilsson | 4d64d2e | 2012-01-13 16:20:43 +0100 | [diff] [blame] | 891 | } |
| 892 | |
| 893 | unlock_and_return: |
| 894 | /* Release the HW semaphore. */ |
| 895 | writel(0, PRCM_SEM); |
| 896 | |
| 897 | spin_unlock_irqrestore(&clk_mgt_lock, flags); |
| 898 | } |
| 899 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 900 | /** |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 901 | * db8500_set_ape_opp - set the appropriate APE OPP |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 902 | * @opp: The new APE operating point to which transition is to be made |
| 903 | * Returns: 0 on success, non-zero on failure |
| 904 | * |
| 905 | * This function sets the operating point of the APE. |
| 906 | */ |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 907 | int db8500_prcmu_set_ape_opp(u8 opp) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 908 | { |
| 909 | int r = 0; |
| 910 | |
Mattias Nilsson | 4d64d2e | 2012-01-13 16:20:43 +0100 | [diff] [blame] | 911 | if (opp == mb1_transfer.ape_opp) |
| 912 | return 0; |
| 913 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 914 | mutex_lock(&mb1_transfer.lock); |
| 915 | |
Mattias Nilsson | 4d64d2e | 2012-01-13 16:20:43 +0100 | [diff] [blame] | 916 | if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP) |
| 917 | request_even_slower_clocks(false); |
| 918 | |
| 919 | if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP)) |
| 920 | goto skip_message; |
| 921 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 922 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 923 | cpu_relax(); |
| 924 | |
| 925 | writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); |
| 926 | writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); |
Mattias Nilsson | 4d64d2e | 2012-01-13 16:20:43 +0100 | [diff] [blame] | 927 | writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp), |
| 928 | (tcdm_base + PRCM_REQ_MB1_APE_OPP)); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 929 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 930 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 931 | wait_for_completion(&mb1_transfer.work); |
| 932 | |
| 933 | if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || |
| 934 | (mb1_transfer.ack.ape_opp != opp)) |
| 935 | r = -EIO; |
| 936 | |
Mattias Nilsson | 4d64d2e | 2012-01-13 16:20:43 +0100 | [diff] [blame] | 937 | skip_message: |
| 938 | if ((!r && (opp == APE_50_PARTLY_25_OPP)) || |
| 939 | (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP))) |
| 940 | request_even_slower_clocks(true); |
| 941 | if (!r) |
| 942 | mb1_transfer.ape_opp = opp; |
| 943 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 944 | mutex_unlock(&mb1_transfer.lock); |
| 945 | |
| 946 | return r; |
| 947 | } |
| 948 | |
| 949 | /** |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 950 | * db8500_prcmu_get_ape_opp - get the current APE OPP |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 951 | * |
| 952 | * Returns: the current APE OPP |
| 953 | */ |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 954 | int db8500_prcmu_get_ape_opp(void) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 955 | { |
| 956 | return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); |
| 957 | } |
| 958 | |
| 959 | /** |
Ulf Hansson | 686f871 | 2012-09-24 16:43:17 +0200 | [diff] [blame] | 960 | * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 961 | * @enable: true to request the higher voltage, false to drop a request. |
| 962 | * |
| 963 | * Calls to this function to enable and disable requests must be balanced. |
| 964 | */ |
Ulf Hansson | 686f871 | 2012-09-24 16:43:17 +0200 | [diff] [blame] | 965 | int db8500_prcmu_request_ape_opp_100_voltage(bool enable) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 966 | { |
| 967 | int r = 0; |
| 968 | u8 header; |
| 969 | static unsigned int requests; |
| 970 | |
| 971 | mutex_lock(&mb1_transfer.lock); |
| 972 | |
| 973 | if (enable) { |
| 974 | if (0 != requests++) |
| 975 | goto unlock_and_return; |
| 976 | header = MB1H_REQUEST_APE_OPP_100_VOLT; |
| 977 | } else { |
| 978 | if (requests == 0) { |
| 979 | r = -EIO; |
| 980 | goto unlock_and_return; |
| 981 | } else if (1 != requests--) { |
| 982 | goto unlock_and_return; |
| 983 | } |
| 984 | header = MB1H_RELEASE_APE_OPP_100_VOLT; |
| 985 | } |
| 986 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 987 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 988 | cpu_relax(); |
| 989 | |
| 990 | writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); |
| 991 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 992 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 993 | wait_for_completion(&mb1_transfer.work); |
| 994 | |
| 995 | if ((mb1_transfer.ack.header != header) || |
| 996 | ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) |
| 997 | r = -EIO; |
| 998 | |
| 999 | unlock_and_return: |
| 1000 | mutex_unlock(&mb1_transfer.lock); |
| 1001 | |
| 1002 | return r; |
| 1003 | } |
| 1004 | |
| 1005 | /** |
| 1006 | * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup |
| 1007 | * |
| 1008 | * This function releases the power state requirements of a USB wakeup. |
| 1009 | */ |
| 1010 | int prcmu_release_usb_wakeup_state(void) |
| 1011 | { |
| 1012 | int r = 0; |
| 1013 | |
| 1014 | mutex_lock(&mb1_transfer.lock); |
| 1015 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 1016 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1017 | cpu_relax(); |
| 1018 | |
| 1019 | writeb(MB1H_RELEASE_USB_WAKEUP, |
| 1020 | (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); |
| 1021 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 1022 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1023 | wait_for_completion(&mb1_transfer.work); |
| 1024 | |
| 1025 | if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) || |
| 1026 | ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) |
| 1027 | r = -EIO; |
| 1028 | |
| 1029 | mutex_unlock(&mb1_transfer.lock); |
| 1030 | |
| 1031 | return r; |
| 1032 | } |
| 1033 | |
Mattias Nilsson | 0837bb7 | 2011-08-12 10:28:18 +0200 | [diff] [blame] | 1034 | static int request_pll(u8 clock, bool enable) |
| 1035 | { |
| 1036 | int r = 0; |
| 1037 | |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1038 | if (clock == PRCMU_PLLSOC0) |
| 1039 | clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF); |
| 1040 | else if (clock == PRCMU_PLLSOC1) |
Mattias Nilsson | 0837bb7 | 2011-08-12 10:28:18 +0200 | [diff] [blame] | 1041 | clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); |
| 1042 | else |
| 1043 | return -EINVAL; |
| 1044 | |
| 1045 | mutex_lock(&mb1_transfer.lock); |
| 1046 | |
| 1047 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
| 1048 | cpu_relax(); |
| 1049 | |
| 1050 | writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); |
| 1051 | writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); |
| 1052 | |
| 1053 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
| 1054 | wait_for_completion(&mb1_transfer.work); |
| 1055 | |
| 1056 | if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF) |
| 1057 | r = -EIO; |
| 1058 | |
| 1059 | mutex_unlock(&mb1_transfer.lock); |
| 1060 | |
| 1061 | return r; |
| 1062 | } |
| 1063 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1064 | /** |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 1065 | * db8500_prcmu_set_epod - set the state of a EPOD (power domain) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1066 | * @epod_id: The EPOD to set |
| 1067 | * @epod_state: The new EPOD state |
| 1068 | * |
| 1069 | * This function sets the state of a EPOD (power domain). It may not be called |
| 1070 | * from interrupt context. |
| 1071 | */ |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 1072 | int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1073 | { |
| 1074 | int r = 0; |
| 1075 | bool ram_retention = false; |
| 1076 | int i; |
| 1077 | |
| 1078 | /* check argument */ |
| 1079 | BUG_ON(epod_id >= NUM_EPOD_ID); |
| 1080 | |
| 1081 | /* set flag if retention is possible */ |
| 1082 | switch (epod_id) { |
| 1083 | case EPOD_ID_SVAMMDSP: |
| 1084 | case EPOD_ID_SIAMMDSP: |
| 1085 | case EPOD_ID_ESRAM12: |
| 1086 | case EPOD_ID_ESRAM34: |
| 1087 | ram_retention = true; |
| 1088 | break; |
| 1089 | } |
| 1090 | |
| 1091 | /* check argument */ |
| 1092 | BUG_ON(epod_state > EPOD_STATE_ON); |
| 1093 | BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention); |
| 1094 | |
| 1095 | /* get lock */ |
| 1096 | mutex_lock(&mb2_transfer.lock); |
| 1097 | |
| 1098 | /* wait for mailbox */ |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 1099 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1100 | cpu_relax(); |
| 1101 | |
| 1102 | /* fill in mailbox */ |
| 1103 | for (i = 0; i < NUM_EPOD_ID; i++) |
| 1104 | writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); |
| 1105 | writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); |
| 1106 | |
| 1107 | writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); |
| 1108 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 1109 | writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1110 | |
| 1111 | /* |
| 1112 | * The current firmware version does not handle errors correctly, |
| 1113 | * and we cannot recover if there is an error. |
| 1114 | * This is expected to change when the firmware is updated. |
| 1115 | */ |
| 1116 | if (!wait_for_completion_timeout(&mb2_transfer.work, |
| 1117 | msecs_to_jiffies(20000))) { |
| 1118 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", |
| 1119 | __func__); |
| 1120 | r = -EIO; |
| 1121 | goto unlock_and_return; |
| 1122 | } |
| 1123 | |
| 1124 | if (mb2_transfer.ack.status != HWACC_PWR_ST_OK) |
| 1125 | r = -EIO; |
| 1126 | |
| 1127 | unlock_and_return: |
| 1128 | mutex_unlock(&mb2_transfer.lock); |
| 1129 | return r; |
| 1130 | } |
| 1131 | |
| 1132 | /** |
| 1133 | * prcmu_configure_auto_pm - Configure autonomous power management. |
| 1134 | * @sleep: Configuration for ApSleep. |
| 1135 | * @idle: Configuration for ApIdle. |
| 1136 | */ |
| 1137 | void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, |
| 1138 | struct prcmu_auto_pm_config *idle) |
| 1139 | { |
| 1140 | u32 sleep_cfg; |
| 1141 | u32 idle_cfg; |
| 1142 | unsigned long flags; |
| 1143 | |
| 1144 | BUG_ON((sleep == NULL) || (idle == NULL)); |
| 1145 | |
| 1146 | sleep_cfg = (sleep->sva_auto_pm_enable & 0xF); |
| 1147 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF)); |
| 1148 | sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF)); |
| 1149 | sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF)); |
| 1150 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF)); |
| 1151 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF)); |
| 1152 | |
| 1153 | idle_cfg = (idle->sva_auto_pm_enable & 0xF); |
| 1154 | idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF)); |
| 1155 | idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF)); |
| 1156 | idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF)); |
| 1157 | idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF)); |
| 1158 | idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF)); |
| 1159 | |
| 1160 | spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags); |
| 1161 | |
| 1162 | /* |
| 1163 | * The autonomous power management configuration is done through |
| 1164 | * fields in mailbox 2, but these fields are only used as shared |
| 1165 | * variables - i.e. there is no need to send a message. |
| 1166 | */ |
| 1167 | writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); |
| 1168 | writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); |
| 1169 | |
| 1170 | mb2_transfer.auto_pm_enabled = |
| 1171 | ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || |
| 1172 | (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) || |
| 1173 | (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || |
| 1174 | (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON)); |
| 1175 | |
| 1176 | spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags); |
| 1177 | } |
| 1178 | EXPORT_SYMBOL(prcmu_configure_auto_pm); |
| 1179 | |
| 1180 | bool prcmu_is_auto_pm_enabled(void) |
| 1181 | { |
| 1182 | return mb2_transfer.auto_pm_enabled; |
| 1183 | } |
| 1184 | |
| 1185 | static int request_sysclk(bool enable) |
| 1186 | { |
| 1187 | int r; |
| 1188 | unsigned long flags; |
| 1189 | |
| 1190 | r = 0; |
| 1191 | |
| 1192 | mutex_lock(&mb3_transfer.sysclk_lock); |
| 1193 | |
| 1194 | spin_lock_irqsave(&mb3_transfer.lock, flags); |
| 1195 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 1196 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3)) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1197 | cpu_relax(); |
| 1198 | |
| 1199 | writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); |
| 1200 | |
| 1201 | writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 1202 | writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1203 | |
| 1204 | spin_unlock_irqrestore(&mb3_transfer.lock, flags); |
| 1205 | |
| 1206 | /* |
| 1207 | * The firmware only sends an ACK if we want to enable the |
| 1208 | * SysClk, and it succeeds. |
| 1209 | */ |
| 1210 | if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work, |
| 1211 | msecs_to_jiffies(20000))) { |
| 1212 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", |
| 1213 | __func__); |
| 1214 | r = -EIO; |
| 1215 | } |
| 1216 | |
| 1217 | mutex_unlock(&mb3_transfer.sysclk_lock); |
| 1218 | |
| 1219 | return r; |
| 1220 | } |
| 1221 | |
| 1222 | static int request_timclk(bool enable) |
| 1223 | { |
Linus Walleij | 22fb3ad | 2019-10-26 23:47:32 +0200 | [diff] [blame] | 1224 | u32 val; |
| 1225 | |
| 1226 | /* |
| 1227 | * On the U8420_CLKSEL firmware, the ULP (Ultra Low Power) |
| 1228 | * PLL is disabled so we cannot use doze mode, this will |
| 1229 | * stop the clock on this firmware. |
| 1230 | */ |
| 1231 | if (prcmu_is_ulppll_disabled()) |
| 1232 | val = 0; |
| 1233 | else |
| 1234 | val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1235 | |
| 1236 | if (!enable) |
Linus Walleij | 22fb3ad | 2019-10-26 23:47:32 +0200 | [diff] [blame] | 1237 | val |= PRCM_TCR_STOP_TIMERS | |
| 1238 | PRCM_TCR_DOZE_MODE | |
| 1239 | PRCM_TCR_TENSEL_MASK; |
| 1240 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 1241 | writel(val, PRCM_TCR); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1242 | |
| 1243 | return 0; |
| 1244 | } |
| 1245 | |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1246 | static int request_clock(u8 clock, bool enable) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1247 | { |
| 1248 | u32 val; |
| 1249 | unsigned long flags; |
| 1250 | |
| 1251 | spin_lock_irqsave(&clk_mgt_lock, flags); |
| 1252 | |
| 1253 | /* Grab the HW semaphore. */ |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 1254 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1255 | cpu_relax(); |
| 1256 | |
Linus Walleij | b047d98 | 2013-03-19 14:21:47 +0100 | [diff] [blame] | 1257 | val = readl(prcmu_base + clk_mgt[clock].offset); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1258 | if (enable) { |
| 1259 | val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); |
| 1260 | } else { |
| 1261 | clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); |
| 1262 | val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); |
| 1263 | } |
Linus Walleij | b047d98 | 2013-03-19 14:21:47 +0100 | [diff] [blame] | 1264 | writel(val, prcmu_base + clk_mgt[clock].offset); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1265 | |
| 1266 | /* Release the HW semaphore. */ |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 1267 | writel(0, PRCM_SEM); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1268 | |
| 1269 | spin_unlock_irqrestore(&clk_mgt_lock, flags); |
| 1270 | |
| 1271 | return 0; |
| 1272 | } |
| 1273 | |
Mattias Nilsson | 0837bb7 | 2011-08-12 10:28:18 +0200 | [diff] [blame] | 1274 | static int request_sga_clock(u8 clock, bool enable) |
| 1275 | { |
| 1276 | u32 val; |
| 1277 | int ret; |
| 1278 | |
| 1279 | if (enable) { |
| 1280 | val = readl(PRCM_CGATING_BYPASS); |
| 1281 | writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); |
| 1282 | } |
| 1283 | |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1284 | ret = request_clock(clock, enable); |
Mattias Nilsson | 0837bb7 | 2011-08-12 10:28:18 +0200 | [diff] [blame] | 1285 | |
| 1286 | if (!ret && !enable) { |
| 1287 | val = readl(PRCM_CGATING_BYPASS); |
| 1288 | writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); |
| 1289 | } |
| 1290 | |
| 1291 | return ret; |
| 1292 | } |
| 1293 | |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1294 | static inline bool plldsi_locked(void) |
| 1295 | { |
| 1296 | return (readl(PRCM_PLLDSI_LOCKP) & |
| 1297 | (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | |
| 1298 | PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) == |
| 1299 | (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | |
| 1300 | PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3); |
| 1301 | } |
| 1302 | |
| 1303 | static int request_plldsi(bool enable) |
| 1304 | { |
| 1305 | int r = 0; |
| 1306 | u32 val; |
| 1307 | |
| 1308 | writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | |
| 1309 | PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ? |
| 1310 | PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET)); |
| 1311 | |
| 1312 | val = readl(PRCM_PLLDSI_ENABLE); |
| 1313 | if (enable) |
| 1314 | val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; |
| 1315 | else |
| 1316 | val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; |
| 1317 | writel(val, PRCM_PLLDSI_ENABLE); |
| 1318 | |
| 1319 | if (enable) { |
| 1320 | unsigned int i; |
| 1321 | bool locked = plldsi_locked(); |
| 1322 | |
| 1323 | for (i = 10; !locked && (i > 0); --i) { |
| 1324 | udelay(100); |
| 1325 | locked = plldsi_locked(); |
| 1326 | } |
| 1327 | if (locked) { |
| 1328 | writel(PRCM_APE_RESETN_DSIPLL_RESETN, |
| 1329 | PRCM_APE_RESETN_SET); |
| 1330 | } else { |
| 1331 | writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | |
| 1332 | PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), |
| 1333 | PRCM_MMIP_LS_CLAMP_SET); |
| 1334 | val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; |
| 1335 | writel(val, PRCM_PLLDSI_ENABLE); |
| 1336 | r = -EAGAIN; |
| 1337 | } |
| 1338 | } else { |
| 1339 | writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR); |
| 1340 | } |
| 1341 | return r; |
| 1342 | } |
| 1343 | |
| 1344 | static int request_dsiclk(u8 n, bool enable) |
| 1345 | { |
| 1346 | u32 val; |
| 1347 | |
| 1348 | val = readl(PRCM_DSI_PLLOUT_SEL); |
| 1349 | val &= ~dsiclk[n].divsel_mask; |
| 1350 | val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << |
| 1351 | dsiclk[n].divsel_shift); |
| 1352 | writel(val, PRCM_DSI_PLLOUT_SEL); |
| 1353 | return 0; |
| 1354 | } |
| 1355 | |
| 1356 | static int request_dsiescclk(u8 n, bool enable) |
| 1357 | { |
| 1358 | u32 val; |
| 1359 | |
| 1360 | val = readl(PRCM_DSITVCLK_DIV); |
| 1361 | enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en); |
| 1362 | writel(val, PRCM_DSITVCLK_DIV); |
| 1363 | return 0; |
| 1364 | } |
| 1365 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1366 | /** |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 1367 | * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled. |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1368 | * @clock: The clock for which the request is made. |
| 1369 | * @enable: Whether the clock should be enabled (true) or disabled (false). |
| 1370 | * |
| 1371 | * This function should only be used by the clock implementation. |
| 1372 | * Do not use it from any other place! |
| 1373 | */ |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 1374 | int db8500_prcmu_request_clock(u8 clock, bool enable) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1375 | { |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1376 | if (clock == PRCMU_SGACLK) |
Mattias Nilsson | 0837bb7 | 2011-08-12 10:28:18 +0200 | [diff] [blame] | 1377 | return request_sga_clock(clock, enable); |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1378 | else if (clock < PRCMU_NUM_REG_CLOCKS) |
| 1379 | return request_clock(clock, enable); |
| 1380 | else if (clock == PRCMU_TIMCLK) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1381 | return request_timclk(enable); |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1382 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) |
| 1383 | return request_dsiclk((clock - PRCMU_DSI0CLK), enable); |
| 1384 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) |
| 1385 | return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable); |
| 1386 | else if (clock == PRCMU_PLLDSI) |
| 1387 | return request_plldsi(enable); |
| 1388 | else if (clock == PRCMU_SYSCLK) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1389 | return request_sysclk(enable); |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1390 | else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1)) |
Mattias Nilsson | 0837bb7 | 2011-08-12 10:28:18 +0200 | [diff] [blame] | 1391 | return request_pll(clock, enable); |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1392 | else |
| 1393 | return -EINVAL; |
| 1394 | } |
| 1395 | |
| 1396 | static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, |
| 1397 | int branch) |
| 1398 | { |
| 1399 | u64 rate; |
| 1400 | u32 val; |
| 1401 | u32 d; |
| 1402 | u32 div = 1; |
| 1403 | |
| 1404 | val = readl(reg); |
| 1405 | |
| 1406 | rate = src_rate; |
| 1407 | rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT); |
| 1408 | |
| 1409 | d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT); |
| 1410 | if (d > 1) |
| 1411 | div *= d; |
| 1412 | |
| 1413 | d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT); |
| 1414 | if (d > 1) |
| 1415 | div *= d; |
| 1416 | |
| 1417 | if (val & PRCM_PLL_FREQ_SELDIV2) |
| 1418 | div *= 2; |
| 1419 | |
| 1420 | if ((branch == PLL_FIX) || ((branch == PLL_DIV) && |
| 1421 | (val & PRCM_PLL_FREQ_DIV2EN) && |
| 1422 | ((reg == PRCM_PLLSOC0_FREQ) || |
Michel Jaouen | 20aee5b | 2012-08-31 14:21:30 +0200 | [diff] [blame] | 1423 | (reg == PRCM_PLLARM_FREQ) || |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1424 | (reg == PRCM_PLLDDR_FREQ)))) |
| 1425 | div *= 2; |
| 1426 | |
| 1427 | (void)do_div(rate, div); |
| 1428 | |
| 1429 | return (unsigned long)rate; |
| 1430 | } |
| 1431 | |
| 1432 | #define ROOT_CLOCK_RATE 38400000 |
| 1433 | |
| 1434 | static unsigned long clock_rate(u8 clock) |
| 1435 | { |
| 1436 | u32 val; |
| 1437 | u32 pllsw; |
| 1438 | unsigned long rate = ROOT_CLOCK_RATE; |
| 1439 | |
Linus Walleij | b047d98 | 2013-03-19 14:21:47 +0100 | [diff] [blame] | 1440 | val = readl(prcmu_base + clk_mgt[clock].offset); |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1441 | |
| 1442 | if (val & PRCM_CLK_MGT_CLK38) { |
| 1443 | if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) |
| 1444 | rate /= 2; |
| 1445 | return rate; |
Linus Walleij | e62ccf3 | 2011-10-10 12:14:14 +0200 | [diff] [blame] | 1446 | } |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1447 | |
| 1448 | val |= clk_mgt[clock].pllsw; |
| 1449 | pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); |
| 1450 | |
| 1451 | if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0) |
| 1452 | rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); |
| 1453 | else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1) |
| 1454 | rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); |
| 1455 | else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR) |
| 1456 | rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); |
| 1457 | else |
| 1458 | return 0; |
| 1459 | |
| 1460 | if ((clock == PRCMU_SGACLK) && |
| 1461 | (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) { |
| 1462 | u64 r = (rate * 10); |
| 1463 | |
| 1464 | (void)do_div(r, 25); |
| 1465 | return (unsigned long)r; |
| 1466 | } |
| 1467 | val &= PRCM_CLK_MGT_CLKPLLDIV_MASK; |
| 1468 | if (val) |
| 1469 | return rate / val; |
| 1470 | else |
| 1471 | return 0; |
| 1472 | } |
Michel Jaouen | 20aee5b | 2012-08-31 14:21:30 +0200 | [diff] [blame] | 1473 | |
Ulf Hansson | b2302c8 | 2012-10-10 13:42:26 +0200 | [diff] [blame] | 1474 | static unsigned long armss_rate(void) |
Michel Jaouen | 20aee5b | 2012-08-31 14:21:30 +0200 | [diff] [blame] | 1475 | { |
| 1476 | u32 r; |
| 1477 | unsigned long rate; |
| 1478 | |
| 1479 | r = readl(PRCM_ARM_CHGCLKREQ); |
| 1480 | |
| 1481 | if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) { |
| 1482 | /* External ARMCLKFIX clock */ |
| 1483 | |
| 1484 | rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX); |
| 1485 | |
| 1486 | /* Check PRCM_ARM_CHGCLKREQ divider */ |
| 1487 | if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL)) |
| 1488 | rate /= 2; |
| 1489 | |
| 1490 | /* Check PRCM_ARMCLKFIX_MGT divider */ |
| 1491 | r = readl(PRCM_ARMCLKFIX_MGT); |
| 1492 | r &= PRCM_CLK_MGT_CLKPLLDIV_MASK; |
| 1493 | rate /= r; |
| 1494 | |
| 1495 | } else {/* ARM PLL */ |
| 1496 | rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV); |
| 1497 | } |
| 1498 | |
Ulf Hansson | b2302c8 | 2012-10-10 13:42:26 +0200 | [diff] [blame] | 1499 | return rate; |
Michel Jaouen | 20aee5b | 2012-08-31 14:21:30 +0200 | [diff] [blame] | 1500 | } |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1501 | |
| 1502 | static unsigned long dsiclk_rate(u8 n) |
| 1503 | { |
| 1504 | u32 divsel; |
| 1505 | u32 div = 1; |
| 1506 | |
| 1507 | divsel = readl(PRCM_DSI_PLLOUT_SEL); |
| 1508 | divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); |
| 1509 | |
| 1510 | if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) |
| 1511 | divsel = dsiclk[n].divsel; |
Ulf Hansson | e9d7b4b | 2013-05-14 15:14:55 +0200 | [diff] [blame] | 1512 | else |
| 1513 | dsiclk[n].divsel = divsel; |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1514 | |
| 1515 | switch (divsel) { |
| 1516 | case PRCM_DSI_PLLOUT_SEL_PHI_4: |
| 1517 | div *= 2; |
Gustavo A. R. Silva | df561f66 | 2020-08-23 17:36:59 -0500 | [diff] [blame] | 1518 | fallthrough; |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1519 | case PRCM_DSI_PLLOUT_SEL_PHI_2: |
| 1520 | div *= 2; |
Gustavo A. R. Silva | df561f66 | 2020-08-23 17:36:59 -0500 | [diff] [blame] | 1521 | fallthrough; |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1522 | case PRCM_DSI_PLLOUT_SEL_PHI: |
| 1523 | return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), |
| 1524 | PLL_RAW) / div; |
| 1525 | default: |
| 1526 | return 0; |
| 1527 | } |
| 1528 | } |
| 1529 | |
| 1530 | static unsigned long dsiescclk_rate(u8 n) |
| 1531 | { |
| 1532 | u32 div; |
| 1533 | |
| 1534 | div = readl(PRCM_DSITVCLK_DIV); |
| 1535 | div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); |
| 1536 | return clock_rate(PRCMU_TVCLK) / max((u32)1, div); |
| 1537 | } |
| 1538 | |
| 1539 | unsigned long prcmu_clock_rate(u8 clock) |
| 1540 | { |
Linus Walleij | e62ccf3 | 2011-10-10 12:14:14 +0200 | [diff] [blame] | 1541 | if (clock < PRCMU_NUM_REG_CLOCKS) |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1542 | return clock_rate(clock); |
| 1543 | else if (clock == PRCMU_TIMCLK) |
Linus Walleij | 22fb3ad | 2019-10-26 23:47:32 +0200 | [diff] [blame] | 1544 | return prcmu_is_ulppll_disabled() ? |
| 1545 | 32768 : ROOT_CLOCK_RATE / 16; |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1546 | else if (clock == PRCMU_SYSCLK) |
| 1547 | return ROOT_CLOCK_RATE; |
| 1548 | else if (clock == PRCMU_PLLSOC0) |
| 1549 | return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); |
| 1550 | else if (clock == PRCMU_PLLSOC1) |
| 1551 | return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); |
Michel Jaouen | 20aee5b | 2012-08-31 14:21:30 +0200 | [diff] [blame] | 1552 | else if (clock == PRCMU_ARMSS) |
| 1553 | return armss_rate(); |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1554 | else if (clock == PRCMU_PLLDDR) |
| 1555 | return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); |
| 1556 | else if (clock == PRCMU_PLLDSI) |
| 1557 | return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), |
| 1558 | PLL_RAW); |
| 1559 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) |
| 1560 | return dsiclk_rate(clock - PRCMU_DSI0CLK); |
| 1561 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) |
| 1562 | return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK); |
| 1563 | else |
| 1564 | return 0; |
| 1565 | } |
| 1566 | |
| 1567 | static unsigned long clock_source_rate(u32 clk_mgt_val, int branch) |
| 1568 | { |
| 1569 | if (clk_mgt_val & PRCM_CLK_MGT_CLK38) |
| 1570 | return ROOT_CLOCK_RATE; |
| 1571 | clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK; |
| 1572 | if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0) |
| 1573 | return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch); |
| 1574 | else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1) |
| 1575 | return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch); |
| 1576 | else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR) |
| 1577 | return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch); |
| 1578 | else |
| 1579 | return 0; |
| 1580 | } |
| 1581 | |
| 1582 | static u32 clock_divider(unsigned long src_rate, unsigned long rate) |
| 1583 | { |
| 1584 | u32 div; |
| 1585 | |
| 1586 | div = (src_rate / rate); |
| 1587 | if (div == 0) |
| 1588 | return 1; |
| 1589 | if (rate < (src_rate / div)) |
| 1590 | div++; |
| 1591 | return div; |
| 1592 | } |
| 1593 | |
| 1594 | static long round_clock_rate(u8 clock, unsigned long rate) |
| 1595 | { |
| 1596 | u32 val; |
| 1597 | u32 div; |
| 1598 | unsigned long src_rate; |
| 1599 | long rounded_rate; |
| 1600 | |
Linus Walleij | b047d98 | 2013-03-19 14:21:47 +0100 | [diff] [blame] | 1601 | val = readl(prcmu_base + clk_mgt[clock].offset); |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1602 | src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), |
| 1603 | clk_mgt[clock].branch); |
| 1604 | div = clock_divider(src_rate, rate); |
| 1605 | if (val & PRCM_CLK_MGT_CLK38) { |
| 1606 | if (clk_mgt[clock].clk38div) { |
| 1607 | if (div > 2) |
| 1608 | div = 2; |
| 1609 | } else { |
| 1610 | div = 1; |
| 1611 | } |
| 1612 | } else if ((clock == PRCMU_SGACLK) && (div == 3)) { |
| 1613 | u64 r = (src_rate * 10); |
| 1614 | |
| 1615 | (void)do_div(r, 25); |
| 1616 | if (r <= rate) |
| 1617 | return (unsigned long)r; |
| 1618 | } |
| 1619 | rounded_rate = (src_rate / min(div, (u32)31)); |
| 1620 | |
| 1621 | return rounded_rate; |
| 1622 | } |
| 1623 | |
Linus Walleij | fea3ac5 | 2019-08-29 13:25:01 +0200 | [diff] [blame] | 1624 | static const unsigned long db8500_armss_freqs[] = { |
Linus Walleij | 836a1e2 | 2017-08-22 15:17:40 +0200 | [diff] [blame] | 1625 | 200000000, |
| 1626 | 400000000, |
| 1627 | 800000000, |
| 1628 | 998400000 |
Ulf Hansson | b2302c8 | 2012-10-10 13:42:26 +0200 | [diff] [blame] | 1629 | }; |
| 1630 | |
Linus Walleij | fea3ac5 | 2019-08-29 13:25:01 +0200 | [diff] [blame] | 1631 | /* The DB8520 has slightly higher ARMSS max frequency */ |
| 1632 | static const unsigned long db8520_armss_freqs[] = { |
| 1633 | 200000000, |
| 1634 | 400000000, |
| 1635 | 800000000, |
| 1636 | 1152000000 |
| 1637 | }; |
| 1638 | |
| 1639 | |
| 1640 | |
Ulf Hansson | b2302c8 | 2012-10-10 13:42:26 +0200 | [diff] [blame] | 1641 | static long round_armss_rate(unsigned long rate) |
| 1642 | { |
Linus Walleij | 836a1e2 | 2017-08-22 15:17:40 +0200 | [diff] [blame] | 1643 | unsigned long freq = 0; |
Linus Walleij | fea3ac5 | 2019-08-29 13:25:01 +0200 | [diff] [blame] | 1644 | const unsigned long *freqs; |
| 1645 | int nfreqs; |
Linus Walleij | 836a1e2 | 2017-08-22 15:17:40 +0200 | [diff] [blame] | 1646 | int i; |
Ulf Hansson | b2302c8 | 2012-10-10 13:42:26 +0200 | [diff] [blame] | 1647 | |
Linus Walleij | fea3ac5 | 2019-08-29 13:25:01 +0200 | [diff] [blame] | 1648 | if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) { |
| 1649 | freqs = db8520_armss_freqs; |
| 1650 | nfreqs = ARRAY_SIZE(db8520_armss_freqs); |
| 1651 | } else { |
| 1652 | freqs = db8500_armss_freqs; |
| 1653 | nfreqs = ARRAY_SIZE(db8500_armss_freqs); |
| 1654 | } |
| 1655 | |
Ulf Hansson | b2302c8 | 2012-10-10 13:42:26 +0200 | [diff] [blame] | 1656 | /* Find the corresponding arm opp from the cpufreq table. */ |
Linus Walleij | fea3ac5 | 2019-08-29 13:25:01 +0200 | [diff] [blame] | 1657 | for (i = 0; i < nfreqs; i++) { |
| 1658 | freq = freqs[i]; |
Linus Walleij | 836a1e2 | 2017-08-22 15:17:40 +0200 | [diff] [blame] | 1659 | if (rate <= freq) |
Ulf Hansson | b2302c8 | 2012-10-10 13:42:26 +0200 | [diff] [blame] | 1660 | break; |
Ulf Hansson | b2302c8 | 2012-10-10 13:42:26 +0200 | [diff] [blame] | 1661 | } |
| 1662 | |
| 1663 | /* Return the last valid value, even if a match was not found. */ |
Linus Walleij | 836a1e2 | 2017-08-22 15:17:40 +0200 | [diff] [blame] | 1664 | return freq; |
Ulf Hansson | b2302c8 | 2012-10-10 13:42:26 +0200 | [diff] [blame] | 1665 | } |
| 1666 | |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1667 | #define MIN_PLL_VCO_RATE 600000000ULL |
| 1668 | #define MAX_PLL_VCO_RATE 1680640000ULL |
| 1669 | |
| 1670 | static long round_plldsi_rate(unsigned long rate) |
| 1671 | { |
| 1672 | long rounded_rate = 0; |
| 1673 | unsigned long src_rate; |
| 1674 | unsigned long rem; |
| 1675 | u32 r; |
| 1676 | |
| 1677 | src_rate = clock_rate(PRCMU_HDMICLK); |
| 1678 | rem = rate; |
| 1679 | |
| 1680 | for (r = 7; (rem > 0) && (r > 0); r--) { |
| 1681 | u64 d; |
| 1682 | |
| 1683 | d = (r * rate); |
| 1684 | (void)do_div(d, src_rate); |
| 1685 | if (d < 6) |
| 1686 | d = 6; |
| 1687 | else if (d > 255) |
| 1688 | d = 255; |
| 1689 | d *= src_rate; |
| 1690 | if (((2 * d) < (r * MIN_PLL_VCO_RATE)) || |
| 1691 | ((r * MAX_PLL_VCO_RATE) < (2 * d))) |
| 1692 | continue; |
| 1693 | (void)do_div(d, r); |
| 1694 | if (rate < d) { |
| 1695 | if (rounded_rate == 0) |
| 1696 | rounded_rate = (long)d; |
| 1697 | break; |
| 1698 | } |
| 1699 | if ((rate - d) < rem) { |
| 1700 | rem = (rate - d); |
| 1701 | rounded_rate = (long)d; |
| 1702 | } |
| 1703 | } |
| 1704 | return rounded_rate; |
| 1705 | } |
| 1706 | |
| 1707 | static long round_dsiclk_rate(unsigned long rate) |
| 1708 | { |
| 1709 | u32 div; |
| 1710 | unsigned long src_rate; |
| 1711 | long rounded_rate; |
| 1712 | |
| 1713 | src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), |
| 1714 | PLL_RAW); |
| 1715 | div = clock_divider(src_rate, rate); |
| 1716 | rounded_rate = (src_rate / ((div > 2) ? 4 : div)); |
| 1717 | |
| 1718 | return rounded_rate; |
| 1719 | } |
| 1720 | |
| 1721 | static long round_dsiescclk_rate(unsigned long rate) |
| 1722 | { |
| 1723 | u32 div; |
| 1724 | unsigned long src_rate; |
| 1725 | long rounded_rate; |
| 1726 | |
| 1727 | src_rate = clock_rate(PRCMU_TVCLK); |
| 1728 | div = clock_divider(src_rate, rate); |
| 1729 | rounded_rate = (src_rate / min(div, (u32)255)); |
| 1730 | |
| 1731 | return rounded_rate; |
| 1732 | } |
| 1733 | |
| 1734 | long prcmu_round_clock_rate(u8 clock, unsigned long rate) |
| 1735 | { |
| 1736 | if (clock < PRCMU_NUM_REG_CLOCKS) |
| 1737 | return round_clock_rate(clock, rate); |
Ulf Hansson | b2302c8 | 2012-10-10 13:42:26 +0200 | [diff] [blame] | 1738 | else if (clock == PRCMU_ARMSS) |
| 1739 | return round_armss_rate(rate); |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1740 | else if (clock == PRCMU_PLLDSI) |
| 1741 | return round_plldsi_rate(rate); |
| 1742 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) |
| 1743 | return round_dsiclk_rate(rate); |
| 1744 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) |
| 1745 | return round_dsiescclk_rate(rate); |
| 1746 | else |
| 1747 | return (long)prcmu_clock_rate(clock); |
| 1748 | } |
| 1749 | |
| 1750 | static void set_clock_rate(u8 clock, unsigned long rate) |
| 1751 | { |
| 1752 | u32 val; |
| 1753 | u32 div; |
| 1754 | unsigned long src_rate; |
| 1755 | unsigned long flags; |
| 1756 | |
| 1757 | spin_lock_irqsave(&clk_mgt_lock, flags); |
| 1758 | |
| 1759 | /* Grab the HW semaphore. */ |
| 1760 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
| 1761 | cpu_relax(); |
| 1762 | |
Linus Walleij | b047d98 | 2013-03-19 14:21:47 +0100 | [diff] [blame] | 1763 | val = readl(prcmu_base + clk_mgt[clock].offset); |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1764 | src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), |
| 1765 | clk_mgt[clock].branch); |
| 1766 | div = clock_divider(src_rate, rate); |
| 1767 | if (val & PRCM_CLK_MGT_CLK38) { |
| 1768 | if (clk_mgt[clock].clk38div) { |
| 1769 | if (div > 1) |
| 1770 | val |= PRCM_CLK_MGT_CLK38DIV; |
| 1771 | else |
| 1772 | val &= ~PRCM_CLK_MGT_CLK38DIV; |
| 1773 | } |
| 1774 | } else if (clock == PRCMU_SGACLK) { |
| 1775 | val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK | |
| 1776 | PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN); |
| 1777 | if (div == 3) { |
| 1778 | u64 r = (src_rate * 10); |
| 1779 | |
| 1780 | (void)do_div(r, 25); |
| 1781 | if (r <= rate) { |
| 1782 | val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN; |
| 1783 | div = 0; |
| 1784 | } |
| 1785 | } |
| 1786 | val |= min(div, (u32)31); |
| 1787 | } else { |
| 1788 | val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK; |
| 1789 | val |= min(div, (u32)31); |
| 1790 | } |
Linus Walleij | b047d98 | 2013-03-19 14:21:47 +0100 | [diff] [blame] | 1791 | writel(val, prcmu_base + clk_mgt[clock].offset); |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1792 | |
| 1793 | /* Release the HW semaphore. */ |
| 1794 | writel(0, PRCM_SEM); |
| 1795 | |
| 1796 | spin_unlock_irqrestore(&clk_mgt_lock, flags); |
| 1797 | } |
| 1798 | |
Ulf Hansson | b2302c8 | 2012-10-10 13:42:26 +0200 | [diff] [blame] | 1799 | static int set_armss_rate(unsigned long rate) |
| 1800 | { |
Linus Walleij | 836a1e2 | 2017-08-22 15:17:40 +0200 | [diff] [blame] | 1801 | unsigned long freq; |
| 1802 | u8 opps[] = { ARM_EXTCLK, ARM_50_OPP, ARM_100_OPP, ARM_MAX_OPP }; |
Linus Walleij | fea3ac5 | 2019-08-29 13:25:01 +0200 | [diff] [blame] | 1803 | const unsigned long *freqs; |
| 1804 | int nfreqs; |
Linus Walleij | 836a1e2 | 2017-08-22 15:17:40 +0200 | [diff] [blame] | 1805 | int i; |
Ulf Hansson | b2302c8 | 2012-10-10 13:42:26 +0200 | [diff] [blame] | 1806 | |
Linus Walleij | fea3ac5 | 2019-08-29 13:25:01 +0200 | [diff] [blame] | 1807 | if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) { |
| 1808 | freqs = db8520_armss_freqs; |
| 1809 | nfreqs = ARRAY_SIZE(db8520_armss_freqs); |
| 1810 | } else { |
| 1811 | freqs = db8500_armss_freqs; |
| 1812 | nfreqs = ARRAY_SIZE(db8500_armss_freqs); |
| 1813 | } |
| 1814 | |
Ulf Hansson | b2302c8 | 2012-10-10 13:42:26 +0200 | [diff] [blame] | 1815 | /* Find the corresponding arm opp from the cpufreq table. */ |
Linus Walleij | fea3ac5 | 2019-08-29 13:25:01 +0200 | [diff] [blame] | 1816 | for (i = 0; i < nfreqs; i++) { |
| 1817 | freq = freqs[i]; |
Linus Walleij | 836a1e2 | 2017-08-22 15:17:40 +0200 | [diff] [blame] | 1818 | if (rate == freq) |
Ulf Hansson | b2302c8 | 2012-10-10 13:42:26 +0200 | [diff] [blame] | 1819 | break; |
Linus Walleij | 836a1e2 | 2017-08-22 15:17:40 +0200 | [diff] [blame] | 1820 | } |
Ulf Hansson | b2302c8 | 2012-10-10 13:42:26 +0200 | [diff] [blame] | 1821 | |
Linus Walleij | 836a1e2 | 2017-08-22 15:17:40 +0200 | [diff] [blame] | 1822 | if (rate != freq) |
Ulf Hansson | b2302c8 | 2012-10-10 13:42:26 +0200 | [diff] [blame] | 1823 | return -EINVAL; |
| 1824 | |
| 1825 | /* Set the new arm opp. */ |
Linus Walleij | 836a1e2 | 2017-08-22 15:17:40 +0200 | [diff] [blame] | 1826 | pr_debug("SET ARM OPP 0x%02x\n", opps[i]); |
| 1827 | return db8500_prcmu_set_arm_opp(opps[i]); |
Ulf Hansson | b2302c8 | 2012-10-10 13:42:26 +0200 | [diff] [blame] | 1828 | } |
| 1829 | |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1830 | static int set_plldsi_rate(unsigned long rate) |
| 1831 | { |
| 1832 | unsigned long src_rate; |
| 1833 | unsigned long rem; |
| 1834 | u32 pll_freq = 0; |
| 1835 | u32 r; |
| 1836 | |
| 1837 | src_rate = clock_rate(PRCMU_HDMICLK); |
| 1838 | rem = rate; |
| 1839 | |
| 1840 | for (r = 7; (rem > 0) && (r > 0); r--) { |
| 1841 | u64 d; |
| 1842 | u64 hwrate; |
| 1843 | |
| 1844 | d = (r * rate); |
| 1845 | (void)do_div(d, src_rate); |
| 1846 | if (d < 6) |
| 1847 | d = 6; |
| 1848 | else if (d > 255) |
| 1849 | d = 255; |
| 1850 | hwrate = (d * src_rate); |
| 1851 | if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) || |
| 1852 | ((r * MAX_PLL_VCO_RATE) < (2 * hwrate))) |
| 1853 | continue; |
| 1854 | (void)do_div(hwrate, r); |
| 1855 | if (rate < hwrate) { |
| 1856 | if (pll_freq == 0) |
| 1857 | pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | |
| 1858 | (r << PRCM_PLL_FREQ_R_SHIFT)); |
| 1859 | break; |
| 1860 | } |
| 1861 | if ((rate - hwrate) < rem) { |
| 1862 | rem = (rate - hwrate); |
| 1863 | pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | |
| 1864 | (r << PRCM_PLL_FREQ_R_SHIFT)); |
| 1865 | } |
| 1866 | } |
| 1867 | if (pll_freq == 0) |
| 1868 | return -EINVAL; |
| 1869 | |
| 1870 | pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT); |
| 1871 | writel(pll_freq, PRCM_PLLDSI_FREQ); |
| 1872 | |
| 1873 | return 0; |
| 1874 | } |
| 1875 | |
| 1876 | static void set_dsiclk_rate(u8 n, unsigned long rate) |
| 1877 | { |
| 1878 | u32 val; |
| 1879 | u32 div; |
| 1880 | |
| 1881 | div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ, |
| 1882 | clock_rate(PRCMU_HDMICLK), PLL_RAW), rate); |
| 1883 | |
| 1884 | dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : |
| 1885 | (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 : |
| 1886 | /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4; |
| 1887 | |
| 1888 | val = readl(PRCM_DSI_PLLOUT_SEL); |
| 1889 | val &= ~dsiclk[n].divsel_mask; |
| 1890 | val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); |
| 1891 | writel(val, PRCM_DSI_PLLOUT_SEL); |
| 1892 | } |
| 1893 | |
| 1894 | static void set_dsiescclk_rate(u8 n, unsigned long rate) |
| 1895 | { |
| 1896 | u32 val; |
| 1897 | u32 div; |
| 1898 | |
| 1899 | div = clock_divider(clock_rate(PRCMU_TVCLK), rate); |
| 1900 | val = readl(PRCM_DSITVCLK_DIV); |
| 1901 | val &= ~dsiescclk[n].div_mask; |
| 1902 | val |= (min(div, (u32)255) << dsiescclk[n].div_shift); |
| 1903 | writel(val, PRCM_DSITVCLK_DIV); |
| 1904 | } |
| 1905 | |
| 1906 | int prcmu_set_clock_rate(u8 clock, unsigned long rate) |
| 1907 | { |
| 1908 | if (clock < PRCMU_NUM_REG_CLOCKS) |
| 1909 | set_clock_rate(clock, rate); |
Ulf Hansson | b2302c8 | 2012-10-10 13:42:26 +0200 | [diff] [blame] | 1910 | else if (clock == PRCMU_ARMSS) |
| 1911 | return set_armss_rate(rate); |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 1912 | else if (clock == PRCMU_PLLDSI) |
| 1913 | return set_plldsi_rate(rate); |
| 1914 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) |
| 1915 | set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate); |
| 1916 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) |
| 1917 | set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate); |
| 1918 | return 0; |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1919 | } |
| 1920 | |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 1921 | int db8500_prcmu_config_esram0_deep_sleep(u8 state) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1922 | { |
| 1923 | if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || |
| 1924 | (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) |
| 1925 | return -EINVAL; |
| 1926 | |
| 1927 | mutex_lock(&mb4_transfer.lock); |
| 1928 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 1929 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1930 | cpu_relax(); |
| 1931 | |
| 1932 | writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); |
| 1933 | writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON), |
| 1934 | (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); |
| 1935 | writeb(DDR_PWR_STATE_ON, |
| 1936 | (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); |
| 1937 | writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); |
| 1938 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 1939 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1940 | wait_for_completion(&mb4_transfer.work); |
| 1941 | |
| 1942 | mutex_unlock(&mb4_transfer.lock); |
| 1943 | |
| 1944 | return 0; |
| 1945 | } |
| 1946 | |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 1947 | int db8500_prcmu_config_hotdog(u8 threshold) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1948 | { |
| 1949 | mutex_lock(&mb4_transfer.lock); |
| 1950 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 1951 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1952 | cpu_relax(); |
| 1953 | |
| 1954 | writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); |
| 1955 | writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); |
| 1956 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 1957 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1958 | wait_for_completion(&mb4_transfer.work); |
| 1959 | |
| 1960 | mutex_unlock(&mb4_transfer.lock); |
| 1961 | |
| 1962 | return 0; |
| 1963 | } |
| 1964 | |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 1965 | int db8500_prcmu_config_hotmon(u8 low, u8 high) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1966 | { |
| 1967 | mutex_lock(&mb4_transfer.lock); |
| 1968 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 1969 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1970 | cpu_relax(); |
| 1971 | |
| 1972 | writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); |
| 1973 | writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); |
| 1974 | writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH), |
| 1975 | (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); |
| 1976 | writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); |
| 1977 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 1978 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1979 | wait_for_completion(&mb4_transfer.work); |
| 1980 | |
| 1981 | mutex_unlock(&mb4_transfer.lock); |
| 1982 | |
| 1983 | return 0; |
| 1984 | } |
Arnd Bergmann | 26716ce | 2016-01-25 17:44:12 +0100 | [diff] [blame] | 1985 | EXPORT_SYMBOL_GPL(db8500_prcmu_config_hotmon); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1986 | |
| 1987 | static int config_hot_period(u16 val) |
| 1988 | { |
| 1989 | mutex_lock(&mb4_transfer.lock); |
| 1990 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 1991 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1992 | cpu_relax(); |
| 1993 | |
| 1994 | writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); |
| 1995 | writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); |
| 1996 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 1997 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 1998 | wait_for_completion(&mb4_transfer.work); |
| 1999 | |
| 2000 | mutex_unlock(&mb4_transfer.lock); |
| 2001 | |
| 2002 | return 0; |
| 2003 | } |
| 2004 | |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 2005 | int db8500_prcmu_start_temp_sense(u16 cycles32k) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2006 | { |
| 2007 | if (cycles32k == 0xFFFF) |
| 2008 | return -EINVAL; |
| 2009 | |
| 2010 | return config_hot_period(cycles32k); |
| 2011 | } |
Arnd Bergmann | 26716ce | 2016-01-25 17:44:12 +0100 | [diff] [blame] | 2012 | EXPORT_SYMBOL_GPL(db8500_prcmu_start_temp_sense); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2013 | |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 2014 | int db8500_prcmu_stop_temp_sense(void) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2015 | { |
| 2016 | return config_hot_period(0xFFFF); |
| 2017 | } |
Arnd Bergmann | 26716ce | 2016-01-25 17:44:12 +0100 | [diff] [blame] | 2018 | EXPORT_SYMBOL_GPL(db8500_prcmu_stop_temp_sense); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2019 | |
Jonas Aberg | 84165b8 | 2011-08-12 10:28:33 +0200 | [diff] [blame] | 2020 | static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3) |
| 2021 | { |
| 2022 | |
| 2023 | mutex_lock(&mb4_transfer.lock); |
| 2024 | |
| 2025 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
| 2026 | cpu_relax(); |
| 2027 | |
| 2028 | writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0)); |
| 2029 | writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1)); |
| 2030 | writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2)); |
| 2031 | writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3)); |
| 2032 | |
| 2033 | writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); |
| 2034 | |
| 2035 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
| 2036 | wait_for_completion(&mb4_transfer.work); |
| 2037 | |
| 2038 | mutex_unlock(&mb4_transfer.lock); |
| 2039 | |
| 2040 | return 0; |
| 2041 | |
| 2042 | } |
| 2043 | |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 2044 | int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) |
Jonas Aberg | 84165b8 | 2011-08-12 10:28:33 +0200 | [diff] [blame] | 2045 | { |
| 2046 | BUG_ON(num == 0 || num > 0xf); |
| 2047 | return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0, |
| 2048 | sleep_auto_off ? A9WDOG_AUTO_OFF_EN : |
| 2049 | A9WDOG_AUTO_OFF_DIS); |
| 2050 | } |
Fabio Baltieri | 6f8cfa9 | 2013-01-18 12:40:12 +0100 | [diff] [blame] | 2051 | EXPORT_SYMBOL(db8500_prcmu_config_a9wdog); |
Jonas Aberg | 84165b8 | 2011-08-12 10:28:33 +0200 | [diff] [blame] | 2052 | |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 2053 | int db8500_prcmu_enable_a9wdog(u8 id) |
Jonas Aberg | 84165b8 | 2011-08-12 10:28:33 +0200 | [diff] [blame] | 2054 | { |
| 2055 | return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0); |
| 2056 | } |
Fabio Baltieri | 6f8cfa9 | 2013-01-18 12:40:12 +0100 | [diff] [blame] | 2057 | EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog); |
Jonas Aberg | 84165b8 | 2011-08-12 10:28:33 +0200 | [diff] [blame] | 2058 | |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 2059 | int db8500_prcmu_disable_a9wdog(u8 id) |
Jonas Aberg | 84165b8 | 2011-08-12 10:28:33 +0200 | [diff] [blame] | 2060 | { |
| 2061 | return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0); |
| 2062 | } |
Fabio Baltieri | 6f8cfa9 | 2013-01-18 12:40:12 +0100 | [diff] [blame] | 2063 | EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog); |
Jonas Aberg | 84165b8 | 2011-08-12 10:28:33 +0200 | [diff] [blame] | 2064 | |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 2065 | int db8500_prcmu_kick_a9wdog(u8 id) |
Jonas Aberg | 84165b8 | 2011-08-12 10:28:33 +0200 | [diff] [blame] | 2066 | { |
| 2067 | return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0); |
| 2068 | } |
Fabio Baltieri | 6f8cfa9 | 2013-01-18 12:40:12 +0100 | [diff] [blame] | 2069 | EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog); |
Jonas Aberg | 84165b8 | 2011-08-12 10:28:33 +0200 | [diff] [blame] | 2070 | |
| 2071 | /* |
| 2072 | * timeout is 28 bit, in ms. |
| 2073 | */ |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 2074 | int db8500_prcmu_load_a9wdog(u8 id, u32 timeout) |
Jonas Aberg | 84165b8 | 2011-08-12 10:28:33 +0200 | [diff] [blame] | 2075 | { |
Jonas Aberg | 84165b8 | 2011-08-12 10:28:33 +0200 | [diff] [blame] | 2076 | return prcmu_a9wdog(MB4H_A9WDOG_LOAD, |
| 2077 | (id & A9WDOG_ID_MASK) | |
| 2078 | /* |
| 2079 | * Put the lowest 28 bits of timeout at |
| 2080 | * offset 4. Four first bits are used for id. |
| 2081 | */ |
| 2082 | (u8)((timeout << 4) & 0xf0), |
| 2083 | (u8)((timeout >> 4) & 0xff), |
| 2084 | (u8)((timeout >> 12) & 0xff), |
| 2085 | (u8)((timeout >> 20) & 0xff)); |
| 2086 | } |
Fabio Baltieri | 6f8cfa9 | 2013-01-18 12:40:12 +0100 | [diff] [blame] | 2087 | EXPORT_SYMBOL(db8500_prcmu_load_a9wdog); |
Jonas Aberg | 84165b8 | 2011-08-12 10:28:33 +0200 | [diff] [blame] | 2088 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2089 | /** |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2090 | * prcmu_abb_read() - Read register value(s) from the ABB. |
| 2091 | * @slave: The I2C slave address. |
| 2092 | * @reg: The (start) register address. |
| 2093 | * @value: The read out value(s). |
| 2094 | * @size: The number of registers to read. |
| 2095 | * |
| 2096 | * Reads register value(s) from the ABB. |
| 2097 | * @size has to be 1 for the current firmware version. |
| 2098 | */ |
| 2099 | int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) |
| 2100 | { |
| 2101 | int r; |
| 2102 | |
| 2103 | if (size != 1) |
| 2104 | return -EINVAL; |
| 2105 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2106 | mutex_lock(&mb5_transfer.lock); |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2107 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2108 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2109 | cpu_relax(); |
| 2110 | |
Mattias Nilsson | 3c3e489 | 2012-03-08 14:02:05 +0100 | [diff] [blame] | 2111 | writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2112 | writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); |
| 2113 | writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); |
| 2114 | writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); |
| 2115 | writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2116 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2117 | writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2118 | |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2119 | if (!wait_for_completion_timeout(&mb5_transfer.work, |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2120 | msecs_to_jiffies(20000))) { |
| 2121 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", |
| 2122 | __func__); |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2123 | r = -EIO; |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2124 | } else { |
| 2125 | r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2126 | } |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2127 | |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2128 | if (!r) |
| 2129 | *value = mb5_transfer.ack.value; |
| 2130 | |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2131 | mutex_unlock(&mb5_transfer.lock); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2132 | |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2133 | return r; |
| 2134 | } |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2135 | |
| 2136 | /** |
Mattias Nilsson | 3c3e489 | 2012-03-08 14:02:05 +0100 | [diff] [blame] | 2137 | * prcmu_abb_write_masked() - Write masked register value(s) to the ABB. |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2138 | * @slave: The I2C slave address. |
| 2139 | * @reg: The (start) register address. |
| 2140 | * @value: The value(s) to write. |
Mattias Nilsson | 3c3e489 | 2012-03-08 14:02:05 +0100 | [diff] [blame] | 2141 | * @mask: The mask(s) to use. |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2142 | * @size: The number of registers to write. |
| 2143 | * |
Mattias Nilsson | 3c3e489 | 2012-03-08 14:02:05 +0100 | [diff] [blame] | 2144 | * Writes masked register value(s) to the ABB. |
| 2145 | * For each @value, only the bits set to 1 in the corresponding @mask |
| 2146 | * will be written. The other bits are not changed. |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2147 | * @size has to be 1 for the current firmware version. |
| 2148 | */ |
Mattias Nilsson | 3c3e489 | 2012-03-08 14:02:05 +0100 | [diff] [blame] | 2149 | int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size) |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2150 | { |
| 2151 | int r; |
| 2152 | |
| 2153 | if (size != 1) |
| 2154 | return -EINVAL; |
| 2155 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2156 | mutex_lock(&mb5_transfer.lock); |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2157 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2158 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2159 | cpu_relax(); |
| 2160 | |
Mattias Nilsson | 3c3e489 | 2012-03-08 14:02:05 +0100 | [diff] [blame] | 2161 | writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2162 | writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); |
| 2163 | writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); |
| 2164 | writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); |
| 2165 | writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2166 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2167 | writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2168 | |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2169 | if (!wait_for_completion_timeout(&mb5_transfer.work, |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2170 | msecs_to_jiffies(20000))) { |
| 2171 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", |
| 2172 | __func__); |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2173 | r = -EIO; |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2174 | } else { |
| 2175 | r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2176 | } |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2177 | |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2178 | mutex_unlock(&mb5_transfer.lock); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2179 | |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2180 | return r; |
| 2181 | } |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2182 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2183 | /** |
Mattias Nilsson | 3c3e489 | 2012-03-08 14:02:05 +0100 | [diff] [blame] | 2184 | * prcmu_abb_write() - Write register value(s) to the ABB. |
| 2185 | * @slave: The I2C slave address. |
| 2186 | * @reg: The (start) register address. |
| 2187 | * @value: The value(s) to write. |
| 2188 | * @size: The number of registers to write. |
| 2189 | * |
| 2190 | * Writes register value(s) to the ABB. |
| 2191 | * @size has to be 1 for the current firmware version. |
| 2192 | */ |
| 2193 | int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) |
| 2194 | { |
| 2195 | u8 mask = ~0; |
| 2196 | |
| 2197 | return prcmu_abb_write_masked(slave, reg, value, &mask, size); |
| 2198 | } |
| 2199 | |
| 2200 | /** |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2201 | * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem |
| 2202 | */ |
Arun Murthy | 5261e10 | 2012-05-21 14:28:21 +0530 | [diff] [blame] | 2203 | int prcmu_ac_wake_req(void) |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 2204 | { |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2205 | u32 val; |
Arun Murthy | 5261e10 | 2012-05-21 14:28:21 +0530 | [diff] [blame] | 2206 | int ret = 0; |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 2207 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2208 | mutex_lock(&mb0_transfer.ac_wake_lock); |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 2209 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2210 | val = readl(PRCM_HOSTACCESS_REQ); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2211 | if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) |
| 2212 | goto unlock_and_return; |
| 2213 | |
| 2214 | atomic_set(&ac_wake_req_state, 1); |
| 2215 | |
Arun Murthy | 5261e10 | 2012-05-21 14:28:21 +0530 | [diff] [blame] | 2216 | /* |
| 2217 | * Force Modem Wake-up before hostaccess_req ping-pong. |
| 2218 | * It prevents Modem to enter in Sleep while acking the hostaccess |
| 2219 | * request. The 31us delay has been calculated by HWI. |
| 2220 | */ |
| 2221 | val |= PRCM_HOSTACCESS_REQ_WAKE_REQ; |
| 2222 | writel(val, PRCM_HOSTACCESS_REQ); |
| 2223 | |
| 2224 | udelay(31); |
| 2225 | |
| 2226 | val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ; |
| 2227 | writel(val, PRCM_HOSTACCESS_REQ); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2228 | |
| 2229 | if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, |
Mattias Nilsson | d6e3002 | 2011-08-12 10:28:43 +0200 | [diff] [blame] | 2230 | msecs_to_jiffies(5000))) { |
Linus Walleij | 57265bc | 2011-10-10 13:04:44 +0200 | [diff] [blame] | 2231 | pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", |
Mattias Nilsson | d6e3002 | 2011-08-12 10:28:43 +0200 | [diff] [blame] | 2232 | __func__); |
Arun Murthy | 5261e10 | 2012-05-21 14:28:21 +0530 | [diff] [blame] | 2233 | ret = -EFAULT; |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2234 | } |
| 2235 | |
| 2236 | unlock_and_return: |
| 2237 | mutex_unlock(&mb0_transfer.ac_wake_lock); |
Arun Murthy | 5261e10 | 2012-05-21 14:28:21 +0530 | [diff] [blame] | 2238 | return ret; |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2239 | } |
| 2240 | |
| 2241 | /** |
| 2242 | * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem |
| 2243 | */ |
Sachin Kamat | ffb0116 | 2013-08-23 17:05:19 +0530 | [diff] [blame] | 2244 | void prcmu_ac_sleep_req(void) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2245 | { |
| 2246 | u32 val; |
| 2247 | |
| 2248 | mutex_lock(&mb0_transfer.ac_wake_lock); |
| 2249 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2250 | val = readl(PRCM_HOSTACCESS_REQ); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2251 | if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) |
| 2252 | goto unlock_and_return; |
| 2253 | |
| 2254 | writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2255 | PRCM_HOSTACCESS_REQ); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2256 | |
| 2257 | if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, |
Mattias Nilsson | d6e3002 | 2011-08-12 10:28:43 +0200 | [diff] [blame] | 2258 | msecs_to_jiffies(5000))) { |
Linus Walleij | 57265bc | 2011-10-10 13:04:44 +0200 | [diff] [blame] | 2259 | pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2260 | __func__); |
| 2261 | } |
| 2262 | |
| 2263 | atomic_set(&ac_wake_req_state, 0); |
| 2264 | |
| 2265 | unlock_and_return: |
| 2266 | mutex_unlock(&mb0_transfer.ac_wake_lock); |
| 2267 | } |
| 2268 | |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 2269 | bool db8500_prcmu_is_ac_wake_requested(void) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2270 | { |
| 2271 | return (atomic_read(&ac_wake_req_state) != 0); |
| 2272 | } |
| 2273 | |
| 2274 | /** |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 2275 | * db8500_prcmu_system_reset - System reset |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2276 | * |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 2277 | * Saves the reset reason code and then sets the APE_SOFTRST register which |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2278 | * fires interrupt to fw |
Lee Jones | 3ecbcd2 | 2020-06-24 09:34:00 +0100 | [diff] [blame] | 2279 | * |
| 2280 | * @reset_code: The reason for system reset |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2281 | */ |
Mattias Nilsson | 73180f8 | 2011-08-12 10:28:10 +0200 | [diff] [blame] | 2282 | void db8500_prcmu_system_reset(u16 reset_code) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2283 | { |
| 2284 | writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2285 | writel(1, PRCM_APE_SOFTRST); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2286 | } |
| 2287 | |
| 2288 | /** |
Sebastian Rasmussen | 597045d | 2011-08-12 10:28:53 +0200 | [diff] [blame] | 2289 | * db8500_prcmu_get_reset_code - Retrieve SW reset reason code |
| 2290 | * |
| 2291 | * Retrieves the reset reason code stored by prcmu_system_reset() before |
| 2292 | * last restart. |
| 2293 | */ |
| 2294 | u16 db8500_prcmu_get_reset_code(void) |
| 2295 | { |
| 2296 | return readw(tcdm_base + PRCM_SW_RST_REASON); |
| 2297 | } |
| 2298 | |
| 2299 | /** |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 2300 | * db8500_prcmu_reset_modem - ask the PRCMU to reset modem |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2301 | */ |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 2302 | void db8500_prcmu_modem_reset(void) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2303 | { |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 2304 | mutex_lock(&mb1_transfer.lock); |
| 2305 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2306 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 2307 | cpu_relax(); |
| 2308 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2309 | writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2310 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 2311 | wait_for_completion(&mb1_transfer.work); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2312 | |
| 2313 | /* |
| 2314 | * No need to check return from PRCMU as modem should go in reset state |
| 2315 | * This state is already managed by upper layer |
| 2316 | */ |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 2317 | |
| 2318 | mutex_unlock(&mb1_transfer.lock); |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 2319 | } |
| 2320 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2321 | static void ack_dbb_wakeup(void) |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 2322 | { |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2323 | unsigned long flags; |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 2324 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2325 | spin_lock_irqsave(&mb0_transfer.lock, flags); |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 2326 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2327 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2328 | cpu_relax(); |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 2329 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2330 | writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2331 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 2332 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2333 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 2334 | } |
| 2335 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2336 | static inline void print_unknown_header_warning(u8 n, u8 header) |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2337 | { |
Joe Perches | 81d30ed | 2017-02-16 23:11:36 -0800 | [diff] [blame] | 2338 | pr_warn("prcmu: Unknown message header (%d) in mailbox %d\n", |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2339 | header, n); |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2340 | } |
| 2341 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2342 | static bool read_mailbox_0(void) |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2343 | { |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2344 | bool r; |
| 2345 | u32 ev; |
| 2346 | unsigned int n; |
| 2347 | u8 header; |
| 2348 | |
| 2349 | header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); |
| 2350 | switch (header) { |
| 2351 | case MB0H_WAKEUP_EXE: |
| 2352 | case MB0H_WAKEUP_SLEEP: |
| 2353 | if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) |
| 2354 | ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); |
| 2355 | else |
| 2356 | ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); |
| 2357 | |
| 2358 | if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK)) |
| 2359 | complete(&mb0_transfer.ac_wake_work); |
| 2360 | if (ev & WAKEUP_BIT_SYSCLK_OK) |
| 2361 | complete(&mb3_transfer.sysclk_work); |
| 2362 | |
| 2363 | ev &= mb0_transfer.req.dbb_irqs; |
| 2364 | |
| 2365 | for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) { |
| 2366 | if (ev & prcmu_irq_bit[n]) |
Linus Walleij | 89d9b1c | 2012-12-20 10:20:15 +0100 | [diff] [blame] | 2367 | generic_handle_irq(irq_find_mapping(db8500_irq_domain, n)); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2368 | } |
| 2369 | r = true; |
| 2370 | break; |
| 2371 | default: |
| 2372 | print_unknown_header_warning(0, header); |
| 2373 | r = false; |
| 2374 | break; |
| 2375 | } |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2376 | writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2377 | return r; |
| 2378 | } |
| 2379 | |
| 2380 | static bool read_mailbox_1(void) |
| 2381 | { |
| 2382 | mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); |
| 2383 | mb1_transfer.ack.arm_opp = readb(tcdm_base + |
| 2384 | PRCM_ACK_MB1_CURRENT_ARM_OPP); |
| 2385 | mb1_transfer.ack.ape_opp = readb(tcdm_base + |
| 2386 | PRCM_ACK_MB1_CURRENT_APE_OPP); |
| 2387 | mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + |
| 2388 | PRCM_ACK_MB1_APE_VOLTAGE_STATUS); |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2389 | writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 2390 | complete(&mb1_transfer.work); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2391 | return false; |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2392 | } |
| 2393 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2394 | static bool read_mailbox_2(void) |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2395 | { |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2396 | mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2397 | writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2398 | complete(&mb2_transfer.work); |
| 2399 | return false; |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2400 | } |
| 2401 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2402 | static bool read_mailbox_3(void) |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2403 | { |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2404 | writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2405 | return false; |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2406 | } |
| 2407 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2408 | static bool read_mailbox_4(void) |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2409 | { |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2410 | u8 header; |
| 2411 | bool do_complete = true; |
| 2412 | |
| 2413 | header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); |
| 2414 | switch (header) { |
| 2415 | case MB4H_MEM_ST: |
| 2416 | case MB4H_HOTDOG: |
| 2417 | case MB4H_HOTMON: |
| 2418 | case MB4H_HOT_PERIOD: |
Mattias Nilsson | a592c2e | 2011-08-12 10:27:41 +0200 | [diff] [blame] | 2419 | case MB4H_A9WDOG_CONF: |
| 2420 | case MB4H_A9WDOG_EN: |
| 2421 | case MB4H_A9WDOG_DIS: |
| 2422 | case MB4H_A9WDOG_LOAD: |
| 2423 | case MB4H_A9WDOG_KICK: |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2424 | break; |
| 2425 | default: |
| 2426 | print_unknown_header_warning(4, header); |
| 2427 | do_complete = false; |
| 2428 | break; |
| 2429 | } |
| 2430 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2431 | writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2432 | |
| 2433 | if (do_complete) |
| 2434 | complete(&mb4_transfer.work); |
| 2435 | |
| 2436 | return false; |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2437 | } |
| 2438 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2439 | static bool read_mailbox_5(void) |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2440 | { |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2441 | mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); |
| 2442 | mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2443 | writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2444 | complete(&mb5_transfer.work); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2445 | return false; |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2446 | } |
| 2447 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2448 | static bool read_mailbox_6(void) |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2449 | { |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2450 | writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2451 | return false; |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2452 | } |
| 2453 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2454 | static bool read_mailbox_7(void) |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2455 | { |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2456 | writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2457 | return false; |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2458 | } |
| 2459 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2460 | static bool (* const read_mailbox[NUM_MB])(void) = { |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2461 | read_mailbox_0, |
| 2462 | read_mailbox_1, |
| 2463 | read_mailbox_2, |
| 2464 | read_mailbox_3, |
| 2465 | read_mailbox_4, |
| 2466 | read_mailbox_5, |
| 2467 | read_mailbox_6, |
| 2468 | read_mailbox_7 |
| 2469 | }; |
| 2470 | |
| 2471 | static irqreturn_t prcmu_irq_handler(int irq, void *data) |
| 2472 | { |
| 2473 | u32 bits; |
| 2474 | u8 n; |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2475 | irqreturn_t r; |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2476 | |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 2477 | bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS); |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2478 | if (unlikely(!bits)) |
| 2479 | return IRQ_NONE; |
| 2480 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2481 | r = IRQ_HANDLED; |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2482 | for (n = 0; bits; n++) { |
| 2483 | if (bits & MBOX_BIT(n)) { |
| 2484 | bits -= MBOX_BIT(n); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2485 | if (read_mailbox[n]()) |
| 2486 | r = IRQ_WAKE_THREAD; |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2487 | } |
| 2488 | } |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2489 | return r; |
| 2490 | } |
| 2491 | |
| 2492 | static irqreturn_t prcmu_irq_thread_fn(int irq, void *data) |
| 2493 | { |
| 2494 | ack_dbb_wakeup(); |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2495 | return IRQ_HANDLED; |
| 2496 | } |
| 2497 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2498 | static void prcmu_mask_work(struct work_struct *work) |
| 2499 | { |
| 2500 | unsigned long flags; |
| 2501 | |
| 2502 | spin_lock_irqsave(&mb0_transfer.lock, flags); |
| 2503 | |
| 2504 | config_wakeups(); |
| 2505 | |
| 2506 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); |
| 2507 | } |
| 2508 | |
| 2509 | static void prcmu_irq_mask(struct irq_data *d) |
| 2510 | { |
| 2511 | unsigned long flags; |
| 2512 | |
| 2513 | spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); |
| 2514 | |
Lee Jones | f3f1f0a | 2012-09-24 09:11:46 +0100 | [diff] [blame] | 2515 | mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq]; |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2516 | |
| 2517 | spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); |
| 2518 | |
| 2519 | if (d->irq != IRQ_PRCMU_CA_SLEEP) |
| 2520 | schedule_work(&mb0_transfer.mask_work); |
| 2521 | } |
| 2522 | |
| 2523 | static void prcmu_irq_unmask(struct irq_data *d) |
| 2524 | { |
| 2525 | unsigned long flags; |
| 2526 | |
| 2527 | spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); |
| 2528 | |
Lee Jones | f3f1f0a | 2012-09-24 09:11:46 +0100 | [diff] [blame] | 2529 | mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq]; |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2530 | |
| 2531 | spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); |
| 2532 | |
| 2533 | if (d->irq != IRQ_PRCMU_CA_SLEEP) |
| 2534 | schedule_work(&mb0_transfer.mask_work); |
| 2535 | } |
| 2536 | |
| 2537 | static void noop(struct irq_data *d) |
| 2538 | { |
| 2539 | } |
| 2540 | |
| 2541 | static struct irq_chip prcmu_irq_chip = { |
| 2542 | .name = "prcmu", |
| 2543 | .irq_disable = prcmu_irq_mask, |
| 2544 | .irq_ack = noop, |
| 2545 | .irq_mask = prcmu_irq_mask, |
| 2546 | .irq_unmask = prcmu_irq_unmask, |
| 2547 | }; |
| 2548 | |
Nathan Chancellor | a3888f6 | 2018-10-17 17:56:28 -0700 | [diff] [blame] | 2549 | static char *fw_project_name(u32 project) |
Mattias Nilsson | b58d12f | 2012-01-13 16:20:10 +0100 | [diff] [blame] | 2550 | { |
| 2551 | switch (project) { |
| 2552 | case PRCMU_FW_PROJECT_U8500: |
| 2553 | return "U8500"; |
Linus Walleij | 05ec260 | 2013-02-07 10:17:31 +0100 | [diff] [blame] | 2554 | case PRCMU_FW_PROJECT_U8400: |
| 2555 | return "U8400"; |
Mattias Nilsson | b58d12f | 2012-01-13 16:20:10 +0100 | [diff] [blame] | 2556 | case PRCMU_FW_PROJECT_U9500: |
| 2557 | return "U9500"; |
Linus Walleij | 05ec260 | 2013-02-07 10:17:31 +0100 | [diff] [blame] | 2558 | case PRCMU_FW_PROJECT_U8500_MBB: |
| 2559 | return "U8500 MBB"; |
| 2560 | case PRCMU_FW_PROJECT_U8500_C1: |
| 2561 | return "U8500 C1"; |
| 2562 | case PRCMU_FW_PROJECT_U8500_C2: |
| 2563 | return "U8500 C2"; |
| 2564 | case PRCMU_FW_PROJECT_U8500_C3: |
| 2565 | return "U8500 C3"; |
| 2566 | case PRCMU_FW_PROJECT_U8500_C4: |
| 2567 | return "U8500 C4"; |
| 2568 | case PRCMU_FW_PROJECT_U9500_MBL: |
| 2569 | return "U9500 MBL"; |
| 2570 | case PRCMU_FW_PROJECT_U8500_MBL: |
| 2571 | return "U8500 MBL"; |
| 2572 | case PRCMU_FW_PROJECT_U8500_MBL2: |
| 2573 | return "U8500 MBL2"; |
Bengt Jonsson | 5f96a1a6 | 2012-03-15 19:50:40 +0100 | [diff] [blame] | 2574 | case PRCMU_FW_PROJECT_U8520: |
Linus Walleij | 05ec260 | 2013-02-07 10:17:31 +0100 | [diff] [blame] | 2575 | return "U8520 MBL"; |
Bengt Jonsson | 1927ddf | 2012-03-15 19:50:51 +0100 | [diff] [blame] | 2576 | case PRCMU_FW_PROJECT_U8420: |
| 2577 | return "U8420"; |
Linus Walleij | 22fb3ad | 2019-10-26 23:47:32 +0200 | [diff] [blame] | 2578 | case PRCMU_FW_PROJECT_U8420_SYSCLK: |
| 2579 | return "U8420-sysclk"; |
Linus Walleij | 05ec260 | 2013-02-07 10:17:31 +0100 | [diff] [blame] | 2580 | case PRCMU_FW_PROJECT_U9540: |
| 2581 | return "U9540"; |
| 2582 | case PRCMU_FW_PROJECT_A9420: |
| 2583 | return "A9420"; |
| 2584 | case PRCMU_FW_PROJECT_L8540: |
| 2585 | return "L8540"; |
| 2586 | case PRCMU_FW_PROJECT_L8580: |
| 2587 | return "L8580"; |
Mattias Nilsson | b58d12f | 2012-01-13 16:20:10 +0100 | [diff] [blame] | 2588 | default: |
| 2589 | return "Unknown"; |
| 2590 | } |
| 2591 | } |
| 2592 | |
Lee Jones | f3f1f0a | 2012-09-24 09:11:46 +0100 | [diff] [blame] | 2593 | static int db8500_irq_map(struct irq_domain *d, unsigned int virq, |
| 2594 | irq_hw_number_t hwirq) |
| 2595 | { |
| 2596 | irq_set_chip_and_handler(virq, &prcmu_irq_chip, |
| 2597 | handle_simple_irq); |
Lee Jones | f3f1f0a | 2012-09-24 09:11:46 +0100 | [diff] [blame] | 2598 | |
| 2599 | return 0; |
| 2600 | } |
| 2601 | |
Krzysztof Kozlowski | 7ce7b26 | 2015-04-27 21:54:13 +0900 | [diff] [blame] | 2602 | static const struct irq_domain_ops db8500_irq_ops = { |
Linus Walleij | 89d9b1c | 2012-12-20 10:20:15 +0100 | [diff] [blame] | 2603 | .map = db8500_irq_map, |
| 2604 | .xlate = irq_domain_xlate_twocell, |
Lee Jones | f3f1f0a | 2012-09-24 09:11:46 +0100 | [diff] [blame] | 2605 | }; |
| 2606 | |
Linus Walleij | f864c46 | 2014-02-04 00:35:56 +0100 | [diff] [blame] | 2607 | static int db8500_irq_init(struct device_node *np) |
Lee Jones | f3f1f0a | 2012-09-24 09:11:46 +0100 | [diff] [blame] | 2608 | { |
Linus Walleij | 89d9b1c | 2012-12-20 10:20:15 +0100 | [diff] [blame] | 2609 | int i; |
Linus Walleij | a7238e4 | 2012-10-18 18:22:11 +0200 | [diff] [blame] | 2610 | |
Linus Walleij | a7238e4 | 2012-10-18 18:22:11 +0200 | [diff] [blame] | 2611 | db8500_irq_domain = irq_domain_add_simple( |
Linus Walleij | f864c46 | 2014-02-04 00:35:56 +0100 | [diff] [blame] | 2612 | np, NUM_PRCMU_WAKEUPS, 0, |
Linus Walleij | a7238e4 | 2012-10-18 18:22:11 +0200 | [diff] [blame] | 2613 | &db8500_irq_ops, NULL); |
Lee Jones | f3f1f0a | 2012-09-24 09:11:46 +0100 | [diff] [blame] | 2614 | |
| 2615 | if (!db8500_irq_domain) { |
| 2616 | pr_err("Failed to create irqdomain\n"); |
| 2617 | return -ENOSYS; |
| 2618 | } |
| 2619 | |
Linus Walleij | 89d9b1c | 2012-12-20 10:20:15 +0100 | [diff] [blame] | 2620 | /* All wakeups will be used, so create mappings for all */ |
| 2621 | for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) |
| 2622 | irq_create_mapping(db8500_irq_domain, i); |
| 2623 | |
Lee Jones | f3f1f0a | 2012-09-24 09:11:46 +0100 | [diff] [blame] | 2624 | return 0; |
| 2625 | } |
| 2626 | |
Linus Walleij | 22fb3ad | 2019-10-26 23:47:32 +0200 | [diff] [blame] | 2627 | static void dbx500_fw_version_init(struct device_node *np) |
Linus Walleij | 05ec260 | 2013-02-07 10:17:31 +0100 | [diff] [blame] | 2628 | { |
Linus Walleij | 05ec260 | 2013-02-07 10:17:31 +0100 | [diff] [blame] | 2629 | void __iomem *tcpm_base; |
Lee Jones | 741cdec | 2013-04-04 11:39:00 +0100 | [diff] [blame] | 2630 | u32 version; |
Linus Walleij | 05ec260 | 2013-02-07 10:17:31 +0100 | [diff] [blame] | 2631 | |
Linus Walleij | 22fb3ad | 2019-10-26 23:47:32 +0200 | [diff] [blame] | 2632 | tcpm_base = of_iomap(np, 1); |
Lee Jones | 741cdec | 2013-04-04 11:39:00 +0100 | [diff] [blame] | 2633 | if (!tcpm_base) { |
Linus Walleij | 22fb3ad | 2019-10-26 23:47:32 +0200 | [diff] [blame] | 2634 | pr_err("no prcmu tcpm mem region provided\n"); |
Lee Jones | 741cdec | 2013-04-04 11:39:00 +0100 | [diff] [blame] | 2635 | return; |
Linus Walleij | 05ec260 | 2013-02-07 10:17:31 +0100 | [diff] [blame] | 2636 | } |
Lee Jones | 741cdec | 2013-04-04 11:39:00 +0100 | [diff] [blame] | 2637 | |
Linus Walleij | 22fb3ad | 2019-10-26 23:47:32 +0200 | [diff] [blame] | 2638 | version = readl(tcpm_base + DB8500_PRCMU_FW_VERSION_OFFSET); |
Lee Jones | 741cdec | 2013-04-04 11:39:00 +0100 | [diff] [blame] | 2639 | fw_info.version.project = (version & 0xFF); |
| 2640 | fw_info.version.api_version = (version >> 8) & 0xFF; |
| 2641 | fw_info.version.func_version = (version >> 16) & 0xFF; |
| 2642 | fw_info.version.errata = (version >> 24) & 0xFF; |
| 2643 | strncpy(fw_info.version.project_name, |
| 2644 | fw_project_name(fw_info.version.project), |
| 2645 | PRCMU_FW_PROJECT_NAME_LEN); |
| 2646 | fw_info.valid = true; |
| 2647 | pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n", |
| 2648 | fw_info.version.project_name, |
| 2649 | fw_info.version.project, |
| 2650 | fw_info.version.api_version, |
| 2651 | fw_info.version.func_version, |
| 2652 | fw_info.version.errata); |
| 2653 | iounmap(tcpm_base); |
Linus Walleij | 05ec260 | 2013-02-07 10:17:31 +0100 | [diff] [blame] | 2654 | } |
| 2655 | |
Linus Walleij | 22fb3ad | 2019-10-26 23:47:32 +0200 | [diff] [blame] | 2656 | void __init db8500_prcmu_early_init(void) |
Mattias Wallin | fcbd458 | 2010-12-02 16:20:42 +0100 | [diff] [blame] | 2657 | { |
Linus Walleij | 9a47a8d | 2013-03-21 12:27:25 +0100 | [diff] [blame] | 2658 | /* |
| 2659 | * This is a temporary remap to bring up the clocks. It is |
| 2660 | * subsequently replaces with a real remap. After the merge of |
| 2661 | * the mailbox subsystem all of this early code goes away, and the |
| 2662 | * clock driver can probe independently. An early initcall will |
| 2663 | * still be needed, but it can be diverted into drivers/clk/ux500. |
| 2664 | */ |
Linus Walleij | 22fb3ad | 2019-10-26 23:47:32 +0200 | [diff] [blame] | 2665 | struct device_node *np; |
| 2666 | |
| 2667 | np = of_find_compatible_node(NULL, NULL, "stericsson,db8500-prcmu"); |
| 2668 | prcmu_base = of_iomap(np, 0); |
| 2669 | if (!prcmu_base) { |
| 2670 | of_node_put(np); |
Linus Walleij | 9a47a8d | 2013-03-21 12:27:25 +0100 | [diff] [blame] | 2671 | pr_err("%s: ioremap() of prcmu registers failed!\n", __func__); |
Linus Walleij | 22fb3ad | 2019-10-26 23:47:32 +0200 | [diff] [blame] | 2672 | return; |
| 2673 | } |
| 2674 | dbx500_fw_version_init(np); |
| 2675 | of_node_put(np); |
Linus Walleij | 9a47a8d | 2013-03-21 12:27:25 +0100 | [diff] [blame] | 2676 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2677 | spin_lock_init(&mb0_transfer.lock); |
| 2678 | spin_lock_init(&mb0_transfer.dbb_irqs_lock); |
| 2679 | mutex_init(&mb0_transfer.ac_wake_lock); |
| 2680 | init_completion(&mb0_transfer.ac_wake_work); |
Martin Persson | e0befb2 | 2010-12-08 15:13:28 +0100 | [diff] [blame] | 2681 | mutex_init(&mb1_transfer.lock); |
| 2682 | init_completion(&mb1_transfer.work); |
Mattias Nilsson | 4d64d2e | 2012-01-13 16:20:43 +0100 | [diff] [blame] | 2683 | mb1_transfer.ape_opp = APE_NO_CHANGE; |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2684 | mutex_init(&mb2_transfer.lock); |
| 2685 | init_completion(&mb2_transfer.work); |
| 2686 | spin_lock_init(&mb2_transfer.auto_pm_lock); |
| 2687 | spin_lock_init(&mb3_transfer.lock); |
| 2688 | mutex_init(&mb3_transfer.sysclk_lock); |
| 2689 | init_completion(&mb3_transfer.sysclk_work); |
| 2690 | mutex_init(&mb4_transfer.lock); |
| 2691 | init_completion(&mb4_transfer.work); |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2692 | mutex_init(&mb5_transfer.lock); |
| 2693 | init_completion(&mb5_transfer.work); |
| 2694 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2695 | INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); |
Linus Walleij | e3726fc | 2010-08-19 12:36:01 +0100 | [diff] [blame] | 2696 | } |
| 2697 | |
Nathan Chancellor | a3888f6 | 2018-10-17 17:56:28 -0700 | [diff] [blame] | 2698 | static void init_prcm_registers(void) |
Mattias Nilsson | d65e12d | 2011-08-12 10:27:50 +0200 | [diff] [blame] | 2699 | { |
| 2700 | u32 val; |
| 2701 | |
| 2702 | val = readl(PRCM_A9PL_FORCE_CLKEN); |
| 2703 | val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN | |
| 2704 | PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN); |
| 2705 | writel(val, (PRCM_A9PL_FORCE_CLKEN)); |
| 2706 | } |
| 2707 | |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2708 | /* |
| 2709 | * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC |
| 2710 | */ |
| 2711 | static struct regulator_consumer_supply db8500_vape_consumers[] = { |
| 2712 | REGULATOR_SUPPLY("v-ape", NULL), |
| 2713 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"), |
| 2714 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"), |
| 2715 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"), |
| 2716 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"), |
Lee Jones | ae840635 | 2012-05-04 19:23:20 +0100 | [diff] [blame] | 2717 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"), |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2718 | /* "v-mmc" changed to "vcore" in the mainline kernel */ |
| 2719 | REGULATOR_SUPPLY("vcore", "sdi0"), |
| 2720 | REGULATOR_SUPPLY("vcore", "sdi1"), |
| 2721 | REGULATOR_SUPPLY("vcore", "sdi2"), |
| 2722 | REGULATOR_SUPPLY("vcore", "sdi3"), |
| 2723 | REGULATOR_SUPPLY("vcore", "sdi4"), |
| 2724 | REGULATOR_SUPPLY("v-dma", "dma40.0"), |
| 2725 | REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"), |
| 2726 | /* "v-uart" changed to "vcore" in the mainline kernel */ |
| 2727 | REGULATOR_SUPPLY("vcore", "uart0"), |
| 2728 | REGULATOR_SUPPLY("vcore", "uart1"), |
| 2729 | REGULATOR_SUPPLY("vcore", "uart2"), |
| 2730 | REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"), |
Bengt Jonsson | 992b133 | 2012-01-13 16:20:36 +0100 | [diff] [blame] | 2731 | REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"), |
Lee Jones | bc36748 | 2012-05-03 11:23:47 +0100 | [diff] [blame] | 2732 | REGULATOR_SUPPLY("vddvario", "smsc911x.0"), |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2733 | }; |
| 2734 | |
| 2735 | static struct regulator_consumer_supply db8500_vsmps2_consumers[] = { |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2736 | REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"), |
| 2737 | /* AV8100 regulator */ |
| 2738 | REGULATOR_SUPPLY("hdmi_1v8", "0-0070"), |
| 2739 | }; |
| 2740 | |
| 2741 | static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = { |
Bengt Jonsson | 992b133 | 2012-01-13 16:20:36 +0100 | [diff] [blame] | 2742 | REGULATOR_SUPPLY("vsupply", "b2r2_bus"), |
Bengt Jonsson | 624e87c | 2011-08-12 10:29:02 +0200 | [diff] [blame] | 2743 | REGULATOR_SUPPLY("vsupply", "mcde"), |
| 2744 | }; |
| 2745 | |
| 2746 | /* SVA MMDSP regulator switch */ |
| 2747 | static struct regulator_consumer_supply db8500_svammdsp_consumers[] = { |
| 2748 | REGULATOR_SUPPLY("sva-mmdsp", "cm_control"), |
| 2749 | }; |
| 2750 | |
| 2751 | /* SVA pipe regulator switch */ |
| 2752 | static struct regulator_consumer_supply db8500_svapipe_consumers[] = { |
| 2753 | REGULATOR_SUPPLY("sva-pipe", "cm_control"), |
| 2754 | }; |
| 2755 | |
| 2756 | /* SIA MMDSP regulator switch */ |
| 2757 | static struct regulator_consumer_supply db8500_siammdsp_consumers[] = { |
| 2758 | REGULATOR_SUPPLY("sia-mmdsp", "cm_control"), |
| 2759 | }; |
| 2760 | |
| 2761 | /* SIA pipe regulator switch */ |
| 2762 | static struct regulator_consumer_supply db8500_siapipe_consumers[] = { |
| 2763 | REGULATOR_SUPPLY("sia-pipe", "cm_control"), |
| 2764 | }; |
| 2765 | |
| 2766 | static struct regulator_consumer_supply db8500_sga_consumers[] = { |
| 2767 | REGULATOR_SUPPLY("v-mali", NULL), |
| 2768 | }; |
| 2769 | |
| 2770 | /* ESRAM1 and 2 regulator switch */ |
| 2771 | static struct regulator_consumer_supply db8500_esram12_consumers[] = { |
| 2772 | REGULATOR_SUPPLY("esram12", "cm_control"), |
| 2773 | }; |
| 2774 | |
| 2775 | /* ESRAM3 and 4 regulator switch */ |
| 2776 | static struct regulator_consumer_supply db8500_esram34_consumers[] = { |
| 2777 | REGULATOR_SUPPLY("v-esram34", "mcde"), |
| 2778 | REGULATOR_SUPPLY("esram34", "cm_control"), |
Bengt Jonsson | 992b133 | 2012-01-13 16:20:36 +0100 | [diff] [blame] | 2779 | REGULATOR_SUPPLY("lcla_esram", "dma40.0"), |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2780 | }; |
| 2781 | |
| 2782 | static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { |
| 2783 | [DB8500_REGULATOR_VAPE] = { |
| 2784 | .constraints = { |
| 2785 | .name = "db8500-vape", |
| 2786 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
Mark Brown | 1e45860 | 2012-04-13 13:11:50 +0100 | [diff] [blame] | 2787 | .always_on = true, |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2788 | }, |
| 2789 | .consumer_supplies = db8500_vape_consumers, |
| 2790 | .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), |
| 2791 | }, |
| 2792 | [DB8500_REGULATOR_VARM] = { |
| 2793 | .constraints = { |
| 2794 | .name = "db8500-varm", |
| 2795 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2796 | }, |
| 2797 | }, |
| 2798 | [DB8500_REGULATOR_VMODEM] = { |
| 2799 | .constraints = { |
| 2800 | .name = "db8500-vmodem", |
| 2801 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2802 | }, |
| 2803 | }, |
| 2804 | [DB8500_REGULATOR_VPLL] = { |
| 2805 | .constraints = { |
| 2806 | .name = "db8500-vpll", |
| 2807 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2808 | }, |
| 2809 | }, |
| 2810 | [DB8500_REGULATOR_VSMPS1] = { |
| 2811 | .constraints = { |
| 2812 | .name = "db8500-vsmps1", |
| 2813 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2814 | }, |
| 2815 | }, |
| 2816 | [DB8500_REGULATOR_VSMPS2] = { |
| 2817 | .constraints = { |
| 2818 | .name = "db8500-vsmps2", |
| 2819 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2820 | }, |
| 2821 | .consumer_supplies = db8500_vsmps2_consumers, |
| 2822 | .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers), |
| 2823 | }, |
| 2824 | [DB8500_REGULATOR_VSMPS3] = { |
| 2825 | .constraints = { |
| 2826 | .name = "db8500-vsmps3", |
| 2827 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2828 | }, |
| 2829 | }, |
| 2830 | [DB8500_REGULATOR_VRF1] = { |
| 2831 | .constraints = { |
| 2832 | .name = "db8500-vrf1", |
| 2833 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2834 | }, |
| 2835 | }, |
| 2836 | [DB8500_REGULATOR_SWITCH_SVAMMDSP] = { |
Bengt Jonsson | 992b133 | 2012-01-13 16:20:36 +0100 | [diff] [blame] | 2837 | /* dependency to u8500-vape is handled outside regulator framework */ |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2838 | .constraints = { |
| 2839 | .name = "db8500-sva-mmdsp", |
| 2840 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2841 | }, |
Bengt Jonsson | 624e87c | 2011-08-12 10:29:02 +0200 | [diff] [blame] | 2842 | .consumer_supplies = db8500_svammdsp_consumers, |
| 2843 | .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers), |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2844 | }, |
| 2845 | [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = { |
| 2846 | .constraints = { |
| 2847 | /* "ret" means "retention" */ |
| 2848 | .name = "db8500-sva-mmdsp-ret", |
| 2849 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2850 | }, |
| 2851 | }, |
| 2852 | [DB8500_REGULATOR_SWITCH_SVAPIPE] = { |
Bengt Jonsson | 992b133 | 2012-01-13 16:20:36 +0100 | [diff] [blame] | 2853 | /* dependency to u8500-vape is handled outside regulator framework */ |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2854 | .constraints = { |
| 2855 | .name = "db8500-sva-pipe", |
| 2856 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2857 | }, |
Bengt Jonsson | 624e87c | 2011-08-12 10:29:02 +0200 | [diff] [blame] | 2858 | .consumer_supplies = db8500_svapipe_consumers, |
| 2859 | .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers), |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2860 | }, |
| 2861 | [DB8500_REGULATOR_SWITCH_SIAMMDSP] = { |
Bengt Jonsson | 992b133 | 2012-01-13 16:20:36 +0100 | [diff] [blame] | 2862 | /* dependency to u8500-vape is handled outside regulator framework */ |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2863 | .constraints = { |
| 2864 | .name = "db8500-sia-mmdsp", |
| 2865 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2866 | }, |
Bengt Jonsson | 624e87c | 2011-08-12 10:29:02 +0200 | [diff] [blame] | 2867 | .consumer_supplies = db8500_siammdsp_consumers, |
| 2868 | .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers), |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2869 | }, |
| 2870 | [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = { |
| 2871 | .constraints = { |
| 2872 | .name = "db8500-sia-mmdsp-ret", |
| 2873 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2874 | }, |
| 2875 | }, |
| 2876 | [DB8500_REGULATOR_SWITCH_SIAPIPE] = { |
Bengt Jonsson | 992b133 | 2012-01-13 16:20:36 +0100 | [diff] [blame] | 2877 | /* dependency to u8500-vape is handled outside regulator framework */ |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2878 | .constraints = { |
| 2879 | .name = "db8500-sia-pipe", |
| 2880 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2881 | }, |
Bengt Jonsson | 624e87c | 2011-08-12 10:29:02 +0200 | [diff] [blame] | 2882 | .consumer_supplies = db8500_siapipe_consumers, |
| 2883 | .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers), |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2884 | }, |
| 2885 | [DB8500_REGULATOR_SWITCH_SGA] = { |
| 2886 | .supply_regulator = "db8500-vape", |
| 2887 | .constraints = { |
| 2888 | .name = "db8500-sga", |
| 2889 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2890 | }, |
Bengt Jonsson | 624e87c | 2011-08-12 10:29:02 +0200 | [diff] [blame] | 2891 | .consumer_supplies = db8500_sga_consumers, |
| 2892 | .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers), |
| 2893 | |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2894 | }, |
| 2895 | [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = { |
| 2896 | .supply_regulator = "db8500-vape", |
| 2897 | .constraints = { |
| 2898 | .name = "db8500-b2r2-mcde", |
| 2899 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2900 | }, |
| 2901 | .consumer_supplies = db8500_b2r2_mcde_consumers, |
| 2902 | .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers), |
| 2903 | }, |
| 2904 | [DB8500_REGULATOR_SWITCH_ESRAM12] = { |
Bengt Jonsson | 992b133 | 2012-01-13 16:20:36 +0100 | [diff] [blame] | 2905 | /* |
| 2906 | * esram12 is set in retention and supplied by Vsafe when Vape is off, |
| 2907 | * no need to hold Vape |
| 2908 | */ |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2909 | .constraints = { |
| 2910 | .name = "db8500-esram12", |
| 2911 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2912 | }, |
Bengt Jonsson | 624e87c | 2011-08-12 10:29:02 +0200 | [diff] [blame] | 2913 | .consumer_supplies = db8500_esram12_consumers, |
| 2914 | .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers), |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2915 | }, |
| 2916 | [DB8500_REGULATOR_SWITCH_ESRAM12RET] = { |
| 2917 | .constraints = { |
| 2918 | .name = "db8500-esram12-ret", |
| 2919 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2920 | }, |
| 2921 | }, |
| 2922 | [DB8500_REGULATOR_SWITCH_ESRAM34] = { |
Bengt Jonsson | 992b133 | 2012-01-13 16:20:36 +0100 | [diff] [blame] | 2923 | /* |
| 2924 | * esram34 is set in retention and supplied by Vsafe when Vape is off, |
| 2925 | * no need to hold Vape |
| 2926 | */ |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2927 | .constraints = { |
| 2928 | .name = "db8500-esram34", |
| 2929 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2930 | }, |
Bengt Jonsson | 624e87c | 2011-08-12 10:29:02 +0200 | [diff] [blame] | 2931 | .consumer_supplies = db8500_esram34_consumers, |
| 2932 | .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers), |
Bengt Jonsson | 1032fbf | 2011-04-01 14:43:33 +0200 | [diff] [blame] | 2933 | }, |
| 2934 | [DB8500_REGULATOR_SWITCH_ESRAM34RET] = { |
| 2935 | .constraints = { |
| 2936 | .name = "db8500-esram34-ret", |
| 2937 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
| 2938 | }, |
| 2939 | }, |
| 2940 | }; |
| 2941 | |
Fabio Baltieri | b3aac62 | 2013-01-18 12:40:14 +0100 | [diff] [blame] | 2942 | static struct ux500_wdt_data db8500_wdt_pdata = { |
| 2943 | .timeout = 600, /* 10 minutes */ |
| 2944 | .has_28_bits_resolution = true, |
| 2945 | }; |
| 2946 | |
Geert Uytterhoeven | 5ac9855 | 2013-11-18 14:33:06 +0100 | [diff] [blame] | 2947 | static const struct mfd_cell common_prcmu_devs[] = { |
Lee Jones | d98a538 | 2013-04-09 20:52:58 +0100 | [diff] [blame] | 2948 | { |
| 2949 | .name = "ux500_wdt", |
| 2950 | .platform_data = &db8500_wdt_pdata, |
| 2951 | .pdata_size = sizeof(db8500_wdt_pdata), |
| 2952 | .id = -1, |
| 2953 | }, |
| 2954 | }; |
| 2955 | |
Geert Uytterhoeven | 5ac9855 | 2013-11-18 14:33:06 +0100 | [diff] [blame] | 2956 | static const struct mfd_cell db8500_prcmu_devs[] = { |
Lee Jones | a04b4be | 2016-06-30 15:40:21 +0100 | [diff] [blame] | 2957 | OF_MFD_CELL("db8500-prcmu-regulators", NULL, |
| 2958 | &db8500_regulators, sizeof(db8500_regulators), 0, |
| 2959 | "stericsson,db8500-prcmu-regulator"), |
| 2960 | OF_MFD_CELL("cpuidle-dbx500", |
| 2961 | NULL, NULL, 0, 0, "stericsson,cpuidle-dbx500"), |
| 2962 | OF_MFD_CELL("db8500-thermal", |
| 2963 | NULL, NULL, 0, 0, "stericsson,db8500-thermal"), |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 2964 | }; |
| 2965 | |
Arnd Bergmann | 4e65794 | 2016-03-18 16:53:31 +0100 | [diff] [blame] | 2966 | static int db8500_prcmu_register_ab8500(struct device *parent) |
Arnd Bergmann | 55b175d | 2013-03-21 22:51:07 +0100 | [diff] [blame] | 2967 | { |
Linus Walleij | f864c46 | 2014-02-04 00:35:56 +0100 | [diff] [blame] | 2968 | struct device_node *np; |
Stephan Gerhold | 1c0769d | 2019-11-17 23:10:53 +0100 | [diff] [blame] | 2969 | struct resource ab850x_resource; |
Krzysztof Kozlowski | 5785a97 | 2014-05-13 12:58:41 +0200 | [diff] [blame] | 2970 | const struct mfd_cell ab8500_cell = { |
Arnd Bergmann | 55b175d | 2013-03-21 22:51:07 +0100 | [diff] [blame] | 2971 | .name = "ab8500-core", |
| 2972 | .of_compatible = "stericsson,ab8500", |
| 2973 | .id = AB8500_VERSION_AB8500, |
Stephan Gerhold | 1c0769d | 2019-11-17 23:10:53 +0100 | [diff] [blame] | 2974 | .resources = &ab850x_resource, |
Arnd Bergmann | 55b175d | 2013-03-21 22:51:07 +0100 | [diff] [blame] | 2975 | .num_resources = 1, |
| 2976 | }; |
Stephan Gerhold | 1c0769d | 2019-11-17 23:10:53 +0100 | [diff] [blame] | 2977 | const struct mfd_cell ab8505_cell = { |
| 2978 | .name = "ab8505-core", |
| 2979 | .of_compatible = "stericsson,ab8505", |
| 2980 | .id = AB8500_VERSION_AB8505, |
| 2981 | .resources = &ab850x_resource, |
| 2982 | .num_resources = 1, |
| 2983 | }; |
| 2984 | const struct mfd_cell *ab850x_cell; |
Arnd Bergmann | 55b175d | 2013-03-21 22:51:07 +0100 | [diff] [blame] | 2985 | |
Linus Walleij | f864c46 | 2014-02-04 00:35:56 +0100 | [diff] [blame] | 2986 | if (!parent->of_node) |
| 2987 | return -ENODEV; |
| 2988 | |
| 2989 | /* Look up the device node, sneak the IRQ out of it */ |
| 2990 | for_each_child_of_node(parent->of_node, np) { |
Stephan Gerhold | 1c0769d | 2019-11-17 23:10:53 +0100 | [diff] [blame] | 2991 | if (of_device_is_compatible(np, ab8500_cell.of_compatible)) { |
| 2992 | ab850x_cell = &ab8500_cell; |
Linus Walleij | f864c46 | 2014-02-04 00:35:56 +0100 | [diff] [blame] | 2993 | break; |
Stephan Gerhold | 1c0769d | 2019-11-17 23:10:53 +0100 | [diff] [blame] | 2994 | } |
| 2995 | if (of_device_is_compatible(np, ab8505_cell.of_compatible)) { |
| 2996 | ab850x_cell = &ab8505_cell; |
| 2997 | break; |
| 2998 | } |
Linus Walleij | f864c46 | 2014-02-04 00:35:56 +0100 | [diff] [blame] | 2999 | } |
| 3000 | if (!np) { |
Stephan Gerhold | 1c0769d | 2019-11-17 23:10:53 +0100 | [diff] [blame] | 3001 | dev_info(parent, "could not find AB850X node in the device tree\n"); |
Linus Walleij | f864c46 | 2014-02-04 00:35:56 +0100 | [diff] [blame] | 3002 | return -ENODEV; |
| 3003 | } |
Stephan Gerhold | 1c0769d | 2019-11-17 23:10:53 +0100 | [diff] [blame] | 3004 | of_irq_to_resource_table(np, &ab850x_resource, 1); |
Linus Walleij | f864c46 | 2014-02-04 00:35:56 +0100 | [diff] [blame] | 3005 | |
Stephan Gerhold | 1c0769d | 2019-11-17 23:10:53 +0100 | [diff] [blame] | 3006 | return mfd_add_devices(parent, 0, ab850x_cell, 1, NULL, 0, NULL); |
Arnd Bergmann | 55b175d | 2013-03-21 22:51:07 +0100 | [diff] [blame] | 3007 | } |
| 3008 | |
Bill Pemberton | f791be4 | 2012-11-19 13:23:04 -0500 | [diff] [blame] | 3009 | static int db8500_prcmu_probe(struct platform_device *pdev) |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 3010 | { |
Lee Jones | ca7edd1 | 2012-05-09 17:19:25 +0200 | [diff] [blame] | 3011 | struct device_node *np = pdev->dev.of_node; |
Arnd Bergmann | 55b175d | 2013-03-21 22:51:07 +0100 | [diff] [blame] | 3012 | int irq = 0, err = 0; |
Linus Walleij | 05ec260 | 2013-02-07 10:17:31 +0100 | [diff] [blame] | 3013 | struct resource *res; |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 3014 | |
Linus Walleij | b047d98 | 2013-03-19 14:21:47 +0100 | [diff] [blame] | 3015 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu"); |
| 3016 | if (!res) { |
| 3017 | dev_err(&pdev->dev, "no prcmu memory region provided\n"); |
Lee Jones | 6bdf891 | 2014-11-03 16:12:26 +0000 | [diff] [blame] | 3018 | return -EINVAL; |
Linus Walleij | b047d98 | 2013-03-19 14:21:47 +0100 | [diff] [blame] | 3019 | } |
| 3020 | prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); |
| 3021 | if (!prcmu_base) { |
| 3022 | dev_err(&pdev->dev, |
| 3023 | "failed to ioremap prcmu register memory\n"); |
Lee Jones | 6bdf891 | 2014-11-03 16:12:26 +0000 | [diff] [blame] | 3024 | return -ENOMEM; |
Linus Walleij | b047d98 | 2013-03-19 14:21:47 +0100 | [diff] [blame] | 3025 | } |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 3026 | init_prcm_registers(); |
Linus Walleij | 05ec260 | 2013-02-07 10:17:31 +0100 | [diff] [blame] | 3027 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm"); |
| 3028 | if (!res) { |
| 3029 | dev_err(&pdev->dev, "no prcmu tcdm region provided\n"); |
Lee Jones | 6bdf891 | 2014-11-03 16:12:26 +0000 | [diff] [blame] | 3030 | return -EINVAL; |
Linus Walleij | 05ec260 | 2013-02-07 10:17:31 +0100 | [diff] [blame] | 3031 | } |
| 3032 | tcdm_base = devm_ioremap(&pdev->dev, res->start, |
| 3033 | resource_size(res)); |
Pramod Gurav | 51a7e02 | 2014-10-30 14:51:35 +0530 | [diff] [blame] | 3034 | if (!tcdm_base) { |
| 3035 | dev_err(&pdev->dev, |
| 3036 | "failed to ioremap prcmu-tcdm register memory\n"); |
Lee Jones | 6bdf891 | 2014-11-03 16:12:26 +0000 | [diff] [blame] | 3037 | return -ENOMEM; |
Pramod Gurav | 51a7e02 | 2014-10-30 14:51:35 +0530 | [diff] [blame] | 3038 | } |
Linus Walleij | 05ec260 | 2013-02-07 10:17:31 +0100 | [diff] [blame] | 3039 | |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 3040 | /* Clean up the mailbox interrupts after pre-kernel code. */ |
Mattias Nilsson | c553b3c | 2011-08-12 10:27:20 +0200 | [diff] [blame] | 3041 | writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 3042 | |
Linus Walleij | 05ec260 | 2013-02-07 10:17:31 +0100 | [diff] [blame] | 3043 | irq = platform_get_irq(pdev, 0); |
Stephen Boyd | 802d9bd | 2019-07-30 11:15:27 -0700 | [diff] [blame] | 3044 | if (irq <= 0) |
Lee Jones | 6bdf891 | 2014-11-03 16:12:26 +0000 | [diff] [blame] | 3045 | return irq; |
Lee Jones | ca7edd1 | 2012-05-09 17:19:25 +0200 | [diff] [blame] | 3046 | |
| 3047 | err = request_threaded_irq(irq, prcmu_irq_handler, |
| 3048 | prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 3049 | if (err < 0) { |
| 3050 | pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n"); |
Lee Jones | 6bdf891 | 2014-11-03 16:12:26 +0000 | [diff] [blame] | 3051 | return err; |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 3052 | } |
| 3053 | |
Linus Walleij | f864c46 | 2014-02-04 00:35:56 +0100 | [diff] [blame] | 3054 | db8500_irq_init(np); |
Lee Jones | 3a8e39c | 2012-07-06 12:46:23 +0200 | [diff] [blame] | 3055 | |
Linus Walleij | 7a4f260 | 2012-09-19 19:31:19 +0200 | [diff] [blame] | 3056 | prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 3057 | |
Lee Jones | d98a538 | 2013-04-09 20:52:58 +0100 | [diff] [blame] | 3058 | err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs, |
| 3059 | ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain); |
Lee Jones | 5d90322 | 2012-06-20 13:56:41 +0100 | [diff] [blame] | 3060 | if (err) { |
| 3061 | pr_err("prcmu: Failed to add subdevices\n"); |
| 3062 | return err; |
Lee Jones | ca7edd1 | 2012-05-09 17:19:25 +0200 | [diff] [blame] | 3063 | } |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 3064 | |
Lee Jones | d98a538 | 2013-04-09 20:52:58 +0100 | [diff] [blame] | 3065 | /* TODO: Remove restriction when clk definitions are available. */ |
| 3066 | if (!of_machine_is_compatible("st-ericsson,u8540")) { |
| 3067 | err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, |
| 3068 | ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, |
| 3069 | db8500_irq_domain); |
| 3070 | if (err) { |
| 3071 | mfd_remove_devices(&pdev->dev); |
| 3072 | pr_err("prcmu: Failed to add subdevices\n"); |
Lee Jones | 6bdf891 | 2014-11-03 16:12:26 +0000 | [diff] [blame] | 3073 | return err; |
Lee Jones | d98a538 | 2013-04-09 20:52:58 +0100 | [diff] [blame] | 3074 | } |
| 3075 | } |
| 3076 | |
Arnd Bergmann | 4e65794 | 2016-03-18 16:53:31 +0100 | [diff] [blame] | 3077 | err = db8500_prcmu_register_ab8500(&pdev->dev); |
Arnd Bergmann | 55b175d | 2013-03-21 22:51:07 +0100 | [diff] [blame] | 3078 | if (err) { |
| 3079 | mfd_remove_devices(&pdev->dev); |
| 3080 | pr_err("prcmu: Failed to add ab8500 subdevice\n"); |
Lee Jones | 6bdf891 | 2014-11-03 16:12:26 +0000 | [diff] [blame] | 3081 | return err; |
Arnd Bergmann | 55b175d | 2013-03-21 22:51:07 +0100 | [diff] [blame] | 3082 | } |
| 3083 | |
Lee Jones | ca7edd1 | 2012-05-09 17:19:25 +0200 | [diff] [blame] | 3084 | pr_info("DB8500 PRCMU initialized\n"); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 3085 | return err; |
| 3086 | } |
Lee Jones | 3c14476 | 2012-06-29 15:41:38 +0200 | [diff] [blame] | 3087 | static const struct of_device_id db8500_prcmu_match[] = { |
| 3088 | { .compatible = "stericsson,db8500-prcmu"}, |
| 3089 | { }, |
| 3090 | }; |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 3091 | |
| 3092 | static struct platform_driver db8500_prcmu_driver = { |
| 3093 | .driver = { |
| 3094 | .name = "db8500-prcmu", |
Lee Jones | 3c14476 | 2012-06-29 15:41:38 +0200 | [diff] [blame] | 3095 | .of_match_table = db8500_prcmu_match, |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 3096 | }, |
Lee Jones | 9fc63f6 | 2012-04-19 21:36:41 +0100 | [diff] [blame] | 3097 | .probe = db8500_prcmu_probe, |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 3098 | }; |
| 3099 | |
| 3100 | static int __init db8500_prcmu_init(void) |
| 3101 | { |
Lee Jones | 9fc63f6 | 2012-04-19 21:36:41 +0100 | [diff] [blame] | 3102 | return platform_driver_register(&db8500_prcmu_driver); |
Mattias Nilsson | 3df57bc | 2011-05-16 00:15:05 +0200 | [diff] [blame] | 3103 | } |
Lee Jones | a661aca | 2012-06-11 16:24:59 +0100 | [diff] [blame] | 3104 | core_initcall(db8500_prcmu_init); |