Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | /* |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 2 | * Set up the interrupt priorities |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 3 | * |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 4 | * Copyright 2004-2009 Analog Devices Inc. |
| 5 | * 2003 Bas Vermeulen <bas@buyways.nl> |
| 6 | * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> |
| 7 | * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca> |
| 8 | * 1999 D. Jeff Dionne <jeff@uclinux.org> |
| 9 | * 1996 Roman Zippel |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 10 | * |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 11 | * Licensed under the GPL-2 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 12 | */ |
| 13 | |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/kernel_stat.h> |
| 16 | #include <linux/seq_file.h> |
| 17 | #include <linux/irq.h> |
Philippe Gerum | 5b5da4c | 2011-03-17 02:12:48 -0400 | [diff] [blame] | 18 | #include <linux/sched.h> |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 19 | #include <linux/syscore_ops.h> |
| 20 | #include <asm/delay.h> |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 21 | #ifdef CONFIG_IPIPE |
| 22 | #include <linux/ipipe.h> |
| 23 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 24 | #include <asm/traps.h> |
| 25 | #include <asm/blackfin.h> |
| 26 | #include <asm/gpio.h> |
| 27 | #include <asm/irq_handler.h> |
Mike Frysinger | 761ec44 | 2009-10-15 17:12:05 +0000 | [diff] [blame] | 28 | #include <asm/dpmc.h> |
Sonic Zhang | 06051fd | 2012-07-04 19:22:55 +0800 | [diff] [blame] | 29 | #include <asm/traps.h> |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 30 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 31 | /* |
| 32 | * NOTES: |
| 33 | * - we have separated the physical Hardware interrupt from the |
| 34 | * levels that the LINUX kernel sees (see the description in irq.h) |
| 35 | * - |
| 36 | */ |
| 37 | |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 38 | #ifndef CONFIG_SMP |
Mike Frysinger | a99bbcc | 2007-10-22 00:19:31 +0800 | [diff] [blame] | 39 | /* Initialize this to an actual value to force it into the .data |
| 40 | * section so that we know it is properly initialized at entry into |
| 41 | * the kernel but before bss is initialized to zero (which is where |
| 42 | * it would live otherwise). The 0x1f magic represents the IRQs we |
| 43 | * cannot actually mask out in hardware. |
| 44 | */ |
Mike Frysinger | 4005978 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 45 | unsigned long bfin_irq_flags = 0x1f; |
| 46 | EXPORT_SYMBOL(bfin_irq_flags); |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 47 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 48 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 49 | #ifdef CONFIG_PM |
| 50 | unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */ |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 51 | unsigned vr_wakeup; |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 52 | #endif |
| 53 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 54 | #ifndef SEC_GCTL |
Mike Frysinger | e9e334c | 2011-03-30 00:43:52 -0400 | [diff] [blame] | 55 | static struct ivgx { |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 56 | /* irq number for request_irq, available in mach-bf5xx/irq.h */ |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 57 | unsigned int irqno; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 58 | /* corresponding bit in the SIC_ISR register */ |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 59 | unsigned int isrflag; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 60 | } ivg_table[NR_PERI_INTS]; |
| 61 | |
Mike Frysinger | e9e334c | 2011-03-30 00:43:52 -0400 | [diff] [blame] | 62 | static struct ivg_slice { |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 63 | /* position of first irq in ivg_table for given ivg */ |
| 64 | struct ivgx *ifirst; |
| 65 | struct ivgx *istop; |
| 66 | } ivg7_13[IVG13 - IVG7 + 1]; |
| 67 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 68 | |
| 69 | /* |
| 70 | * Search SIC_IAR and fill tables with the irqvalues |
| 71 | * and their positions in the SIC_ISR register. |
| 72 | */ |
| 73 | static void __init search_IAR(void) |
| 74 | { |
| 75 | unsigned ivg, irq_pos = 0; |
| 76 | for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) { |
Mike Frysinger | 80fcdb9 | 2010-04-22 21:15:00 +0000 | [diff] [blame] | 77 | int irqN; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 78 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 79 | ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos]; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 80 | |
Mike Frysinger | 80fcdb9 | 2010-04-22 21:15:00 +0000 | [diff] [blame] | 81 | for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) { |
| 82 | int irqn; |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 83 | u32 iar = |
| 84 | bfin_read32((unsigned long *)SIC_IAR0 + |
Mike Frysinger | 80fcdb9 | 2010-04-22 21:15:00 +0000 | [diff] [blame] | 85 | #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \ |
| 86 | defined(CONFIG_BF538) || defined(CONFIG_BF539) |
| 87 | ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4)) |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 88 | #else |
Mike Frysinger | 80fcdb9 | 2010-04-22 21:15:00 +0000 | [diff] [blame] | 89 | (irqN >> 3) |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 90 | #endif |
Mike Frysinger | 80fcdb9 | 2010-04-22 21:15:00 +0000 | [diff] [blame] | 91 | ); |
Mike Frysinger | 80fcdb9 | 2010-04-22 21:15:00 +0000 | [diff] [blame] | 92 | for (irqn = irqN; irqn < irqN + 4; ++irqn) { |
| 93 | int iar_shift = (irqn & 7) * 4; |
| 94 | if (ivg == (0xf & (iar >> iar_shift))) { |
| 95 | ivg_table[irq_pos].irqno = IVG7 + irqn; |
| 96 | ivg_table[irq_pos].isrflag = 1 << (irqn % 32); |
| 97 | ivg7_13[ivg].istop++; |
| 98 | irq_pos++; |
| 99 | } |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 100 | } |
| 101 | } |
| 102 | } |
| 103 | } |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 104 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 105 | |
| 106 | /* |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 107 | * This is for core internal IRQs |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 108 | */ |
Mike Frysinger | f58c327 | 2011-04-15 03:08:20 -0400 | [diff] [blame] | 109 | void bfin_ack_noop(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 110 | { |
| 111 | /* Dummy function. */ |
| 112 | } |
| 113 | |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame] | 114 | static void bfin_core_mask_irq(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 115 | { |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame] | 116 | bfin_irq_flags &= ~(1 << d->irq); |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 117 | if (!hard_irqs_disabled()) |
| 118 | hard_local_irq_enable(); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 119 | } |
| 120 | |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame] | 121 | static void bfin_core_unmask_irq(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 122 | { |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame] | 123 | bfin_irq_flags |= 1 << d->irq; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 124 | /* |
| 125 | * If interrupts are enabled, IMASK must contain the same value |
Mike Frysinger | 4005978 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 126 | * as bfin_irq_flags. Make sure that invariant holds. If interrupts |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 127 | * are currently disabled we need not do anything; one of the |
| 128 | * callers will take care of setting IMASK to the proper value |
| 129 | * when reenabling interrupts. |
Mike Frysinger | 4005978 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 130 | * local_irq_enable just does "STI bfin_irq_flags", so it's exactly |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 131 | * what we need. |
| 132 | */ |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 133 | if (!hard_irqs_disabled()) |
| 134 | hard_local_irq_enable(); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 135 | return; |
| 136 | } |
| 137 | |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 138 | #ifndef SEC_GCTL |
Mike Frysinger | f58c327 | 2011-04-15 03:08:20 -0400 | [diff] [blame] | 139 | void bfin_internal_mask_irq(unsigned int irq) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 140 | { |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 141 | unsigned long flags = hard_local_irq_save(); |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 142 | #ifdef SIC_IMASK0 |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 143 | unsigned mask_bank = BFIN_SYSIRQ(irq) / 32; |
| 144 | unsigned mask_bit = BFIN_SYSIRQ(irq) % 32; |
Bryan Wu | c04d66b | 2007-07-12 17:26:31 +0800 | [diff] [blame] | 145 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 146 | ~(1 << mask_bit)); |
| 147 | # if defined(CONFIG_SMP) || defined(CONFIG_ICC) |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 148 | bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) & |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 149 | ~(1 << mask_bit)); |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 150 | # endif |
| 151 | #else |
| 152 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 153 | ~(1 << BFIN_SYSIRQ(irq))); |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 154 | #endif /* end of SIC_IMASK0 */ |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 155 | hard_local_irq_restore(flags); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 156 | } |
| 157 | |
Thomas Gleixner | ff43a67 | 2011-02-06 18:23:29 +0000 | [diff] [blame] | 158 | static void bfin_internal_mask_irq_chip(struct irq_data *d) |
| 159 | { |
| 160 | bfin_internal_mask_irq(d->irq); |
| 161 | } |
| 162 | |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 163 | #ifdef CONFIG_SMP |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 164 | void bfin_internal_unmask_irq_affinity(unsigned int irq, |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 165 | const struct cpumask *affinity) |
| 166 | #else |
Mike Frysinger | f58c327 | 2011-04-15 03:08:20 -0400 | [diff] [blame] | 167 | void bfin_internal_unmask_irq(unsigned int irq) |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 168 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 169 | { |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 170 | unsigned long flags = hard_local_irq_save(); |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 171 | |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 172 | #ifdef SIC_IMASK0 |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 173 | unsigned mask_bank = BFIN_SYSIRQ(irq) / 32; |
| 174 | unsigned mask_bit = BFIN_SYSIRQ(irq) % 32; |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 175 | # ifdef CONFIG_SMP |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 176 | if (cpumask_test_cpu(0, affinity)) |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 177 | # endif |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 178 | bfin_write_SIC_IMASK(mask_bank, |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 179 | bfin_read_SIC_IMASK(mask_bank) | |
| 180 | (1 << mask_bit)); |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 181 | # ifdef CONFIG_SMP |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 182 | if (cpumask_test_cpu(1, affinity)) |
| 183 | bfin_write_SICB_IMASK(mask_bank, |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 184 | bfin_read_SICB_IMASK(mask_bank) | |
| 185 | (1 << mask_bit)); |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 186 | # endif |
| 187 | #else |
| 188 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 189 | (1 << BFIN_SYSIRQ(irq))); |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 190 | #endif |
| 191 | hard_local_irq_restore(flags); |
| 192 | } |
| 193 | |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 194 | #ifdef CONFIG_SMP |
| 195 | static void bfin_internal_unmask_irq_chip(struct irq_data *d) |
| 196 | { |
| 197 | bfin_internal_unmask_irq_affinity(d->irq, d->affinity); |
| 198 | } |
| 199 | |
| 200 | static int bfin_internal_set_affinity(struct irq_data *d, |
| 201 | const struct cpumask *mask, bool force) |
| 202 | { |
| 203 | bfin_internal_mask_irq(d->irq); |
| 204 | bfin_internal_unmask_irq_affinity(d->irq, mask); |
| 205 | |
| 206 | return 0; |
| 207 | } |
| 208 | #else |
| 209 | static void bfin_internal_unmask_irq_chip(struct irq_data *d) |
| 210 | { |
| 211 | bfin_internal_unmask_irq(d->irq); |
| 212 | } |
| 213 | #endif |
| 214 | |
| 215 | #if defined(CONFIG_PM) |
| 216 | int bfin_internal_set_wake(unsigned int irq, unsigned int state) |
| 217 | { |
| 218 | u32 bank, bit, wakeup = 0; |
| 219 | unsigned long flags; |
| 220 | bank = BFIN_SYSIRQ(irq) / 32; |
| 221 | bit = BFIN_SYSIRQ(irq) % 32; |
| 222 | |
| 223 | switch (irq) { |
| 224 | #ifdef IRQ_RTC |
| 225 | case IRQ_RTC: |
| 226 | wakeup |= WAKE; |
| 227 | break; |
| 228 | #endif |
| 229 | #ifdef IRQ_CAN0_RX |
| 230 | case IRQ_CAN0_RX: |
| 231 | wakeup |= CANWE; |
| 232 | break; |
| 233 | #endif |
| 234 | #ifdef IRQ_CAN1_RX |
| 235 | case IRQ_CAN1_RX: |
| 236 | wakeup |= CANWE; |
| 237 | break; |
| 238 | #endif |
| 239 | #ifdef IRQ_USB_INT0 |
| 240 | case IRQ_USB_INT0: |
| 241 | wakeup |= USBWE; |
| 242 | break; |
| 243 | #endif |
| 244 | #ifdef CONFIG_BF54x |
| 245 | case IRQ_CNT: |
| 246 | wakeup |= ROTWE; |
| 247 | break; |
| 248 | #endif |
| 249 | default: |
| 250 | break; |
| 251 | } |
| 252 | |
| 253 | flags = hard_local_irq_save(); |
| 254 | |
| 255 | if (state) { |
| 256 | bfin_sic_iwr[bank] |= (1 << bit); |
| 257 | vr_wakeup |= wakeup; |
| 258 | |
| 259 | } else { |
| 260 | bfin_sic_iwr[bank] &= ~(1 << bit); |
| 261 | vr_wakeup &= ~wakeup; |
| 262 | } |
| 263 | |
| 264 | hard_local_irq_restore(flags); |
| 265 | |
| 266 | return 0; |
| 267 | } |
| 268 | |
| 269 | static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state) |
| 270 | { |
| 271 | return bfin_internal_set_wake(d->irq, state); |
| 272 | } |
| 273 | #else |
| 274 | inline int bfin_internal_set_wake(unsigned int irq, unsigned int state) |
| 275 | { |
| 276 | return 0; |
| 277 | } |
| 278 | # define bfin_internal_set_wake_chip NULL |
| 279 | #endif |
| 280 | |
| 281 | #else /* SEC_GCTL */ |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 282 | static void bfin_sec_preflow_handler(struct irq_data *d) |
| 283 | { |
| 284 | unsigned long flags = hard_local_irq_save(); |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 285 | unsigned int sid = BFIN_SYSIRQ(d->irq); |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 286 | |
| 287 | bfin_write_SEC_SCI(0, SEC_CSID, sid); |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 288 | |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 289 | hard_local_irq_restore(flags); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 290 | } |
| 291 | |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 292 | static void bfin_sec_mask_ack_irq(struct irq_data *d) |
| 293 | { |
| 294 | unsigned long flags = hard_local_irq_save(); |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 295 | unsigned int sid = BFIN_SYSIRQ(d->irq); |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 296 | |
| 297 | bfin_write_SEC_SCI(0, SEC_CSID, sid); |
| 298 | |
| 299 | hard_local_irq_restore(flags); |
| 300 | } |
| 301 | |
| 302 | static void bfin_sec_unmask_irq(struct irq_data *d) |
| 303 | { |
| 304 | unsigned long flags = hard_local_irq_save(); |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 305 | unsigned int sid = BFIN_SYSIRQ(d->irq); |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 306 | |
| 307 | bfin_write32(SEC_END, sid); |
| 308 | |
| 309 | hard_local_irq_restore(flags); |
| 310 | } |
| 311 | |
| 312 | static void bfin_sec_enable_ssi(unsigned int sid) |
| 313 | { |
| 314 | unsigned long flags = hard_local_irq_save(); |
| 315 | uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); |
| 316 | |
| 317 | reg_sctl |= SEC_SCTL_SRC_EN; |
| 318 | bfin_write_SEC_SCTL(sid, reg_sctl); |
| 319 | |
| 320 | hard_local_irq_restore(flags); |
| 321 | } |
| 322 | |
| 323 | static void bfin_sec_disable_ssi(unsigned int sid) |
| 324 | { |
| 325 | unsigned long flags = hard_local_irq_save(); |
| 326 | uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); |
| 327 | |
| 328 | reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN); |
| 329 | bfin_write_SEC_SCTL(sid, reg_sctl); |
| 330 | |
| 331 | hard_local_irq_restore(flags); |
| 332 | } |
| 333 | |
| 334 | static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid) |
| 335 | { |
| 336 | unsigned long flags = hard_local_irq_save(); |
| 337 | uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); |
| 338 | |
| 339 | reg_sctl &= ((uint32_t)~SEC_SCTL_CTG); |
| 340 | bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG)); |
| 341 | |
| 342 | hard_local_irq_restore(flags); |
| 343 | } |
| 344 | |
| 345 | static void bfin_sec_enable_sci(unsigned int sid) |
| 346 | { |
| 347 | unsigned long flags = hard_local_irq_save(); |
| 348 | uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); |
| 349 | |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 350 | if (sid == BFIN_SYSIRQ(IRQ_WATCH0)) |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 351 | reg_sctl |= SEC_SCTL_FAULT_EN; |
| 352 | else |
| 353 | reg_sctl |= SEC_SCTL_INT_EN; |
| 354 | bfin_write_SEC_SCTL(sid, reg_sctl); |
| 355 | |
| 356 | hard_local_irq_restore(flags); |
| 357 | } |
| 358 | |
| 359 | static void bfin_sec_disable_sci(unsigned int sid) |
| 360 | { |
| 361 | unsigned long flags = hard_local_irq_save(); |
| 362 | uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); |
| 363 | |
| 364 | reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN); |
| 365 | bfin_write_SEC_SCTL(sid, reg_sctl); |
| 366 | |
| 367 | hard_local_irq_restore(flags); |
| 368 | } |
| 369 | |
| 370 | static void bfin_sec_enable(struct irq_data *d) |
| 371 | { |
| 372 | unsigned long flags = hard_local_irq_save(); |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 373 | unsigned int sid = BFIN_SYSIRQ(d->irq); |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 374 | |
| 375 | bfin_sec_enable_sci(sid); |
| 376 | bfin_sec_enable_ssi(sid); |
| 377 | |
| 378 | hard_local_irq_restore(flags); |
| 379 | } |
| 380 | |
| 381 | static void bfin_sec_disable(struct irq_data *d) |
| 382 | { |
| 383 | unsigned long flags = hard_local_irq_save(); |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 384 | unsigned int sid = BFIN_SYSIRQ(d->irq); |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 385 | |
| 386 | bfin_sec_disable_sci(sid); |
| 387 | bfin_sec_disable_ssi(sid); |
| 388 | |
| 389 | hard_local_irq_restore(flags); |
| 390 | } |
| 391 | |
Sonic Zhang | e0a5931 | 2012-06-29 18:19:29 +0800 | [diff] [blame] | 392 | static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority) |
| 393 | { |
| 394 | unsigned long flags = hard_local_irq_save(); |
| 395 | uint32_t reg_sctl; |
| 396 | int i; |
| 397 | |
| 398 | bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels); |
| 399 | |
| 400 | for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) { |
| 401 | reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO; |
| 402 | reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET; |
| 403 | bfin_write_SEC_SCTL(i, reg_sctl); |
| 404 | } |
| 405 | |
| 406 | hard_local_irq_restore(flags); |
| 407 | } |
| 408 | |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 409 | void bfin_sec_raise_irq(unsigned int irq) |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 410 | { |
| 411 | unsigned long flags = hard_local_irq_save(); |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 412 | unsigned int sid = BFIN_SYSIRQ(irq); |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 413 | |
| 414 | bfin_write32(SEC_RAISE, sid); |
| 415 | |
| 416 | hard_local_irq_restore(flags); |
| 417 | } |
| 418 | |
| 419 | static void init_software_driven_irq(void) |
| 420 | { |
| 421 | bfin_sec_set_ssi_coreid(34, 0); |
| 422 | bfin_sec_set_ssi_coreid(35, 1); |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 423 | |
| 424 | bfin_sec_enable_sci(35); |
| 425 | bfin_sec_enable_ssi(35); |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 426 | bfin_sec_set_ssi_coreid(36, 0); |
| 427 | bfin_sec_set_ssi_coreid(37, 1); |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 428 | bfin_sec_enable_sci(37); |
| 429 | bfin_sec_enable_ssi(37); |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 430 | } |
| 431 | |
| 432 | void bfin_sec_resume(void) |
| 433 | { |
| 434 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); |
| 435 | udelay(100); |
| 436 | bfin_write_SEC_GCTL(SEC_GCTL_EN); |
| 437 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); |
| 438 | } |
| 439 | |
| 440 | void handle_sec_sfi_fault(uint32_t gstat) |
| 441 | { |
| 442 | |
| 443 | } |
| 444 | |
| 445 | void handle_sec_sci_fault(uint32_t gstat) |
| 446 | { |
| 447 | uint32_t core_id; |
| 448 | uint32_t cstat; |
| 449 | |
| 450 | core_id = gstat & SEC_GSTAT_SCI; |
| 451 | cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT); |
| 452 | if (cstat & SEC_CSTAT_ERR) { |
| 453 | switch (cstat & SEC_CSTAT_ERRC) { |
| 454 | case SEC_CSTAT_ACKERR: |
| 455 | printk(KERN_DEBUG "sec ack err\n"); |
| 456 | break; |
| 457 | default: |
| 458 | printk(KERN_DEBUG "sec sci unknow err\n"); |
| 459 | } |
| 460 | } |
| 461 | |
| 462 | } |
| 463 | |
| 464 | void handle_sec_ssi_fault(uint32_t gstat) |
| 465 | { |
| 466 | uint32_t sid; |
| 467 | uint32_t sstat; |
| 468 | |
| 469 | sid = gstat & SEC_GSTAT_SID; |
| 470 | sstat = bfin_read_SEC_SSTAT(sid); |
| 471 | |
| 472 | } |
| 473 | |
| 474 | void handle_sec_fault(unsigned int irq, struct irq_desc *desc) |
| 475 | { |
| 476 | uint32_t sec_gstat; |
| 477 | |
| 478 | raw_spin_lock(&desc->lock); |
| 479 | |
| 480 | sec_gstat = bfin_read32(SEC_GSTAT); |
| 481 | if (sec_gstat & SEC_GSTAT_ERR) { |
| 482 | |
| 483 | switch (sec_gstat & SEC_GSTAT_ERRC) { |
| 484 | case 0: |
| 485 | handle_sec_sfi_fault(sec_gstat); |
| 486 | break; |
| 487 | case SEC_GSTAT_SCIERR: |
| 488 | handle_sec_sci_fault(sec_gstat); |
| 489 | break; |
| 490 | case SEC_GSTAT_SSIERR: |
| 491 | handle_sec_ssi_fault(sec_gstat); |
| 492 | break; |
| 493 | } |
| 494 | |
| 495 | |
| 496 | } |
| 497 | |
| 498 | raw_spin_unlock(&desc->lock); |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 499 | |
| 500 | handle_fasteoi_irq(irq, desc); |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 501 | } |
| 502 | |
Sonic Zhang | 06051fd | 2012-07-04 19:22:55 +0800 | [diff] [blame] | 503 | void handle_core_fault(unsigned int irq, struct irq_desc *desc) |
| 504 | { |
| 505 | struct pt_regs *fp = get_irq_regs(); |
| 506 | |
| 507 | raw_spin_lock(&desc->lock); |
| 508 | |
| 509 | switch (irq) { |
| 510 | case IRQ_C0_DBL_FAULT: |
| 511 | double_fault_c(fp); |
| 512 | break; |
| 513 | case IRQ_C0_HW_ERR: |
| 514 | dump_bfin_process(fp); |
| 515 | dump_bfin_mem(fp); |
| 516 | show_regs(fp); |
| 517 | printk(KERN_NOTICE "Kernel Stack\n"); |
| 518 | show_stack(current, NULL); |
| 519 | print_modules(); |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 520 | panic("Core 0 hardware error"); |
Sonic Zhang | 06051fd | 2012-07-04 19:22:55 +0800 | [diff] [blame] | 521 | break; |
| 522 | case IRQ_C0_NMI_L1_PARITY_ERR: |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 523 | panic("Core 0 NMI L1 parity error"); |
Sonic Zhang | 06051fd | 2012-07-04 19:22:55 +0800 | [diff] [blame] | 524 | break; |
| 525 | default: |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 526 | panic("Core 1 fault %d occurs unexpectedly", irq); |
Sonic Zhang | 06051fd | 2012-07-04 19:22:55 +0800 | [diff] [blame] | 527 | } |
| 528 | |
| 529 | raw_spin_unlock(&desc->lock); |
| 530 | } |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 531 | #endif /* SEC_GCTL */ |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 532 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 533 | static struct irq_chip bfin_core_irqchip = { |
Graf Yang | 763e63c | 2008-10-08 17:08:15 +0800 | [diff] [blame] | 534 | .name = "CORE", |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame] | 535 | .irq_mask = bfin_core_mask_irq, |
| 536 | .irq_unmask = bfin_core_unmask_irq, |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 537 | }; |
| 538 | |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 539 | #ifndef SEC_GCTL |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 540 | static struct irq_chip bfin_internal_irqchip = { |
Graf Yang | 763e63c | 2008-10-08 17:08:15 +0800 | [diff] [blame] | 541 | .name = "INTN", |
Thomas Gleixner | ff43a67 | 2011-02-06 18:23:29 +0000 | [diff] [blame] | 542 | .irq_mask = bfin_internal_mask_irq_chip, |
| 543 | .irq_unmask = bfin_internal_unmask_irq_chip, |
Thomas Gleixner | ff43a67 | 2011-02-06 18:23:29 +0000 | [diff] [blame] | 544 | .irq_disable = bfin_internal_mask_irq_chip, |
| 545 | .irq_enable = bfin_internal_unmask_irq_chip, |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 546 | #ifdef CONFIG_SMP |
Thomas Gleixner | ff43a67 | 2011-02-06 18:23:29 +0000 | [diff] [blame] | 547 | .irq_set_affinity = bfin_internal_set_affinity, |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 548 | #endif |
Thomas Gleixner | ff43a67 | 2011-02-06 18:23:29 +0000 | [diff] [blame] | 549 | .irq_set_wake = bfin_internal_set_wake_chip, |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 550 | }; |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 551 | #else |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 552 | static struct irq_chip bfin_sec_irqchip = { |
| 553 | .name = "SEC", |
| 554 | .irq_mask_ack = bfin_sec_mask_ack_irq, |
| 555 | .irq_mask = bfin_sec_mask_ack_irq, |
| 556 | .irq_unmask = bfin_sec_unmask_irq, |
| 557 | .irq_eoi = bfin_sec_unmask_irq, |
| 558 | .irq_disable = bfin_sec_disable, |
| 559 | .irq_enable = bfin_sec_enable, |
| 560 | }; |
| 561 | #endif |
| 562 | |
Mike Frysinger | f58c327 | 2011-04-15 03:08:20 -0400 | [diff] [blame] | 563 | void bfin_handle_irq(unsigned irq) |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 564 | { |
| 565 | #ifdef CONFIG_IPIPE |
| 566 | struct pt_regs regs; /* Contents not used. */ |
| 567 | ipipe_trace_irq_entry(irq); |
| 568 | __ipipe_handle_irq(irq, ®s); |
| 569 | ipipe_trace_irq_exit(irq); |
| 570 | #else /* !CONFIG_IPIPE */ |
Thomas Gleixner | b10bbbb | 2011-02-06 18:23:25 +0000 | [diff] [blame] | 571 | generic_handle_irq(irq); |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 572 | #endif /* !CONFIG_IPIPE */ |
| 573 | } |
| 574 | |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 575 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) |
| 576 | static int mac_stat_int_mask; |
| 577 | |
| 578 | static void bfin_mac_status_ack_irq(unsigned int irq) |
| 579 | { |
| 580 | switch (irq) { |
| 581 | case IRQ_MAC_MMCINT: |
| 582 | bfin_write_EMAC_MMC_TIRQS( |
| 583 | bfin_read_EMAC_MMC_TIRQE() & |
| 584 | bfin_read_EMAC_MMC_TIRQS()); |
| 585 | bfin_write_EMAC_MMC_RIRQS( |
| 586 | bfin_read_EMAC_MMC_RIRQE() & |
| 587 | bfin_read_EMAC_MMC_RIRQS()); |
| 588 | break; |
| 589 | case IRQ_MAC_RXFSINT: |
| 590 | bfin_write_EMAC_RX_STKY( |
| 591 | bfin_read_EMAC_RX_IRQE() & |
| 592 | bfin_read_EMAC_RX_STKY()); |
| 593 | break; |
| 594 | case IRQ_MAC_TXFSINT: |
| 595 | bfin_write_EMAC_TX_STKY( |
| 596 | bfin_read_EMAC_TX_IRQE() & |
| 597 | bfin_read_EMAC_TX_STKY()); |
| 598 | break; |
| 599 | case IRQ_MAC_WAKEDET: |
| 600 | bfin_write_EMAC_WKUP_CTL( |
| 601 | bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS); |
| 602 | break; |
| 603 | default: |
| 604 | /* These bits are W1C */ |
| 605 | bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT)); |
| 606 | break; |
| 607 | } |
| 608 | } |
| 609 | |
Thomas Gleixner | 172d2d1 | 2011-02-06 18:23:34 +0000 | [diff] [blame] | 610 | static void bfin_mac_status_mask_irq(struct irq_data *d) |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 611 | { |
Thomas Gleixner | 172d2d1 | 2011-02-06 18:23:34 +0000 | [diff] [blame] | 612 | unsigned int irq = d->irq; |
| 613 | |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 614 | mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT)); |
Mike Frysinger | f58c327 | 2011-04-15 03:08:20 -0400 | [diff] [blame] | 615 | #ifdef BF537_FAMILY |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 616 | switch (irq) { |
| 617 | case IRQ_MAC_PHYINT: |
| 618 | bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE); |
| 619 | break; |
| 620 | default: |
| 621 | break; |
| 622 | } |
| 623 | #else |
| 624 | if (!mac_stat_int_mask) |
| 625 | bfin_internal_mask_irq(IRQ_MAC_ERROR); |
| 626 | #endif |
| 627 | bfin_mac_status_ack_irq(irq); |
| 628 | } |
| 629 | |
Thomas Gleixner | 172d2d1 | 2011-02-06 18:23:34 +0000 | [diff] [blame] | 630 | static void bfin_mac_status_unmask_irq(struct irq_data *d) |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 631 | { |
Thomas Gleixner | 172d2d1 | 2011-02-06 18:23:34 +0000 | [diff] [blame] | 632 | unsigned int irq = d->irq; |
| 633 | |
Mike Frysinger | f58c327 | 2011-04-15 03:08:20 -0400 | [diff] [blame] | 634 | #ifdef BF537_FAMILY |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 635 | switch (irq) { |
| 636 | case IRQ_MAC_PHYINT: |
| 637 | bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE); |
| 638 | break; |
| 639 | default: |
| 640 | break; |
| 641 | } |
| 642 | #else |
| 643 | if (!mac_stat_int_mask) |
| 644 | bfin_internal_unmask_irq(IRQ_MAC_ERROR); |
| 645 | #endif |
| 646 | mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT); |
| 647 | } |
| 648 | |
| 649 | #ifdef CONFIG_PM |
Thomas Gleixner | 172d2d1 | 2011-02-06 18:23:34 +0000 | [diff] [blame] | 650 | int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state) |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 651 | { |
Mike Frysinger | f58c327 | 2011-04-15 03:08:20 -0400 | [diff] [blame] | 652 | #ifdef BF537_FAMILY |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 653 | return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state); |
| 654 | #else |
| 655 | return bfin_internal_set_wake(IRQ_MAC_ERROR, state); |
| 656 | #endif |
| 657 | } |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 658 | #else |
| 659 | # define bfin_mac_status_set_wake NULL |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 660 | #endif |
| 661 | |
| 662 | static struct irq_chip bfin_mac_status_irqchip = { |
| 663 | .name = "MACST", |
Thomas Gleixner | 172d2d1 | 2011-02-06 18:23:34 +0000 | [diff] [blame] | 664 | .irq_mask = bfin_mac_status_mask_irq, |
| 665 | .irq_unmask = bfin_mac_status_unmask_irq, |
Thomas Gleixner | 172d2d1 | 2011-02-06 18:23:34 +0000 | [diff] [blame] | 666 | .irq_set_wake = bfin_mac_status_set_wake, |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 667 | }; |
| 668 | |
Mike Frysinger | f58c327 | 2011-04-15 03:08:20 -0400 | [diff] [blame] | 669 | void bfin_demux_mac_status_irq(unsigned int int_err_irq, |
| 670 | struct irq_desc *inta_desc) |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 671 | { |
| 672 | int i, irq = 0; |
| 673 | u32 status = bfin_read_EMAC_SYSTAT(); |
| 674 | |
Michael Hennerich | bedeea6 | 2010-08-20 11:59:27 +0000 | [diff] [blame] | 675 | for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++) |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 676 | if (status & (1L << i)) { |
| 677 | irq = IRQ_MAC_PHYINT + i; |
| 678 | break; |
| 679 | } |
| 680 | |
| 681 | if (irq) { |
| 682 | if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) { |
| 683 | bfin_handle_irq(irq); |
| 684 | } else { |
| 685 | bfin_mac_status_ack_irq(irq); |
| 686 | pr_debug("IRQ %d:" |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 687 | " MASKED MAC ERROR INTERRUPT ASSERTED\n", |
| 688 | irq); |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 689 | } |
| 690 | } else |
| 691 | printk(KERN_ERR |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 692 | "%s : %s : LINE %d :\nIRQ ?: MAC ERROR" |
| 693 | " INTERRUPT ASSERTED BUT NO SOURCE FOUND" |
| 694 | "(EMAC_SYSTAT=0x%X)\n", |
| 695 | __func__, __FILE__, __LINE__, status); |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 696 | } |
| 697 | #endif |
| 698 | |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 699 | static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) |
| 700 | { |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 701 | #ifdef CONFIG_IPIPE |
Philippe Gerum | 5b5da4c | 2011-03-17 02:12:48 -0400 | [diff] [blame] | 702 | handle = handle_level_irq; |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 703 | #endif |
Thomas Gleixner | 43f2f115 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 704 | __irq_set_handler_locked(irq, handle); |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 705 | } |
| 706 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 707 | static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); |
Michael Hennerich | affee2b2 | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 708 | extern void bfin_gpio_irq_prepare(unsigned gpio); |
Michael Hennerich | 6fce6a8 | 2007-12-24 16:56:12 +0800 | [diff] [blame] | 709 | |
Mike Frysinger | 01f8e34 | 2011-06-26 13:56:23 -0400 | [diff] [blame] | 710 | #if !BFIN_GPIO_PINT |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 711 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 712 | static void bfin_gpio_ack_irq(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 713 | { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 714 | /* AFAIK ack_irq in case mask_ack is provided |
| 715 | * get's only called for edge sense irqs |
| 716 | */ |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 717 | set_gpio_data(irq_to_gpio(d->irq), 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 718 | } |
| 719 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 720 | static void bfin_gpio_mask_ack_irq(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 721 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 722 | unsigned int irq = d->irq; |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 723 | u32 gpionr = irq_to_gpio(irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 724 | |
Thomas Gleixner | 1907d8b | 2011-03-24 17:21:01 +0100 | [diff] [blame] | 725 | if (!irqd_is_level_type(d)) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 726 | set_gpio_data(gpionr, 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 727 | |
| 728 | set_gpio_maska(gpionr, 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 729 | } |
| 730 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 731 | static void bfin_gpio_mask_irq(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 732 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 733 | set_gpio_maska(irq_to_gpio(d->irq), 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 734 | } |
| 735 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 736 | static void bfin_gpio_unmask_irq(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 737 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 738 | set_gpio_maska(irq_to_gpio(d->irq), 1); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 739 | } |
| 740 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 741 | static unsigned int bfin_gpio_irq_startup(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 742 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 743 | u32 gpionr = irq_to_gpio(d->irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 744 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 745 | if (__test_and_set_bit(gpionr, gpio_enabled)) |
Michael Hennerich | affee2b2 | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 746 | bfin_gpio_irq_prepare(gpionr); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 747 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 748 | bfin_gpio_unmask_irq(d); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 749 | |
Michael Hennerich | affee2b2 | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 750 | return 0; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 751 | } |
| 752 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 753 | static void bfin_gpio_irq_shutdown(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 754 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 755 | u32 gpionr = irq_to_gpio(d->irq); |
Graf Yang | 30af6d4 | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 756 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 757 | bfin_gpio_mask_irq(d); |
Graf Yang | 30af6d4 | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 758 | __clear_bit(gpionr, gpio_enabled); |
Graf Yang | 9570ff4 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 759 | bfin_gpio_irq_free(gpionr); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 760 | } |
| 761 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 762 | static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 763 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 764 | unsigned int irq = d->irq; |
Graf Yang | 8eb3e3b | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 765 | int ret; |
| 766 | char buf[16]; |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 767 | u32 gpionr = irq_to_gpio(irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 768 | |
| 769 | if (type == IRQ_TYPE_PROBE) { |
| 770 | /* only probe unenabled GPIO interrupt lines */ |
Mike Frysinger | c369534 | 2009-06-13 10:32:29 -0400 | [diff] [blame] | 771 | if (test_bit(gpionr, gpio_enabled)) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 772 | return 0; |
| 773 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 774 | } |
| 775 | |
| 776 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 777 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 778 | |
Graf Yang | 9570ff4 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 779 | snprintf(buf, 16, "gpio-irq%d", irq); |
| 780 | ret = bfin_gpio_irq_request(gpionr, buf); |
| 781 | if (ret) |
| 782 | return ret; |
| 783 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 784 | if (__test_and_set_bit(gpionr, gpio_enabled)) |
Michael Hennerich | affee2b2 | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 785 | bfin_gpio_irq_prepare(gpionr); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 786 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 787 | } else { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 788 | __clear_bit(gpionr, gpio_enabled); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 789 | return 0; |
| 790 | } |
| 791 | |
Michael Hennerich | f1bceb4 | 2008-02-02 16:17:52 +0800 | [diff] [blame] | 792 | set_gpio_inen(gpionr, 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 793 | set_gpio_dir(gpionr, 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 794 | |
| 795 | if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
| 796 | == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
| 797 | set_gpio_both(gpionr, 1); |
| 798 | else |
| 799 | set_gpio_both(gpionr, 0); |
| 800 | |
| 801 | if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) |
| 802 | set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */ |
| 803 | else |
| 804 | set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */ |
| 805 | |
Michael Hennerich | f1bceb4 | 2008-02-02 16:17:52 +0800 | [diff] [blame] | 806 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
| 807 | set_gpio_edge(gpionr, 1); |
| 808 | set_gpio_inen(gpionr, 1); |
Michael Hennerich | f1bceb4 | 2008-02-02 16:17:52 +0800 | [diff] [blame] | 809 | set_gpio_data(gpionr, 0); |
| 810 | |
| 811 | } else { |
| 812 | set_gpio_edge(gpionr, 0); |
Michael Hennerich | f1bceb4 | 2008-02-02 16:17:52 +0800 | [diff] [blame] | 813 | set_gpio_inen(gpionr, 1); |
| 814 | } |
| 815 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 816 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 817 | bfin_set_irq_handler(irq, handle_edge_irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 818 | else |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 819 | bfin_set_irq_handler(irq, handle_level_irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 820 | |
| 821 | return 0; |
| 822 | } |
| 823 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 824 | #ifdef CONFIG_PM |
Mike Frysinger | dd8cb37 | 2011-04-15 03:19:22 -0400 | [diff] [blame] | 825 | static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 826 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 827 | return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state); |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 828 | } |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 829 | #else |
| 830 | # define bfin_gpio_set_wake NULL |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 831 | #endif |
| 832 | |
Mike Frysinger | e2a8092 | 2011-04-15 12:51:33 -0400 | [diff] [blame] | 833 | static void bfin_demux_gpio_block(unsigned int irq) |
| 834 | { |
| 835 | unsigned int gpio, mask; |
| 836 | |
| 837 | gpio = irq_to_gpio(irq); |
| 838 | mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio); |
| 839 | |
| 840 | while (mask) { |
| 841 | if (mask & 1) |
| 842 | bfin_handle_irq(irq); |
| 843 | irq++; |
| 844 | mask >>= 1; |
| 845 | } |
| 846 | } |
| 847 | |
Mike Frysinger | 8c05410 | 2011-04-15 13:04:59 -0400 | [diff] [blame] | 848 | void bfin_demux_gpio_irq(unsigned int inta_irq, |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 849 | struct irq_desc *desc) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 850 | { |
Mike Frysinger | e2a8092 | 2011-04-15 12:51:33 -0400 | [diff] [blame] | 851 | unsigned int irq; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 852 | |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 853 | switch (inta_irq) { |
Mike Frysinger | e2a8092 | 2011-04-15 12:51:33 -0400 | [diff] [blame] | 854 | #if defined(BF537_FAMILY) |
Mike Frysinger | 8c05410 | 2011-04-15 13:04:59 -0400 | [diff] [blame] | 855 | case IRQ_PF_INTA_PG_INTA: |
Mike Frysinger | e2a8092 | 2011-04-15 12:51:33 -0400 | [diff] [blame] | 856 | bfin_demux_gpio_block(IRQ_PF0); |
| 857 | irq = IRQ_PG0; |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 858 | break; |
Mike Frysinger | 8c05410 | 2011-04-15 13:04:59 -0400 | [diff] [blame] | 859 | case IRQ_PH_INTA_MAC_RX: |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 860 | irq = IRQ_PH0; |
| 861 | break; |
Mike Frysinger | e2a8092 | 2011-04-15 12:51:33 -0400 | [diff] [blame] | 862 | #elif defined(BF533_FAMILY) |
| 863 | case IRQ_PROG_INTA: |
| 864 | irq = IRQ_PF0; |
| 865 | break; |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 866 | #elif defined(BF538_FAMILY) |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 867 | case IRQ_PORTF_INTA: |
| 868 | irq = IRQ_PF0; |
| 869 | break; |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 870 | #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 871 | case IRQ_PORTF_INTA: |
| 872 | irq = IRQ_PF0; |
| 873 | break; |
| 874 | case IRQ_PORTG_INTA: |
| 875 | irq = IRQ_PG0; |
| 876 | break; |
| 877 | case IRQ_PORTH_INTA: |
| 878 | irq = IRQ_PH0; |
| 879 | break; |
| 880 | #elif defined(CONFIG_BF561) |
| 881 | case IRQ_PROG0_INTA: |
| 882 | irq = IRQ_PF0; |
| 883 | break; |
| 884 | case IRQ_PROG1_INTA: |
| 885 | irq = IRQ_PF16; |
| 886 | break; |
| 887 | case IRQ_PROG2_INTA: |
| 888 | irq = IRQ_PF32; |
| 889 | break; |
| 890 | #endif |
| 891 | default: |
| 892 | BUG(); |
| 893 | return; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 894 | } |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 895 | |
Mike Frysinger | e2a8092 | 2011-04-15 12:51:33 -0400 | [diff] [blame] | 896 | bfin_demux_gpio_block(irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 897 | } |
| 898 | |
Mike Frysinger | 01f8e34 | 2011-06-26 13:56:23 -0400 | [diff] [blame] | 899 | #else |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 900 | |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 901 | #define NR_PINT_BITS 32 |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 902 | #define IRQ_NOT_AVAIL 0xFF |
| 903 | |
| 904 | #define PINT_2_BANK(x) ((x) >> 5) |
| 905 | #define PINT_2_BIT(x) ((x) & 0x1F) |
| 906 | #define PINT_BIT(x) (1 << (PINT_2_BIT(x))) |
| 907 | |
| 908 | static unsigned char irq2pint_lut[NR_PINTS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 909 | static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS]; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 910 | |
Mike Frysinger | 82ed5f7 | 2011-06-26 13:22:05 -0400 | [diff] [blame] | 911 | static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = { |
| 912 | (struct bfin_pint_regs *)PINT0_MASK_SET, |
| 913 | (struct bfin_pint_regs *)PINT1_MASK_SET, |
| 914 | (struct bfin_pint_regs *)PINT2_MASK_SET, |
| 915 | (struct bfin_pint_regs *)PINT3_MASK_SET, |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 916 | #ifdef CONFIG_BF60x |
| 917 | (struct bfin_pint_regs *)PINT4_MASK_SET, |
| 918 | (struct bfin_pint_regs *)PINT5_MASK_SET, |
| 919 | #endif |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 920 | }; |
| 921 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 922 | inline unsigned int get_irq_base(u32 bank, u8 bmap) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 923 | { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 924 | unsigned int irq_base; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 925 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 926 | #ifndef CONFIG_BF60x |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 927 | if (bank < 2) { /*PA-PB */ |
| 928 | irq_base = IRQ_PA0 + bmap * 16; |
| 929 | } else { /*PC-PJ */ |
| 930 | irq_base = IRQ_PC0 + bmap * 16; |
| 931 | } |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 932 | #else |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 933 | irq_base = IRQ_PA0 + bank * 16 + bmap * 16; |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 934 | #endif |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 935 | return irq_base; |
| 936 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 937 | |
| 938 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ |
| 939 | void init_pint_lut(void) |
| 940 | { |
| 941 | u16 bank, bit, irq_base, bit_pos; |
| 942 | u32 pint_assign; |
| 943 | u8 bmap; |
| 944 | |
| 945 | memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut)); |
| 946 | |
| 947 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { |
| 948 | |
| 949 | pint_assign = pint[bank]->assign; |
| 950 | |
| 951 | for (bit = 0; bit < NR_PINT_BITS; bit++) { |
| 952 | |
| 953 | bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF; |
| 954 | |
| 955 | irq_base = get_irq_base(bank, bmap); |
| 956 | |
| 957 | irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0); |
| 958 | bit_pos = bit + bank * NR_PINT_BITS; |
| 959 | |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 960 | pint2irq_lut[bit_pos] = irq_base - SYS_IRQS; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 961 | irq2pint_lut[irq_base - SYS_IRQS] = bit_pos; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 962 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 963 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 964 | } |
| 965 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 966 | static void bfin_gpio_ack_irq(struct irq_data *d) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 967 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 968 | u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 969 | u32 pintbit = PINT_BIT(pint_val); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 970 | u32 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 971 | |
Thomas Gleixner | 1907d8b | 2011-03-24 17:21:01 +0100 | [diff] [blame] | 972 | if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 973 | if (pint[bank]->invert_set & pintbit) |
| 974 | pint[bank]->invert_clear = pintbit; |
| 975 | else |
| 976 | pint[bank]->invert_set = pintbit; |
| 977 | } |
| 978 | pint[bank]->request = pintbit; |
| 979 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 980 | } |
| 981 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 982 | static void bfin_gpio_mask_ack_irq(struct irq_data *d) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 983 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 984 | u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 985 | u32 pintbit = PINT_BIT(pint_val); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 986 | u32 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 987 | |
Thomas Gleixner | 1907d8b | 2011-03-24 17:21:01 +0100 | [diff] [blame] | 988 | if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 989 | if (pint[bank]->invert_set & pintbit) |
| 990 | pint[bank]->invert_clear = pintbit; |
| 991 | else |
| 992 | pint[bank]->invert_set = pintbit; |
| 993 | } |
| 994 | |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 995 | pint[bank]->request = pintbit; |
| 996 | pint[bank]->mask_clear = pintbit; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 997 | } |
| 998 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 999 | static void bfin_gpio_mask_irq(struct irq_data *d) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1000 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1001 | u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1002 | |
| 1003 | pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1004 | } |
| 1005 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1006 | static void bfin_gpio_unmask_irq(struct irq_data *d) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1007 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1008 | u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 1009 | u32 pintbit = PINT_BIT(pint_val); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1010 | u32 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1011 | |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 1012 | pint[bank]->mask_set = pintbit; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1013 | } |
| 1014 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1015 | static unsigned int bfin_gpio_irq_startup(struct irq_data *d) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1016 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1017 | unsigned int irq = d->irq; |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1018 | u32 gpionr = irq_to_gpio(irq); |
| 1019 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1020 | |
Michael Hennerich | 50e163c | 2007-07-24 16:17:28 +0800 | [diff] [blame] | 1021 | if (pint_val == IRQ_NOT_AVAIL) { |
| 1022 | printk(KERN_ERR |
| 1023 | "GPIO IRQ %d :Not in PINT Assign table " |
| 1024 | "Reconfigure Interrupt to Port Assignemt\n", irq); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1025 | return -ENODEV; |
Michael Hennerich | 50e163c | 2007-07-24 16:17:28 +0800 | [diff] [blame] | 1026 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1027 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1028 | if (__test_and_set_bit(gpionr, gpio_enabled)) |
Michael Hennerich | affee2b2 | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 1029 | bfin_gpio_irq_prepare(gpionr); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1030 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1031 | bfin_gpio_unmask_irq(d); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1032 | |
Michael Hennerich | affee2b2 | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 1033 | return 0; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1034 | } |
| 1035 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1036 | static void bfin_gpio_irq_shutdown(struct irq_data *d) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1037 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1038 | u32 gpionr = irq_to_gpio(d->irq); |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 1039 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1040 | bfin_gpio_mask_irq(d); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1041 | __clear_bit(gpionr, gpio_enabled); |
Graf Yang | 9570ff4 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 1042 | bfin_gpio_irq_free(gpionr); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1043 | } |
| 1044 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1045 | static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1046 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1047 | unsigned int irq = d->irq; |
Graf Yang | 8eb3e3b | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1048 | int ret; |
| 1049 | char buf[16]; |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1050 | u32 gpionr = irq_to_gpio(irq); |
| 1051 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 1052 | u32 pintbit = PINT_BIT(pint_val); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1053 | u32 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1054 | |
| 1055 | if (pint_val == IRQ_NOT_AVAIL) |
| 1056 | return -ENODEV; |
| 1057 | |
| 1058 | if (type == IRQ_TYPE_PROBE) { |
| 1059 | /* only probe unenabled GPIO interrupt lines */ |
Mike Frysinger | c369534 | 2009-06-13 10:32:29 -0400 | [diff] [blame] | 1060 | if (test_bit(gpionr, gpio_enabled)) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1061 | return 0; |
| 1062 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 1063 | } |
| 1064 | |
| 1065 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | |
| 1066 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
Graf Yang | 9570ff4 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 1067 | |
| 1068 | snprintf(buf, 16, "gpio-irq%d", irq); |
| 1069 | ret = bfin_gpio_irq_request(gpionr, buf); |
| 1070 | if (ret) |
| 1071 | return ret; |
| 1072 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1073 | if (__test_and_set_bit(gpionr, gpio_enabled)) |
Michael Hennerich | affee2b2 | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 1074 | bfin_gpio_irq_prepare(gpionr); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1075 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1076 | } else { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1077 | __clear_bit(gpionr, gpio_enabled); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1078 | return 0; |
| 1079 | } |
| 1080 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1081 | if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 1082 | pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */ |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1083 | else |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 1084 | pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */ |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1085 | |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 1086 | if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
| 1087 | == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 1088 | if (gpio_get_value(gpionr)) |
| 1089 | pint[bank]->invert_set = pintbit; |
| 1090 | else |
| 1091 | pint[bank]->invert_clear = pintbit; |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 1092 | } |
| 1093 | |
| 1094 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
| 1095 | pint[bank]->edge_set = pintbit; |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 1096 | bfin_set_irq_handler(irq, handle_edge_irq); |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 1097 | } else { |
| 1098 | pint[bank]->edge_clear = pintbit; |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 1099 | bfin_set_irq_handler(irq, handle_level_irq); |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 1100 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1101 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1102 | return 0; |
| 1103 | } |
| 1104 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1105 | #ifdef CONFIG_PM |
Steven Miao | d49cdf840 | 2012-06-14 18:04:01 +0800 | [diff] [blame] | 1106 | static struct bfin_pm_pint_save save_pint_reg[NR_PINT_SYS_IRQS]; |
| 1107 | static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS]; |
| 1108 | |
Mike Frysinger | dd8cb37 | 2011-04-15 03:19:22 -0400 | [diff] [blame] | 1109 | static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1110 | { |
| 1111 | u32 pint_irq; |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1112 | u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1113 | u32 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1114 | |
| 1115 | switch (bank) { |
| 1116 | case 0: |
| 1117 | pint_irq = IRQ_PINT0; |
| 1118 | break; |
| 1119 | case 2: |
| 1120 | pint_irq = IRQ_PINT2; |
| 1121 | break; |
| 1122 | case 3: |
| 1123 | pint_irq = IRQ_PINT3; |
| 1124 | break; |
| 1125 | case 1: |
| 1126 | pint_irq = IRQ_PINT1; |
| 1127 | break; |
Bob Liu | 494b794 | 2012-04-27 14:13:01 +0800 | [diff] [blame] | 1128 | #ifdef CONFIG_BF60x |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1129 | case 4: |
| 1130 | pint_irq = IRQ_PINT4; |
| 1131 | break; |
| 1132 | case 5: |
| 1133 | pint_irq = IRQ_PINT5; |
| 1134 | break; |
Bob Liu | 494b794 | 2012-04-27 14:13:01 +0800 | [diff] [blame] | 1135 | #endif |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1136 | default: |
| 1137 | return -EINVAL; |
| 1138 | } |
| 1139 | |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 1140 | #ifndef SEC_GCTL |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1141 | bfin_internal_set_wake(pint_irq, state); |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 1142 | #endif |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1143 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1144 | return 0; |
| 1145 | } |
Steven Miao | d49cdf840 | 2012-06-14 18:04:01 +0800 | [diff] [blame] | 1146 | |
| 1147 | void bfin_pint_suspend(void) |
| 1148 | { |
| 1149 | u32 bank; |
| 1150 | |
| 1151 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { |
| 1152 | save_pint_reg[bank].mask_set = pint[bank]->mask_set; |
| 1153 | save_pint_reg[bank].assign = pint[bank]->assign; |
| 1154 | save_pint_reg[bank].edge_set = pint[bank]->edge_set; |
| 1155 | save_pint_reg[bank].invert_set = pint[bank]->invert_set; |
| 1156 | } |
| 1157 | } |
| 1158 | |
| 1159 | void bfin_pint_resume(void) |
| 1160 | { |
| 1161 | u32 bank; |
| 1162 | |
| 1163 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { |
| 1164 | pint[bank]->mask_set = save_pint_reg[bank].mask_set; |
| 1165 | pint[bank]->assign = save_pint_reg[bank].assign; |
| 1166 | pint[bank]->edge_set = save_pint_reg[bank].edge_set; |
| 1167 | pint[bank]->invert_set = save_pint_reg[bank].invert_set; |
| 1168 | } |
| 1169 | } |
| 1170 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1171 | #ifdef SEC_GCTL |
Steven Miao | d49cdf840 | 2012-06-14 18:04:01 +0800 | [diff] [blame] | 1172 | static int sec_suspend(void) |
| 1173 | { |
| 1174 | u32 bank; |
| 1175 | |
| 1176 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 1177 | save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0)); |
Steven Miao | d49cdf840 | 2012-06-14 18:04:01 +0800 | [diff] [blame] | 1178 | return 0; |
| 1179 | } |
| 1180 | |
| 1181 | static void sec_resume(void) |
| 1182 | { |
| 1183 | u32 bank; |
| 1184 | |
| 1185 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); |
| 1186 | udelay(100); |
| 1187 | bfin_write_SEC_GCTL(SEC_GCTL_EN); |
| 1188 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); |
| 1189 | |
| 1190 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 1191 | bfin_write_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]); |
Steven Miao | d49cdf840 | 2012-06-14 18:04:01 +0800 | [diff] [blame] | 1192 | } |
| 1193 | |
| 1194 | static struct syscore_ops sec_pm_syscore_ops = { |
| 1195 | .suspend = sec_suspend, |
| 1196 | .resume = sec_resume, |
| 1197 | }; |
Steven Miao | 36c4723 | 2012-12-21 14:34:16 +0800 | [diff] [blame] | 1198 | |
Steven Miao | 3375a43 | 2012-06-15 12:59:19 +0800 | [diff] [blame] | 1199 | #endif |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 1200 | #else |
| 1201 | # define bfin_gpio_set_wake NULL |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1202 | #endif |
| 1203 | |
Mike Frysinger | 8c05410 | 2011-04-15 13:04:59 -0400 | [diff] [blame] | 1204 | void bfin_demux_gpio_irq(unsigned int inta_irq, |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1205 | struct irq_desc *desc) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1206 | { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1207 | u32 bank, pint_val; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1208 | u32 request, irq; |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1209 | u32 level_mask; |
| 1210 | int umask = 0; |
| 1211 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 1212 | |
| 1213 | if (chip->irq_mask_ack) { |
| 1214 | chip->irq_mask_ack(&desc->irq_data); |
| 1215 | } else { |
| 1216 | chip->irq_mask(&desc->irq_data); |
| 1217 | if (chip->irq_ack) |
| 1218 | chip->irq_ack(&desc->irq_data); |
| 1219 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1220 | |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 1221 | switch (inta_irq) { |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1222 | case IRQ_PINT0: |
| 1223 | bank = 0; |
| 1224 | break; |
| 1225 | case IRQ_PINT2: |
| 1226 | bank = 2; |
| 1227 | break; |
| 1228 | case IRQ_PINT3: |
| 1229 | bank = 3; |
| 1230 | break; |
| 1231 | case IRQ_PINT1: |
| 1232 | bank = 1; |
| 1233 | break; |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1234 | #ifdef CONFIG_BF60x |
| 1235 | case IRQ_PINT4: |
| 1236 | bank = 4; |
| 1237 | break; |
| 1238 | case IRQ_PINT5: |
| 1239 | bank = 5; |
| 1240 | break; |
| 1241 | #endif |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 1242 | default: |
| 1243 | return; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1244 | } |
| 1245 | |
| 1246 | pint_val = bank * NR_PINT_BITS; |
| 1247 | |
| 1248 | request = pint[bank]->request; |
| 1249 | |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1250 | level_mask = pint[bank]->edge_set & request; |
| 1251 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1252 | while (request) { |
| 1253 | if (request & 1) { |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 1254 | irq = pint2irq_lut[pint_val] + SYS_IRQS; |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1255 | if (level_mask & PINT_BIT(pint_val)) { |
| 1256 | umask = 1; |
| 1257 | chip->irq_unmask(&desc->irq_data); |
| 1258 | } |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1259 | bfin_handle_irq(irq); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1260 | } |
| 1261 | pint_val++; |
| 1262 | request >>= 1; |
| 1263 | } |
| 1264 | |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1265 | if (!umask) |
| 1266 | chip->irq_unmask(&desc->irq_data); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1267 | } |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1268 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1269 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1270 | static struct irq_chip bfin_gpio_irqchip = { |
| 1271 | .name = "GPIO", |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1272 | .irq_ack = bfin_gpio_ack_irq, |
| 1273 | .irq_mask = bfin_gpio_mask_irq, |
| 1274 | .irq_mask_ack = bfin_gpio_mask_ack_irq, |
| 1275 | .irq_unmask = bfin_gpio_unmask_irq, |
| 1276 | .irq_disable = bfin_gpio_mask_irq, |
| 1277 | .irq_enable = bfin_gpio_unmask_irq, |
| 1278 | .irq_set_type = bfin_gpio_irq_type, |
| 1279 | .irq_startup = bfin_gpio_irq_startup, |
| 1280 | .irq_shutdown = bfin_gpio_irq_shutdown, |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1281 | .irq_set_wake = bfin_gpio_set_wake, |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1282 | }; |
| 1283 | |
Paul Gortmaker | 13dff62 | 2013-06-18 16:56:21 -0400 | [diff] [blame] | 1284 | void init_exception_vectors(void) |
Bernd Schmidt | 8be80ed | 2007-07-25 14:44:49 +0800 | [diff] [blame] | 1285 | { |
Mike Frysinger | f0b5d12 | 2007-08-05 17:03:59 +0800 | [diff] [blame] | 1286 | /* cannot program in software: |
| 1287 | * evt0 - emulation (jtag) |
| 1288 | * evt1 - reset |
| 1289 | */ |
| 1290 | bfin_write_EVT2(evt_nmi); |
Bernd Schmidt | 8be80ed | 2007-07-25 14:44:49 +0800 | [diff] [blame] | 1291 | bfin_write_EVT3(trap); |
| 1292 | bfin_write_EVT5(evt_ivhw); |
| 1293 | bfin_write_EVT6(evt_timer); |
| 1294 | bfin_write_EVT7(evt_evt7); |
| 1295 | bfin_write_EVT8(evt_evt8); |
| 1296 | bfin_write_EVT9(evt_evt9); |
| 1297 | bfin_write_EVT10(evt_evt10); |
| 1298 | bfin_write_EVT11(evt_evt11); |
| 1299 | bfin_write_EVT12(evt_evt12); |
| 1300 | bfin_write_EVT13(evt_evt13); |
Philippe Gerum | 9703a73 | 2009-06-22 18:23:48 +0200 | [diff] [blame] | 1301 | bfin_write_EVT14(evt_evt14); |
Bernd Schmidt | 8be80ed | 2007-07-25 14:44:49 +0800 | [diff] [blame] | 1302 | bfin_write_EVT15(evt_system_call); |
| 1303 | CSYNC(); |
| 1304 | } |
| 1305 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1306 | #ifndef SEC_GCTL |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1307 | /* |
| 1308 | * This function should be called during kernel startup to initialize |
| 1309 | * the BFin IRQ handling routines. |
| 1310 | */ |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1311 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1312 | int __init init_arch_irq(void) |
| 1313 | { |
| 1314 | int irq; |
| 1315 | unsigned long ilat = 0; |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 1316 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1317 | /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 1318 | #ifdef SIC_IMASK0 |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1319 | bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); |
| 1320 | bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 1321 | # ifdef SIC_IMASK2 |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 1322 | bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1323 | # endif |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1324 | # if defined(CONFIG_SMP) || defined(CONFIG_ICC) |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1325 | bfin_write_SICB_IMASK0(SIC_UNMASK_ALL); |
| 1326 | bfin_write_SICB_IMASK1(SIC_UNMASK_ALL); |
| 1327 | # endif |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1328 | #else |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1329 | bfin_write_SIC_IMASK(SIC_UNMASK_ALL); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1330 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1331 | |
| 1332 | local_irq_disable(); |
| 1333 | |
Mike Frysinger | 01f8e34 | 2011-06-26 13:56:23 -0400 | [diff] [blame] | 1334 | #if BFIN_GPIO_PINT |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1335 | # ifdef CONFIG_PINTx_REASSIGN |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1336 | pint[0]->assign = CONFIG_PINT0_ASSIGN; |
| 1337 | pint[1]->assign = CONFIG_PINT1_ASSIGN; |
| 1338 | pint[2]->assign = CONFIG_PINT2_ASSIGN; |
| 1339 | pint[3]->assign = CONFIG_PINT3_ASSIGN; |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1340 | # endif |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1341 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ |
| 1342 | init_pint_lut(); |
| 1343 | #endif |
| 1344 | |
| 1345 | for (irq = 0; irq <= SYS_IRQS; irq++) { |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1346 | if (irq <= IRQ_CORETMR) |
Thomas Gleixner | 43f2f115 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1347 | irq_set_chip(irq, &bfin_core_irqchip); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1348 | else |
Thomas Gleixner | 43f2f115 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1349 | irq_set_chip(irq, &bfin_internal_irqchip); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1350 | |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1351 | switch (irq) { |
Mike Frysinger | 01f8e34 | 2011-06-26 13:56:23 -0400 | [diff] [blame] | 1352 | #if BFIN_GPIO_PINT |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1353 | case IRQ_PINT0: |
| 1354 | case IRQ_PINT1: |
| 1355 | case IRQ_PINT2: |
| 1356 | case IRQ_PINT3: |
Mike Frysinger | 01f8e34 | 2011-06-26 13:56:23 -0400 | [diff] [blame] | 1357 | #elif defined(BF537_FAMILY) |
| 1358 | case IRQ_PH_INTA_MAC_RX: |
| 1359 | case IRQ_PF_INTA_PG_INTA: |
| 1360 | #elif defined(BF533_FAMILY) |
| 1361 | case IRQ_PROG_INTA: |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 1362 | #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1363 | case IRQ_PORTF_INTA: |
| 1364 | case IRQ_PORTG_INTA: |
| 1365 | case IRQ_PORTH_INTA: |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 1366 | #elif defined(CONFIG_BF561) |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1367 | case IRQ_PROG0_INTA: |
| 1368 | case IRQ_PROG1_INTA: |
| 1369 | case IRQ_PROG2_INTA: |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 1370 | #elif defined(BF538_FAMILY) |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1371 | case IRQ_PORTF_INTA: |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 1372 | #endif |
Thomas Gleixner | 43f2f115 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1373 | irq_set_chained_handler(irq, bfin_demux_gpio_irq); |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1374 | break; |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 1375 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) |
| 1376 | case IRQ_MAC_ERROR: |
Thomas Gleixner | 43f2f115 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1377 | irq_set_chained_handler(irq, |
| 1378 | bfin_demux_mac_status_irq); |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 1379 | break; |
| 1380 | #endif |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1381 | #if defined(CONFIG_SMP) || defined(CONFIG_ICC) |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1382 | case IRQ_SUPPLE_0: |
| 1383 | case IRQ_SUPPLE_1: |
Thomas Gleixner | 43f2f115 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1384 | irq_set_handler(irq, handle_percpu_irq); |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1385 | break; |
| 1386 | #endif |
Graf Yang | 17941314 | 2009-08-18 04:29:33 +0000 | [diff] [blame] | 1387 | |
Yi Li | cb19171 | 2009-12-30 07:12:50 +0000 | [diff] [blame] | 1388 | #ifdef CONFIG_TICKSOURCE_CORETMR |
| 1389 | case IRQ_CORETMR: |
| 1390 | # ifdef CONFIG_SMP |
Thomas Gleixner | 43f2f115 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1391 | irq_set_handler(irq, handle_percpu_irq); |
Yi Li | cb19171 | 2009-12-30 07:12:50 +0000 | [diff] [blame] | 1392 | # else |
Thomas Gleixner | 43f2f115 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1393 | irq_set_handler(irq, handle_simple_irq); |
Yi Li | cb19171 | 2009-12-30 07:12:50 +0000 | [diff] [blame] | 1394 | # endif |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 1395 | break; |
Yi Li | cb19171 | 2009-12-30 07:12:50 +0000 | [diff] [blame] | 1396 | #endif |
| 1397 | |
| 1398 | #ifdef CONFIG_TICKSOURCE_GPTMR0 |
Philippe Gerum | a40494a | 2009-06-16 05:25:42 +0200 | [diff] [blame] | 1399 | case IRQ_TIMER0: |
Thomas Gleixner | 43f2f115 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1400 | irq_set_handler(irq, handle_simple_irq); |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1401 | break; |
Graf Yang | 17941314 | 2009-08-18 04:29:33 +0000 | [diff] [blame] | 1402 | #endif |
Yi Li | cb19171 | 2009-12-30 07:12:50 +0000 | [diff] [blame] | 1403 | |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 1404 | default: |
Yi Li | cb19171 | 2009-12-30 07:12:50 +0000 | [diff] [blame] | 1405 | #ifdef CONFIG_IPIPE |
Thomas Gleixner | 43f2f115 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1406 | irq_set_handler(irq, handle_level_irq); |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 1407 | #else |
Thomas Gleixner | 43f2f115 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1408 | irq_set_handler(irq, handle_simple_irq); |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 1409 | #endif |
Philippe Gerum | a40494a | 2009-06-16 05:25:42 +0200 | [diff] [blame] | 1410 | break; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1411 | } |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1412 | } |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1413 | |
Mike Frysinger | f58c327 | 2011-04-15 03:08:20 -0400 | [diff] [blame] | 1414 | init_mach_irq(); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1415 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1416 | #if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 1417 | for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++) |
Thomas Gleixner | 43f2f115 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1418 | irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip, |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 1419 | handle_level_irq); |
| 1420 | #endif |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1421 | /* if configured as edge, then will be changed to do_edge_IRQ */ |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 1422 | for (irq = GPIO_IRQ_BASE; |
| 1423 | irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) |
Thomas Gleixner | 43f2f115 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1424 | irq_set_chip_and_handler(irq, &bfin_gpio_irqchip, |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1425 | handle_level_irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1426 | bfin_write_IMASK(0); |
| 1427 | CSYNC(); |
| 1428 | ilat = bfin_read_ILAT(); |
| 1429 | CSYNC(); |
| 1430 | bfin_write_ILAT(ilat); |
| 1431 | CSYNC(); |
| 1432 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1433 | printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n"); |
Mike Frysinger | 4005978 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1434 | /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx, |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1435 | * local_irq_enable() |
| 1436 | */ |
| 1437 | program_IAR(); |
| 1438 | /* Therefore it's better to setup IARs before interrupts enabled */ |
| 1439 | search_IAR(); |
| 1440 | |
| 1441 | /* Enable interrupts IVG7-15 */ |
Mike Frysinger | 4005978 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1442 | bfin_irq_flags |= IMASK_IVG15 | |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1443 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | |
| 1444 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; |
| 1445 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1446 | |
Michael Hennerich | 349ebbcc | 2009-04-15 08:48:08 +0000 | [diff] [blame] | 1447 | /* This implicitly covers ANOMALY_05000171 |
| 1448 | * Boot-ROM code modifies SICA_IWRx wakeup registers |
| 1449 | */ |
Mike Frysinger | be1d854 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 1450 | #ifdef SIC_IWR0 |
Michael Hennerich | 56f5f59 | 2008-08-06 17:55:32 +0800 | [diff] [blame] | 1451 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); |
Mike Frysinger | be1d854 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 1452 | # ifdef SIC_IWR1 |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 1453 | /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which |
Michael Hennerich | 55546ac | 2008-08-13 17:41:13 +0800 | [diff] [blame] | 1454 | * will screw up the bootrom as it relies on MDMA0/1 waking it |
| 1455 | * up from IDLE instructions. See this report for more info: |
| 1456 | * http://blackfin.uclinux.org/gf/tracker/4323 |
| 1457 | */ |
Mike Frysinger | b7e1129 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1458 | if (ANOMALY_05000435) |
| 1459 | bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); |
| 1460 | else |
| 1461 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); |
Mike Frysinger | be1d854 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 1462 | # endif |
| 1463 | # ifdef SIC_IWR2 |
Michael Hennerich | 56f5f59 | 2008-08-06 17:55:32 +0800 | [diff] [blame] | 1464 | bfin_write_SIC_IWR2(IWR_DISABLE_ALL); |
Michael Hennerich | fe9ec9b | 2008-02-25 12:04:57 +0800 | [diff] [blame] | 1465 | # endif |
| 1466 | #else |
Michael Hennerich | 56f5f59 | 2008-08-06 17:55:32 +0800 | [diff] [blame] | 1467 | bfin_write_SIC_IWR(IWR_DISABLE_ALL); |
Michael Hennerich | fe9ec9b | 2008-02-25 12:04:57 +0800 | [diff] [blame] | 1468 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1469 | return 0; |
| 1470 | } |
| 1471 | |
| 1472 | #ifdef CONFIG_DO_IRQ_L1 |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1473 | __attribute__((l1_text)) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1474 | #endif |
Mike Frysinger | 6b10804 | 2011-03-30 01:35:41 -0400 | [diff] [blame] | 1475 | static int vec_to_irq(int vec) |
| 1476 | { |
| 1477 | struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; |
| 1478 | struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; |
| 1479 | unsigned long sic_status[3]; |
Mike Frysinger | 6b10804 | 2011-03-30 01:35:41 -0400 | [diff] [blame] | 1480 | if (likely(vec == EVT_IVTMR_P)) |
| 1481 | return IRQ_CORETMR; |
Mike Frysinger | 6b10804 | 2011-03-30 01:35:41 -0400 | [diff] [blame] | 1482 | #ifdef SIC_ISR |
| 1483 | sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); |
| 1484 | #else |
| 1485 | if (smp_processor_id()) { |
| 1486 | # ifdef SICB_ISR0 |
| 1487 | /* This will be optimized out in UP mode. */ |
| 1488 | sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0(); |
| 1489 | sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1(); |
| 1490 | # endif |
| 1491 | } else { |
| 1492 | sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); |
| 1493 | sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); |
| 1494 | } |
| 1495 | #endif |
| 1496 | #ifdef SIC_ISR2 |
| 1497 | sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); |
| 1498 | #endif |
| 1499 | |
| 1500 | for (;; ivg++) { |
| 1501 | if (ivg >= ivg_stop) |
| 1502 | return -1; |
| 1503 | #ifdef SIC_ISR |
| 1504 | if (sic_status[0] & ivg->isrflag) |
| 1505 | #else |
| 1506 | if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) |
| 1507 | #endif |
| 1508 | return ivg->irqno; |
| 1509 | } |
| 1510 | } |
| 1511 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1512 | #else /* SEC_GCTL */ |
| 1513 | |
| 1514 | /* |
| 1515 | * This function should be called during kernel startup to initialize |
| 1516 | * the BFin IRQ handling routines. |
| 1517 | */ |
| 1518 | |
| 1519 | int __init init_arch_irq(void) |
| 1520 | { |
| 1521 | int irq; |
| 1522 | unsigned long ilat = 0; |
| 1523 | |
| 1524 | bfin_write_SEC_GCTL(SEC_GCTL_RESET); |
| 1525 | |
| 1526 | local_irq_disable(); |
| 1527 | |
| 1528 | #if BFIN_GPIO_PINT |
| 1529 | # ifdef CONFIG_PINTx_REASSIGN |
| 1530 | pint[0]->assign = CONFIG_PINT0_ASSIGN; |
| 1531 | pint[1]->assign = CONFIG_PINT1_ASSIGN; |
| 1532 | pint[2]->assign = CONFIG_PINT2_ASSIGN; |
| 1533 | pint[3]->assign = CONFIG_PINT3_ASSIGN; |
| 1534 | pint[4]->assign = CONFIG_PINT4_ASSIGN; |
| 1535 | pint[5]->assign = CONFIG_PINT5_ASSIGN; |
| 1536 | # endif |
| 1537 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ |
| 1538 | init_pint_lut(); |
| 1539 | #endif |
| 1540 | |
| 1541 | for (irq = 0; irq <= SYS_IRQS; irq++) { |
| 1542 | if (irq <= IRQ_CORETMR) { |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 1543 | irq_set_chip_and_handler(irq, &bfin_core_irqchip, |
| 1544 | handle_simple_irq); |
| 1545 | #if defined(CONFIG_TICKSOURCE_CORETMR) && defined(CONFIG_SMP) |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1546 | if (irq == IRQ_CORETMR) |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1547 | irq_set_handler(irq, handle_percpu_irq); |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1548 | #endif |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1549 | } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) { |
| 1550 | irq_set_chip(irq, &bfin_sec_irqchip); |
| 1551 | irq_set_chained_handler(irq, bfin_demux_gpio_irq); |
| 1552 | } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) { |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1553 | irq_set_chip_and_handler(irq, &bfin_sec_irqchip, |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 1554 | handle_percpu_irq); |
| 1555 | } else { |
| 1556 | irq_set_chip(irq, &bfin_sec_irqchip); |
| 1557 | if (irq == IRQ_SEC_ERR) |
| 1558 | irq_set_handler(irq, handle_sec_fault); |
| 1559 | else if (irq >= IRQ_C0_DBL_FAULT && irq < CORE_IRQS) |
| 1560 | irq_set_handler(irq, handle_core_fault); |
| 1561 | else |
| 1562 | irq_set_handler(irq, handle_fasteoi_irq); |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1563 | __irq_set_preflow_handler(irq, bfin_sec_preflow_handler); |
| 1564 | } |
| 1565 | } |
| 1566 | for (irq = GPIO_IRQ_BASE; |
| 1567 | irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) |
| 1568 | irq_set_chip_and_handler(irq, &bfin_gpio_irqchip, |
| 1569 | handle_level_irq); |
| 1570 | |
| 1571 | bfin_write_IMASK(0); |
| 1572 | CSYNC(); |
| 1573 | ilat = bfin_read_ILAT(); |
| 1574 | CSYNC(); |
| 1575 | bfin_write_ILAT(ilat); |
| 1576 | CSYNC(); |
| 1577 | |
| 1578 | printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n"); |
| 1579 | |
Sonic Zhang | e0a5931 | 2012-06-29 18:19:29 +0800 | [diff] [blame] | 1580 | bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority); |
| 1581 | |
| 1582 | bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority); |
| 1583 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1584 | /* Enable interrupts IVG7-15 */ |
| 1585 | bfin_irq_flags |= IMASK_IVG15 | |
| 1586 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | |
| 1587 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; |
| 1588 | |
| 1589 | |
| 1590 | bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN); |
Sonic Zhang | 86794b4 | 2012-12-14 11:19:24 +0800 | [diff] [blame] | 1591 | bfin_sec_enable_sci(BFIN_SYSIRQ(IRQ_WATCH0)); |
| 1592 | bfin_sec_enable_ssi(BFIN_SYSIRQ(IRQ_WATCH0)); |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1593 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); |
| 1594 | udelay(100); |
| 1595 | bfin_write_SEC_GCTL(SEC_GCTL_EN); |
| 1596 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); |
| 1597 | bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); |
| 1598 | |
| 1599 | init_software_driven_irq(); |
Steven Miao | 36c4723 | 2012-12-21 14:34:16 +0800 | [diff] [blame] | 1600 | |
| 1601 | #ifdef CONFIG_PM |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1602 | register_syscore_ops(&sec_pm_syscore_ops); |
Steven Miao | 36c4723 | 2012-12-21 14:34:16 +0800 | [diff] [blame] | 1603 | #endif |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1604 | |
| 1605 | return 0; |
| 1606 | } |
| 1607 | |
| 1608 | #ifdef CONFIG_DO_IRQ_L1 |
| 1609 | __attribute__((l1_text)) |
| 1610 | #endif |
| 1611 | static int vec_to_irq(int vec) |
| 1612 | { |
| 1613 | if (likely(vec == EVT_IVTMR_P)) |
| 1614 | return IRQ_CORETMR; |
| 1615 | |
| 1616 | return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID)); |
| 1617 | } |
| 1618 | #endif /* SEC_GCTL */ |
| 1619 | |
Mike Frysinger | 6b10804 | 2011-03-30 01:35:41 -0400 | [diff] [blame] | 1620 | #ifdef CONFIG_DO_IRQ_L1 |
| 1621 | __attribute__((l1_text)) |
| 1622 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1623 | void do_irq(int vec, struct pt_regs *fp) |
| 1624 | { |
Mike Frysinger | 6b10804 | 2011-03-30 01:35:41 -0400 | [diff] [blame] | 1625 | int irq = vec_to_irq(vec); |
| 1626 | if (irq == -1) |
| 1627 | return; |
| 1628 | asm_do_IRQ(irq, fp); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1629 | } |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1630 | |
| 1631 | #ifdef CONFIG_IPIPE |
| 1632 | |
| 1633 | int __ipipe_get_irq_priority(unsigned irq) |
| 1634 | { |
| 1635 | int ient, prio; |
| 1636 | |
| 1637 | if (irq <= IRQ_CORETMR) |
| 1638 | return irq; |
| 1639 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1640 | #ifdef SEC_GCTL |
| 1641 | if (irq >= BFIN_IRQ(0)) |
| 1642 | return IVG11; |
| 1643 | #else |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1644 | for (ient = 0; ient < NR_PERI_INTS; ient++) { |
| 1645 | struct ivgx *ivg = ivg_table + ient; |
| 1646 | if (ivg->irqno == irq) { |
| 1647 | for (prio = 0; prio <= IVG13-IVG7; prio++) { |
| 1648 | if (ivg7_13[prio].ifirst <= ivg && |
| 1649 | ivg7_13[prio].istop > ivg) |
| 1650 | return IVG7 + prio; |
| 1651 | } |
| 1652 | } |
| 1653 | } |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1654 | #endif |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1655 | |
| 1656 | return IVG15; |
| 1657 | } |
| 1658 | |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1659 | /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */ |
| 1660 | #ifdef CONFIG_DO_IRQ_L1 |
| 1661 | __attribute__((l1_text)) |
| 1662 | #endif |
| 1663 | asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) |
| 1664 | { |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1665 | struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); |
Philippe Gerum | a40494a | 2009-06-16 05:25:42 +0200 | [diff] [blame] | 1666 | struct ipipe_domain *this_domain = __ipipe_current_domain; |
Philippe Gerum | 5b5da4c | 2011-03-17 02:12:48 -0400 | [diff] [blame] | 1667 | int irq, s = 0; |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1668 | |
Mike Frysinger | 6b10804 | 2011-03-30 01:35:41 -0400 | [diff] [blame] | 1669 | irq = vec_to_irq(vec); |
| 1670 | if (irq == -1) |
| 1671 | return 0; |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1672 | |
| 1673 | if (irq == IRQ_SYSTMR) { |
Philippe Gerum | a40494a | 2009-06-16 05:25:42 +0200 | [diff] [blame] | 1674 | #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0) |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1675 | bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1676 | #endif |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1677 | /* This is basically what we need from the register frame. */ |
| 1678 | __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend; |
| 1679 | __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc; |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1680 | if (this_domain != ipipe_root_domain) |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1681 | __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10; |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1682 | else |
| 1683 | __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1684 | } |
| 1685 | |
Philippe Gerum | 5b5da4c | 2011-03-17 02:12:48 -0400 | [diff] [blame] | 1686 | /* |
| 1687 | * We don't want Linux interrupt handlers to run at the |
| 1688 | * current core priority level (i.e. < EVT15), since this |
| 1689 | * might delay other interrupts handled by a high priority |
| 1690 | * domain. Here is what we do instead: |
| 1691 | * |
| 1692 | * - we raise the SYNCDEFER bit to prevent |
| 1693 | * __ipipe_handle_irq() to sync the pipeline for the root |
| 1694 | * stage for the incoming interrupt. Upon return, that IRQ is |
| 1695 | * pending in the interrupt log. |
| 1696 | * |
| 1697 | * - we raise the TIF_IRQ_SYNC bit for the current thread, so |
| 1698 | * that _schedule_and_signal_from_int will eventually sync the |
| 1699 | * pipeline from EVT15. |
| 1700 | */ |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1701 | if (this_domain == ipipe_root_domain) { |
| 1702 | s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status); |
| 1703 | barrier(); |
| 1704 | } |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1705 | |
| 1706 | ipipe_trace_irq_entry(irq); |
| 1707 | __ipipe_handle_irq(irq, regs); |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1708 | ipipe_trace_irq_exit(irq); |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1709 | |
Philippe Gerum | 5b5da4c | 2011-03-17 02:12:48 -0400 | [diff] [blame] | 1710 | if (user_mode(regs) && |
| 1711 | !ipipe_test_foreign_stack() && |
| 1712 | (current->ipipe_flags & PF_EVTRET) != 0) { |
| 1713 | /* |
| 1714 | * Testing for user_regs() does NOT fully eliminate |
| 1715 | * foreign stack contexts, because of the forged |
| 1716 | * interrupt returns we do through |
| 1717 | * __ipipe_call_irqtail. In that case, we might have |
| 1718 | * preempted a foreign stack context in a high |
| 1719 | * priority domain, with a single interrupt level now |
| 1720 | * pending after the irqtail unwinding is done. In |
| 1721 | * which case user_mode() is now true, and the event |
| 1722 | * gets dispatched spuriously. |
| 1723 | */ |
| 1724 | current->ipipe_flags &= ~PF_EVTRET; |
| 1725 | __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs); |
| 1726 | } |
| 1727 | |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1728 | if (this_domain == ipipe_root_domain) { |
| 1729 | set_thread_flag(TIF_IRQ_SYNC); |
| 1730 | if (!s) { |
| 1731 | __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status); |
| 1732 | return !test_bit(IPIPE_STALL_FLAG, &p->status); |
| 1733 | } |
| 1734 | } |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1735 | |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 1736 | return 0; |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1737 | } |
| 1738 | |
| 1739 | #endif /* CONFIG_IPIPE */ |