blob: e6e35e6958f6dfb66b550b0a8ce943fe1668cb46 [file] [log] [blame]
Thomas Gleixnere3976af2020-09-08 14:34:47 +02001// SPDX-License-Identifier: GPL-2.0-only
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05302/*
3 * QLogic iSCSI HBA Driver
Vikas Chaudhary4a4f51e2013-08-16 07:03:04 -04004 * Copyright (c) 2003-2013 QLogic Corporation
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05305 */
6#include <linux/delay.h>
Jiri Slabya6751cc2010-09-14 14:12:54 +02007#include <linux/io.h>
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05308#include <linux/pci.h>
Tej Parkash068237c82012-05-18 04:41:44 -04009#include <linux/ratelimit.h>
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +053010#include "ql4_def.h"
11#include "ql4_glbl.h"
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -040012#include "ql4_inline.h"
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +053013
Christoph Hellwig2f8e2c82015-08-28 09:27:14 +020014#include <linux/io-64-nonatomic-lo-hi.h>
Hitoshi Mitake797a7962012-02-07 11:45:33 +090015
Tej Parkashb1829782014-02-24 22:06:59 -050016#define TIMEOUT_100_MS 100
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +053017#define MASK(n) DMA_BIT_MASK(n)
18#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
19#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
20#define MS_WIN(addr) (addr & 0x0ffc0000)
21#define QLA82XX_PCI_MN_2M (0)
22#define QLA82XX_PCI_MS_2M (0x80000)
23#define QLA82XX_PCI_OCM0_2M (0xc0000)
24#define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
25#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
26
27/* CRB window related */
28#define CRB_BLK(off) ((off >> 20) & 0x3f)
29#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30#define CRB_WINDOW_2M (0x130060)
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -040031#define CRB_HI(off) ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +053032 ((off) & 0xf0000))
33#define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
34#define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
35#define CRB_INDIRECT_2M (0x1e0000UL)
36
37static inline void __iomem *
38qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
39{
40 if ((off < ha->first_page_group_end) &&
41 (off >= ha->first_page_group_start))
42 return (void __iomem *)(ha->nx_pcibase + off);
43
44 return NULL;
45}
46
Bart Van Asschebb83e592018-01-23 16:33:50 -080047static const int MD_MIU_TEST_AGT_RDDATA[] = { 0x410000A8,
48 0x410000AC, 0x410000B8, 0x410000BC };
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +053049#define MAX_CRB_XFORM 60
50static unsigned long crb_addr_xform[MAX_CRB_XFORM];
51static int qla4_8xxx_crb_table_initialized;
52
53#define qla4_8xxx_crb_addr_transform(name) \
54 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
55 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
56static void
Vikas Chaudharyf8086f42012-08-22 07:54:59 -040057qla4_82xx_crb_addr_transform_setup(void)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +053058{
59 qla4_8xxx_crb_addr_transform(XDMA);
60 qla4_8xxx_crb_addr_transform(TIMR);
61 qla4_8xxx_crb_addr_transform(SRE);
62 qla4_8xxx_crb_addr_transform(SQN3);
63 qla4_8xxx_crb_addr_transform(SQN2);
64 qla4_8xxx_crb_addr_transform(SQN1);
65 qla4_8xxx_crb_addr_transform(SQN0);
66 qla4_8xxx_crb_addr_transform(SQS3);
67 qla4_8xxx_crb_addr_transform(SQS2);
68 qla4_8xxx_crb_addr_transform(SQS1);
69 qla4_8xxx_crb_addr_transform(SQS0);
70 qla4_8xxx_crb_addr_transform(RPMX7);
71 qla4_8xxx_crb_addr_transform(RPMX6);
72 qla4_8xxx_crb_addr_transform(RPMX5);
73 qla4_8xxx_crb_addr_transform(RPMX4);
74 qla4_8xxx_crb_addr_transform(RPMX3);
75 qla4_8xxx_crb_addr_transform(RPMX2);
76 qla4_8xxx_crb_addr_transform(RPMX1);
77 qla4_8xxx_crb_addr_transform(RPMX0);
78 qla4_8xxx_crb_addr_transform(ROMUSB);
79 qla4_8xxx_crb_addr_transform(SN);
80 qla4_8xxx_crb_addr_transform(QMN);
81 qla4_8xxx_crb_addr_transform(QMS);
82 qla4_8xxx_crb_addr_transform(PGNI);
83 qla4_8xxx_crb_addr_transform(PGND);
84 qla4_8xxx_crb_addr_transform(PGN3);
85 qla4_8xxx_crb_addr_transform(PGN2);
86 qla4_8xxx_crb_addr_transform(PGN1);
87 qla4_8xxx_crb_addr_transform(PGN0);
88 qla4_8xxx_crb_addr_transform(PGSI);
89 qla4_8xxx_crb_addr_transform(PGSD);
90 qla4_8xxx_crb_addr_transform(PGS3);
91 qla4_8xxx_crb_addr_transform(PGS2);
92 qla4_8xxx_crb_addr_transform(PGS1);
93 qla4_8xxx_crb_addr_transform(PGS0);
94 qla4_8xxx_crb_addr_transform(PS);
95 qla4_8xxx_crb_addr_transform(PH);
96 qla4_8xxx_crb_addr_transform(NIU);
97 qla4_8xxx_crb_addr_transform(I2Q);
98 qla4_8xxx_crb_addr_transform(EG);
99 qla4_8xxx_crb_addr_transform(MN);
100 qla4_8xxx_crb_addr_transform(MS);
101 qla4_8xxx_crb_addr_transform(CAS2);
102 qla4_8xxx_crb_addr_transform(CAS1);
103 qla4_8xxx_crb_addr_transform(CAS0);
104 qla4_8xxx_crb_addr_transform(CAM);
105 qla4_8xxx_crb_addr_transform(C2C1);
106 qla4_8xxx_crb_addr_transform(C2C0);
107 qla4_8xxx_crb_addr_transform(SMB);
108 qla4_8xxx_crb_addr_transform(OCM0);
109 qla4_8xxx_crb_addr_transform(I2C0);
110
111 qla4_8xxx_crb_table_initialized = 1;
112}
113
114static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
115 {{{0, 0, 0, 0} } }, /* 0: PCI */
116 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
117 {1, 0x0110000, 0x0120000, 0x130000},
118 {1, 0x0120000, 0x0122000, 0x124000},
119 {1, 0x0130000, 0x0132000, 0x126000},
120 {1, 0x0140000, 0x0142000, 0x128000},
121 {1, 0x0150000, 0x0152000, 0x12a000},
122 {1, 0x0160000, 0x0170000, 0x110000},
123 {1, 0x0170000, 0x0172000, 0x12e000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {1, 0x01e0000, 0x01e0800, 0x122000},
131 {0, 0x0000000, 0x0000000, 0x000000} } },
132 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
133 {{{0, 0, 0, 0} } }, /* 3: */
134 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
135 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
136 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
137 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
138 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {1, 0x08f0000, 0x08f2000, 0x172000} } },
154 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {1, 0x09f0000, 0x09f2000, 0x176000} } },
170 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
186 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {0, 0x0000000, 0x0000000, 0x000000},
196 {0, 0x0000000, 0x0000000, 0x000000},
197 {0, 0x0000000, 0x0000000, 0x000000},
198 {0, 0x0000000, 0x0000000, 0x000000},
199 {0, 0x0000000, 0x0000000, 0x000000},
200 {0, 0x0000000, 0x0000000, 0x000000},
201 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
202 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
203 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
204 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
205 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
206 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
207 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
208 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
209 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
210 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
211 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
212 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
213 {{{0, 0, 0, 0} } }, /* 23: */
214 {{{0, 0, 0, 0} } }, /* 24: */
215 {{{0, 0, 0, 0} } }, /* 25: */
216 {{{0, 0, 0, 0} } }, /* 26: */
217 {{{0, 0, 0, 0} } }, /* 27: */
218 {{{0, 0, 0, 0} } }, /* 28: */
219 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
220 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
221 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
222 {{{0} } }, /* 32: PCI */
223 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
224 {1, 0x2110000, 0x2120000, 0x130000},
225 {1, 0x2120000, 0x2122000, 0x124000},
226 {1, 0x2130000, 0x2132000, 0x126000},
227 {1, 0x2140000, 0x2142000, 0x128000},
228 {1, 0x2150000, 0x2152000, 0x12a000},
229 {1, 0x2160000, 0x2170000, 0x110000},
230 {1, 0x2170000, 0x2172000, 0x12e000},
231 {0, 0x0000000, 0x0000000, 0x000000},
232 {0, 0x0000000, 0x0000000, 0x000000},
233 {0, 0x0000000, 0x0000000, 0x000000},
234 {0, 0x0000000, 0x0000000, 0x000000},
235 {0, 0x0000000, 0x0000000, 0x000000},
236 {0, 0x0000000, 0x0000000, 0x000000},
237 {0, 0x0000000, 0x0000000, 0x000000},
238 {0, 0x0000000, 0x0000000, 0x000000} } },
239 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
240 {{{0} } }, /* 35: */
241 {{{0} } }, /* 36: */
242 {{{0} } }, /* 37: */
243 {{{0} } }, /* 38: */
244 {{{0} } }, /* 39: */
245 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
246 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
247 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
248 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
249 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
250 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
251 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
252 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
253 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
254 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
255 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
256 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
257 {{{0} } }, /* 52: */
258 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
259 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
260 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
261 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
262 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
263 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
264 {{{0} } }, /* 59: I2C0 */
265 {{{0} } }, /* 60: I2C1 */
266 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
267 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
268 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
269};
270
271/*
272 * top 12 bits of crb internal address (hub, agent)
273 */
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -0400274static unsigned qla4_82xx_crb_hub_agt[64] = {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530275 0,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
279 0,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
296 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
298 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
299 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
301 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
302 0,
303 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
304 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
305 0,
306 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
307 0,
308 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
309 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
310 0,
311 0,
312 0,
313 0,
314 0,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
316 0,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
323 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
326 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
327 0,
328 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
329 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
330 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
331 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
332 0,
333 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
334 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
335 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
336 0,
337 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
338 0,
339};
340
341/* Device states */
342static char *qdev_state[] = {
343 "Unknown",
344 "Cold",
345 "Initializing",
346 "Ready",
347 "Need Reset",
348 "Need Quiescent",
349 "Failed",
350 "Quiescent",
351};
352
353/*
354 * In: 'off' is offset from CRB space in 128M pci map
355 * Out: 'off' is 2M pci map addr
356 * side effect: lock crb window
357 */
358static void
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400359qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530360{
361 u32 win_read;
362
363 ha->crb_win = CRB_HI(*off);
364 writel(ha->crb_win,
365 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
366
367 /* Read back value to make sure write has gone through before trying
368 * to use it. */
369 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
370 if (win_read != ha->crb_win) {
371 DEBUG2(ql4_printk(KERN_INFO, ha,
372 "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
373 " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
374 }
375 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
376}
377
Ahmed S. Darwisha93c3832020-11-26 14:29:41 +0100378#define CRB_WIN_LOCK_TIMEOUT 100000000
379
380/*
381 * Context: atomic
382 */
383static int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha)
384{
385 int done = 0, timeout = 0;
386
387 while (!done) {
388 /* acquire semaphore3 from PCI HW block */
389 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
390 if (done == 1)
391 break;
392 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
393 return -1;
394
395 timeout++;
396 udelay(10);
397 }
398 qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
399 return 0;
400}
401
402void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha)
403{
404 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
405}
406
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530407void
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400408qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530409{
410 unsigned long flags = 0;
411 int rv;
412
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400413 rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530414
415 BUG_ON(rv == -1);
416
417 if (rv == 1) {
418 write_lock_irqsave(&ha->hw_lock, flags);
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400419 qla4_82xx_crb_win_lock(ha);
420 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530421 }
422
423 writel(data, (void __iomem *)off);
424
425 if (rv == 1) {
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400426 qla4_82xx_crb_win_unlock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530427 write_unlock_irqrestore(&ha->hw_lock, flags);
428 }
429}
430
Vikas Chaudhary33693c72012-08-22 07:55:04 -0400431uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530432{
433 unsigned long flags = 0;
434 int rv;
435 u32 data;
436
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400437 rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530438
439 BUG_ON(rv == -1);
440
441 if (rv == 1) {
442 write_lock_irqsave(&ha->hw_lock, flags);
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400443 qla4_82xx_crb_win_lock(ha);
444 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530445 }
446 data = readl((void __iomem *)off);
447
448 if (rv == 1) {
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400449 qla4_82xx_crb_win_unlock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530450 write_unlock_irqrestore(&ha->hw_lock, flags);
451 }
452 return data;
453}
454
Tej Parkash068237c82012-05-18 04:41:44 -0400455/* Minidump related functions */
Vikas Chaudhary33693c72012-08-22 07:55:04 -0400456int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data)
Tej Parkash068237c82012-05-18 04:41:44 -0400457{
Vikas Chaudhary33693c72012-08-22 07:55:04 -0400458 uint32_t win_read, off_value;
459 int rval = QLA_SUCCESS;
460
461 off_value = off & 0xFFFF0000;
462 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
463
464 /*
465 * Read back value to make sure write has gone through before trying
466 * to use it.
467 */
468 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
469 if (win_read != off_value) {
470 DEBUG2(ql4_printk(KERN_INFO, ha,
471 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
472 __func__, off_value, win_read, off));
473 rval = QLA_ERROR;
474 } else {
475 off_value = off & 0x0000FFFF;
476 *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
477 ha->nx_pcibase));
478 }
479 return rval;
480}
481
482int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data)
483{
484 uint32_t win_read, off_value;
485 int rval = QLA_SUCCESS;
Tej Parkash068237c82012-05-18 04:41:44 -0400486
487 off_value = off & 0xFFFF0000;
488 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
489
490 /* Read back value to make sure write has gone through before trying
491 * to use it.
492 */
493 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
494 if (win_read != off_value) {
495 DEBUG2(ql4_printk(KERN_INFO, ha,
496 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
Vikas Chaudhary33693c72012-08-22 07:55:04 -0400497 __func__, off_value, win_read, off));
498 rval = QLA_ERROR;
499 } else {
500 off_value = off & 0x0000FFFF;
Tej Parkash068237c82012-05-18 04:41:44 -0400501 writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M +
502 ha->nx_pcibase));
Vikas Chaudhary33693c72012-08-22 07:55:04 -0400503 }
Tej Parkash068237c82012-05-18 04:41:44 -0400504 return rval;
505}
506
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530507#define IDC_LOCK_TIMEOUT 100000000
508
509/**
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400510 * qla4_82xx_idc_lock - hw_lock
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530511 * @ha: pointer to adapter structure
512 *
513 * General purpose lock used to synchronize access to
514 * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
Ahmed S. Darwish36276682020-11-26 14:29:45 +0100515 *
516 * Context: task, can sleep
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530517 **/
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400518int qla4_82xx_idc_lock(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530519{
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530520 int done = 0, timeout = 0;
521
Ahmed S. Darwish36276682020-11-26 14:29:45 +0100522 might_sleep();
523
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530524 while (!done) {
525 /* acquire semaphore5 from PCI HW block */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400526 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530527 if (done == 1)
528 break;
529 if (timeout >= IDC_LOCK_TIMEOUT)
530 return -1;
531
532 timeout++;
Ahmed S. Darwish36276682020-11-26 14:29:45 +0100533 msleep(100);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530534 }
535 return 0;
536}
537
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400538void qla4_82xx_idc_unlock(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530539{
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400540 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530541}
542
543int
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400544qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530545{
546 struct crb_128M_2M_sub_block_map *m;
547
548 if (*off >= QLA82XX_CRB_MAX)
549 return -1;
550
551 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
552 *off = (*off - QLA82XX_PCI_CAMQM) +
553 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
554 return 0;
555 }
556
557 if (*off < QLA82XX_PCI_CRBSPACE)
558 return -1;
559
560 *off -= QLA82XX_PCI_CRBSPACE;
561 /*
562 * Try direct map
563 */
564
565 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
566
567 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
568 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
569 return 0;
570 }
571
572 /*
573 * Not in direct map, use crb window
574 */
575 return 1;
576}
577
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530578/*
579* check memory access boundary.
580* used by test agent. support ddr access only for now
581*/
582static unsigned long
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400583qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530584 unsigned long long addr, int size)
585{
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -0400586 if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
587 QLA8XXX_ADDR_DDR_NET_MAX) ||
588 !QLA8XXX_ADDR_IN_RANGE(addr + size - 1,
589 QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) ||
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530590 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
591 return 0;
592 }
593 return 1;
594}
595
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -0400596static int qla4_82xx_pci_set_window_warning_count;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530597
598static unsigned long
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400599qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530600{
601 int window;
602 u32 win_read;
603
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -0400604 if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
605 QLA8XXX_ADDR_DDR_NET_MAX)) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530606 /* DDR network side */
607 window = MN_WIN(addr);
608 ha->ddr_mn_window = window;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400609 qla4_82xx_wr_32(ha, ha->mn_win_crb |
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530610 QLA82XX_PCI_CRBSPACE, window);
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400611 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530612 QLA82XX_PCI_CRBSPACE);
613 if ((win_read << 17) != window) {
614 ql4_printk(KERN_WARNING, ha,
615 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
616 __func__, window, win_read);
617 }
618 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -0400619 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
620 QLA8XXX_ADDR_OCM0_MAX)) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530621 unsigned int temp1;
622 /* if bits 19:18&17:11 are on */
623 if ((addr & 0x00ff800) == 0xff800) {
624 printk("%s: QM access not handled.\n", __func__);
625 addr = -1UL;
626 }
627
628 window = OCM_WIN(addr);
629 ha->ddr_mn_window = window;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400630 qla4_82xx_wr_32(ha, ha->mn_win_crb |
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530631 QLA82XX_PCI_CRBSPACE, window);
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400632 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530633 QLA82XX_PCI_CRBSPACE);
634 temp1 = ((window & 0x1FF) << 7) |
635 ((window & 0x0FFFE0000) >> 17);
636 if (win_read != temp1) {
637 printk("%s: Written OCMwin (0x%x) != Read"
638 " OCMwin (0x%x)\n", __func__, temp1, win_read);
639 }
640 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
641
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -0400642 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530643 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
644 /* QDR network side */
645 window = MS_WIN(addr);
646 ha->qdr_sn_window = window;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400647 qla4_82xx_wr_32(ha, ha->ms_win_crb |
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530648 QLA82XX_PCI_CRBSPACE, window);
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400649 win_read = qla4_82xx_rd_32(ha,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530650 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
651 if (win_read != window) {
652 printk("%s: Written MSwin (0x%x) != Read "
653 "MSwin (0x%x)\n", __func__, window, win_read);
654 }
655 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
656
657 } else {
658 /*
659 * peg gdb frequently accesses memory that doesn't exist,
660 * this limits the chit chat so debugging isn't slowed down.
661 */
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -0400662 if ((qla4_82xx_pci_set_window_warning_count++ < 8) ||
663 (qla4_82xx_pci_set_window_warning_count%64 == 0)) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530664 printk("%s: Warning:%s Unknown address range!\n",
665 __func__, DRIVER_NAME);
666 }
667 addr = -1UL;
668 }
669 return addr;
670}
671
672/* check if address is in the same windows as the previous access */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400673static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530674 unsigned long long addr)
675{
676 int window;
677 unsigned long long qdr_max;
678
679 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
680
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -0400681 if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
682 QLA8XXX_ADDR_DDR_NET_MAX)) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530683 /* DDR network side */
684 BUG(); /* MN access can not come here */
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -0400685 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
686 QLA8XXX_ADDR_OCM0_MAX)) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530687 return 1;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -0400688 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1,
689 QLA8XXX_ADDR_OCM1_MAX)) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530690 return 1;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -0400691 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530692 qdr_max)) {
693 /* QDR network side */
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -0400694 window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530695 if (ha->qdr_sn_window == window)
696 return 1;
697 }
698
699 return 0;
700}
701
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400702static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530703 u64 off, void *data, int size)
704{
705 unsigned long flags;
706 void __iomem *addr;
707 int ret = 0;
708 u64 start;
709 void __iomem *mem_ptr = NULL;
710 unsigned long mem_base;
711 unsigned long mem_page;
712
713 write_lock_irqsave(&ha->hw_lock, flags);
714
715 /*
716 * If attempting to access unknown address or straddle hw windows,
717 * do not access.
718 */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400719 start = qla4_82xx_pci_set_window(ha, off);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530720 if ((start == -1UL) ||
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400721 (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530722 write_unlock_irqrestore(&ha->hw_lock, flags);
723 printk(KERN_ERR"%s out of bound pci memory access. "
724 "offset is 0x%llx\n", DRIVER_NAME, off);
725 return -1;
726 }
727
728 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
729 if (!addr) {
730 write_unlock_irqrestore(&ha->hw_lock, flags);
731 mem_base = pci_resource_start(ha->pdev, 0);
732 mem_page = start & PAGE_MASK;
733 /* Map two pages whenever user tries to access addresses in two
734 consecutive pages.
735 */
736 if (mem_page != ((start + size - 1) & PAGE_MASK))
737 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
738 else
739 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
740
741 if (mem_ptr == NULL) {
742 *(u8 *)data = 0;
743 return -1;
744 }
745 addr = mem_ptr;
746 addr += start & (PAGE_SIZE - 1);
747 write_lock_irqsave(&ha->hw_lock, flags);
748 }
749
750 switch (size) {
751 case 1:
752 *(u8 *)data = readb(addr);
753 break;
754 case 2:
755 *(u16 *)data = readw(addr);
756 break;
757 case 4:
758 *(u32 *)data = readl(addr);
759 break;
760 case 8:
761 *(u64 *)data = readq(addr);
762 break;
763 default:
764 ret = -1;
765 break;
766 }
767 write_unlock_irqrestore(&ha->hw_lock, flags);
768
769 if (mem_ptr)
770 iounmap(mem_ptr);
771 return ret;
772}
773
774static int
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400775qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530776 void *data, int size)
777{
778 unsigned long flags;
779 void __iomem *addr;
780 int ret = 0;
781 u64 start;
782 void __iomem *mem_ptr = NULL;
783 unsigned long mem_base;
784 unsigned long mem_page;
785
786 write_lock_irqsave(&ha->hw_lock, flags);
787
788 /*
789 * If attempting to access unknown address or straddle hw windows,
790 * do not access.
791 */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400792 start = qla4_82xx_pci_set_window(ha, off);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530793 if ((start == -1UL) ||
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400794 (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530795 write_unlock_irqrestore(&ha->hw_lock, flags);
796 printk(KERN_ERR"%s out of bound pci memory access. "
797 "offset is 0x%llx\n", DRIVER_NAME, off);
798 return -1;
799 }
800
801 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
802 if (!addr) {
803 write_unlock_irqrestore(&ha->hw_lock, flags);
804 mem_base = pci_resource_start(ha->pdev, 0);
805 mem_page = start & PAGE_MASK;
806 /* Map two pages whenever user tries to access addresses in two
807 consecutive pages.
808 */
809 if (mem_page != ((start + size - 1) & PAGE_MASK))
810 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
811 else
812 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
813 if (mem_ptr == NULL)
814 return -1;
815
816 addr = mem_ptr;
817 addr += start & (PAGE_SIZE - 1);
818 write_lock_irqsave(&ha->hw_lock, flags);
819 }
820
821 switch (size) {
822 case 1:
823 writeb(*(u8 *)data, addr);
824 break;
825 case 2:
826 writew(*(u16 *)data, addr);
827 break;
828 case 4:
829 writel(*(u32 *)data, addr);
830 break;
831 case 8:
832 writeq(*(u64 *)data, addr);
833 break;
834 default:
835 ret = -1;
836 break;
837 }
838 write_unlock_irqrestore(&ha->hw_lock, flags);
839 if (mem_ptr)
840 iounmap(mem_ptr);
841 return ret;
842}
843
844#define MTU_FUDGE_FACTOR 100
845
846static unsigned long
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400847qla4_82xx_decode_crb_addr(unsigned long addr)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530848{
849 int i;
850 unsigned long base_addr, offset, pci_base;
851
852 if (!qla4_8xxx_crb_table_initialized)
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400853 qla4_82xx_crb_addr_transform_setup();
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530854
855 pci_base = ADDR_ERROR;
856 base_addr = addr & 0xfff00000;
857 offset = addr & 0x000fffff;
858
859 for (i = 0; i < MAX_CRB_XFORM; i++) {
860 if (crb_addr_xform[i] == base_addr) {
861 pci_base = i << 20;
862 break;
863 }
864 }
865 if (pci_base == ADDR_ERROR)
866 return pci_base;
867 else
868 return pci_base + offset;
869}
870
871static long rom_max_timeout = 100;
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -0400872static long qla4_82xx_rom_lock_timeout = 100;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530873
Ahmed S. Darwish014aced2020-11-26 14:29:46 +0100874/*
875 * Context: task, can_sleep
876 */
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530877static int
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400878qla4_82xx_rom_lock(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530879{
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530880 int done = 0, timeout = 0;
881
Ahmed S. Darwish014aced2020-11-26 14:29:46 +0100882 might_sleep();
883
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530884 while (!done) {
885 /* acquire semaphore2 from PCI HW block */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400886 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530887 if (done == 1)
888 break;
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -0400889 if (timeout >= qla4_82xx_rom_lock_timeout)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530890 return -1;
891
892 timeout++;
Ahmed S. Darwish014aced2020-11-26 14:29:46 +0100893 msleep(20);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530894 }
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400895 qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530896 return 0;
897}
898
899static void
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400900qla4_82xx_rom_unlock(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530901{
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400902 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530903}
904
905static int
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400906qla4_82xx_wait_rom_done(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530907{
908 long timeout = 0;
909 long done = 0 ;
910
911 while (done == 0) {
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400912 done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530913 done &= 2;
914 timeout++;
915 if (timeout >= rom_max_timeout) {
916 printk("%s: Timeout reached waiting for rom done",
917 DRIVER_NAME);
918 return -1;
919 }
920 }
921 return 0;
922}
923
924static int
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400925qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530926{
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400927 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
928 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
929 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
930 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
931 if (qla4_82xx_wait_rom_done(ha)) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530932 printk("%s: Error waiting for rom done\n", DRIVER_NAME);
933 return -1;
934 }
935 /* reset abyte_cnt and dummy_byte_cnt */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400936 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530937 udelay(10);
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400938 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530939
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400940 *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530941 return 0;
942}
943
944static int
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400945qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530946{
947 int ret, loops = 0;
948
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400949 while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530950 udelay(100);
951 loops++;
952 }
953 if (loops >= 50000) {
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400954 ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n",
955 DRIVER_NAME);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530956 return -1;
957 }
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400958 ret = qla4_82xx_do_rom_fast_read(ha, addr, valp);
959 qla4_82xx_rom_unlock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530960 return ret;
961}
962
Lee Jones653557d2020-07-21 17:41:41 +0100963/*
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530964 * This routine does CRB initialize sequence
965 * to put the ISP into operational state
Lee Jones653557d2020-07-21 17:41:41 +0100966 */
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530967static int
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400968qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530969{
970 int addr, val;
971 int i ;
972 struct crb_addr_pair *buf;
973 unsigned long off;
974 unsigned offset, n;
975
976 struct crb_addr_pair {
977 long addr;
978 long data;
979 };
980
981 /* Halt all the indiviual PEGs and other blocks of the ISP */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400982 qla4_82xx_rom_lock(ha);
Swapnil Naglea1fc26b2010-12-02 22:12:15 -0800983
Vikas Chaudharycb744282011-05-17 23:17:04 -0700984 /* disable all I2Q */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400985 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
986 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
987 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
988 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
989 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
990 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
Vikas Chaudharycb744282011-05-17 23:17:04 -0700991
992 /* disable all niu interrupts */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400993 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
Swapnil Naglea1fc26b2010-12-02 22:12:15 -0800994 /* disable xge rx/tx */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400995 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
Swapnil Naglea1fc26b2010-12-02 22:12:15 -0800996 /* disable xg1 rx/tx */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400997 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
Vikas Chaudharycb744282011-05-17 23:17:04 -0700998 /* disable sideband mac */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -0400999 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
Vikas Chaudharycb744282011-05-17 23:17:04 -07001000 /* disable ap0 mac */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001001 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
Vikas Chaudharycb744282011-05-17 23:17:04 -07001002 /* disable ap1 mac */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001003 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
Swapnil Naglea1fc26b2010-12-02 22:12:15 -08001004
1005 /* halt sre */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001006 val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1007 qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
Swapnil Naglea1fc26b2010-12-02 22:12:15 -08001008
1009 /* halt epg */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001010 qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
Swapnil Naglea1fc26b2010-12-02 22:12:15 -08001011
1012 /* halt timers */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001013 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1014 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1015 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1016 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1017 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1018 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
Swapnil Naglea1fc26b2010-12-02 22:12:15 -08001019
1020 /* halt pegs */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001021 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1022 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1023 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1024 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1025 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
Vikas Chaudharycb744282011-05-17 23:17:04 -07001026 msleep(5);
Swapnil Naglea1fc26b2010-12-02 22:12:15 -08001027
1028 /* big hammer */
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301029 if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
1030 /* don't reset CAM block on reset */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001031 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301032 else
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001033 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301034
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001035 qla4_82xx_rom_unlock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301036
1037 /* Read the signature value from the flash.
1038 * Offset 0: Contain signature (0xcafecafe)
1039 * Offset 4: Offset and number of addr/value pairs
1040 * that present in CRB initialize sequence
1041 */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001042 if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1043 qla4_82xx_rom_fast_read(ha, 4, &n) != 0) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301044 ql4_printk(KERN_WARNING, ha,
1045 "[ERROR] Reading crb_init area: n: %08x\n", n);
1046 return -1;
1047 }
1048
1049 /* Offset in flash = lower 16 bits
1050 * Number of enteries = upper 16 bits
1051 */
1052 offset = n & 0xffffU;
1053 n = (n >> 16) & 0xffffU;
1054
1055 /* number of addr/value pair should not exceed 1024 enteries */
1056 if (n >= 1024) {
1057 ql4_printk(KERN_WARNING, ha,
1058 "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
1059 DRIVER_NAME, __func__, n);
1060 return -1;
1061 }
1062
1063 ql4_printk(KERN_INFO, ha,
1064 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n);
1065
Kees Cook6da2ec52018-06-12 13:55:00 -07001066 buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301067 if (buf == NULL) {
1068 ql4_printk(KERN_WARNING, ha,
1069 "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
1070 return -1;
1071 }
1072
1073 for (i = 0; i < n; i++) {
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001074 if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1075 qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301076 0) {
1077 kfree(buf);
1078 return -1;
1079 }
1080
1081 buf[i].addr = addr;
1082 buf[i].data = val;
1083 }
1084
1085 for (i = 0; i < n; i++) {
1086 /* Translate internal CRB initialization
1087 * address to PCI bus address
1088 */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001089 off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) +
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301090 QLA82XX_PCI_CRBSPACE;
1091 /* Not all CRB addr/value pair to be written,
1092 * some of them are skipped
1093 */
1094
1095 /* skip if LS bit is set*/
1096 if (off & 0x1) {
1097 DEBUG2(ql4_printk(KERN_WARNING, ha,
1098 "Skip CRB init replay for offset = 0x%lx\n", off));
1099 continue;
1100 }
1101
1102 /* skipping cold reboot MAGIC */
1103 if (off == QLA82XX_CAM_RAM(0x1fc))
1104 continue;
1105
1106 /* do not reset PCI */
1107 if (off == (ROMUSB_GLB + 0xbc))
1108 continue;
1109
1110 /* skip core clock, so that firmware can increase the clock */
1111 if (off == (ROMUSB_GLB + 0xc8))
1112 continue;
1113
1114 /* skip the function enable register */
1115 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1116 continue;
1117
1118 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1119 continue;
1120
1121 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1122 continue;
1123
1124 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1125 continue;
1126
1127 if (off == ADDR_ERROR) {
1128 ql4_printk(KERN_WARNING, ha,
1129 "%s: [ERROR] Unknown addr: 0x%08lx\n",
1130 DRIVER_NAME, buf[i].addr);
1131 continue;
1132 }
1133
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001134 qla4_82xx_wr_32(ha, off, buf[i].data);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301135
1136 /* ISP requires much bigger delay to settle down,
1137 * else crb_window returns 0xffffffff
1138 */
1139 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1140 msleep(1000);
1141
1142 /* ISP requires millisec delay between
1143 * successive CRB register updation
1144 */
1145 msleep(1);
1146 }
1147
1148 kfree(buf);
1149
1150 /* Resetting the data and instruction cache */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001151 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1152 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1153 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301154
1155 /* Clear all protocol processing engines */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001156 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1157 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1158 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1159 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1160 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1161 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1162 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1163 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301164
1165 return 0;
1166}
1167
Vikas Chaudharydd3b8542014-02-24 22:07:01 -05001168/**
1169 * qla4_8xxx_ms_mem_write_128b - Writes data to MS/off-chip memory
1170 * @ha: Pointer to adapter structure
1171 * @addr: Flash address to write to
1172 * @data: Data to be written
1173 * @count: word_count to be written
1174 *
1175 * Return: On success return QLA_SUCCESS
1176 * On error return QLA_ERROR
1177 **/
1178int qla4_8xxx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr,
1179 uint32_t *data, uint32_t count)
1180{
1181 int i, j;
1182 uint32_t agt_ctrl;
1183 unsigned long flags;
1184 int ret_val = QLA_SUCCESS;
1185
1186 /* Only 128-bit aligned access */
1187 if (addr & 0xF) {
1188 ret_val = QLA_ERROR;
1189 goto exit_ms_mem_write;
1190 }
1191
1192 write_lock_irqsave(&ha->hw_lock, flags);
1193
1194 /* Write address */
1195 ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 0);
1196 if (ret_val == QLA_ERROR) {
1197 ql4_printk(KERN_ERR, ha, "%s: write to AGT_ADDR_HI failed\n",
1198 __func__);
1199 goto exit_ms_mem_write_unlock;
1200 }
1201
1202 for (i = 0; i < count; i++, addr += 16) {
1203 if (!((QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
1204 QLA8XXX_ADDR_QDR_NET_MAX)) ||
1205 (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
1206 QLA8XXX_ADDR_DDR_NET_MAX)))) {
1207 ret_val = QLA_ERROR;
1208 goto exit_ms_mem_write_unlock;
1209 }
1210
1211 ret_val = ha->isp_ops->wr_reg_indirect(ha,
1212 MD_MIU_TEST_AGT_ADDR_LO,
1213 addr);
1214 /* Write data */
1215 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
1216 MD_MIU_TEST_AGT_WRDATA_LO,
1217 *data++);
1218 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
1219 MD_MIU_TEST_AGT_WRDATA_HI,
1220 *data++);
1221 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
1222 MD_MIU_TEST_AGT_WRDATA_ULO,
1223 *data++);
1224 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
1225 MD_MIU_TEST_AGT_WRDATA_UHI,
1226 *data++);
1227 if (ret_val == QLA_ERROR) {
1228 ql4_printk(KERN_ERR, ha, "%s: write to AGT_WRDATA failed\n",
1229 __func__);
1230 goto exit_ms_mem_write_unlock;
1231 }
1232
1233 /* Check write status */
1234 ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
1235 MIU_TA_CTL_WRITE_ENABLE);
1236 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
1237 MD_MIU_TEST_AGT_CTRL,
1238 MIU_TA_CTL_WRITE_START);
1239 if (ret_val == QLA_ERROR) {
1240 ql4_printk(KERN_ERR, ha, "%s: write to AGT_CTRL failed\n",
1241 __func__);
1242 goto exit_ms_mem_write_unlock;
1243 }
1244
1245 for (j = 0; j < MAX_CTL_CHECK; j++) {
1246 ret_val = ha->isp_ops->rd_reg_indirect(ha,
1247 MD_MIU_TEST_AGT_CTRL,
1248 &agt_ctrl);
1249 if (ret_val == QLA_ERROR) {
1250 ql4_printk(KERN_ERR, ha, "%s: failed to read MD_MIU_TEST_AGT_CTRL\n",
1251 __func__);
1252 goto exit_ms_mem_write_unlock;
1253 }
1254 if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0)
1255 break;
1256 }
1257
1258 /* Status check failed */
1259 if (j >= MAX_CTL_CHECK) {
1260 printk_ratelimited(KERN_ERR "%s: MS memory write failed!\n",
1261 __func__);
1262 ret_val = QLA_ERROR;
1263 goto exit_ms_mem_write_unlock;
1264 }
1265 }
1266
1267exit_ms_mem_write_unlock:
1268 write_unlock_irqrestore(&ha->hw_lock, flags);
1269
1270exit_ms_mem_write:
1271 return ret_val;
1272}
1273
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301274static int
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001275qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301276{
Lalit Chandivade4cd83cbe2010-12-02 22:12:40 -08001277 int i, rval = 0;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301278 long size = 0;
1279 long flashaddr, memaddr;
1280 u64 data;
1281 u32 high, low;
1282
1283 flashaddr = memaddr = ha->hw.flt_region_bootload;
Lalit Chandivade4cd83cbe2010-12-02 22:12:40 -08001284 size = (image_start - flashaddr) / 8;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301285
1286 DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
1287 ha->host_no, __func__, flashaddr, image_start));
1288
1289 for (i = 0; i < size; i++) {
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001290 if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1291 (qla4_82xx_rom_fast_read(ha, flashaddr + 4,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301292 (int *)&high))) {
Lalit Chandivade4cd83cbe2010-12-02 22:12:40 -08001293 rval = -1;
1294 goto exit_load_from_flash;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301295 }
1296 data = ((u64)high << 32) | low ;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001297 rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
Lalit Chandivade4cd83cbe2010-12-02 22:12:40 -08001298 if (rval)
1299 goto exit_load_from_flash;
1300
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301301 flashaddr += 8;
1302 memaddr += 8;
1303
Lalit Chandivade4cd83cbe2010-12-02 22:12:40 -08001304 if (i % 0x1000 == 0)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301305 msleep(1);
1306
1307 }
1308
1309 udelay(100);
1310
1311 read_lock(&ha->hw_lock);
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001312 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1313 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301314 read_unlock(&ha->hw_lock);
1315
Lalit Chandivade4cd83cbe2010-12-02 22:12:40 -08001316exit_load_from_flash:
1317 return rval;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301318}
1319
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001320static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301321{
1322 u32 rst;
1323
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001324 qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1325 if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301326 printk(KERN_WARNING "%s: Error during CRB Initialization\n",
1327 __func__);
1328 return QLA_ERROR;
1329 }
1330
1331 udelay(500);
1332
1333 /* at this point, QM is in reset. This could be a problem if there are
1334 * incoming d* transition queue messages. QM/PCIE could wedge.
1335 * To get around this, QM is brought out of reset.
1336 */
1337
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001338 rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301339 /* unreset qm */
1340 rst &= ~(1 << 28);
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001341 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301342
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001343 if (qla4_82xx_load_from_flash(ha, image_start)) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301344 printk("%s: Error trying to load fw from flash!\n", __func__);
1345 return QLA_ERROR;
1346 }
1347
1348 return QLA_SUCCESS;
1349}
1350
1351int
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001352qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301353 u64 off, void *data, int size)
1354{
1355 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1356 int shift_amount;
1357 uint32_t temp;
1358 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1359
1360 /*
1361 * If not MN, go check for MS or invalid.
1362 */
1363
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04001364 if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301365 mem_crb = QLA82XX_CRB_QDR_NET;
1366 else {
1367 mem_crb = QLA82XX_CRB_DDR_NET;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001368 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1369 return qla4_82xx_pci_mem_read_direct(ha,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301370 off, data, size);
1371 }
1372
1373
1374 off8 = off & 0xfffffff0;
1375 off0[0] = off & 0xf;
1376 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1377 shift_amount = 4;
1378
1379 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1380 off0[1] = 0;
1381 sz[1] = size - sz[0];
1382
1383 for (i = 0; i < loop; i++) {
1384 temp = off8 + (i << shift_amount);
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001385 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301386 temp = 0;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001387 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301388 temp = MIU_TA_CTL_ENABLE;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001389 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
Vikas Chaudharyc38fa3a2012-08-22 07:55:03 -04001390 temp = MIU_TA_CTL_START_ENABLE;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001391 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301392
1393 for (j = 0; j < MAX_CTL_CHECK; j++) {
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001394 temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301395 if ((temp & MIU_TA_CTL_BUSY) == 0)
1396 break;
1397 }
1398
1399 if (j >= MAX_CTL_CHECK) {
Tej Parkash068237c82012-05-18 04:41:44 -04001400 printk_ratelimited(KERN_ERR
1401 "%s: failed to read through agent\n",
1402 __func__);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301403 break;
1404 }
1405
1406 start = off0[i] >> 2;
1407 end = (off0[i] + sz[i] - 1) >> 2;
1408 for (k = start; k <= end; k++) {
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001409 temp = qla4_82xx_rd_32(ha,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301410 mem_crb + MIU_TEST_AGT_RDDATA(k));
1411 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1412 }
1413 }
1414
1415 if (j >= MAX_CTL_CHECK)
1416 return -1;
1417
1418 if ((off0[0] & 7) == 0) {
1419 val = word[0];
1420 } else {
1421 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1422 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1423 }
1424
1425 switch (size) {
1426 case 1:
1427 *(uint8_t *)data = val;
1428 break;
1429 case 2:
1430 *(uint16_t *)data = val;
1431 break;
1432 case 4:
1433 *(uint32_t *)data = val;
1434 break;
1435 case 8:
1436 *(uint64_t *)data = val;
1437 break;
1438 }
1439 return 0;
1440}
1441
1442int
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001443qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301444 u64 off, void *data, int size)
1445{
1446 int i, j, ret = 0, loop, sz[2], off0;
1447 int scale, shift_amount, startword;
1448 uint32_t temp;
1449 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1450
1451 /*
1452 * If not MN, go check for MS or invalid.
1453 */
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04001454 if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301455 mem_crb = QLA82XX_CRB_QDR_NET;
1456 else {
1457 mem_crb = QLA82XX_CRB_DDR_NET;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001458 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1459 return qla4_82xx_pci_mem_write_direct(ha,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301460 off, data, size);
1461 }
1462
1463 off0 = off & 0x7;
1464 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1465 sz[1] = size - sz[0];
1466
1467 off8 = off & 0xfffffff0;
1468 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1469 shift_amount = 4;
1470 scale = 2;
1471 startword = (off & 0xf)/8;
1472
1473 for (i = 0; i < loop; i++) {
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001474 if (qla4_82xx_pci_mem_read_2M(ha, off8 +
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301475 (i << shift_amount), &word[i * scale], 8))
1476 return -1;
1477 }
1478
1479 switch (size) {
1480 case 1:
1481 tmpw = *((uint8_t *)data);
1482 break;
1483 case 2:
1484 tmpw = *((uint16_t *)data);
1485 break;
1486 case 4:
1487 tmpw = *((uint32_t *)data);
1488 break;
1489 case 8:
1490 default:
1491 tmpw = *((uint64_t *)data);
1492 break;
1493 }
1494
1495 if (sz[0] == 8)
1496 word[startword] = tmpw;
1497 else {
1498 word[startword] &=
1499 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1500 word[startword] |= tmpw << (off0 * 8);
1501 }
1502
1503 if (sz[1] != 0) {
1504 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1505 word[startword+1] |= tmpw >> (sz[0] * 8);
1506 }
1507
1508 for (i = 0; i < loop; i++) {
1509 temp = off8 + (i << shift_amount);
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001510 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301511 temp = 0;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001512 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301513 temp = word[i * scale] & 0xffffffff;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001514 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301515 temp = (word[i * scale] >> 32) & 0xffffffff;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001516 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301517 temp = word[i*scale + 1] & 0xffffffff;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001518 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301519 temp);
1520 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001521 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301522 temp);
1523
Vikas Chaudharyc38fa3a2012-08-22 07:55:03 -04001524 temp = MIU_TA_CTL_WRITE_ENABLE;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001525 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
Vikas Chaudharyc38fa3a2012-08-22 07:55:03 -04001526 temp = MIU_TA_CTL_WRITE_START;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001527 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301528
1529 for (j = 0; j < MAX_CTL_CHECK; j++) {
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001530 temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301531 if ((temp & MIU_TA_CTL_BUSY) == 0)
1532 break;
1533 }
1534
1535 if (j >= MAX_CTL_CHECK) {
1536 if (printk_ratelimit())
1537 ql4_printk(KERN_ERR, ha,
Tej Parkash068237c82012-05-18 04:41:44 -04001538 "%s: failed to read through agent\n",
1539 __func__);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301540 ret = -1;
1541 break;
1542 }
1543 }
1544
1545 return ret;
1546}
1547
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001548static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301549{
1550 u32 val = 0;
1551 int retries = 60;
1552
1553 if (!pegtune_val) {
1554 do {
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001555 val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301556 if ((val == PHAN_INITIALIZE_COMPLETE) ||
1557 (val == PHAN_INITIALIZE_ACK))
1558 return 0;
1559 set_current_state(TASK_UNINTERRUPTIBLE);
1560 schedule_timeout(500);
1561
1562 } while (--retries);
1563
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301564 if (!retries) {
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001565 pegtune_val = qla4_82xx_rd_32(ha,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301566 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1567 printk(KERN_WARNING "%s: init failed, "
1568 "pegtune_val = %x\n", __func__, pegtune_val);
1569 return -1;
1570 }
1571 }
1572 return 0;
1573}
1574
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001575static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301576{
1577 uint32_t state = 0;
1578 int loops = 0;
1579
1580 /* Window 1 call */
1581 read_lock(&ha->hw_lock);
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001582 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301583 read_unlock(&ha->hw_lock);
1584
1585 while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
1586 udelay(100);
1587 /* Window 1 call */
1588 read_lock(&ha->hw_lock);
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001589 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301590 read_unlock(&ha->hw_lock);
1591
1592 loops++;
1593 }
1594
1595 if (loops >= 30000) {
1596 DEBUG2(ql4_printk(KERN_INFO, ha,
1597 "Receive Peg initialization not complete: 0x%x.\n", state));
1598 return QLA_ERROR;
1599 }
1600
1601 return QLA_SUCCESS;
1602}
1603
Andrew Morton626115c2010-08-19 14:13:42 -07001604void
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301605qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1606{
1607 uint32_t drv_active;
1608
Vikas Chaudhary33693c72012-08-22 07:55:04 -04001609 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001610
1611 /*
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04001612 * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001613 * shift 1 by func_num to set a bit for the function.
1614 * For ISP8022, drv_active has 4 bits per function
1615 */
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04001616 if (is_qla8032(ha) || is_qla8042(ha))
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001617 drv_active |= (1 << ha->func_num);
1618 else
1619 drv_active |= (1 << (ha->func_num * 4));
1620
Tej Parkash068237c82012-05-18 04:41:44 -04001621 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1622 __func__, ha->host_no, drv_active);
Vikas Chaudhary33693c72012-08-22 07:55:04 -04001623 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301624}
1625
1626void
1627qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1628{
1629 uint32_t drv_active;
1630
Vikas Chaudhary33693c72012-08-22 07:55:04 -04001631 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001632
1633 /*
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04001634 * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001635 * shift 1 by func_num to set a bit for the function.
1636 * For ISP8022, drv_active has 4 bits per function
1637 */
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04001638 if (is_qla8032(ha) || is_qla8042(ha))
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001639 drv_active &= ~(1 << (ha->func_num));
1640 else
1641 drv_active &= ~(1 << (ha->func_num * 4));
1642
Tej Parkash068237c82012-05-18 04:41:44 -04001643 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1644 __func__, ha->host_no, drv_active);
Vikas Chaudhary33693c72012-08-22 07:55:04 -04001645 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301646}
1647
Vikas Chaudhary33693c72012-08-22 07:55:04 -04001648inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301649{
Lalit Chandivade2232be02010-07-30 14:38:47 +05301650 uint32_t drv_state, drv_active;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301651 int rval;
1652
Vikas Chaudhary33693c72012-08-22 07:55:04 -04001653 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1654 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001655
1656 /*
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04001657 * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001658 * shift 1 by func_num to set a bit for the function.
1659 * For ISP8022, drv_active has 4 bits per function
1660 */
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04001661 if (is_qla8032(ha) || is_qla8042(ha))
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001662 rval = drv_state & (1 << ha->func_num);
1663 else
1664 rval = drv_state & (1 << (ha->func_num * 4));
1665
Lalit Chandivade2232be02010-07-30 14:38:47 +05301666 if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1667 rval = 1;
1668
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301669 return rval;
1670}
1671
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001672void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301673{
1674 uint32_t drv_state;
1675
Vikas Chaudhary33693c72012-08-22 07:55:04 -04001676 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001677
1678 /*
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04001679 * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001680 * shift 1 by func_num to set a bit for the function.
1681 * For ISP8022, drv_active has 4 bits per function
1682 */
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04001683 if (is_qla8032(ha) || is_qla8042(ha))
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001684 drv_state |= (1 << ha->func_num);
1685 else
1686 drv_state |= (1 << (ha->func_num * 4));
1687
Tej Parkash068237c82012-05-18 04:41:44 -04001688 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1689 __func__, ha->host_no, drv_state);
Vikas Chaudhary33693c72012-08-22 07:55:04 -04001690 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301691}
1692
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001693void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301694{
1695 uint32_t drv_state;
1696
Vikas Chaudhary33693c72012-08-22 07:55:04 -04001697 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001698
1699 /*
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04001700 * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001701 * shift 1 by func_num to set a bit for the function.
1702 * For ISP8022, drv_active has 4 bits per function
1703 */
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04001704 if (is_qla8032(ha) || is_qla8042(ha))
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001705 drv_state &= ~(1 << ha->func_num);
1706 else
1707 drv_state &= ~(1 << (ha->func_num * 4));
1708
Tej Parkash068237c82012-05-18 04:41:44 -04001709 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1710 __func__, ha->host_no, drv_state);
Vikas Chaudhary33693c72012-08-22 07:55:04 -04001711 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301712}
1713
1714static inline void
1715qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1716{
1717 uint32_t qsnt_state;
1718
Vikas Chaudhary33693c72012-08-22 07:55:04 -04001719 qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001720
1721 /*
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04001722 * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001723 * shift 1 by func_num to set a bit for the function.
1724 * For ISP8022, drv_active has 4 bits per function.
1725 */
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04001726 if (is_qla8032(ha) || is_qla8042(ha))
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04001727 qsnt_state |= (1 << ha->func_num);
1728 else
1729 qsnt_state |= (2 << (ha->func_num * 4));
1730
Vikas Chaudhary33693c72012-08-22 07:55:04 -04001731 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301732}
1733
1734
1735static int
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001736qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301737{
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301738 uint16_t lnk;
1739
1740 /* scrub dma mask expansion register */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001741 qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301742
1743 /* Overwrite stale initialization register values */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001744 qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1745 qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1746 qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1747 qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301748
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001749 if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301750 printk("%s: Error trying to start fw!\n", __func__);
1751 return QLA_ERROR;
1752 }
1753
1754 /* Handshake with the card before we register the devices. */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001755 if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301756 printk("%s: Error during card handshake!\n", __func__);
1757 return QLA_ERROR;
1758 }
1759
1760 /* Negotiated Link width */
Jiang Liu5548bfd2012-08-20 14:25:06 -06001761 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301762 ha->link_width = (lnk >> 4) & 0x3f;
1763
1764 /* Synchronize with Receive peg */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001765 return qla4_82xx_rcvpeg_ready(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301766}
1767
Vikas Chaudhary33693c72012-08-22 07:55:04 -04001768int qla4_82xx_try_start_fw(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301769{
Colin Ian King3a5b9fa2020-12-04 19:18:10 +00001770 int rval;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301771
1772 /*
1773 * FW Load priority:
1774 * 1) Operational firmware residing in flash.
1775 * 2) Fail
1776 */
1777
1778 ql4_printk(KERN_INFO, ha,
1779 "FW: Retrieving flash offsets from FLT/FDT ...\n");
1780 rval = qla4_8xxx_get_flash_info(ha);
1781 if (rval != QLA_SUCCESS)
1782 return rval;
1783
1784 ql4_printk(KERN_INFO, ha,
1785 "FW: Attempting to load firmware from flash...\n");
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001786 rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301787
Vikas Chaudharyf581a3f2010-10-06 22:47:48 -07001788 if (rval != QLA_SUCCESS) {
1789 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
1790 " FAILED...\n");
1791 return rval;
1792 }
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05301793
1794 return rval;
1795}
1796
Vikas Chaudhary33693c72012-08-22 07:55:04 -04001797void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha)
Shyam Sundarb25ee662010-10-06 22:50:51 -07001798{
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001799 if (qla4_82xx_rom_lock(ha)) {
Shyam Sundarb25ee662010-10-06 22:50:51 -07001800 /* Someone else is holding the lock. */
1801 dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
1802 }
1803
1804 /*
1805 * Either we got the lock, or someone
1806 * else died while holding it.
1807 * In either case, unlock.
1808 */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04001809 qla4_82xx_rom_unlock(ha);
Shyam Sundarb25ee662010-10-06 22:50:51 -07001810}
1811
Tej Parkashb1829782014-02-24 22:06:59 -05001812static uint32_t ql4_84xx_poll_wait_for_ready(struct scsi_qla_host *ha,
1813 uint32_t addr1, uint32_t mask)
1814{
1815 unsigned long timeout;
1816 uint32_t rval = QLA_SUCCESS;
1817 uint32_t temp;
1818
1819 timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
1820 do {
1821 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
1822 if ((temp & mask) != 0)
1823 break;
1824
1825 if (time_after_eq(jiffies, timeout)) {
1826 ql4_printk(KERN_INFO, ha, "Error in processing rdmdio entry\n");
1827 return QLA_ERROR;
1828 }
1829 } while (1);
1830
1831 return rval;
1832}
1833
Baoyou Xie02ccda22016-08-29 18:46:51 +08001834static uint32_t ql4_84xx_ipmdio_rd_reg(struct scsi_qla_host *ha, uint32_t addr1,
Tej Parkashb1829782014-02-24 22:06:59 -05001835 uint32_t addr3, uint32_t mask, uint32_t addr,
1836 uint32_t *data_ptr)
1837{
1838 int rval = QLA_SUCCESS;
1839 uint32_t temp;
1840 uint32_t data;
1841
1842 rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1843 if (rval)
1844 goto exit_ipmdio_rd_reg;
1845
1846 temp = (0x40000000 | addr);
1847 ha->isp_ops->wr_reg_indirect(ha, addr1, temp);
1848
1849 rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1850 if (rval)
1851 goto exit_ipmdio_rd_reg;
1852
1853 ha->isp_ops->rd_reg_indirect(ha, addr3, &data);
1854 *data_ptr = data;
1855
1856exit_ipmdio_rd_reg:
1857 return rval;
1858}
1859
1860
1861static uint32_t ql4_84xx_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *ha,
1862 uint32_t addr1,
1863 uint32_t addr2,
1864 uint32_t addr3,
1865 uint32_t mask)
1866{
1867 unsigned long timeout;
1868 uint32_t temp;
1869 uint32_t rval = QLA_SUCCESS;
1870
1871 timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
1872 do {
1873 ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3, mask, addr2, &temp);
1874 if ((temp & 0x1) != 1)
1875 break;
1876 if (time_after_eq(jiffies, timeout)) {
1877 ql4_printk(KERN_INFO, ha, "Error in processing mdiobus idle\n");
1878 return QLA_ERROR;
1879 }
1880 } while (1);
1881
1882 return rval;
1883}
1884
1885static int ql4_84xx_ipmdio_wr_reg(struct scsi_qla_host *ha,
1886 uint32_t addr1, uint32_t addr3,
1887 uint32_t mask, uint32_t addr,
1888 uint32_t value)
1889{
1890 int rval = QLA_SUCCESS;
1891
1892 rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1893 if (rval)
1894 goto exit_ipmdio_wr_reg;
1895
1896 ha->isp_ops->wr_reg_indirect(ha, addr3, value);
1897 ha->isp_ops->wr_reg_indirect(ha, addr1, addr);
1898
1899 rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1900 if (rval)
1901 goto exit_ipmdio_wr_reg;
1902
1903exit_ipmdio_wr_reg:
1904 return rval;
1905}
1906
Tej Parkash068237c82012-05-18 04:41:44 -04001907static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04001908 struct qla8xxx_minidump_entry_hdr *entry_hdr,
Tej Parkash068237c82012-05-18 04:41:44 -04001909 uint32_t **d_ptr)
1910{
1911 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04001912 struct qla8xxx_minidump_entry_crb *crb_hdr;
Tej Parkash068237c82012-05-18 04:41:44 -04001913 uint32_t *data_ptr = *d_ptr;
1914
1915 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04001916 crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
Tej Parkash068237c82012-05-18 04:41:44 -04001917 r_addr = crb_hdr->addr;
1918 r_stride = crb_hdr->crb_strd.addr_stride;
1919 loop_cnt = crb_hdr->op_count;
1920
1921 for (i = 0; i < loop_cnt; i++) {
Vikas Chaudhary33693c72012-08-22 07:55:04 -04001922 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
Tej Parkash068237c82012-05-18 04:41:44 -04001923 *data_ptr++ = cpu_to_le32(r_addr);
1924 *data_ptr++ = cpu_to_le32(r_value);
1925 r_addr += r_stride;
1926 }
1927 *d_ptr = data_ptr;
1928}
1929
Santosh Vernekar41f79bd2013-08-23 03:40:18 -04001930static int qla4_83xx_check_dma_engine_state(struct scsi_qla_host *ha)
1931{
1932 int rval = QLA_SUCCESS;
1933 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
1934 uint64_t dma_base_addr = 0;
1935 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL;
1936
1937 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
1938 ha->fw_dump_tmplt_hdr;
1939 dma_eng_num =
1940 tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX];
1941 dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
1942 (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET);
1943
1944 /* Read the pex-dma's command-status-and-control register. */
1945 rval = ha->isp_ops->rd_reg_indirect(ha,
1946 (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
1947 &cmd_sts_and_cntrl);
1948
1949 if (rval)
1950 return QLA_ERROR;
1951
1952 /* Check if requested pex-dma engine is available. */
1953 if (cmd_sts_and_cntrl & BIT_31)
1954 return QLA_SUCCESS;
1955 else
1956 return QLA_ERROR;
1957}
1958
1959static int qla4_83xx_start_pex_dma(struct scsi_qla_host *ha,
1960 struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr)
1961{
1962 int rval = QLA_SUCCESS, wait = 0;
1963 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
1964 uint64_t dma_base_addr = 0;
1965 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL;
1966
1967 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
1968 ha->fw_dump_tmplt_hdr;
1969 dma_eng_num =
1970 tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX];
1971 dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
1972 (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET);
1973
1974 rval = ha->isp_ops->wr_reg_indirect(ha,
1975 dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_LOW,
1976 m_hdr->desc_card_addr);
1977 if (rval)
1978 goto error_exit;
1979
1980 rval = ha->isp_ops->wr_reg_indirect(ha,
1981 dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_HIGH, 0);
1982 if (rval)
1983 goto error_exit;
1984
1985 rval = ha->isp_ops->wr_reg_indirect(ha,
1986 dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL,
1987 m_hdr->start_dma_cmd);
1988 if (rval)
1989 goto error_exit;
1990
1991 /* Wait for dma operation to complete. */
1992 for (wait = 0; wait < QLA83XX_PEX_DMA_MAX_WAIT; wait++) {
1993 rval = ha->isp_ops->rd_reg_indirect(ha,
1994 (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
1995 &cmd_sts_and_cntrl);
1996 if (rval)
1997 goto error_exit;
1998
1999 if ((cmd_sts_and_cntrl & BIT_1) == 0)
2000 break;
2001 else
2002 udelay(10);
2003 }
2004
2005 /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
2006 if (wait >= QLA83XX_PEX_DMA_MAX_WAIT) {
2007 rval = QLA_ERROR;
2008 goto error_exit;
2009 }
2010
2011error_exit:
2012 return rval;
2013}
2014
Tej Parkash3c3cab12014-02-24 22:07:00 -05002015static int qla4_8xxx_minidump_pex_dma_read(struct scsi_qla_host *ha,
Santosh Vernekar41f79bd2013-08-23 03:40:18 -04002016 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2017 uint32_t **d_ptr)
2018{
2019 int rval = QLA_SUCCESS;
2020 struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr = NULL;
2021 uint32_t size, read_size;
2022 uint8_t *data_ptr = (uint8_t *)*d_ptr;
2023 void *rdmem_buffer = NULL;
2024 dma_addr_t rdmem_dma;
2025 struct qla4_83xx_pex_dma_descriptor dma_desc;
2026
2027 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2028
2029 rval = qla4_83xx_check_dma_engine_state(ha);
2030 if (rval != QLA_SUCCESS) {
2031 DEBUG2(ql4_printk(KERN_INFO, ha,
2032 "%s: DMA engine not available. Fallback to rdmem-read.\n",
2033 __func__));
2034 return QLA_ERROR;
2035 }
2036
2037 m_hdr = (struct qla4_83xx_minidump_entry_rdmem_pex_dma *)entry_hdr;
2038 rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
2039 QLA83XX_PEX_DMA_READ_SIZE,
2040 &rdmem_dma, GFP_KERNEL);
2041 if (!rdmem_buffer) {
2042 DEBUG2(ql4_printk(KERN_INFO, ha,
2043 "%s: Unable to allocate rdmem dma buffer\n",
2044 __func__));
2045 return QLA_ERROR;
2046 }
2047
2048 /* Prepare pex-dma descriptor to be written to MS memory. */
2049 /* dma-desc-cmd layout:
2050 * 0-3: dma-desc-cmd 0-3
2051 * 4-7: pcid function number
2052 * 8-15: dma-desc-cmd 8-15
2053 */
2054 dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f);
2055 dma_desc.cmd.dma_desc_cmd |= ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
2056 dma_desc.dma_bus_addr = rdmem_dma;
2057
2058 size = 0;
2059 read_size = 0;
2060 /*
2061 * Perform rdmem operation using pex-dma.
2062 * Prepare dma in chunks of QLA83XX_PEX_DMA_READ_SIZE.
2063 */
2064 while (read_size < m_hdr->read_data_size) {
2065 if (m_hdr->read_data_size - read_size >=
2066 QLA83XX_PEX_DMA_READ_SIZE)
2067 size = QLA83XX_PEX_DMA_READ_SIZE;
2068 else {
2069 size = (m_hdr->read_data_size - read_size);
2070
2071 if (rdmem_buffer)
2072 dma_free_coherent(&ha->pdev->dev,
2073 QLA83XX_PEX_DMA_READ_SIZE,
2074 rdmem_buffer, rdmem_dma);
2075
2076 rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, size,
2077 &rdmem_dma,
2078 GFP_KERNEL);
2079 if (!rdmem_buffer) {
2080 DEBUG2(ql4_printk(KERN_INFO, ha,
2081 "%s: Unable to allocate rdmem dma buffer\n",
2082 __func__));
2083 return QLA_ERROR;
2084 }
2085 dma_desc.dma_bus_addr = rdmem_dma;
2086 }
2087
2088 dma_desc.src_addr = m_hdr->read_addr + read_size;
2089 dma_desc.cmd.read_data_size = size;
2090
2091 /* Prepare: Write pex-dma descriptor to MS memory. */
Tej Parkash3c3cab12014-02-24 22:07:00 -05002092 rval = qla4_8xxx_ms_mem_write_128b(ha,
Santosh Vernekar41f79bd2013-08-23 03:40:18 -04002093 (uint64_t)m_hdr->desc_card_addr,
2094 (uint32_t *)&dma_desc,
2095 (sizeof(struct qla4_83xx_pex_dma_descriptor)/16));
Vikas Chaudhary9c4f8d92014-02-24 22:07:02 -05002096 if (rval != QLA_SUCCESS) {
Santosh Vernekar41f79bd2013-08-23 03:40:18 -04002097 ql4_printk(KERN_INFO, ha,
2098 "%s: Error writing rdmem-dma-init to MS !!!\n",
2099 __func__);
2100 goto error_exit;
2101 }
2102
2103 DEBUG2(ql4_printk(KERN_INFO, ha,
2104 "%s: Dma-desc: Instruct for rdmem dma (size 0x%x).\n",
2105 __func__, size));
2106 /* Execute: Start pex-dma operation. */
2107 rval = qla4_83xx_start_pex_dma(ha, m_hdr);
2108 if (rval != QLA_SUCCESS) {
2109 DEBUG2(ql4_printk(KERN_INFO, ha,
2110 "scsi(%ld): start-pex-dma failed rval=0x%x\n",
2111 ha->host_no, rval));
2112 goto error_exit;
2113 }
2114
2115 memcpy(data_ptr, rdmem_buffer, size);
2116 data_ptr += size;
2117 read_size += size;
2118 }
2119
2120 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
2121
2122 *d_ptr = (uint32_t *)data_ptr;
2123
2124error_exit:
2125 if (rdmem_buffer)
2126 dma_free_coherent(&ha->pdev->dev, size, rdmem_buffer,
2127 rdmem_dma);
2128
2129 return rval;
2130}
2131
Tej Parkash068237c82012-05-18 04:41:44 -04002132static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002133 struct qla8xxx_minidump_entry_hdr *entry_hdr,
Tej Parkash068237c82012-05-18 04:41:44 -04002134 uint32_t **d_ptr)
2135{
2136 uint32_t addr, r_addr, c_addr, t_r_addr;
2137 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2138 unsigned long p_wait, w_time, p_mask;
2139 uint32_t c_value_w, c_value_r;
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002140 struct qla8xxx_minidump_entry_cache *cache_hdr;
Tej Parkash068237c82012-05-18 04:41:44 -04002141 int rval = QLA_ERROR;
2142 uint32_t *data_ptr = *d_ptr;
2143
2144 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002145 cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
Tej Parkash068237c82012-05-18 04:41:44 -04002146
2147 loop_count = cache_hdr->op_count;
2148 r_addr = cache_hdr->read_addr;
2149 c_addr = cache_hdr->control_addr;
2150 c_value_w = cache_hdr->cache_ctrl.write_value;
2151
2152 t_r_addr = cache_hdr->tag_reg_addr;
2153 t_value = cache_hdr->addr_ctrl.init_tag_value;
2154 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2155 p_wait = cache_hdr->cache_ctrl.poll_wait;
2156 p_mask = cache_hdr->cache_ctrl.poll_mask;
2157
2158 for (i = 0; i < loop_count; i++) {
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002159 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
Tej Parkash068237c82012-05-18 04:41:44 -04002160
2161 if (c_value_w)
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002162 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
Tej Parkash068237c82012-05-18 04:41:44 -04002163
2164 if (p_mask) {
2165 w_time = jiffies + p_wait;
2166 do {
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002167 ha->isp_ops->rd_reg_indirect(ha, c_addr,
2168 &c_value_r);
Tej Parkash068237c82012-05-18 04:41:44 -04002169 if ((c_value_r & p_mask) == 0) {
2170 break;
2171 } else if (time_after_eq(jiffies, w_time)) {
2172 /* capturing dump failed */
2173 return rval;
2174 }
2175 } while (1);
2176 }
2177
2178 addr = r_addr;
2179 for (k = 0; k < r_cnt; k++) {
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002180 ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
Tej Parkash068237c82012-05-18 04:41:44 -04002181 *data_ptr++ = cpu_to_le32(r_value);
2182 addr += cache_hdr->read_ctrl.read_addr_stride;
2183 }
2184
2185 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2186 }
2187 *d_ptr = data_ptr;
2188 return QLA_SUCCESS;
2189}
2190
2191static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002192 struct qla8xxx_minidump_entry_hdr *entry_hdr)
Tej Parkash068237c82012-05-18 04:41:44 -04002193{
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002194 struct qla8xxx_minidump_entry_crb *crb_entry;
Tej Parkash068237c82012-05-18 04:41:44 -04002195 uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS;
2196 uint32_t crb_addr;
2197 unsigned long wtime;
2198 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
2199 int i;
2200
2201 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2202 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
2203 ha->fw_dump_tmplt_hdr;
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002204 crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
Tej Parkash068237c82012-05-18 04:41:44 -04002205
2206 crb_addr = crb_entry->addr;
2207 for (i = 0; i < crb_entry->op_count; i++) {
2208 opcode = crb_entry->crb_ctrl.opcode;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04002209 if (opcode & QLA8XXX_DBG_OPCODE_WR) {
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002210 ha->isp_ops->wr_reg_indirect(ha, crb_addr,
2211 crb_entry->value_1);
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04002212 opcode &= ~QLA8XXX_DBG_OPCODE_WR;
Tej Parkash068237c82012-05-18 04:41:44 -04002213 }
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04002214 if (opcode & QLA8XXX_DBG_OPCODE_RW) {
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002215 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2216 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04002217 opcode &= ~QLA8XXX_DBG_OPCODE_RW;
Tej Parkash068237c82012-05-18 04:41:44 -04002218 }
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04002219 if (opcode & QLA8XXX_DBG_OPCODE_AND) {
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002220 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
Tej Parkash068237c82012-05-18 04:41:44 -04002221 read_value &= crb_entry->value_2;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04002222 opcode &= ~QLA8XXX_DBG_OPCODE_AND;
2223 if (opcode & QLA8XXX_DBG_OPCODE_OR) {
Tej Parkash068237c82012-05-18 04:41:44 -04002224 read_value |= crb_entry->value_3;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04002225 opcode &= ~QLA8XXX_DBG_OPCODE_OR;
Tej Parkash068237c82012-05-18 04:41:44 -04002226 }
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002227 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
Tej Parkash068237c82012-05-18 04:41:44 -04002228 }
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04002229 if (opcode & QLA8XXX_DBG_OPCODE_OR) {
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002230 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
Tej Parkash068237c82012-05-18 04:41:44 -04002231 read_value |= crb_entry->value_3;
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002232 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04002233 opcode &= ~QLA8XXX_DBG_OPCODE_OR;
Tej Parkash068237c82012-05-18 04:41:44 -04002234 }
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04002235 if (opcode & QLA8XXX_DBG_OPCODE_POLL) {
Tej Parkash068237c82012-05-18 04:41:44 -04002236 poll_time = crb_entry->crb_strd.poll_timeout;
2237 wtime = jiffies + poll_time;
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002238 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
Tej Parkash068237c82012-05-18 04:41:44 -04002239
2240 do {
2241 if ((read_value & crb_entry->value_2) ==
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002242 crb_entry->value_1) {
Tej Parkash068237c82012-05-18 04:41:44 -04002243 break;
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002244 } else if (time_after_eq(jiffies, wtime)) {
Tej Parkash068237c82012-05-18 04:41:44 -04002245 /* capturing dump failed */
2246 rval = QLA_ERROR;
2247 break;
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002248 } else {
2249 ha->isp_ops->rd_reg_indirect(ha,
2250 crb_addr, &read_value);
2251 }
Tej Parkash068237c82012-05-18 04:41:44 -04002252 } while (1);
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04002253 opcode &= ~QLA8XXX_DBG_OPCODE_POLL;
Tej Parkash068237c82012-05-18 04:41:44 -04002254 }
2255
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04002256 if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) {
Tej Parkash068237c82012-05-18 04:41:44 -04002257 if (crb_entry->crb_strd.state_index_a) {
2258 index = crb_entry->crb_strd.state_index_a;
2259 addr = tmplt_hdr->saved_state_array[index];
2260 } else {
2261 addr = crb_addr;
2262 }
2263
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002264 ha->isp_ops->rd_reg_indirect(ha, addr, &read_value);
Tej Parkash068237c82012-05-18 04:41:44 -04002265 index = crb_entry->crb_ctrl.state_index_v;
2266 tmplt_hdr->saved_state_array[index] = read_value;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04002267 opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE;
Tej Parkash068237c82012-05-18 04:41:44 -04002268 }
2269
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04002270 if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) {
Tej Parkash068237c82012-05-18 04:41:44 -04002271 if (crb_entry->crb_strd.state_index_a) {
2272 index = crb_entry->crb_strd.state_index_a;
2273 addr = tmplt_hdr->saved_state_array[index];
2274 } else {
2275 addr = crb_addr;
2276 }
2277
2278 if (crb_entry->crb_ctrl.state_index_v) {
2279 index = crb_entry->crb_ctrl.state_index_v;
2280 read_value =
2281 tmplt_hdr->saved_state_array[index];
2282 } else {
2283 read_value = crb_entry->value_1;
2284 }
2285
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002286 ha->isp_ops->wr_reg_indirect(ha, addr, read_value);
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04002287 opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE;
Tej Parkash068237c82012-05-18 04:41:44 -04002288 }
2289
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04002290 if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) {
Tej Parkash068237c82012-05-18 04:41:44 -04002291 index = crb_entry->crb_ctrl.state_index_v;
2292 read_value = tmplt_hdr->saved_state_array[index];
2293 read_value <<= crb_entry->crb_ctrl.shl;
2294 read_value >>= crb_entry->crb_ctrl.shr;
2295 if (crb_entry->value_2)
2296 read_value &= crb_entry->value_2;
2297 read_value |= crb_entry->value_3;
2298 read_value += crb_entry->value_1;
2299 tmplt_hdr->saved_state_array[index] = read_value;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04002300 opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE;
Tej Parkash068237c82012-05-18 04:41:44 -04002301 }
2302 crb_addr += crb_entry->crb_strd.addr_stride;
2303 }
2304 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
2305 return rval;
2306}
2307
2308static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha,
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002309 struct qla8xxx_minidump_entry_hdr *entry_hdr,
Tej Parkash068237c82012-05-18 04:41:44 -04002310 uint32_t **d_ptr)
2311{
2312 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002313 struct qla8xxx_minidump_entry_rdocm *ocm_hdr;
Tej Parkash068237c82012-05-18 04:41:44 -04002314 uint32_t *data_ptr = *d_ptr;
2315
2316 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002317 ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr;
Tej Parkash068237c82012-05-18 04:41:44 -04002318 r_addr = ocm_hdr->read_addr;
2319 r_stride = ocm_hdr->read_addr_stride;
2320 loop_cnt = ocm_hdr->op_count;
2321
2322 DEBUG2(ql4_printk(KERN_INFO, ha,
2323 "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
2324 __func__, r_addr, r_stride, loop_cnt));
2325
2326 for (i = 0; i < loop_cnt; i++) {
2327 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
2328 *data_ptr++ = cpu_to_le32(r_value);
2329 r_addr += r_stride;
2330 }
2331 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n",
Vikas Chaudhary26fdf922012-08-07 07:57:14 -04002332 __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))));
Tej Parkash068237c82012-05-18 04:41:44 -04002333 *d_ptr = data_ptr;
2334}
2335
2336static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002337 struct qla8xxx_minidump_entry_hdr *entry_hdr,
Tej Parkash068237c82012-05-18 04:41:44 -04002338 uint32_t **d_ptr)
2339{
2340 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002341 struct qla8xxx_minidump_entry_mux *mux_hdr;
Tej Parkash068237c82012-05-18 04:41:44 -04002342 uint32_t *data_ptr = *d_ptr;
2343
2344 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002345 mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr;
Tej Parkash068237c82012-05-18 04:41:44 -04002346 r_addr = mux_hdr->read_addr;
2347 s_addr = mux_hdr->select_addr;
2348 s_stride = mux_hdr->select_value_stride;
2349 s_value = mux_hdr->select_value;
2350 loop_cnt = mux_hdr->op_count;
2351
2352 for (i = 0; i < loop_cnt; i++) {
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002353 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
2354 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
Tej Parkash068237c82012-05-18 04:41:44 -04002355 *data_ptr++ = cpu_to_le32(s_value);
2356 *data_ptr++ = cpu_to_le32(r_value);
2357 s_value += s_stride;
2358 }
2359 *d_ptr = data_ptr;
2360}
2361
2362static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha,
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002363 struct qla8xxx_minidump_entry_hdr *entry_hdr,
Tej Parkash068237c82012-05-18 04:41:44 -04002364 uint32_t **d_ptr)
2365{
2366 uint32_t addr, r_addr, c_addr, t_r_addr;
2367 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2368 uint32_t c_value_w;
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002369 struct qla8xxx_minidump_entry_cache *cache_hdr;
Tej Parkash068237c82012-05-18 04:41:44 -04002370 uint32_t *data_ptr = *d_ptr;
2371
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002372 cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
Tej Parkash068237c82012-05-18 04:41:44 -04002373 loop_count = cache_hdr->op_count;
2374 r_addr = cache_hdr->read_addr;
2375 c_addr = cache_hdr->control_addr;
2376 c_value_w = cache_hdr->cache_ctrl.write_value;
2377
2378 t_r_addr = cache_hdr->tag_reg_addr;
2379 t_value = cache_hdr->addr_ctrl.init_tag_value;
2380 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2381
2382 for (i = 0; i < loop_count; i++) {
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002383 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
2384 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
Tej Parkash068237c82012-05-18 04:41:44 -04002385 addr = r_addr;
2386 for (k = 0; k < r_cnt; k++) {
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002387 ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
Tej Parkash068237c82012-05-18 04:41:44 -04002388 *data_ptr++ = cpu_to_le32(r_value);
2389 addr += cache_hdr->read_ctrl.read_addr_stride;
2390 }
2391 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2392 }
2393 *d_ptr = data_ptr;
2394}
2395
2396static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha,
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002397 struct qla8xxx_minidump_entry_hdr *entry_hdr,
Tej Parkash068237c82012-05-18 04:41:44 -04002398 uint32_t **d_ptr)
2399{
2400 uint32_t s_addr, r_addr;
2401 uint32_t r_stride, r_value, r_cnt, qid = 0;
2402 uint32_t i, k, loop_cnt;
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002403 struct qla8xxx_minidump_entry_queue *q_hdr;
Tej Parkash068237c82012-05-18 04:41:44 -04002404 uint32_t *data_ptr = *d_ptr;
2405
2406 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002407 q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr;
Tej Parkash068237c82012-05-18 04:41:44 -04002408 s_addr = q_hdr->select_addr;
2409 r_cnt = q_hdr->rd_strd.read_addr_cnt;
2410 r_stride = q_hdr->rd_strd.read_addr_stride;
2411 loop_cnt = q_hdr->op_count;
2412
2413 for (i = 0; i < loop_cnt; i++) {
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002414 ha->isp_ops->wr_reg_indirect(ha, s_addr, qid);
Tej Parkash068237c82012-05-18 04:41:44 -04002415 r_addr = q_hdr->read_addr;
2416 for (k = 0; k < r_cnt; k++) {
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002417 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
Tej Parkash068237c82012-05-18 04:41:44 -04002418 *data_ptr++ = cpu_to_le32(r_value);
2419 r_addr += r_stride;
2420 }
2421 qid += q_hdr->q_strd.queue_id_stride;
2422 }
2423 *d_ptr = data_ptr;
2424}
2425
2426#define MD_DIRECT_ROM_WINDOW 0x42110030
2427#define MD_DIRECT_ROM_READ_BASE 0x42150000
2428
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04002429static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha,
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002430 struct qla8xxx_minidump_entry_hdr *entry_hdr,
Tej Parkash068237c82012-05-18 04:41:44 -04002431 uint32_t **d_ptr)
2432{
2433 uint32_t r_addr, r_value;
2434 uint32_t i, loop_cnt;
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002435 struct qla8xxx_minidump_entry_rdrom *rom_hdr;
Tej Parkash068237c82012-05-18 04:41:44 -04002436 uint32_t *data_ptr = *d_ptr;
2437
2438 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002439 rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
Tej Parkash068237c82012-05-18 04:41:44 -04002440 r_addr = rom_hdr->read_addr;
2441 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
2442
2443 DEBUG2(ql4_printk(KERN_INFO, ha,
2444 "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n",
2445 __func__, r_addr, loop_cnt));
2446
2447 for (i = 0; i < loop_cnt; i++) {
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002448 ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW,
2449 (r_addr & 0xFFFF0000));
2450 ha->isp_ops->rd_reg_indirect(ha,
2451 MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF),
2452 &r_value);
Tej Parkash068237c82012-05-18 04:41:44 -04002453 *data_ptr++ = cpu_to_le32(r_value);
2454 r_addr += sizeof(uint32_t);
2455 }
2456 *d_ptr = data_ptr;
2457}
2458
2459#define MD_MIU_TEST_AGT_CTRL 0x41000090
2460#define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
2461#define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
2462
Santosh Vernekar41f79bd2013-08-23 03:40:18 -04002463static int __qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002464 struct qla8xxx_minidump_entry_hdr *entry_hdr,
Tej Parkash068237c82012-05-18 04:41:44 -04002465 uint32_t **d_ptr)
2466{
2467 uint32_t r_addr, r_value, r_data;
2468 uint32_t i, j, loop_cnt;
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002469 struct qla8xxx_minidump_entry_rdmem *m_hdr;
Tej Parkash068237c82012-05-18 04:41:44 -04002470 unsigned long flags;
2471 uint32_t *data_ptr = *d_ptr;
2472
2473 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002474 m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr;
Tej Parkash068237c82012-05-18 04:41:44 -04002475 r_addr = m_hdr->read_addr;
2476 loop_cnt = m_hdr->read_data_size/16;
2477
2478 DEBUG2(ql4_printk(KERN_INFO, ha,
2479 "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2480 __func__, r_addr, m_hdr->read_data_size));
2481
2482 if (r_addr & 0xf) {
2483 DEBUG2(ql4_printk(KERN_INFO, ha,
Masanari Iidacf2fbdd2013-03-16 20:53:05 +09002484 "[%s]: Read addr 0x%x not 16 bytes aligned\n",
Tej Parkash068237c82012-05-18 04:41:44 -04002485 __func__, r_addr));
2486 return QLA_ERROR;
2487 }
2488
2489 if (m_hdr->read_data_size % 16) {
2490 DEBUG2(ql4_printk(KERN_INFO, ha,
2491 "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
2492 __func__, m_hdr->read_data_size));
2493 return QLA_ERROR;
2494 }
2495
2496 DEBUG2(ql4_printk(KERN_INFO, ha,
2497 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
2498 __func__, r_addr, m_hdr->read_data_size, loop_cnt));
2499
2500 write_lock_irqsave(&ha->hw_lock, flags);
2501 for (i = 0; i < loop_cnt; i++) {
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002502 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO,
2503 r_addr);
Tej Parkash068237c82012-05-18 04:41:44 -04002504 r_value = 0;
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002505 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI,
2506 r_value);
Tej Parkash068237c82012-05-18 04:41:44 -04002507 r_value = MIU_TA_CTL_ENABLE;
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002508 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
Vikas Chaudharyc38fa3a2012-08-22 07:55:03 -04002509 r_value = MIU_TA_CTL_START_ENABLE;
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002510 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
Tej Parkash068237c82012-05-18 04:41:44 -04002511
2512 for (j = 0; j < MAX_CTL_CHECK; j++) {
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002513 ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
2514 &r_value);
Tej Parkash068237c82012-05-18 04:41:44 -04002515 if ((r_value & MIU_TA_CTL_BUSY) == 0)
2516 break;
2517 }
2518
2519 if (j >= MAX_CTL_CHECK) {
2520 printk_ratelimited(KERN_ERR
2521 "%s: failed to read through agent\n",
2522 __func__);
2523 write_unlock_irqrestore(&ha->hw_lock, flags);
2524 return QLA_SUCCESS;
2525 }
2526
2527 for (j = 0; j < 4; j++) {
Vikas Chaudhary33693c72012-08-22 07:55:04 -04002528 ha->isp_ops->rd_reg_indirect(ha,
2529 MD_MIU_TEST_AGT_RDDATA[j],
2530 &r_data);
Tej Parkash068237c82012-05-18 04:41:44 -04002531 *data_ptr++ = cpu_to_le32(r_data);
2532 }
2533
2534 r_addr += 16;
2535 }
2536 write_unlock_irqrestore(&ha->hw_lock, flags);
2537
2538 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n",
2539 __func__, (loop_cnt * 16)));
2540
2541 *d_ptr = data_ptr;
2542 return QLA_SUCCESS;
2543}
2544
Santosh Vernekar41f79bd2013-08-23 03:40:18 -04002545static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2546 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2547 uint32_t **d_ptr)
2548{
2549 uint32_t *data_ptr = *d_ptr;
2550 int rval = QLA_SUCCESS;
2551
Tej Parkash3c3cab12014-02-24 22:07:00 -05002552 rval = qla4_8xxx_minidump_pex_dma_read(ha, entry_hdr, &data_ptr);
2553 if (rval != QLA_SUCCESS)
Santosh Vernekar41f79bd2013-08-23 03:40:18 -04002554 rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2555 &data_ptr);
Santosh Vernekar41f79bd2013-08-23 03:40:18 -04002556 *d_ptr = data_ptr;
2557 return rval;
2558}
2559
Vikas Chaudhary5e9bcec2012-08-22 07:55:01 -04002560static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha,
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002561 struct qla8xxx_minidump_entry_hdr *entry_hdr,
Tej Parkash068237c82012-05-18 04:41:44 -04002562 int index)
2563{
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04002564 entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG;
Tej Parkash068237c82012-05-18 04:41:44 -04002565 DEBUG2(ql4_printk(KERN_INFO, ha,
2566 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2567 ha->host_no, index, entry_hdr->entry_type,
2568 entry_hdr->d_ctrl.entry_capture_mask));
Tej Parkash58e2bbe2013-12-16 06:49:44 -05002569 /* If driver encounters a new entry type that it cannot process,
2570 * it should just skip the entry and adjust the total buffer size by
2571 * from subtracting the skipped bytes from it
2572 */
2573 ha->fw_dump_skip_size += entry_hdr->entry_capture_size;
Tej Parkash068237c82012-05-18 04:41:44 -04002574}
2575
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04002576/* ISP83xx functions to process new minidump entries... */
2577static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha,
2578 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2579 uint32_t **d_ptr)
2580{
2581 uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
2582 uint16_t s_stride, i;
2583 uint32_t *data_ptr = *d_ptr;
2584 uint32_t rval = QLA_SUCCESS;
2585 struct qla83xx_minidump_entry_pollrd *pollrd_hdr;
2586
2587 pollrd_hdr = (struct qla83xx_minidump_entry_pollrd *)entry_hdr;
2588 s_addr = le32_to_cpu(pollrd_hdr->select_addr);
2589 r_addr = le32_to_cpu(pollrd_hdr->read_addr);
2590 s_value = le32_to_cpu(pollrd_hdr->select_value);
2591 s_stride = le32_to_cpu(pollrd_hdr->select_value_stride);
2592
2593 poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
2594 poll_mask = le32_to_cpu(pollrd_hdr->poll_mask);
2595
2596 for (i = 0; i < le32_to_cpu(pollrd_hdr->op_count); i++) {
2597 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
2598 poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
2599 while (1) {
2600 ha->isp_ops->rd_reg_indirect(ha, s_addr, &r_value);
2601
2602 if ((r_value & poll_mask) != 0) {
2603 break;
2604 } else {
2605 msleep(1);
2606 if (--poll_wait == 0) {
2607 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2608 __func__);
2609 rval = QLA_ERROR;
2610 goto exit_process_pollrd;
2611 }
2612 }
2613 }
2614 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2615 *data_ptr++ = cpu_to_le32(s_value);
2616 *data_ptr++ = cpu_to_le32(r_value);
2617 s_value += s_stride;
2618 }
2619
2620 *d_ptr = data_ptr;
2621
2622exit_process_pollrd:
2623 return rval;
2624}
2625
Tej Parkashb1829782014-02-24 22:06:59 -05002626static uint32_t qla4_84xx_minidump_process_rddfe(struct scsi_qla_host *ha,
2627 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2628 uint32_t **d_ptr)
2629{
2630 int loop_cnt;
2631 uint32_t addr1, addr2, value, data, temp, wrval;
2632 uint8_t stride, stride2;
2633 uint16_t count;
Lee Jonesf67e8162020-07-21 17:41:40 +01002634 uint32_t poll, mask, modify_mask;
Tej Parkashb1829782014-02-24 22:06:59 -05002635 uint32_t wait_count = 0;
2636 uint32_t *data_ptr = *d_ptr;
2637 struct qla8044_minidump_entry_rddfe *rddfe;
2638 uint32_t rval = QLA_SUCCESS;
2639
2640 rddfe = (struct qla8044_minidump_entry_rddfe *)entry_hdr;
2641 addr1 = le32_to_cpu(rddfe->addr_1);
2642 value = le32_to_cpu(rddfe->value);
2643 stride = le32_to_cpu(rddfe->stride);
2644 stride2 = le32_to_cpu(rddfe->stride2);
2645 count = le32_to_cpu(rddfe->count);
2646
2647 poll = le32_to_cpu(rddfe->poll);
2648 mask = le32_to_cpu(rddfe->mask);
2649 modify_mask = le32_to_cpu(rddfe->modify_mask);
Tej Parkashb1829782014-02-24 22:06:59 -05002650
2651 addr2 = addr1 + stride;
2652
2653 for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) {
2654 ha->isp_ops->wr_reg_indirect(ha, addr1, (0x40000000 | value));
2655
2656 wait_count = 0;
2657 while (wait_count < poll) {
2658 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
2659 if ((temp & mask) != 0)
2660 break;
2661 wait_count++;
2662 }
2663
2664 if (wait_count == poll) {
2665 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__);
2666 rval = QLA_ERROR;
2667 goto exit_process_rddfe;
2668 } else {
2669 ha->isp_ops->rd_reg_indirect(ha, addr2, &temp);
2670 temp = temp & modify_mask;
2671 temp = (temp | ((loop_cnt << 16) | loop_cnt));
2672 wrval = ((temp << 16) | temp);
2673
2674 ha->isp_ops->wr_reg_indirect(ha, addr2, wrval);
2675 ha->isp_ops->wr_reg_indirect(ha, addr1, value);
2676
2677 wait_count = 0;
2678 while (wait_count < poll) {
2679 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
2680 if ((temp & mask) != 0)
2681 break;
2682 wait_count++;
2683 }
2684 if (wait_count == poll) {
2685 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2686 __func__);
2687 rval = QLA_ERROR;
2688 goto exit_process_rddfe;
2689 }
2690
2691 ha->isp_ops->wr_reg_indirect(ha, addr1,
2692 ((0x40000000 | value) +
2693 stride2));
2694 wait_count = 0;
2695 while (wait_count < poll) {
2696 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
2697 if ((temp & mask) != 0)
2698 break;
2699 wait_count++;
2700 }
2701
2702 if (wait_count == poll) {
2703 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2704 __func__);
2705 rval = QLA_ERROR;
2706 goto exit_process_rddfe;
2707 }
2708
2709 ha->isp_ops->rd_reg_indirect(ha, addr2, &data);
2710
2711 *data_ptr++ = cpu_to_le32(wrval);
2712 *data_ptr++ = cpu_to_le32(data);
2713 }
2714 }
2715
2716 *d_ptr = data_ptr;
2717exit_process_rddfe:
2718 return rval;
2719}
2720
2721static uint32_t qla4_84xx_minidump_process_rdmdio(struct scsi_qla_host *ha,
2722 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2723 uint32_t **d_ptr)
2724{
2725 int rval = QLA_SUCCESS;
2726 uint32_t addr1, addr2, value1, value2, data, selval;
2727 uint8_t stride1, stride2;
2728 uint32_t addr3, addr4, addr5, addr6, addr7;
2729 uint16_t count, loop_cnt;
Lee Jonesf67e8162020-07-21 17:41:40 +01002730 uint32_t mask;
Tej Parkashb1829782014-02-24 22:06:59 -05002731 uint32_t *data_ptr = *d_ptr;
2732 struct qla8044_minidump_entry_rdmdio *rdmdio;
2733
2734 rdmdio = (struct qla8044_minidump_entry_rdmdio *)entry_hdr;
2735 addr1 = le32_to_cpu(rdmdio->addr_1);
2736 addr2 = le32_to_cpu(rdmdio->addr_2);
2737 value1 = le32_to_cpu(rdmdio->value_1);
2738 stride1 = le32_to_cpu(rdmdio->stride_1);
2739 stride2 = le32_to_cpu(rdmdio->stride_2);
2740 count = le32_to_cpu(rdmdio->count);
2741
Tej Parkashb1829782014-02-24 22:06:59 -05002742 mask = le32_to_cpu(rdmdio->mask);
2743 value2 = le32_to_cpu(rdmdio->value_2);
2744
2745 addr3 = addr1 + stride1;
2746
2747 for (loop_cnt = 0; loop_cnt < count; loop_cnt++) {
2748 rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2,
2749 addr3, mask);
2750 if (rval)
2751 goto exit_process_rdmdio;
2752
2753 addr4 = addr2 - stride1;
2754 rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr4,
2755 value2);
2756 if (rval)
2757 goto exit_process_rdmdio;
2758
2759 addr5 = addr2 - (2 * stride1);
2760 rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr5,
2761 value1);
2762 if (rval)
2763 goto exit_process_rdmdio;
2764
2765 addr6 = addr2 - (3 * stride1);
2766 rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask,
2767 addr6, 0x2);
2768 if (rval)
2769 goto exit_process_rdmdio;
2770
2771 rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2,
2772 addr3, mask);
2773 if (rval)
2774 goto exit_process_rdmdio;
2775
2776 addr7 = addr2 - (4 * stride1);
2777 rval = ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3,
2778 mask, addr7, &data);
2779 if (rval)
2780 goto exit_process_rdmdio;
2781
2782 selval = (value2 << 18) | (value1 << 2) | 2;
2783
2784 stride2 = le32_to_cpu(rdmdio->stride_2);
2785 *data_ptr++ = cpu_to_le32(selval);
2786 *data_ptr++ = cpu_to_le32(data);
2787
2788 value1 = value1 + stride2;
2789 *d_ptr = data_ptr;
2790 }
2791
2792exit_process_rdmdio:
2793 return rval;
2794}
2795
2796static uint32_t qla4_84xx_minidump_process_pollwr(struct scsi_qla_host *ha,
2797 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2798 uint32_t **d_ptr)
2799{
Lee Jonesf67e8162020-07-21 17:41:40 +01002800 uint32_t addr1, addr2, value1, value2, poll, r_value;
Tej Parkashb1829782014-02-24 22:06:59 -05002801 struct qla8044_minidump_entry_pollwr *pollwr_hdr;
2802 uint32_t wait_count = 0;
2803 uint32_t rval = QLA_SUCCESS;
2804
2805 pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr;
2806 addr1 = le32_to_cpu(pollwr_hdr->addr_1);
2807 addr2 = le32_to_cpu(pollwr_hdr->addr_2);
2808 value1 = le32_to_cpu(pollwr_hdr->value_1);
2809 value2 = le32_to_cpu(pollwr_hdr->value_2);
2810
2811 poll = le32_to_cpu(pollwr_hdr->poll);
Tej Parkashb1829782014-02-24 22:06:59 -05002812
2813 while (wait_count < poll) {
2814 ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value);
2815
2816 if ((r_value & poll) != 0)
2817 break;
2818
2819 wait_count++;
2820 }
2821
2822 if (wait_count == poll) {
2823 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__);
2824 rval = QLA_ERROR;
2825 goto exit_process_pollwr;
2826 }
2827
2828 ha->isp_ops->wr_reg_indirect(ha, addr2, value2);
2829 ha->isp_ops->wr_reg_indirect(ha, addr1, value1);
2830
2831 wait_count = 0;
2832 while (wait_count < poll) {
2833 ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value);
2834
2835 if ((r_value & poll) != 0)
2836 break;
2837 wait_count++;
2838 }
2839
2840exit_process_pollwr:
2841 return rval;
2842}
2843
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04002844static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha,
2845 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2846 uint32_t **d_ptr)
2847{
2848 uint32_t sel_val1, sel_val2, t_sel_val, data, i;
2849 uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
2850 struct qla83xx_minidump_entry_rdmux2 *rdmux2_hdr;
2851 uint32_t *data_ptr = *d_ptr;
2852
2853 rdmux2_hdr = (struct qla83xx_minidump_entry_rdmux2 *)entry_hdr;
2854 sel_val1 = le32_to_cpu(rdmux2_hdr->select_value_1);
2855 sel_val2 = le32_to_cpu(rdmux2_hdr->select_value_2);
2856 sel_addr1 = le32_to_cpu(rdmux2_hdr->select_addr_1);
2857 sel_addr2 = le32_to_cpu(rdmux2_hdr->select_addr_2);
2858 sel_val_mask = le32_to_cpu(rdmux2_hdr->select_value_mask);
2859 read_addr = le32_to_cpu(rdmux2_hdr->read_addr);
2860
2861 for (i = 0; i < rdmux2_hdr->op_count; i++) {
2862 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val1);
2863 t_sel_val = sel_val1 & sel_val_mask;
2864 *data_ptr++ = cpu_to_le32(t_sel_val);
2865
2866 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
2867 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
2868
2869 *data_ptr++ = cpu_to_le32(data);
2870
2871 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val2);
2872 t_sel_val = sel_val2 & sel_val_mask;
2873 *data_ptr++ = cpu_to_le32(t_sel_val);
2874
2875 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
2876 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
2877
2878 *data_ptr++ = cpu_to_le32(data);
2879
2880 sel_val1 += rdmux2_hdr->select_value_stride;
2881 sel_val2 += rdmux2_hdr->select_value_stride;
2882 }
2883
2884 *d_ptr = data_ptr;
2885}
2886
2887static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha,
2888 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2889 uint32_t **d_ptr)
2890{
2891 uint32_t poll_wait, poll_mask, r_value, data;
2892 uint32_t addr_1, addr_2, value_1, value_2;
2893 uint32_t *data_ptr = *d_ptr;
2894 uint32_t rval = QLA_SUCCESS;
2895 struct qla83xx_minidump_entry_pollrdmwr *poll_hdr;
2896
2897 poll_hdr = (struct qla83xx_minidump_entry_pollrdmwr *)entry_hdr;
2898 addr_1 = le32_to_cpu(poll_hdr->addr_1);
2899 addr_2 = le32_to_cpu(poll_hdr->addr_2);
2900 value_1 = le32_to_cpu(poll_hdr->value_1);
2901 value_2 = le32_to_cpu(poll_hdr->value_2);
2902 poll_mask = le32_to_cpu(poll_hdr->poll_mask);
2903
2904 ha->isp_ops->wr_reg_indirect(ha, addr_1, value_1);
2905
2906 poll_wait = le32_to_cpu(poll_hdr->poll_wait);
2907 while (1) {
2908 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
2909
2910 if ((r_value & poll_mask) != 0) {
2911 break;
2912 } else {
2913 msleep(1);
2914 if (--poll_wait == 0) {
2915 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_1\n",
2916 __func__);
2917 rval = QLA_ERROR;
2918 goto exit_process_pollrdmwr;
2919 }
2920 }
2921 }
2922
2923 ha->isp_ops->rd_reg_indirect(ha, addr_2, &data);
2924 data &= le32_to_cpu(poll_hdr->modify_mask);
2925 ha->isp_ops->wr_reg_indirect(ha, addr_2, data);
2926 ha->isp_ops->wr_reg_indirect(ha, addr_1, value_2);
2927
2928 poll_wait = le32_to_cpu(poll_hdr->poll_wait);
2929 while (1) {
2930 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
2931
2932 if ((r_value & poll_mask) != 0) {
2933 break;
2934 } else {
2935 msleep(1);
2936 if (--poll_wait == 0) {
2937 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_2\n",
2938 __func__);
2939 rval = QLA_ERROR;
2940 goto exit_process_pollrdmwr;
2941 }
2942 }
2943 }
2944
2945 *data_ptr++ = cpu_to_le32(addr_2);
2946 *data_ptr++ = cpu_to_le32(data);
2947 *d_ptr = data_ptr;
2948
2949exit_process_pollrdmwr:
2950 return rval;
2951}
2952
2953static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha,
2954 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2955 uint32_t **d_ptr)
2956{
2957 uint32_t fl_addr, u32_count, rval;
2958 struct qla8xxx_minidump_entry_rdrom *rom_hdr;
2959 uint32_t *data_ptr = *d_ptr;
2960
2961 rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
2962 fl_addr = le32_to_cpu(rom_hdr->read_addr);
2963 u32_count = le32_to_cpu(rom_hdr->read_data_size)/sizeof(uint32_t);
2964
2965 DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
2966 __func__, fl_addr, u32_count));
2967
2968 rval = qla4_83xx_lockless_flash_read_u32(ha, fl_addr,
2969 (u8 *)(data_ptr), u32_count);
2970
2971 if (rval == QLA_ERROR) {
2972 ql4_printk(KERN_ERR, ha, "%s: Flash Read Error,Count=%d\n",
2973 __func__, u32_count);
2974 goto exit_process_rdrom;
2975 }
2976
2977 data_ptr += u32_count;
2978 *d_ptr = data_ptr;
2979
2980exit_process_rdrom:
2981 return rval;
2982}
2983
Tej Parkash068237c82012-05-18 04:41:44 -04002984/**
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04002985 * qla4_8xxx_collect_md_data - Retrieve firmware minidump data.
Tej Parkash068237c82012-05-18 04:41:44 -04002986 * @ha: pointer to adapter structure
2987 **/
2988static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
2989{
2990 int num_entry_hdr = 0;
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04002991 struct qla8xxx_minidump_entry_hdr *entry_hdr;
Tej Parkash068237c82012-05-18 04:41:44 -04002992 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
2993 uint32_t *data_ptr;
2994 uint32_t data_collected = 0;
2995 int i, rval = QLA_ERROR;
2996 uint64_t now;
2997 uint32_t timestamp;
2998
Tej Parkash58e2bbe2013-12-16 06:49:44 -05002999 ha->fw_dump_skip_size = 0;
Tej Parkash068237c82012-05-18 04:41:44 -04003000 if (!ha->fw_dump) {
3001 ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n",
3002 __func__, ha->host_no);
3003 return rval;
3004 }
3005
3006 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
3007 ha->fw_dump_tmplt_hdr;
3008 data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump +
3009 ha->fw_dump_tmplt_size);
3010 data_collected += ha->fw_dump_tmplt_size;
3011
3012 num_entry_hdr = tmplt_hdr->num_of_entries;
3013 ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n",
3014 __func__, data_ptr);
3015 ql4_printk(KERN_INFO, ha,
3016 "[%s]: no of entry headers in Template: 0x%x\n",
3017 __func__, num_entry_hdr);
3018 ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n",
3019 __func__, ha->fw_dump_capture_mask);
3020 ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n",
3021 __func__, ha->fw_dump_size, ha->fw_dump_size);
3022
3023 /* Update current timestamp before taking dump */
3024 now = get_jiffies_64();
3025 timestamp = (u32)(jiffies_to_msecs(now) / 1000);
3026 tmplt_hdr->driver_timestamp = timestamp;
3027
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04003028 entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
Tej Parkash068237c82012-05-18 04:41:44 -04003029 (((uint8_t *)ha->fw_dump_tmplt_hdr) +
3030 tmplt_hdr->first_entry_offset);
3031
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04003032 if (is_qla8032(ha) || is_qla8042(ha))
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003033 tmplt_hdr->saved_state_array[QLA83XX_SS_OCM_WNDREG_INDEX] =
3034 tmplt_hdr->ocm_window_reg[ha->func_num];
3035
Tej Parkash068237c82012-05-18 04:41:44 -04003036 /* Walk through the entry headers - validate/perform required action */
3037 for (i = 0; i < num_entry_hdr; i++) {
Santosh Vernekar4812d072013-08-23 03:40:19 -04003038 if (data_collected > ha->fw_dump_size) {
Tej Parkash068237c82012-05-18 04:41:44 -04003039 ql4_printk(KERN_INFO, ha,
3040 "Data collected: [0x%x], Total Dump size: [0x%x]\n",
3041 data_collected, ha->fw_dump_size);
3042 return rval;
3043 }
3044
3045 if (!(entry_hdr->d_ctrl.entry_capture_mask &
3046 ha->fw_dump_capture_mask)) {
3047 entry_hdr->d_ctrl.driver_flags |=
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003048 QLA8XXX_DBG_SKIPPED_FLAG;
Tej Parkash068237c82012-05-18 04:41:44 -04003049 goto skip_nxt_entry;
3050 }
3051
3052 DEBUG2(ql4_printk(KERN_INFO, ha,
3053 "Data collected: [0x%x], Dump size left:[0x%x]\n",
3054 data_collected,
3055 (ha->fw_dump_size - data_collected)));
3056
3057 /* Decode the entry type and take required action to capture
3058 * debug data
3059 */
3060 switch (entry_hdr->entry_type) {
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003061 case QLA8XXX_RDEND:
Vikas Chaudhary5e9bcec2012-08-22 07:55:01 -04003062 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
Tej Parkash068237c82012-05-18 04:41:44 -04003063 break;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003064 case QLA8XXX_CNTRL:
Tej Parkash068237c82012-05-18 04:41:44 -04003065 rval = qla4_8xxx_minidump_process_control(ha,
3066 entry_hdr);
3067 if (rval != QLA_SUCCESS) {
Vikas Chaudhary5e9bcec2012-08-22 07:55:01 -04003068 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
Tej Parkash068237c82012-05-18 04:41:44 -04003069 goto md_failed;
3070 }
3071 break;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003072 case QLA8XXX_RDCRB:
Tej Parkash068237c82012-05-18 04:41:44 -04003073 qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr,
3074 &data_ptr);
3075 break;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003076 case QLA8XXX_RDMEM:
Tej Parkash068237c82012-05-18 04:41:44 -04003077 rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
3078 &data_ptr);
3079 if (rval != QLA_SUCCESS) {
Vikas Chaudhary5e9bcec2012-08-22 07:55:01 -04003080 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
Tej Parkash068237c82012-05-18 04:41:44 -04003081 goto md_failed;
3082 }
3083 break;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003084 case QLA8XXX_BOARD:
3085 case QLA8XXX_RDROM:
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003086 if (is_qla8022(ha)) {
3087 qla4_82xx_minidump_process_rdrom(ha, entry_hdr,
3088 &data_ptr);
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04003089 } else if (is_qla8032(ha) || is_qla8042(ha)) {
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003090 rval = qla4_83xx_minidump_process_rdrom(ha,
3091 entry_hdr,
3092 &data_ptr);
3093 if (rval != QLA_SUCCESS)
3094 qla4_8xxx_mark_entry_skipped(ha,
3095 entry_hdr,
3096 i);
3097 }
Tej Parkash068237c82012-05-18 04:41:44 -04003098 break;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003099 case QLA8XXX_L2DTG:
3100 case QLA8XXX_L2ITG:
3101 case QLA8XXX_L2DAT:
3102 case QLA8XXX_L2INS:
Tej Parkash068237c82012-05-18 04:41:44 -04003103 rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr,
3104 &data_ptr);
3105 if (rval != QLA_SUCCESS) {
Vikas Chaudhary5e9bcec2012-08-22 07:55:01 -04003106 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
Tej Parkash068237c82012-05-18 04:41:44 -04003107 goto md_failed;
3108 }
3109 break;
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003110 case QLA8XXX_L1DTG:
3111 case QLA8XXX_L1ITG:
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003112 case QLA8XXX_L1DAT:
3113 case QLA8XXX_L1INS:
Tej Parkash068237c82012-05-18 04:41:44 -04003114 qla4_8xxx_minidump_process_l1cache(ha, entry_hdr,
3115 &data_ptr);
3116 break;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003117 case QLA8XXX_RDOCM:
Tej Parkash068237c82012-05-18 04:41:44 -04003118 qla4_8xxx_minidump_process_rdocm(ha, entry_hdr,
3119 &data_ptr);
3120 break;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003121 case QLA8XXX_RDMUX:
Tej Parkash068237c82012-05-18 04:41:44 -04003122 qla4_8xxx_minidump_process_rdmux(ha, entry_hdr,
3123 &data_ptr);
3124 break;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003125 case QLA8XXX_QUEUE:
Tej Parkash068237c82012-05-18 04:41:44 -04003126 qla4_8xxx_minidump_process_queue(ha, entry_hdr,
3127 &data_ptr);
3128 break;
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003129 case QLA83XX_POLLRD:
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04003130 if (is_qla8022(ha)) {
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003131 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3132 break;
3133 }
3134 rval = qla83xx_minidump_process_pollrd(ha, entry_hdr,
3135 &data_ptr);
3136 if (rval != QLA_SUCCESS)
3137 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3138 break;
3139 case QLA83XX_RDMUX2:
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04003140 if (is_qla8022(ha)) {
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003141 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3142 break;
3143 }
3144 qla83xx_minidump_process_rdmux2(ha, entry_hdr,
3145 &data_ptr);
3146 break;
3147 case QLA83XX_POLLRDMWR:
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04003148 if (is_qla8022(ha)) {
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003149 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3150 break;
3151 }
3152 rval = qla83xx_minidump_process_pollrdmwr(ha, entry_hdr,
3153 &data_ptr);
3154 if (rval != QLA_SUCCESS)
3155 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3156 break;
Tej Parkashb1829782014-02-24 22:06:59 -05003157 case QLA8044_RDDFE:
3158 rval = qla4_84xx_minidump_process_rddfe(ha, entry_hdr,
3159 &data_ptr);
3160 if (rval != QLA_SUCCESS)
3161 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3162 break;
3163 case QLA8044_RDMDIO:
3164 rval = qla4_84xx_minidump_process_rdmdio(ha, entry_hdr,
3165 &data_ptr);
3166 if (rval != QLA_SUCCESS)
3167 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3168 break;
3169 case QLA8044_POLLWR:
3170 rval = qla4_84xx_minidump_process_pollwr(ha, entry_hdr,
3171 &data_ptr);
3172 if (rval != QLA_SUCCESS)
3173 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3174 break;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003175 case QLA8XXX_RDNOP:
Tej Parkash068237c82012-05-18 04:41:44 -04003176 default:
Vikas Chaudhary5e9bcec2012-08-22 07:55:01 -04003177 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
Tej Parkash068237c82012-05-18 04:41:44 -04003178 break;
3179 }
3180
Santosh Vernekar4812d072013-08-23 03:40:19 -04003181 data_collected = (uint8_t *)data_ptr - (uint8_t *)ha->fw_dump;
Tej Parkash068237c82012-05-18 04:41:44 -04003182skip_nxt_entry:
3183 /* next entry in the template */
Vikas Chaudhary7664a1f2012-08-22 07:55:00 -04003184 entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
Tej Parkash068237c82012-05-18 04:41:44 -04003185 (((uint8_t *)entry_hdr) +
3186 entry_hdr->entry_size);
3187 }
3188
Tej Parkash58e2bbe2013-12-16 06:49:44 -05003189 if ((data_collected + ha->fw_dump_skip_size) != ha->fw_dump_size) {
Tej Parkash068237c82012-05-18 04:41:44 -04003190 ql4_printk(KERN_INFO, ha,
3191 "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n",
3192 data_collected, ha->fw_dump_size);
Vikas Chaudhary35a9c2a2013-08-23 03:40:20 -04003193 rval = QLA_ERROR;
Tej Parkash068237c82012-05-18 04:41:44 -04003194 goto md_failed;
3195 }
3196
3197 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n",
3198 __func__, i));
3199md_failed:
3200 return rval;
3201}
3202
3203/**
3204 * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready.
3205 * @ha: pointer to adapter structure
Lee Jones653557d2020-07-21 17:41:41 +01003206 * @code: uevent code to act upon
Tej Parkash068237c82012-05-18 04:41:44 -04003207 **/
3208static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code)
3209{
3210 char event_string[40];
3211 char *envp[] = { event_string, NULL };
3212
3213 switch (code) {
3214 case QL4_UEVENT_CODE_FW_DUMP:
Ye Bin5ccdd102020-09-30 10:22:28 +08003215 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
Tej Parkash068237c82012-05-18 04:41:44 -04003216 ha->host_no);
3217 break;
3218 default:
3219 /*do nothing*/
3220 break;
3221 }
3222
3223 kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp);
3224}
3225
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003226void qla4_8xxx_get_minidump(struct scsi_qla_host *ha)
Vikas Chaudharyaec07ca2012-08-22 07:55:07 -04003227{
3228 if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) &&
3229 !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) {
3230 if (!qla4_8xxx_collect_md_data(ha)) {
3231 qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP);
3232 set_bit(AF_82XX_FW_DUMPED, &ha->flags);
3233 } else {
3234 ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n",
3235 __func__);
3236 }
3237 }
3238}
3239
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303240/**
3241 * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
3242 * @ha: pointer to adapter structure
3243 *
3244 * Note: IDC lock must be held upon entry
3245 **/
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003246int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303247{
Shyam Sundarb25ee662010-10-06 22:50:51 -07003248 int rval = QLA_ERROR;
Vikas Chaudhary32436aa2013-12-16 06:49:37 -05003249 int i;
Vikas Chaudhary80645dc2013-12-16 06:49:34 -05003250 uint32_t old_count, count;
Vikas Chaudhary4ebbb5c2013-12-16 06:49:45 -05003251 int need_reset = 0;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303252
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003253 need_reset = ha->isp_ops->need_reset(ha);
Shyam Sundarb25ee662010-10-06 22:50:51 -07003254
3255 if (need_reset) {
3256 /* We are trying to perform a recovery here. */
Vikas Chaudhary4ebbb5c2013-12-16 06:49:45 -05003257 if (test_bit(AF_FW_RECOVERY, &ha->flags))
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003258 ha->isp_ops->rom_lock_recovery(ha);
Shyam Sundarb25ee662010-10-06 22:50:51 -07003259 } else {
Vikas Chaudhary4ebbb5c2013-12-16 06:49:45 -05003260 old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
3261 for (i = 0; i < 10; i++) {
3262 msleep(200);
3263 count = qla4_8xxx_rd_direct(ha,
3264 QLA8XXX_PEG_ALIVE_COUNTER);
3265 if (count != old_count) {
3266 rval = QLA_SUCCESS;
3267 goto dev_ready;
3268 }
Shyam Sundarb25ee662010-10-06 22:50:51 -07003269 }
Vikas Chaudhary4ebbb5c2013-12-16 06:49:45 -05003270 ha->isp_ops->rom_lock_recovery(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303271 }
3272
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303273 /* set to DEV_INITIALIZING */
3274 ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003275 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
3276 QLA8XXX_DEV_INITIALIZING);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303277
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003278 ha->isp_ops->idc_unlock(ha);
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003279
3280 if (is_qla8022(ha))
3281 qla4_8xxx_get_minidump(ha);
3282
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003283 rval = ha->isp_ops->restart_firmware(ha);
3284 ha->isp_ops->idc_lock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303285
3286 if (rval != QLA_SUCCESS) {
3287 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
3288 qla4_8xxx_clear_drv_active(ha);
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003289 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
3290 QLA8XXX_DEV_FAILED);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303291 return rval;
3292 }
3293
3294dev_ready:
3295 ql4_printk(KERN_INFO, ha, "HW State: READY\n");
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003296 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303297
Shyam Sundarb25ee662010-10-06 22:50:51 -07003298 return rval;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303299}
3300
3301/**
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003302 * qla4_82xx_need_reset_handler - Code to start reset sequence
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303303 * @ha: pointer to adapter structure
3304 *
3305 * Note: IDC lock must be held upon entry
3306 **/
3307static void
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003308qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303309{
3310 uint32_t dev_state, drv_state, drv_active;
Tej Parkash068237c82012-05-18 04:41:44 -04003311 uint32_t active_mask = 0xFFFFFFFF;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303312 unsigned long reset_timeout;
3313
3314 ql4_printk(KERN_INFO, ha,
3315 "Performing ISP error recovery\n");
3316
3317 if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003318 qla4_82xx_idc_unlock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303319 ha->isp_ops->disable_intrs(ha);
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003320 qla4_82xx_idc_lock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303321 }
3322
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003323 if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
Tej Parkash068237c82012-05-18 04:41:44 -04003324 DEBUG2(ql4_printk(KERN_INFO, ha,
3325 "%s(%ld): reset acknowledged\n",
3326 __func__, ha->host_no));
3327 qla4_8xxx_set_rst_ready(ha);
3328 } else {
3329 active_mask = (~(1 << (ha->func_num * 4)));
3330 }
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303331
3332 /* wait for 10 seconds for reset ack from all functions */
3333 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
3334
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003335 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3336 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303337
3338 ql4_printk(KERN_INFO, ha,
3339 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
3340 __func__, ha->host_no, drv_state, drv_active);
3341
Tej Parkash068237c82012-05-18 04:41:44 -04003342 while (drv_state != (drv_active & active_mask)) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303343 if (time_after_eq(jiffies, reset_timeout)) {
Tej Parkash068237c82012-05-18 04:41:44 -04003344 ql4_printk(KERN_INFO, ha,
3345 "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n",
3346 DRIVER_NAME, drv_state, drv_active);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303347 break;
3348 }
3349
Tej Parkash068237c82012-05-18 04:41:44 -04003350 /*
3351 * When reset_owner times out, check which functions
3352 * acked/did not ack
3353 */
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003354 if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
Tej Parkash068237c82012-05-18 04:41:44 -04003355 ql4_printk(KERN_INFO, ha,
3356 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
3357 __func__, ha->host_no, drv_state,
3358 drv_active);
3359 }
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003360 qla4_82xx_idc_unlock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303361 msleep(1000);
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003362 qla4_82xx_idc_lock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303363
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003364 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3365 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303366 }
3367
Tej Parkash068237c82012-05-18 04:41:44 -04003368 /* Clear RESET OWNER as we are not going to use it any further */
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003369 clear_bit(AF_8XXX_RST_OWNER, &ha->flags);
Tej Parkash068237c82012-05-18 04:41:44 -04003370
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003371 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
Tej Parkash068237c82012-05-18 04:41:44 -04003372 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state,
3373 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303374
3375 /* Force to DEV_COLD unless someone else is starting a reset */
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003376 if (dev_state != QLA8XXX_DEV_INITIALIZING) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303377 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003378 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
Tej Parkash068237c82012-05-18 04:41:44 -04003379 qla4_8xxx_set_rst_ready(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303380 }
3381}
3382
3383/**
3384 * qla4_8xxx_need_qsnt_handler - Code to start qsnt
3385 * @ha: pointer to adapter structure
3386 **/
3387void
3388qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
3389{
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003390 ha->isp_ops->idc_lock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303391 qla4_8xxx_set_qsnt_ready(ha);
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003392 ha->isp_ops->idc_unlock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303393}
3394
Vikas Chaudhary83dbdf62012-08-22 07:55:06 -04003395static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha)
3396{
3397 int idc_ver;
3398 uint32_t drv_active;
3399
3400 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3401 if (drv_active == (1 << (ha->func_num * 4))) {
3402 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION,
3403 QLA82XX_IDC_VERSION);
3404 ql4_printk(KERN_INFO, ha,
3405 "%s: IDC version updated to %d\n", __func__,
3406 QLA82XX_IDC_VERSION);
3407 } else {
3408 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3409 if (QLA82XX_IDC_VERSION != idc_ver) {
3410 ql4_printk(KERN_INFO, ha,
3411 "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
3412 __func__, QLA82XX_IDC_VERSION, idc_ver);
3413 }
3414 }
3415}
3416
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003417static int qla4_83xx_set_idc_ver(struct scsi_qla_host *ha)
Vikas Chaudhary83dbdf62012-08-22 07:55:06 -04003418{
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003419 int idc_ver;
3420 uint32_t drv_active;
3421 int rval = QLA_SUCCESS;
3422
3423 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3424 if (drv_active == (1 << ha->func_num)) {
3425 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3426 idc_ver &= (~0xFF);
3427 idc_ver |= QLA83XX_IDC_VER_MAJ_VALUE;
3428 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, idc_ver);
3429 ql4_printk(KERN_INFO, ha,
3430 "%s: IDC version updated to %d\n", __func__,
Vikas Chaudharyecca5122012-09-20 07:35:02 -04003431 idc_ver);
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003432 } else {
3433 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3434 idc_ver &= 0xFF;
3435 if (QLA83XX_IDC_VER_MAJ_VALUE != idc_ver) {
3436 ql4_printk(KERN_INFO, ha,
3437 "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
3438 __func__, QLA83XX_IDC_VER_MAJ_VALUE,
3439 idc_ver);
3440 rval = QLA_ERROR;
3441 goto exit_set_idc_ver;
3442 }
Vikas Chaudhary83dbdf62012-08-22 07:55:06 -04003443 }
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003444
3445 /* Update IDC_MINOR_VERSION */
3446 idc_ver = qla4_83xx_rd_reg(ha, QLA83XX_CRB_IDC_VER_MINOR);
3447 idc_ver &= ~(0x03 << (ha->func_num * 2));
3448 idc_ver |= (QLA83XX_IDC_VER_MIN_VALUE << (ha->func_num * 2));
3449 qla4_83xx_wr_reg(ha, QLA83XX_CRB_IDC_VER_MINOR, idc_ver);
3450
3451exit_set_idc_ver:
3452 return rval;
3453}
3454
Vikas Chaudhary39c95822012-09-20 07:35:05 -04003455int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha)
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003456{
3457 uint32_t drv_active;
3458 int rval = QLA_SUCCESS;
3459
3460 if (test_bit(AF_INIT_DONE, &ha->flags))
3461 goto exit_update_idc_reg;
3462
3463 ha->isp_ops->idc_lock(ha);
3464 qla4_8xxx_set_drv_active(ha);
3465
3466 /*
3467 * If we are the first driver to load and
3468 * ql4xdontresethba is not set, clear IDC_CTRL BIT0.
3469 */
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04003470 if (is_qla8032(ha) || is_qla8042(ha)) {
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003471 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3472 if ((drv_active == (1 << ha->func_num)) && !ql4xdontresethba)
3473 qla4_83xx_clear_idc_dontreset(ha);
3474 }
3475
3476 if (is_qla8022(ha)) {
3477 qla4_82xx_set_idc_ver(ha);
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04003478 } else if (is_qla8032(ha) || is_qla8042(ha)) {
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003479 rval = qla4_83xx_set_idc_ver(ha);
3480 if (rval == QLA_ERROR)
3481 qla4_8xxx_clear_drv_active(ha);
3482 }
3483
3484 ha->isp_ops->idc_unlock(ha);
3485
3486exit_update_idc_reg:
3487 return rval;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303488}
3489
3490/**
3491 * qla4_8xxx_device_state_handler - Adapter state machine
3492 * @ha: pointer to host adapter structure.
3493 *
3494 * Note: IDC lock must be UNLOCKED upon entry
3495 **/
3496int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
3497{
3498 uint32_t dev_state;
3499 int rval = QLA_SUCCESS;
3500 unsigned long dev_init_timeout;
3501
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003502 rval = qla4_8xxx_update_idc_reg(ha);
3503 if (rval == QLA_ERROR)
3504 goto exit_state_handler;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303505
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003506 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
Tej Parkash068237c82012-05-18 04:41:44 -04003507 DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
3508 dev_state, dev_state < MAX_STATES ?
3509 qdev_state[dev_state] : "Unknown"));
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303510
3511 /* wait for 30 seconds for device to go ready */
3512 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
3513
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003514 ha->isp_ops->idc_lock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303515 while (1) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303516
3517 if (time_after_eq(jiffies, dev_init_timeout)) {
Tej Parkash068237c82012-05-18 04:41:44 -04003518 ql4_printk(KERN_WARNING, ha,
3519 "%s: Device Init Failed 0x%x = %s\n",
3520 DRIVER_NAME,
3521 dev_state, dev_state < MAX_STATES ?
3522 qdev_state[dev_state] : "Unknown");
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003523 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
3524 QLA8XXX_DEV_FAILED);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303525 }
3526
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003527 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
Tej Parkash068237c82012-05-18 04:41:44 -04003528 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
3529 dev_state, dev_state < MAX_STATES ?
3530 qdev_state[dev_state] : "Unknown");
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303531
3532 /* NOTE: Make sure idc unlocked upon exit of switch statement */
3533 switch (dev_state) {
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003534 case QLA8XXX_DEV_READY:
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303535 goto exit;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003536 case QLA8XXX_DEV_COLD:
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303537 rval = qla4_8xxx_device_bootstrap(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303538 goto exit;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003539 case QLA8XXX_DEV_INITIALIZING:
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003540 ha->isp_ops->idc_unlock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303541 msleep(1000);
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003542 ha->isp_ops->idc_lock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303543 break;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003544 case QLA8XXX_DEV_NEED_RESET:
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003545 /*
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04003546 * For ISP8324 and ISP8042, if NEED_RESET is set by any
3547 * driver, it should be honored, irrespective of
3548 * IDC_CTRL DONTRESET_BIT0
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003549 */
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04003550 if (is_qla8032(ha) || is_qla8042(ha)) {
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003551 qla4_83xx_need_reset_handler(ha);
3552 } else if (is_qla8022(ha)) {
3553 if (!ql4xdontresethba) {
3554 qla4_82xx_need_reset_handler(ha);
3555 /* Update timeout value after need
3556 * reset handler */
3557 dev_init_timeout = jiffies +
3558 (ha->nx_dev_init_timeout * HZ);
3559 } else {
3560 ha->isp_ops->idc_unlock(ha);
3561 msleep(1000);
3562 ha->isp_ops->idc_lock(ha);
3563 }
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303564 }
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303565 break;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003566 case QLA8XXX_DEV_NEED_QUIESCENT:
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303567 /* idc locked/unlocked in handler */
3568 qla4_8xxx_need_qsnt_handler(ha);
Nilesh Javalie3f37d12011-12-01 22:42:11 -08003569 break;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003570 case QLA8XXX_DEV_QUIESCENT:
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003571 ha->isp_ops->idc_unlock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303572 msleep(1000);
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003573 ha->isp_ops->idc_lock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303574 break;
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04003575 case QLA8XXX_DEV_FAILED:
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003576 ha->isp_ops->idc_unlock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303577 qla4xxx_dead_adapter_cleanup(ha);
3578 rval = QLA_ERROR;
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003579 ha->isp_ops->idc_lock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303580 goto exit;
3581 default:
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003582 ha->isp_ops->idc_unlock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303583 qla4xxx_dead_adapter_cleanup(ha);
3584 rval = QLA_ERROR;
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003585 ha->isp_ops->idc_lock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303586 goto exit;
3587 }
3588 }
3589exit:
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003590 ha->isp_ops->idc_unlock(ha);
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003591exit_state_handler:
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303592 return rval;
3593}
3594
3595int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
3596{
3597 int retval;
Sarang Radke78764992012-01-11 02:44:18 -08003598
3599 /* clear the interrupt */
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04003600 if (is_qla8032(ha) || is_qla8042(ha)) {
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003601 writel(0, &ha->qla4_83xx_reg->risc_intr);
3602 readl(&ha->qla4_83xx_reg->risc_intr);
3603 } else if (is_qla8022(ha)) {
3604 writel(0, &ha->qla4_82xx_reg->host_int);
3605 readl(&ha->qla4_82xx_reg->host_int);
3606 }
Sarang Radke78764992012-01-11 02:44:18 -08003607
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303608 retval = qla4_8xxx_device_state_handler(ha);
3609
Tej Parkash1b3d3992013-12-16 06:49:42 -05003610 /* Initialize request and response queues. */
3611 if (retval == QLA_SUCCESS)
3612 qla4xxx_init_rings(ha);
3613
Poornima Vonti137257d2013-01-20 23:51:01 -05003614 if (retval == QLA_SUCCESS && !test_bit(AF_IRQ_ATTACHED, &ha->flags))
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303615 retval = qla4xxx_request_irqs(ha);
Vikas Chaudharyf581a3f2010-10-06 22:47:48 -07003616
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303617 return retval;
3618}
3619
3620/*****************************************************************************/
3621/* Flash Manipulation Routines */
3622/*****************************************************************************/
3623
3624#define OPTROM_BURST_SIZE 0x1000
3625#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
3626
3627#define FARX_DATA_FLAG BIT_31
3628#define FARX_ACCESS_FLASH_CONF 0x7FFD0000
3629#define FARX_ACCESS_FLASH_DATA 0x7FF00000
3630
3631static inline uint32_t
3632flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
3633{
3634 return hw->flash_conf_off | faddr;
3635}
3636
3637static inline uint32_t
3638flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
3639{
3640 return hw->flash_data_off | faddr;
3641}
3642
3643static uint32_t *
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003644qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303645 uint32_t faddr, uint32_t length)
3646{
3647 uint32_t i;
3648 uint32_t val;
3649 int loops = 0;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003650 while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303651 udelay(100);
3652 cond_resched();
3653 loops++;
3654 }
3655 if (loops >= 50000) {
3656 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
3657 return dwptr;
3658 }
3659
3660 /* Dword reads to flash. */
3661 for (i = 0; i < length/4; i++, faddr += 4) {
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003662 if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303663 ql4_printk(KERN_WARNING, ha,
3664 "Do ROM fast read failed\n");
3665 goto done_read;
3666 }
3667 dwptr[i] = __constant_cpu_to_le32(val);
3668 }
3669
3670done_read:
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003671 qla4_82xx_rom_unlock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303672 return dwptr;
3673}
3674
Lee Jones653557d2020-07-21 17:41:41 +01003675/*
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303676 * Address and length are byte address
Lee Jones653557d2020-07-21 17:41:41 +01003677 */
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303678static uint8_t *
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003679qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303680 uint32_t offset, uint32_t length)
3681{
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003682 qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303683 return buf;
3684}
3685
3686static int
3687qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
3688{
3689 const char *loc, *locations[] = { "DEF", "PCI" };
3690
3691 /*
3692 * FLT-location structure resides after the last PCI region.
3693 */
3694
3695 /* Begin with sane defaults. */
3696 loc = locations[0];
3697 *start = FA_FLASH_LAYOUT_ADDR_82;
3698
3699 DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
3700 return QLA_SUCCESS;
3701}
3702
3703static void
3704qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
3705{
3706 const char *loc, *locations[] = { "DEF", "FLT" };
3707 uint16_t *wptr;
3708 uint16_t cnt, chksum;
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003709 uint32_t start, status;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303710 struct qla_flt_header *flt;
3711 struct qla_flt_region *region;
3712 struct ql82xx_hw_data *hw = &ha->hw;
3713
3714 hw->flt_region_flt = flt_addr;
3715 wptr = (uint16_t *)ha->request_ring;
3716 flt = (struct qla_flt_header *)ha->request_ring;
3717 region = (struct qla_flt_region *)&flt[1];
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003718
3719 if (is_qla8022(ha)) {
3720 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3721 flt_addr << 2, OPTROM_BURST_SIZE);
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04003722 } else if (is_qla8032(ha) || is_qla8042(ha)) {
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003723 status = qla4_83xx_flash_read_u32(ha, flt_addr << 2,
3724 (uint8_t *)ha->request_ring,
3725 0x400);
3726 if (status != QLA_SUCCESS)
3727 goto no_flash_data;
3728 }
3729
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303730 if (*wptr == __constant_cpu_to_le16(0xffff))
3731 goto no_flash_data;
3732 if (flt->version != __constant_cpu_to_le16(1)) {
3733 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
3734 "version=0x%x length=0x%x checksum=0x%x.\n",
3735 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
3736 le16_to_cpu(flt->checksum)));
3737 goto no_flash_data;
3738 }
3739
3740 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
3741 for (chksum = 0; cnt; cnt--)
3742 chksum += le16_to_cpu(*wptr++);
3743 if (chksum) {
3744 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
3745 "version=0x%x length=0x%x checksum=0x%x.\n",
3746 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
3747 chksum));
3748 goto no_flash_data;
3749 }
3750
3751 loc = locations[1];
3752 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
3753 for ( ; cnt; cnt--, region++) {
3754 /* Store addresses as DWORD offsets. */
3755 start = le32_to_cpu(region->start) >> 2;
3756
3757 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
3758 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
3759 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
3760
3761 switch (le32_to_cpu(region->code) & 0xff) {
3762 case FLT_REG_FDT:
3763 hw->flt_region_fdt = start;
3764 break;
3765 case FLT_REG_BOOT_CODE_82:
3766 hw->flt_region_boot = start;
3767 break;
3768 case FLT_REG_FW_82:
Nilesh Javali93823952011-10-07 16:55:39 -07003769 case FLT_REG_FW_82_1:
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303770 hw->flt_region_fw = start;
3771 break;
3772 case FLT_REG_BOOTLOAD_82:
3773 hw->flt_region_bootload = start;
3774 break;
Manish Rangankar2a991c22011-07-25 13:48:55 -05003775 case FLT_REG_ISCSI_PARAM:
3776 hw->flt_iscsi_param = start;
3777 break;
Lalit Chandivade45494152011-10-07 16:55:42 -07003778 case FLT_REG_ISCSI_CHAP:
3779 hw->flt_region_chap = start;
3780 hw->flt_chap_size = le32_to_cpu(region->size);
3781 break;
Adheer Chandravanshi1e9e2be2013-03-22 07:41:31 -04003782 case FLT_REG_ISCSI_DDB:
3783 hw->flt_region_ddb = start;
3784 hw->flt_ddb_size = le32_to_cpu(region->size);
3785 break;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303786 }
3787 }
3788 goto done;
3789
3790no_flash_data:
3791 /* Use hardcoded defaults. */
3792 loc = locations[0];
3793
3794 hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82;
3795 hw->flt_region_boot = FA_BOOT_CODE_ADDR_82;
3796 hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82;
3797 hw->flt_region_fw = FA_RISC_CODE_ADDR_82;
Vikas Chaudhary9a16f652013-03-22 07:08:32 -04003798 hw->flt_region_chap = FA_FLASH_ISCSI_CHAP >> 2;
Lalit Chandivade45494152011-10-07 16:55:42 -07003799 hw->flt_chap_size = FA_FLASH_CHAP_SIZE;
Adheer Chandravanshi1e9e2be2013-03-22 07:41:31 -04003800 hw->flt_region_ddb = FA_FLASH_ISCSI_DDB >> 2;
3801 hw->flt_ddb_size = FA_FLASH_DDB_SIZE;
Lalit Chandivade45494152011-10-07 16:55:42 -07003802
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303803done:
Vikas Chaudhary9a16f652013-03-22 07:08:32 -04003804 DEBUG2(ql4_printk(KERN_INFO, ha,
Adheer Chandravanshi1e9e2be2013-03-22 07:41:31 -04003805 "FLT[%s]: flt=0x%x fdt=0x%x boot=0x%x bootload=0x%x fw=0x%x chap=0x%x chap_size=0x%x ddb=0x%x ddb_size=0x%x\n",
Vikas Chaudhary9a16f652013-03-22 07:08:32 -04003806 loc, hw->flt_region_flt, hw->flt_region_fdt,
3807 hw->flt_region_boot, hw->flt_region_bootload,
Adheer Chandravanshi1e9e2be2013-03-22 07:41:31 -04003808 hw->flt_region_fw, hw->flt_region_chap,
3809 hw->flt_chap_size, hw->flt_region_ddb,
3810 hw->flt_ddb_size));
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303811}
3812
3813static void
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003814qla4_82xx_get_fdt_info(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303815{
3816#define FLASH_BLK_SIZE_4K 0x1000
3817#define FLASH_BLK_SIZE_32K 0x8000
3818#define FLASH_BLK_SIZE_64K 0x10000
3819 const char *loc, *locations[] = { "MID", "FDT" };
3820 uint16_t cnt, chksum;
3821 uint16_t *wptr;
3822 struct qla_fdt_layout *fdt;
Vikas Chaudhary3c3e2102010-08-09 05:14:07 -07003823 uint16_t mid = 0;
3824 uint16_t fid = 0;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303825 struct ql82xx_hw_data *hw = &ha->hw;
3826
3827 hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3828 hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
3829
3830 wptr = (uint16_t *)ha->request_ring;
3831 fdt = (struct qla_fdt_layout *)ha->request_ring;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003832 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303833 hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
3834
3835 if (*wptr == __constant_cpu_to_le16(0xffff))
3836 goto no_flash_data;
3837
3838 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
3839 fdt->sig[3] != 'D')
3840 goto no_flash_data;
3841
3842 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
3843 cnt++)
3844 chksum += le16_to_cpu(*wptr++);
3845
3846 if (chksum) {
3847 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
3848 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
3849 le16_to_cpu(fdt->version)));
3850 goto no_flash_data;
3851 }
3852
3853 loc = locations[1];
3854 mid = le16_to_cpu(fdt->man_id);
3855 fid = le16_to_cpu(fdt->id);
3856 hw->fdt_wrt_disable = fdt->wrt_disable_bits;
3857 hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd);
3858 hw->fdt_block_size = le32_to_cpu(fdt->block_size);
3859
3860 if (fdt->unprotect_sec_cmd) {
3861 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 |
3862 fdt->unprotect_sec_cmd);
3863 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
3864 flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) :
3865 flash_conf_addr(hw, 0x0336);
3866 }
3867 goto done;
3868
3869no_flash_data:
3870 loc = locations[0];
3871 hw->fdt_block_size = FLASH_BLK_SIZE_64K;
3872done:
3873 DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
3874 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
3875 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
3876 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
3877 hw->fdt_block_size));
3878}
3879
3880static void
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003881qla4_82xx_get_idc_param(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303882{
3883#define QLA82XX_IDC_PARAM_ADDR 0x003e885c
3884 uint32_t *wptr;
3885
3886 if (!is_qla8022(ha))
3887 return;
3888 wptr = (uint32_t *)ha->request_ring;
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003889 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303890 QLA82XX_IDC_PARAM_ADDR , 8);
3891
3892 if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
3893 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
3894 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
3895 } else {
3896 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
3897 ha->nx_reset_timeout = le32_to_cpu(*wptr);
3898 }
3899
3900 DEBUG2(ql4_printk(KERN_DEBUG, ha,
3901 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
3902 DEBUG2(ql4_printk(KERN_DEBUG, ha,
3903 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
3904 return;
3905}
3906
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003907void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
3908 int in_count)
3909{
3910 int i;
3911
3912 /* Load all mailbox registers, except mailbox 0. */
3913 for (i = 1; i < in_count; i++)
3914 writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]);
3915
3916 /* Wakeup firmware */
3917 writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]);
3918 readl(&ha->qla4_82xx_reg->mailbox_in[0]);
3919 writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint);
3920 readl(&ha->qla4_82xx_reg->hint);
3921}
3922
3923void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
3924{
3925 int intr_status;
3926
3927 intr_status = readl(&ha->qla4_82xx_reg->host_int);
3928 if (intr_status & ISRX_82XX_RISC_INT) {
3929 ha->mbox_status_count = out_count;
3930 intr_status = readl(&ha->qla4_82xx_reg->host_status);
3931 ha->isp_ops->interrupt_service_routine(ha, intr_status);
3932
3933 if (test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
Christoph Hellwigf5b893c2016-12-06 14:56:50 +01003934 (!ha->pdev->msi_enabled && !ha->pdev->msix_enabled))
Vikas Chaudhary33693c72012-08-22 07:55:04 -04003935 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
3936 0xfbff);
3937 }
3938}
3939
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303940int
3941qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
3942{
3943 int ret;
3944 uint32_t flt_addr;
3945
3946 ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
3947 if (ret != QLA_SUCCESS)
3948 return ret;
3949
3950 qla4_8xxx_get_flt_info(ha, flt_addr);
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003951 if (is_qla8022(ha)) {
3952 qla4_82xx_get_fdt_info(ha);
3953 qla4_82xx_get_idc_param(ha);
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04003954 } else if (is_qla8032(ha) || is_qla8042(ha)) {
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -04003955 qla4_83xx_get_idc_param(ha);
3956 }
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303957
3958 return QLA_SUCCESS;
3959}
3960
3961/**
3962 * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
3963 * @ha: pointer to host adapter structure.
3964 *
3965 * Remarks:
3966 * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
3967 * not be available after successful return. Driver must cleanup potential
3968 * outstanding I/O's after calling this funcion.
3969 **/
3970int
3971qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
3972{
3973 int status;
3974 uint32_t mbox_cmd[MBOX_REG_COUNT];
3975 uint32_t mbox_sts[MBOX_REG_COUNT];
3976
3977 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3978 memset(&mbox_sts, 0, sizeof(mbox_sts));
3979
3980 mbox_cmd[0] = MBOX_CMD_STOP_FW;
3981 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
3982 &mbox_cmd[0], &mbox_sts[0]);
3983
3984 DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
3985 __func__, status));
3986 return status;
3987}
3988
3989/**
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003990 * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands.
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303991 * @ha: pointer to host adapter structure.
3992 **/
3993int
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003994qla4_82xx_isp_reset(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05303995{
3996 int rval;
3997 uint32_t dev_state;
3998
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04003999 qla4_82xx_idc_lock(ha);
4000 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304001
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04004002 if (dev_state == QLA8XXX_DEV_READY) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304003 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04004004 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
Vikas Chaudharyde8c72d2012-08-22 09:14:24 -04004005 QLA8XXX_DEV_NEED_RESET);
4006 set_bit(AF_8XXX_RST_OWNER, &ha->flags);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304007 } else
4008 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
4009
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04004010 qla4_82xx_idc_unlock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304011
4012 rval = qla4_8xxx_device_state_handler(ha);
4013
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04004014 qla4_82xx_idc_lock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304015 qla4_8xxx_clear_rst_ready(ha);
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04004016 qla4_82xx_idc_unlock(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304017
Tej Parkash068237c82012-05-18 04:41:44 -04004018 if (rval == QLA_SUCCESS) {
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04004019 ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n");
Nilesh Javali21033632010-07-30 14:28:07 +05304020 clear_bit(AF_FW_RECOVERY, &ha->flags);
Tej Parkash068237c82012-05-18 04:41:44 -04004021 }
Nilesh Javali21033632010-07-30 14:28:07 +05304022
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304023 return rval;
4024}
4025
4026/**
4027 * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
4028 * @ha: pointer to host adapter structure.
4029 *
4030 **/
4031int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
4032{
4033 uint32_t mbox_cmd[MBOX_REG_COUNT];
4034 uint32_t mbox_sts[MBOX_REG_COUNT];
4035 struct mbx_sys_info *sys_info;
4036 dma_addr_t sys_info_dma;
4037 int status = QLA_ERROR;
4038
Luis Chamberlain750afb02019-01-04 09:23:09 +01004039 sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
4040 &sys_info_dma, GFP_KERNEL);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304041 if (sys_info == NULL) {
4042 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
4043 ha->host_no, __func__));
4044 return status;
4045 }
4046
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304047 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
4048 memset(&mbox_sts, 0, sizeof(mbox_sts));
4049
4050 mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO;
4051 mbox_cmd[1] = LSDW(sys_info_dma);
4052 mbox_cmd[2] = MSDW(sys_info_dma);
4053 mbox_cmd[4] = sizeof(*sys_info);
4054
4055 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
4056 &mbox_sts[0]) != QLA_SUCCESS) {
4057 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
4058 ha->host_no, __func__));
4059 goto exit_validate_mac82;
4060 }
4061
Vikas Chaudhary2ccdf0d2010-07-30 14:27:45 +05304062 /* Make sure we receive the minimum required data to cache internally */
Vikas Chaudharyb37ca412013-08-16 07:03:02 -04004063 if (((is_qla8032(ha) || is_qla8042(ha)) ? mbox_sts[3] : mbox_sts[4]) <
Nilesh Javalie19dd662012-12-29 02:24:53 -05004064 offsetof(struct mbx_sys_info, reserved)) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304065 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
4066 " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
4067 goto exit_validate_mac82;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304068 }
4069
4070 /* Save M.A.C. address & serial_number */
Manish Rangankar2a991c22011-07-25 13:48:55 -05004071 ha->port_num = sys_info->port_num;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304072 memcpy(ha->my_mac, &sys_info->mac_addr[0],
4073 min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
4074 memcpy(ha->serial_number, &sys_info->serial_number,
4075 min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
Vikas Chaudhary91ec7ce2011-08-01 03:26:17 -07004076 memcpy(ha->model_name, &sys_info->board_id_str,
4077 min(sizeof(ha->model_name), sizeof(sys_info->board_id_str)));
4078 ha->phy_port_cnt = sys_info->phys_port_cnt;
4079 ha->phy_port_num = sys_info->port_num;
4080 ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304081
Oleksandr Khoshabad1d81bd2016-10-22 20:32:28 +03004082 DEBUG2(printk("scsi%ld: %s: mac %pM serial %s\n",
4083 ha->host_no, __func__, ha->my_mac, ha->serial_number));
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304084
4085 status = QLA_SUCCESS;
4086
4087exit_validate_mac82:
4088 dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
4089 sys_info_dma);
4090 return status;
4091}
4092
4093/* Interrupt handling helpers. */
4094
Vikas Chaudhary5c19b922012-11-23 06:58:38 -05004095int qla4_8xxx_intr_enable(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304096{
4097 uint32_t mbox_cmd[MBOX_REG_COUNT];
4098 uint32_t mbox_sts[MBOX_REG_COUNT];
4099
4100 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
4101
4102 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
4103 memset(&mbox_sts, 0, sizeof(mbox_sts));
4104 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
4105 mbox_cmd[1] = INTR_ENABLE;
4106 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
4107 &mbox_sts[0]) != QLA_SUCCESS) {
4108 DEBUG2(ql4_printk(KERN_INFO, ha,
4109 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
4110 __func__, mbox_sts[0]));
4111 return QLA_ERROR;
4112 }
4113 return QLA_SUCCESS;
4114}
4115
Vikas Chaudhary5c19b922012-11-23 06:58:38 -05004116int qla4_8xxx_intr_disable(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304117{
4118 uint32_t mbox_cmd[MBOX_REG_COUNT];
4119 uint32_t mbox_sts[MBOX_REG_COUNT];
4120
4121 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
4122
4123 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
4124 memset(&mbox_sts, 0, sizeof(mbox_sts));
4125 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
4126 mbox_cmd[1] = INTR_DISABLE;
4127 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
4128 &mbox_sts[0]) != QLA_SUCCESS) {
4129 DEBUG2(ql4_printk(KERN_INFO, ha,
4130 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
4131 __func__, mbox_sts[0]));
4132 return QLA_ERROR;
4133 }
4134
4135 return QLA_SUCCESS;
4136}
4137
4138void
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04004139qla4_82xx_enable_intrs(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304140{
Vikas Chaudhary5c19b922012-11-23 06:58:38 -05004141 qla4_8xxx_intr_enable(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304142
4143 spin_lock_irq(&ha->hardware_lock);
4144 /* BIT 10 - reset */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04004145 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304146 spin_unlock_irq(&ha->hardware_lock);
4147 set_bit(AF_INTERRUPTS_ON, &ha->flags);
4148}
4149
4150void
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04004151qla4_82xx_disable_intrs(struct scsi_qla_host *ha)
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304152{
Sarang Radke5fa8b572011-03-23 08:07:33 -07004153 if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
Vikas Chaudhary5c19b922012-11-23 06:58:38 -05004154 qla4_8xxx_intr_disable(ha);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304155
4156 spin_lock_irq(&ha->hardware_lock);
4157 /* BIT 10 - set */
Vikas Chaudharyf8086f42012-08-22 07:54:59 -04004158 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304159 spin_unlock_irq(&ha->hardware_lock);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304160}
4161
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304162int
4163qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
4164{
Christoph Hellwigf5b893c2016-12-06 14:56:50 +01004165 int ret;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304166
Christoph Hellwigf5b893c2016-12-06 14:56:50 +01004167 ret = pci_alloc_irq_vectors(ha->pdev, QLA_MSIX_ENTRIES,
4168 QLA_MSIX_ENTRIES, PCI_IRQ_MSIX);
4169 if (ret < 0) {
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304170 ql4_printk(KERN_WARNING, ha,
4171 "MSI-X: Failed to enable support -- %d/%d\n",
4172 QLA_MSIX_ENTRIES, ret);
Christoph Hellwigf5b893c2016-12-06 14:56:50 +01004173 return ret;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304174 }
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304175
Christoph Hellwigf5b893c2016-12-06 14:56:50 +01004176 ret = request_irq(pci_irq_vector(ha->pdev, 0),
4177 qla4_8xxx_default_intr_handler, 0, "qla4xxx (default)",
4178 ha);
4179 if (ret)
4180 goto out_free_vectors;
4181
4182 ret = request_irq(pci_irq_vector(ha->pdev, 1),
4183 qla4_8xxx_msix_rsp_q, 0, "qla4xxx (rsp_q)", ha);
4184 if (ret)
4185 goto out_free_default_irq;
4186
4187 return 0;
4188
4189out_free_default_irq:
4190 free_irq(pci_irq_vector(ha->pdev, 0), ha);
4191out_free_vectors:
4192 pci_free_irq_vectors(ha->pdev);
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +05304193 return ret;
4194}
Nilesh Javali37418cc2013-12-16 06:49:31 -05004195
4196int qla4_8xxx_check_init_adapter_retry(struct scsi_qla_host *ha)
4197{
4198 int status = QLA_SUCCESS;
4199
4200 /* Dont retry adapter initialization if IRQ allocation failed */
4201 if (!test_bit(AF_IRQ_ATTACHED, &ha->flags)) {
4202 ql4_printk(KERN_WARNING, ha, "%s: Skipping retry of adapter initialization as IRQs are not attached\n",
4203 __func__);
4204 status = QLA_ERROR;
4205 goto exit_init_adapter_failure;
4206 }
4207
4208 /* Since interrupts are registered in start_firmware for
4209 * 8xxx, release them here if initialize_adapter fails
4210 * and retry adapter initialization */
4211 qla4xxx_free_irqs(ha);
4212
4213exit_init_adapter_failure:
4214 return status;
4215}