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Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +00001#ifndef __POWERNV_PCI_H
2#define __POWERNV_PCI_H
3
Ian Munsief4568342016-07-14 07:17:00 +10004#include <linux/iommu.h>
5#include <asm/iommu.h>
6#include <asm/msi_bitmap.h>
7
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +00008struct pci_dn;
9
Alistair Popple1ab66d12017-04-03 19:51:44 +100010/* Maximum possible number of ATSD MMIO registers per NPU */
11#define NV_NMMU_ATSD_REGS 8
12
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +000013enum pnv_phb_type {
Russell Currey2de50e92016-02-08 15:08:20 +110014 PNV_PHB_IODA1 = 0,
15 PNV_PHB_IODA2 = 1,
16 PNV_PHB_NPU = 2,
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +000017};
18
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +000019/* Precise PHB model for error management */
20enum pnv_phb_model {
21 PNV_PHB_MODEL_UNKNOWN,
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +000022 PNV_PHB_MODEL_P7IOC,
Gavin Shanaa0c0332013-04-25 19:20:57 +000023 PNV_PHB_MODEL_PHB3,
Alistair Popple5d2aa712015-12-17 13:43:13 +110024 PNV_PHB_MODEL_NPU,
Alistair Popple616badd2017-01-10 15:41:44 +110025 PNV_PHB_MODEL_NPU2,
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +000026};
27
Gavin Shan5c9d6d72013-09-06 09:00:03 +080028#define PNV_PCI_DIAG_BUF_SIZE 8192
Gavin Shan7ebdf952012-08-20 03:49:15 +000029#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
30#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
31#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
Guo Chao262af552014-07-21 14:42:30 +100032#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
33#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
Wei Yang781a8682015-03-25 16:23:57 +080034#define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +000035
Russell Currey31bbd452017-06-14 14:19:58 +100036/* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */
37#define PNV_IODA_STOPPED_STATE 0x8000000000000000
38
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +000039/* Data associated with a PE, including IOMMU tracking etc.. */
Gavin Shan4cce9552013-04-25 19:21:00 +000040struct pnv_phb;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +000041struct pnv_ioda_pe {
Gavin Shan7ebdf952012-08-20 03:49:15 +000042 unsigned long flags;
Gavin Shan4cce9552013-04-25 19:21:00 +000043 struct pnv_phb *phb;
Gavin Shanc5f77002016-05-20 16:41:35 +100044 int device_count;
Gavin Shan7ebdf952012-08-20 03:49:15 +000045
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +000046 /* A PE can be associated with a single device or an
47 * entire bus (& children). In the former case, pdev
48 * is populated, in the later case, pbus is.
49 */
Wei Yang781a8682015-03-25 16:23:57 +080050#ifdef CONFIG_PCI_IOV
51 struct pci_dev *parent_dev;
52#endif
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +000053 struct pci_dev *pdev;
54 struct pci_bus *pbus;
55
56 /* Effective RID (device RID for a device PE and base bus
57 * RID with devfn 0 for a bus PE)
58 */
59 unsigned int rid;
60
61 /* PE number */
62 unsigned int pe_number;
63
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +000064 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
Alexey Kardashevskiyb348aa62015-06-05 16:35:08 +100065 struct iommu_table_group table_group;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +000066
Benjamin Herrenschmidtcd15b042014-02-11 11:32:38 +110067 /* 64-bit TCE bypass region */
68 bool tce_bypass_enabled;
69 uint64_t tce_bypass_base;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +000070
71 /* MSIs. MVE index is identical for for 32 and 64 bit MSI
72 * and -1 if not supported. (It's actually identical to the
73 * PE number)
74 */
75 int mve_number;
76
Guo Chao262af552014-07-21 14:42:30 +100077 /* PEs in compound case */
78 struct pnv_ioda_pe *master;
79 struct list_head slaves;
80
Frederic Barrat25529102017-08-04 11:55:14 +020081 /* PCI peer-to-peer*/
82 int p2p_initiator_count;
83
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +000084 /* Link in list of PE#s */
Gavin Shan7ebdf952012-08-20 03:49:15 +000085 struct list_head list;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +000086};
87
Gavin Shanf5bc6b72014-04-24 18:00:09 +100088#define PNV_PHB_FLAG_EEH (1 << 0)
Ian Munsie4361b032016-07-14 07:17:06 +100089#define PNV_PHB_FLAG_CXL (1 << 1) /* Real PHB supporting the cxl kernel API */
Gavin Shanf5bc6b72014-04-24 18:00:09 +100090
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +000091struct pnv_phb {
92 struct pci_controller *hose;
93 enum pnv_phb_type type;
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +000094 enum pnv_phb_model model;
Gavin Shan8747f362013-06-20 13:21:06 +080095 u64 hub_id;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +000096 u64 opal_id;
Gavin Shanf5bc6b72014-04-24 18:00:09 +100097 int flags;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +000098 void __iomem *regs;
Benjamin Herrenschmidtfd141d1a2016-07-08 16:37:14 +100099 u64 regs_phys;
Gavin Shandb1266c2012-08-20 03:49:18 +0000100 int initialized;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000101 spinlock_t lock;
102
Gavin Shan37c367f2013-06-20 18:13:25 +0800103#ifdef CONFIG_DEBUG_FS
Gavin Shan7f52a5262014-04-24 18:00:18 +1000104 int has_dbgfs;
Gavin Shan37c367f2013-06-20 18:13:25 +0800105 struct dentry *dbgfs;
106#endif
107
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000108#ifdef CONFIG_PCI_MSI
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000109 unsigned int msi_base;
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000110 unsigned int msi32_support;
Gavin Shanfb1b55d2013-03-05 21:12:37 +0000111 struct msi_bitmap msi_bmp;
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000112#endif
113 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
Gavin Shan137436c2013-04-25 19:20:59 +0000114 unsigned int hwirq, unsigned int virq,
115 unsigned int is_64, struct msi_msg *msg);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000116 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
117 void (*fixup_phb)(struct pci_controller *hose);
Guo Chao262af552014-07-21 14:42:30 +1000118 int (*init_m64)(struct pnv_phb *phb);
Gavin Shan96a2f922015-06-19 12:26:17 +1000119 void (*reserve_m64_pe)(struct pci_bus *bus,
120 unsigned long *pe_bitmap, bool all);
Gavin Shan1e916772016-05-03 15:41:36 +1000121 struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all);
Gavin Shan49dec922014-07-21 14:42:33 +1000122 int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
123 void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
124 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000125
Russell Currey2de50e92016-02-08 15:08:20 +1100126 struct {
127 /* Global bridge info */
Gavin Shan92b8f132016-05-03 15:41:24 +1000128 unsigned int total_pe_num;
129 unsigned int reserved_pe_idx;
Gavin Shan63803c32016-05-20 16:41:32 +1000130 unsigned int root_pe_idx;
131 bool root_pe_populated;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000132
Russell Currey2de50e92016-02-08 15:08:20 +1100133 /* 32-bit MMIO window */
134 unsigned int m32_size;
135 unsigned int m32_segsize;
136 unsigned int m32_pci_base;
Guo Chao262af552014-07-21 14:42:30 +1000137
Russell Currey2de50e92016-02-08 15:08:20 +1100138 /* 64-bit MMIO window */
139 unsigned int m64_bar_idx;
140 unsigned long m64_size;
141 unsigned long m64_segsize;
142 unsigned long m64_base;
143 unsigned long m64_bar_alloc;
Guo Chao262af552014-07-21 14:42:30 +1000144
Russell Currey2de50e92016-02-08 15:08:20 +1100145 /* IO ports */
146 unsigned int io_size;
147 unsigned int io_segsize;
148 unsigned int io_pci_base;
Guo Chao262af552014-07-21 14:42:30 +1000149
Gavin Shan13ce7592016-05-03 15:41:23 +1000150 /* PE allocation */
Russell Currey2de50e92016-02-08 15:08:20 +1100151 struct mutex pe_alloc_mutex;
Gavin Shan13ce7592016-05-03 15:41:23 +1000152 unsigned long *pe_alloc;
153 struct pnv_ioda_pe *pe_array;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000154
Russell Currey2de50e92016-02-08 15:08:20 +1100155 /* M32 & IO segment maps */
Gavin Shan93289d82016-05-03 15:41:29 +1000156 unsigned int *m64_segmap;
Russell Currey2de50e92016-02-08 15:08:20 +1100157 unsigned int *m32_segmap;
158 unsigned int *io_segmap;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000159
Gavin Shan2b923ed2016-05-05 12:04:16 +1000160 /* DMA32 segment maps - IODA1 only */
161 unsigned int dma32_count;
162 unsigned int *dma32_segmap;
163
Russell Currey2de50e92016-02-08 15:08:20 +1100164 /* IRQ chip */
165 int irq_chip_init;
166 struct irq_chip irq_chip;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000167
Russell Currey2de50e92016-02-08 15:08:20 +1100168 /* Sorted list of used PE's based
169 * on the sequence of creation
170 */
171 struct list_head pe_list;
172 struct mutex pe_list_mutex;
Gavin Shan137436c2013-04-25 19:20:59 +0000173
Gavin Shanc1275622016-05-20 16:41:29 +1000174 /* Reverse map of PEs, indexed by {bus, devfn} */
175 unsigned int pe_rmap[0x10000];
Russell Currey2de50e92016-02-08 15:08:20 +1100176 } ioda;
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000177
Russell Currey5cb1f8f2017-06-14 14:19:59 +1000178 /* PHB and hub diagnostics */
179 unsigned int diag_data_size;
180 u8 *diag_data;
Brian W Hartca1de5d2013-12-20 13:06:01 -0600181
Alistair Popple1ab66d12017-04-03 19:51:44 +1000182 /* Nvlink2 data */
183 struct npu {
184 int index;
185 __be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS];
186 unsigned int mmio_atsd_count;
187
188 /* Bitmask for MMIO register usage */
189 unsigned long mmio_atsd_usage;
190 } npu;
191
Ian Munsie4361b032016-07-14 07:17:06 +1000192#ifdef CONFIG_CXL_BASE
193 struct cxl_afu *cxl_afu;
194#endif
Frederic Barrat25529102017-08-04 11:55:14 +0200195 int p2p_target_count;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000196};
197
198extern struct pci_ops pnv_pci_ops;
Alexey Kardashevskiyda004c32015-06-05 16:35:06 +1000199extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
200 unsigned long uaddr, enum dma_data_direction direction,
Krzysztof Kozlowski00085f12016-08-03 13:46:00 -0700201 unsigned long attrs);
Alexey Kardashevskiyda004c32015-06-05 16:35:06 +1000202extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
Alexey Kardashevskiy05c6cfb2015-06-05 16:35:15 +1000203extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
204 unsigned long *hpa, enum dma_data_direction *direction);
Alexey Kardashevskiyda004c32015-06-05 16:35:06 +1000205extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000206
Gavin Shan93aef2a2013-11-22 16:28:45 +0800207void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
208 unsigned char *log_buff);
Gavin Shan3532a7412015-03-17 16:15:03 +1100209int pnv_pci_cfg_read(struct pci_dn *pdn,
Gavin Shan9bf41be2013-06-27 13:46:48 +0800210 int where, int size, u32 *val);
Gavin Shan3532a7412015-03-17 16:15:03 +1100211int pnv_pci_cfg_write(struct pci_dn *pdn,
Gavin Shan9bf41be2013-06-27 13:46:48 +0800212 int where, int size, u32 val);
Alexey Kardashevskiy0eaf4de2015-06-05 16:35:09 +1000213extern struct iommu_table *pnv_pci_table_alloc(int nid);
214
215extern long pnv_pci_link_table_and_group(int node, int num,
216 struct iommu_table *tbl,
217 struct iommu_table_group *table_group);
218extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
219 struct iommu_table_group *table_group);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000220extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
221 void *tce_mem, u64 tce_size,
Alexey Kardashevskiy8fa5d452014-06-06 18:44:03 +1000222 u64 dma_offset, unsigned page_shift);
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000223extern void pnv_pci_init_ioda_hub(struct device_node *np);
Gavin Shanaa0c0332013-04-25 19:20:57 +0000224extern void pnv_pci_init_ioda2_phb(struct device_node *np);
Alistair Popple5d2aa712015-12-17 13:43:13 +1100225extern void pnv_pci_init_npu_phb(struct device_node *np);
Gavin Shand92a2082014-04-24 18:00:24 +1000226extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
Gavin Shancadf3642015-02-16 14:45:47 +1100227extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
Benjamin Herrenschmidt73ed1482013-05-10 16:59:18 +1000228
Daniel Axtens92ae0352015-04-28 15:12:05 +1000229extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
Gavin Shan1bc74f12016-02-09 15:50:22 +1100230extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
Daniel Axtens92ae0352015-04-28 15:12:05 +1000231extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
232extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
Ian Munsief4568342016-07-14 07:17:00 +1000233extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
234extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
Ian Munsie4361b032016-07-14 07:17:06 +1000235extern bool pnv_pci_enable_device_hook(struct pci_dev *dev);
Frederic Barrat25529102017-08-04 11:55:14 +0200236extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
Daniel Axtens92ae0352015-04-28 15:12:05 +1000237
Alexey Kardashevskiy7d623e42016-04-29 18:55:21 +1000238extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
239 const char *fmt, ...);
240#define pe_err(pe, fmt, ...) \
241 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
242#define pe_warn(pe, fmt, ...) \
243 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
244#define pe_info(pe, fmt, ...) \
245 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
246
Alistair Popple5d2aa712015-12-17 13:43:13 +1100247/* Nvlink functions */
Alexey Kardashevskiyf9f83452016-04-29 18:55:20 +1000248extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
Alistair Popple6b3d12a2017-05-03 13:24:08 +1000249extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
Alexey Kardashevskiyb5cb9ab2016-04-29 18:55:24 +1000250extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
251extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
252 struct iommu_table *tbl);
253extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
254extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
255extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
Alistair Popple1ab66d12017-04-03 19:51:44 +1000256extern int pnv_npu2_init(struct pnv_phb *phb);
Ian Munsie4361b032016-07-14 07:17:06 +1000257
258/* cxl functions */
259extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev);
260extern void pnv_cxl_disable_device(struct pci_dev *dev);
Ian Munsiea2f67d52016-07-14 07:17:10 +1000261extern int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
262extern void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
Ian Munsie4361b032016-07-14 07:17:06 +1000263
264
265/* phb ops (cxl switches these when enabling the kernel api on the phb) */
266extern const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops;
267
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000268#endif /* __POWERNV_PCI_H */