Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
Justin P. Mattock | 79add62 | 2011-04-04 14:15:29 -0700 | [diff] [blame] | 6 | * Copyright (C) 1996 David S. Miller (davem@davemloft.net) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) |
| 8 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. |
| 9 | */ |
James Hogan | 61d7304 | 2014-03-04 10:23:57 +0000 | [diff] [blame] | 10 | #include <linux/cpu_pm.h> |
Ralf Baechle | a754f70 | 2007-11-03 01:01:37 +0000 | [diff] [blame] | 11 | #include <linux/hardirq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | #include <linux/init.h> |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 13 | #include <linux/highmem.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | #include <linux/kernel.h> |
Ralf Baechle | 641e97f | 2007-10-11 23:46:05 +0100 | [diff] [blame] | 15 | #include <linux/linkage.h> |
Ralf Baechle | ff52205 | 2013-09-17 12:44:31 +0200 | [diff] [blame] | 16 | #include <linux/preempt.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | #include <linux/sched.h> |
Ralf Baechle | 631330f | 2009-06-19 14:05:26 +0100 | [diff] [blame] | 18 | #include <linux/smp.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | #include <linux/mm.h> |
Paul Gortmaker | d9ba577 | 2016-08-21 15:58:14 -0400 | [diff] [blame] | 20 | #include <linux/export.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | #include <linux/bitops.h> |
| 22 | |
| 23 | #include <asm/bcache.h> |
| 24 | #include <asm/bootinfo.h> |
Ralf Baechle | ec74e36 | 2005-07-13 11:48:45 +0000 | [diff] [blame] | 25 | #include <asm/cache.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | #include <asm/cacheops.h> |
| 27 | #include <asm/cpu.h> |
| 28 | #include <asm/cpu-features.h> |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 29 | #include <asm/cpu-type.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | #include <asm/io.h> |
| 31 | #include <asm/page.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | #include <asm/r4kcache.h> |
Ralf Baechle | e001e52 | 2007-07-28 12:45:47 +0100 | [diff] [blame] | 33 | #include <asm/sections.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | #include <asm/mmu_context.h> |
| 35 | #include <asm/war.h> |
Thiemo Seufer | ba5187d | 2005-04-25 16:36:23 +0000 | [diff] [blame] | 36 | #include <asm/cacheflush.h> /* for run_uncached() */ |
David Daney | 9cd9669b | 2012-05-15 00:04:49 -0700 | [diff] [blame] | 37 | #include <asm/traps.h> |
Steven J. Hill | b6d92b4 | 2013-03-25 13:47:29 -0500 | [diff] [blame] | 38 | #include <asm/dma-coherence.h> |
Paul Burton | e83f7e0 | 2017-08-12 19:49:41 -0700 | [diff] [blame] | 39 | #include <asm/mips-cps.h> |
Ralf Baechle | 7f3f1d0 | 2006-05-12 13:20:06 +0100 | [diff] [blame] | 40 | |
| 41 | /* |
James Hogan | d374d93 | 2016-07-13 14:12:50 +0100 | [diff] [blame] | 42 | * Bits describing what cache ops an SMP callback function may perform. |
| 43 | * |
| 44 | * R4K_HIT - Virtual user or kernel address based cache operations. The |
| 45 | * active_mm must be checked before using user addresses, falling |
| 46 | * back to kmap. |
| 47 | * R4K_INDEX - Index based cache operations. |
| 48 | */ |
| 49 | |
| 50 | #define R4K_HIT BIT(0) |
| 51 | #define R4K_INDEX BIT(1) |
| 52 | |
| 53 | /** |
| 54 | * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core. |
| 55 | * @type: Type of cache operations (R4K_HIT or R4K_INDEX). |
| 56 | * |
| 57 | * Decides whether a cache op needs to be performed on every core in the system. |
James Hogan | 640511a | 2016-07-13 14:12:52 +0100 | [diff] [blame] | 58 | * This may change depending on the @type of cache operation, as well as the set |
| 59 | * of online CPUs, so preemption should be disabled by the caller to prevent CPU |
| 60 | * hotplug from changing the result. |
James Hogan | d374d93 | 2016-07-13 14:12:50 +0100 | [diff] [blame] | 61 | * |
| 62 | * Returns: 1 if the cache operation @type should be done on every core in |
| 63 | * the system. |
| 64 | * 0 if the cache operation @type is globalized and only needs to |
| 65 | * be performed on a simple CPU. |
| 66 | */ |
| 67 | static inline bool r4k_op_needs_ipi(unsigned int type) |
| 68 | { |
| 69 | /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */ |
James Hogan | 11f7690 | 2016-07-13 14:12:56 +0100 | [diff] [blame] | 70 | if (type == R4K_HIT && mips_cm_present()) |
James Hogan | d374d93 | 2016-07-13 14:12:50 +0100 | [diff] [blame] | 71 | return false; |
| 72 | |
| 73 | /* |
| 74 | * Hardware doesn't globalize the required cache ops, so SMP calls may |
James Hogan | 640511a | 2016-07-13 14:12:52 +0100 | [diff] [blame] | 75 | * be needed, but only if there are foreign CPUs (non-siblings with |
| 76 | * separate caches). |
James Hogan | d374d93 | 2016-07-13 14:12:50 +0100 | [diff] [blame] | 77 | */ |
James Hogan | 640511a | 2016-07-13 14:12:52 +0100 | [diff] [blame] | 78 | /* cpu_foreign_map[] undeclared when !CONFIG_SMP */ |
| 79 | #ifdef CONFIG_SMP |
| 80 | return !cpumask_empty(&cpu_foreign_map[0]); |
| 81 | #else |
| 82 | return false; |
| 83 | #endif |
James Hogan | d374d93 | 2016-07-13 14:12:50 +0100 | [diff] [blame] | 84 | } |
| 85 | |
| 86 | /* |
Ralf Baechle | 7f3f1d0 | 2006-05-12 13:20:06 +0100 | [diff] [blame] | 87 | * Special Variant of smp_call_function for use by cache functions: |
| 88 | * |
| 89 | * o No return value |
| 90 | * o collapses to normal function call on UP kernels |
| 91 | * o collapses to normal function call on systems with a single shared |
| 92 | * primary cache. |
Ralf Baechle | c8c5f3f | 2010-10-29 19:08:25 +0100 | [diff] [blame] | 93 | * o doesn't disable interrupts on the local CPU |
Ralf Baechle | 7f3f1d0 | 2006-05-12 13:20:06 +0100 | [diff] [blame] | 94 | */ |
James Hogan | d374d93 | 2016-07-13 14:12:50 +0100 | [diff] [blame] | 95 | static inline void r4k_on_each_cpu(unsigned int type, |
| 96 | void (*func)(void *info), void *info) |
Ralf Baechle | 7f3f1d0 | 2006-05-12 13:20:06 +0100 | [diff] [blame] | 97 | { |
| 98 | preempt_disable(); |
James Hogan | d374d93 | 2016-07-13 14:12:50 +0100 | [diff] [blame] | 99 | if (r4k_op_needs_ipi(type)) |
James Hogan | 640511a | 2016-07-13 14:12:52 +0100 | [diff] [blame] | 100 | smp_call_function_many(&cpu_foreign_map[smp_processor_id()], |
| 101 | func, info, 1); |
Ralf Baechle | 7f3f1d0 | 2006-05-12 13:20:06 +0100 | [diff] [blame] | 102 | func(info); |
| 103 | preempt_enable(); |
| 104 | } |
| 105 | |
Ralf Baechle | ec74e36 | 2005-07-13 11:48:45 +0000 | [diff] [blame] | 106 | /* |
| 107 | * Must die. |
| 108 | */ |
| 109 | static unsigned long icache_size __read_mostly; |
| 110 | static unsigned long dcache_size __read_mostly; |
Huacai Chen | b2edcfc | 2016-03-03 09:45:09 +0800 | [diff] [blame] | 111 | static unsigned long vcache_size __read_mostly; |
Ralf Baechle | ec74e36 | 2005-07-13 11:48:45 +0000 | [diff] [blame] | 112 | static unsigned long scache_size __read_mostly; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 113 | |
| 114 | /* |
| 115 | * Dummy cache handling routines for machines without boardcaches |
| 116 | */ |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 117 | static void cache_noop(void) {} |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | |
| 119 | static struct bcache_ops no_sc_ops = { |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 120 | .bc_enable = (void *)cache_noop, |
| 121 | .bc_disable = (void *)cache_noop, |
| 122 | .bc_wback_inv = (void *)cache_noop, |
| 123 | .bc_inv = (void *)cache_noop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 124 | }; |
| 125 | |
| 126 | struct bcache_ops *bcops = &no_sc_ops; |
| 127 | |
Thiemo Seufer | 330cfe0 | 2005-09-01 18:33:58 +0000 | [diff] [blame] | 128 | #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) |
| 129 | #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 130 | |
| 131 | #define R4600_HIT_CACHEOP_WAR_IMPL \ |
| 132 | do { \ |
| 133 | if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \ |
| 134 | *(volatile unsigned long *)CKSEG1; \ |
| 135 | if (R4600_V1_HIT_CACHEOP_WAR) \ |
| 136 | __asm__ __volatile__("nop;nop;nop;nop"); \ |
| 137 | } while (0) |
| 138 | |
| 139 | static void (*r4k_blast_dcache_page)(unsigned long addr); |
| 140 | |
| 141 | static inline void r4k_blast_dcache_page_dc32(unsigned long addr) |
| 142 | { |
| 143 | R4600_HIT_CACHEOP_WAR_IMPL; |
| 144 | blast_dcache32_page(addr); |
| 145 | } |
| 146 | |
Kevin Cernekee | 605b7ef | 2009-04-23 17:36:53 -0700 | [diff] [blame] | 147 | static inline void r4k_blast_dcache_page_dc64(unsigned long addr) |
| 148 | { |
Kevin Cernekee | 605b7ef | 2009-04-23 17:36:53 -0700 | [diff] [blame] | 149 | blast_dcache64_page(addr); |
| 150 | } |
| 151 | |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 152 | static inline void r4k_blast_dcache_page_dc128(unsigned long addr) |
| 153 | { |
| 154 | blast_dcache128_page(addr); |
| 155 | } |
| 156 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 157 | static void r4k_blast_dcache_page_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 158 | { |
| 159 | unsigned long dc_lsize = cpu_dcache_line_size(); |
| 160 | |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 161 | switch (dc_lsize) { |
| 162 | case 0: |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 163 | r4k_blast_dcache_page = (void *)cache_noop; |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 164 | break; |
| 165 | case 16: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 166 | r4k_blast_dcache_page = blast_dcache16_page; |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 167 | break; |
| 168 | case 32: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 169 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 170 | break; |
| 171 | case 64: |
Kevin Cernekee | 605b7ef | 2009-04-23 17:36:53 -0700 | [diff] [blame] | 172 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc64; |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 173 | break; |
| 174 | case 128: |
| 175 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc128; |
| 176 | break; |
| 177 | default: |
| 178 | break; |
| 179 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 180 | } |
| 181 | |
Leonid Yegoshin | 4caa906 | 2014-01-15 14:47:28 +0000 | [diff] [blame] | 182 | #ifndef CONFIG_EVA |
| 183 | #define r4k_blast_dcache_user_page r4k_blast_dcache_page |
| 184 | #else |
| 185 | |
| 186 | static void (*r4k_blast_dcache_user_page)(unsigned long addr); |
| 187 | |
| 188 | static void r4k_blast_dcache_user_page_setup(void) |
| 189 | { |
| 190 | unsigned long dc_lsize = cpu_dcache_line_size(); |
| 191 | |
| 192 | if (dc_lsize == 0) |
| 193 | r4k_blast_dcache_user_page = (void *)cache_noop; |
| 194 | else if (dc_lsize == 16) |
| 195 | r4k_blast_dcache_user_page = blast_dcache16_user_page; |
| 196 | else if (dc_lsize == 32) |
| 197 | r4k_blast_dcache_user_page = blast_dcache32_user_page; |
| 198 | else if (dc_lsize == 64) |
| 199 | r4k_blast_dcache_user_page = blast_dcache64_user_page; |
| 200 | } |
| 201 | |
| 202 | #endif |
| 203 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 204 | static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); |
| 205 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 206 | static void r4k_blast_dcache_page_indexed_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 207 | { |
| 208 | unsigned long dc_lsize = cpu_dcache_line_size(); |
| 209 | |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 210 | if (dc_lsize == 0) |
| 211 | r4k_blast_dcache_page_indexed = (void *)cache_noop; |
| 212 | else if (dc_lsize == 16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 213 | r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; |
| 214 | else if (dc_lsize == 32) |
| 215 | r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; |
Kevin Cernekee | 605b7ef | 2009-04-23 17:36:53 -0700 | [diff] [blame] | 216 | else if (dc_lsize == 64) |
| 217 | r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed; |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 218 | else if (dc_lsize == 128) |
| 219 | r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 220 | } |
| 221 | |
Sanjay Lal | f2e3656 | 2012-11-21 18:34:10 -0800 | [diff] [blame] | 222 | void (* r4k_blast_dcache)(void); |
| 223 | EXPORT_SYMBOL(r4k_blast_dcache); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 224 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 225 | static void r4k_blast_dcache_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 226 | { |
| 227 | unsigned long dc_lsize = cpu_dcache_line_size(); |
| 228 | |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 229 | if (dc_lsize == 0) |
| 230 | r4k_blast_dcache = (void *)cache_noop; |
| 231 | else if (dc_lsize == 16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 232 | r4k_blast_dcache = blast_dcache16; |
| 233 | else if (dc_lsize == 32) |
| 234 | r4k_blast_dcache = blast_dcache32; |
Kevin Cernekee | 605b7ef | 2009-04-23 17:36:53 -0700 | [diff] [blame] | 235 | else if (dc_lsize == 64) |
| 236 | r4k_blast_dcache = blast_dcache64; |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 237 | else if (dc_lsize == 128) |
| 238 | r4k_blast_dcache = blast_dcache128; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 239 | } |
| 240 | |
| 241 | /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */ |
| 242 | #define JUMP_TO_ALIGN(order) \ |
| 243 | __asm__ __volatile__( \ |
| 244 | "b\t1f\n\t" \ |
| 245 | ".align\t" #order "\n\t" \ |
| 246 | "1:\n\t" \ |
| 247 | ) |
| 248 | #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */ |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 249 | #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 250 | |
| 251 | static inline void blast_r4600_v1_icache32(void) |
| 252 | { |
| 253 | unsigned long flags; |
| 254 | |
| 255 | local_irq_save(flags); |
| 256 | blast_icache32(); |
| 257 | local_irq_restore(flags); |
| 258 | } |
| 259 | |
| 260 | static inline void tx49_blast_icache32(void) |
| 261 | { |
| 262 | unsigned long start = INDEX_BASE; |
| 263 | unsigned long end = start + current_cpu_data.icache.waysize; |
| 264 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; |
| 265 | unsigned long ws_end = current_cpu_data.icache.ways << |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 266 | current_cpu_data.icache.waybit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 267 | unsigned long ws, addr; |
| 268 | |
| 269 | CACHE32_UNROLL32_ALIGN2; |
| 270 | /* I'm in even chunk. blast odd chunks */ |
Ralf Baechle | 42a3b4f2 | 2005-09-03 15:56:17 -0700 | [diff] [blame] | 271 | for (ws = 0; ws < ws_end; ws += ws_inc) |
| 272 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) |
Paul Burton | 6baaead | 2019-10-08 18:22:00 +0000 | [diff] [blame] | 273 | cache_unroll(32, kernel_cache, Index_Invalidate_I, |
| 274 | addr | ws, 32); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 275 | CACHE32_UNROLL32_ALIGN; |
| 276 | /* I'm in odd chunk. blast even chunks */ |
Ralf Baechle | 42a3b4f2 | 2005-09-03 15:56:17 -0700 | [diff] [blame] | 277 | for (ws = 0; ws < ws_end; ws += ws_inc) |
| 278 | for (addr = start; addr < end; addr += 0x400 * 2) |
Paul Burton | 6baaead | 2019-10-08 18:22:00 +0000 | [diff] [blame] | 279 | cache_unroll(32, kernel_cache, Index_Invalidate_I, |
| 280 | addr | ws, 32); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 281 | } |
| 282 | |
| 283 | static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) |
| 284 | { |
| 285 | unsigned long flags; |
| 286 | |
| 287 | local_irq_save(flags); |
| 288 | blast_icache32_page_indexed(page); |
| 289 | local_irq_restore(flags); |
| 290 | } |
| 291 | |
| 292 | static inline void tx49_blast_icache32_page_indexed(unsigned long page) |
| 293 | { |
Atsushi Nemoto | 67a3f6de | 2006-04-04 17:34:14 +0900 | [diff] [blame] | 294 | unsigned long indexmask = current_cpu_data.icache.waysize - 1; |
| 295 | unsigned long start = INDEX_BASE + (page & indexmask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | unsigned long end = start + PAGE_SIZE; |
| 297 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; |
| 298 | unsigned long ws_end = current_cpu_data.icache.ways << |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 299 | current_cpu_data.icache.waybit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 300 | unsigned long ws, addr; |
| 301 | |
| 302 | CACHE32_UNROLL32_ALIGN2; |
| 303 | /* I'm in even chunk. blast odd chunks */ |
Ralf Baechle | 42a3b4f2 | 2005-09-03 15:56:17 -0700 | [diff] [blame] | 304 | for (ws = 0; ws < ws_end; ws += ws_inc) |
| 305 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) |
Paul Burton | 6baaead | 2019-10-08 18:22:00 +0000 | [diff] [blame] | 306 | cache_unroll(32, kernel_cache, Index_Invalidate_I, |
| 307 | addr | ws, 32); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 308 | CACHE32_UNROLL32_ALIGN; |
| 309 | /* I'm in odd chunk. blast even chunks */ |
Ralf Baechle | 42a3b4f2 | 2005-09-03 15:56:17 -0700 | [diff] [blame] | 310 | for (ws = 0; ws < ws_end; ws += ws_inc) |
| 311 | for (addr = start; addr < end; addr += 0x400 * 2) |
Paul Burton | 6baaead | 2019-10-08 18:22:00 +0000 | [diff] [blame] | 312 | cache_unroll(32, kernel_cache, Index_Invalidate_I, |
| 313 | addr | ws, 32); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 314 | } |
| 315 | |
| 316 | static void (* r4k_blast_icache_page)(unsigned long addr); |
| 317 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 318 | static void r4k_blast_icache_page_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 319 | { |
| 320 | unsigned long ic_lsize = cpu_icache_line_size(); |
| 321 | |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 322 | if (ic_lsize == 0) |
| 323 | r4k_blast_icache_page = (void *)cache_noop; |
| 324 | else if (ic_lsize == 16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 325 | r4k_blast_icache_page = blast_icache16_page; |
Jiaxun Yang | 268a2d6 | 2019-10-20 22:43:13 +0800 | [diff] [blame] | 326 | else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2EF) |
Aaro Koskinen | 43a0684 | 2014-01-14 17:56:38 -0800 | [diff] [blame] | 327 | r4k_blast_icache_page = loongson2_blast_icache32_page; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 328 | else if (ic_lsize == 32) |
| 329 | r4k_blast_icache_page = blast_icache32_page; |
| 330 | else if (ic_lsize == 64) |
| 331 | r4k_blast_icache_page = blast_icache64_page; |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 332 | else if (ic_lsize == 128) |
| 333 | r4k_blast_icache_page = blast_icache128_page; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 334 | } |
| 335 | |
Leonid Yegoshin | 4caa906 | 2014-01-15 14:47:28 +0000 | [diff] [blame] | 336 | #ifndef CONFIG_EVA |
| 337 | #define r4k_blast_icache_user_page r4k_blast_icache_page |
| 338 | #else |
| 339 | |
| 340 | static void (*r4k_blast_icache_user_page)(unsigned long addr); |
| 341 | |
Paul Gortmaker | 9a8f4ea | 2015-04-27 18:47:57 -0400 | [diff] [blame] | 342 | static void r4k_blast_icache_user_page_setup(void) |
Leonid Yegoshin | 4caa906 | 2014-01-15 14:47:28 +0000 | [diff] [blame] | 343 | { |
| 344 | unsigned long ic_lsize = cpu_icache_line_size(); |
| 345 | |
| 346 | if (ic_lsize == 0) |
| 347 | r4k_blast_icache_user_page = (void *)cache_noop; |
| 348 | else if (ic_lsize == 16) |
| 349 | r4k_blast_icache_user_page = blast_icache16_user_page; |
| 350 | else if (ic_lsize == 32) |
| 351 | r4k_blast_icache_user_page = blast_icache32_user_page; |
| 352 | else if (ic_lsize == 64) |
| 353 | r4k_blast_icache_user_page = blast_icache64_user_page; |
| 354 | } |
| 355 | |
| 356 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 357 | |
| 358 | static void (* r4k_blast_icache_page_indexed)(unsigned long addr); |
| 359 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 360 | static void r4k_blast_icache_page_indexed_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 361 | { |
| 362 | unsigned long ic_lsize = cpu_icache_line_size(); |
| 363 | |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 364 | if (ic_lsize == 0) |
| 365 | r4k_blast_icache_page_indexed = (void *)cache_noop; |
| 366 | else if (ic_lsize == 16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 367 | r4k_blast_icache_page_indexed = blast_icache16_page_indexed; |
| 368 | else if (ic_lsize == 32) { |
Thiemo Seufer | 02fe2c9 | 2005-09-09 19:45:41 +0000 | [diff] [blame] | 369 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 370 | r4k_blast_icache_page_indexed = |
| 371 | blast_icache32_r4600_v1_page_indexed; |
Thiemo Seufer | 02fe2c9 | 2005-09-09 19:45:41 +0000 | [diff] [blame] | 372 | else if (TX49XX_ICACHE_INDEX_INV_WAR) |
| 373 | r4k_blast_icache_page_indexed = |
| 374 | tx49_blast_icache32_page_indexed; |
Jiaxun Yang | 268a2d6 | 2019-10-20 22:43:13 +0800 | [diff] [blame] | 375 | else if (current_cpu_type() == CPU_LOONGSON2EF) |
Aaro Koskinen | 43a0684 | 2014-01-14 17:56:38 -0800 | [diff] [blame] | 376 | r4k_blast_icache_page_indexed = |
| 377 | loongson2_blast_icache32_page_indexed; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 378 | else |
| 379 | r4k_blast_icache_page_indexed = |
| 380 | blast_icache32_page_indexed; |
| 381 | } else if (ic_lsize == 64) |
| 382 | r4k_blast_icache_page_indexed = blast_icache64_page_indexed; |
| 383 | } |
| 384 | |
Sanjay Lal | f2e3656 | 2012-11-21 18:34:10 -0800 | [diff] [blame] | 385 | void (* r4k_blast_icache)(void); |
| 386 | EXPORT_SYMBOL(r4k_blast_icache); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 387 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 388 | static void r4k_blast_icache_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 389 | { |
| 390 | unsigned long ic_lsize = cpu_icache_line_size(); |
| 391 | |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 392 | if (ic_lsize == 0) |
| 393 | r4k_blast_icache = (void *)cache_noop; |
| 394 | else if (ic_lsize == 16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 395 | r4k_blast_icache = blast_icache16; |
| 396 | else if (ic_lsize == 32) { |
| 397 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) |
| 398 | r4k_blast_icache = blast_r4600_v1_icache32; |
| 399 | else if (TX49XX_ICACHE_INDEX_INV_WAR) |
| 400 | r4k_blast_icache = tx49_blast_icache32; |
Jiaxun Yang | 268a2d6 | 2019-10-20 22:43:13 +0800 | [diff] [blame] | 401 | else if (current_cpu_type() == CPU_LOONGSON2EF) |
Aaro Koskinen | 43a0684 | 2014-01-14 17:56:38 -0800 | [diff] [blame] | 402 | r4k_blast_icache = loongson2_blast_icache32; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 403 | else |
| 404 | r4k_blast_icache = blast_icache32; |
| 405 | } else if (ic_lsize == 64) |
| 406 | r4k_blast_icache = blast_icache64; |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 407 | else if (ic_lsize == 128) |
| 408 | r4k_blast_icache = blast_icache128; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 409 | } |
| 410 | |
| 411 | static void (* r4k_blast_scache_page)(unsigned long addr); |
| 412 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 413 | static void r4k_blast_scache_page_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 414 | { |
| 415 | unsigned long sc_lsize = cpu_scache_line_size(); |
| 416 | |
Ralf Baechle | 4debe4f | 2006-02-27 19:05:55 +0000 | [diff] [blame] | 417 | if (scache_size == 0) |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 418 | r4k_blast_scache_page = (void *)cache_noop; |
Ralf Baechle | 4debe4f | 2006-02-27 19:05:55 +0000 | [diff] [blame] | 419 | else if (sc_lsize == 16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 420 | r4k_blast_scache_page = blast_scache16_page; |
| 421 | else if (sc_lsize == 32) |
| 422 | r4k_blast_scache_page = blast_scache32_page; |
| 423 | else if (sc_lsize == 64) |
| 424 | r4k_blast_scache_page = blast_scache64_page; |
| 425 | else if (sc_lsize == 128) |
| 426 | r4k_blast_scache_page = blast_scache128_page; |
| 427 | } |
| 428 | |
| 429 | static void (* r4k_blast_scache_page_indexed)(unsigned long addr); |
| 430 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 431 | static void r4k_blast_scache_page_indexed_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 432 | { |
| 433 | unsigned long sc_lsize = cpu_scache_line_size(); |
| 434 | |
Ralf Baechle | 4debe4f | 2006-02-27 19:05:55 +0000 | [diff] [blame] | 435 | if (scache_size == 0) |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 436 | r4k_blast_scache_page_indexed = (void *)cache_noop; |
Ralf Baechle | 4debe4f | 2006-02-27 19:05:55 +0000 | [diff] [blame] | 437 | else if (sc_lsize == 16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 438 | r4k_blast_scache_page_indexed = blast_scache16_page_indexed; |
| 439 | else if (sc_lsize == 32) |
| 440 | r4k_blast_scache_page_indexed = blast_scache32_page_indexed; |
| 441 | else if (sc_lsize == 64) |
| 442 | r4k_blast_scache_page_indexed = blast_scache64_page_indexed; |
| 443 | else if (sc_lsize == 128) |
| 444 | r4k_blast_scache_page_indexed = blast_scache128_page_indexed; |
| 445 | } |
| 446 | |
| 447 | static void (* r4k_blast_scache)(void); |
| 448 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 449 | static void r4k_blast_scache_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 450 | { |
| 451 | unsigned long sc_lsize = cpu_scache_line_size(); |
| 452 | |
Ralf Baechle | 4debe4f | 2006-02-27 19:05:55 +0000 | [diff] [blame] | 453 | if (scache_size == 0) |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 454 | r4k_blast_scache = (void *)cache_noop; |
Ralf Baechle | 4debe4f | 2006-02-27 19:05:55 +0000 | [diff] [blame] | 455 | else if (sc_lsize == 16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 456 | r4k_blast_scache = blast_scache16; |
| 457 | else if (sc_lsize == 32) |
| 458 | r4k_blast_scache = blast_scache32; |
| 459 | else if (sc_lsize == 64) |
| 460 | r4k_blast_scache = blast_scache64; |
| 461 | else if (sc_lsize == 128) |
| 462 | r4k_blast_scache = blast_scache128; |
| 463 | } |
| 464 | |
Huacai Chen | bb53fdf | 2018-11-15 15:53:53 +0800 | [diff] [blame] | 465 | static void (*r4k_blast_scache_node)(long node); |
| 466 | |
| 467 | static void r4k_blast_scache_node_setup(void) |
| 468 | { |
| 469 | unsigned long sc_lsize = cpu_scache_line_size(); |
| 470 | |
Jiaxun Yang | 268a2d6 | 2019-10-20 22:43:13 +0800 | [diff] [blame] | 471 | if (current_cpu_type() != CPU_LOONGSON64) |
Huacai Chen | bb53fdf | 2018-11-15 15:53:53 +0800 | [diff] [blame] | 472 | r4k_blast_scache_node = (void *)cache_noop; |
| 473 | else if (sc_lsize == 16) |
| 474 | r4k_blast_scache_node = blast_scache16_node; |
| 475 | else if (sc_lsize == 32) |
| 476 | r4k_blast_scache_node = blast_scache32_node; |
| 477 | else if (sc_lsize == 64) |
| 478 | r4k_blast_scache_node = blast_scache64_node; |
| 479 | else if (sc_lsize == 128) |
| 480 | r4k_blast_scache_node = blast_scache128_node; |
| 481 | } |
| 482 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 483 | static inline void local_r4k___flush_cache_all(void * args) |
| 484 | { |
Ralf Baechle | 10cc352 | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 485 | switch (current_cpu_type()) { |
Jiaxun Yang | 268a2d6 | 2019-10-20 22:43:13 +0800 | [diff] [blame] | 486 | case CPU_LOONGSON2EF: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 487 | case CPU_R4000SC: |
| 488 | case CPU_R4000MC: |
| 489 | case CPU_R4400SC: |
| 490 | case CPU_R4400MC: |
| 491 | case CPU_R10000: |
| 492 | case CPU_R12000: |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 493 | case CPU_R14000: |
Joshua Kinard | 3057739 | 2015-01-21 07:59:45 -0500 | [diff] [blame] | 494 | case CPU_R16000: |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 495 | /* |
| 496 | * These caches are inclusive caches, that is, if something |
| 497 | * is not cached in the S-cache, we know it also won't be |
| 498 | * in one of the primary caches. |
| 499 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 500 | r4k_blast_scache(); |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 501 | break; |
| 502 | |
Jiaxun Yang | 268a2d6 | 2019-10-20 22:43:13 +0800 | [diff] [blame] | 503 | case CPU_LOONGSON64: |
Huacai Chen | bb53fdf | 2018-11-15 15:53:53 +0800 | [diff] [blame] | 504 | /* Use get_ebase_cpunum() for both NUMA=y/n */ |
| 505 | r4k_blast_scache_node(get_ebase_cpunum() >> 2); |
| 506 | break; |
| 507 | |
Florian Fainelli | f675843 | 2016-04-04 10:55:36 -0700 | [diff] [blame] | 508 | case CPU_BMIPS5000: |
| 509 | r4k_blast_scache(); |
| 510 | __sync(); |
| 511 | break; |
| 512 | |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 513 | default: |
| 514 | r4k_blast_dcache(); |
| 515 | r4k_blast_icache(); |
| 516 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 517 | } |
| 518 | } |
| 519 | |
| 520 | static void r4k___flush_cache_all(void) |
| 521 | { |
James Hogan | d374d93 | 2016-07-13 14:12:50 +0100 | [diff] [blame] | 522 | r4k_on_each_cpu(R4K_INDEX, local_r4k___flush_cache_all, NULL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 523 | } |
| 524 | |
James Hogan | 6d758bf | 2016-07-13 14:12:51 +0100 | [diff] [blame] | 525 | /** |
| 526 | * has_valid_asid() - Determine if an mm already has an ASID. |
| 527 | * @mm: Memory map. |
| 528 | * @type: R4K_HIT or R4K_INDEX, type of cache op. |
| 529 | * |
| 530 | * Determines whether @mm already has an ASID on any of the CPUs which cache ops |
| 531 | * of type @type within an r4k_on_each_cpu() call will affect. If |
| 532 | * r4k_on_each_cpu() does an SMP call to a single VPE in each core, then the |
| 533 | * scope of the operation is confined to sibling CPUs, otherwise all online CPUs |
| 534 | * will need to be checked. |
| 535 | * |
| 536 | * Must be called in non-preemptive context. |
| 537 | * |
| 538 | * Returns: 1 if the CPUs affected by @type cache ops have an ASID for @mm. |
| 539 | * 0 otherwise. |
| 540 | */ |
| 541 | static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type) |
Ralf Baechle | a76ab5c | 2007-10-08 16:38:37 +0100 | [diff] [blame] | 542 | { |
James Hogan | 6d758bf | 2016-07-13 14:12:51 +0100 | [diff] [blame] | 543 | unsigned int i; |
| 544 | const cpumask_t *mask = cpu_present_mask; |
Ralf Baechle | a76ab5c | 2007-10-08 16:38:37 +0100 | [diff] [blame] | 545 | |
Paul Burton | c8790d6 | 2019-02-02 01:43:28 +0000 | [diff] [blame] | 546 | if (cpu_has_mmid) |
| 547 | return cpu_context(0, mm) != 0; |
| 548 | |
James Hogan | 6d758bf | 2016-07-13 14:12:51 +0100 | [diff] [blame] | 549 | /* cpu_sibling_map[] undeclared when !CONFIG_SMP */ |
| 550 | #ifdef CONFIG_SMP |
| 551 | /* |
| 552 | * If r4k_on_each_cpu does SMP calls, it does them to a single VPE in |
| 553 | * each foreign core, so we only need to worry about siblings. |
| 554 | * Otherwise we need to worry about all present CPUs. |
| 555 | */ |
| 556 | if (r4k_op_needs_ipi(type)) |
| 557 | mask = &cpu_sibling_map[smp_processor_id()]; |
| 558 | #endif |
| 559 | for_each_cpu(i, mask) |
Ralf Baechle | a76ab5c | 2007-10-08 16:38:37 +0100 | [diff] [blame] | 560 | if (cpu_context(i, mm)) |
| 561 | return 1; |
Ralf Baechle | a76ab5c | 2007-10-08 16:38:37 +0100 | [diff] [blame] | 562 | return 0; |
Ralf Baechle | a76ab5c | 2007-10-08 16:38:37 +0100 | [diff] [blame] | 563 | } |
| 564 | |
Ralf Baechle | 9c5a3d7 | 2008-04-05 15:13:23 +0100 | [diff] [blame] | 565 | static void r4k__flush_cache_vmap(void) |
| 566 | { |
| 567 | r4k_blast_dcache(); |
| 568 | } |
| 569 | |
| 570 | static void r4k__flush_cache_vunmap(void) |
| 571 | { |
| 572 | r4k_blast_dcache(); |
| 573 | } |
| 574 | |
James Hogan | a05c392 | 2016-07-13 14:12:44 +0100 | [diff] [blame] | 575 | /* |
| 576 | * Note: flush_tlb_range() assumes flush_cache_range() sufficiently flushes |
| 577 | * whole caches when vma is executable. |
| 578 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 579 | static inline void local_r4k_flush_cache_range(void * args) |
| 580 | { |
| 581 | struct vm_area_struct *vma = args; |
Ralf Baechle | 2eaa7ec | 2008-02-11 14:51:40 +0000 | [diff] [blame] | 582 | int exec = vma->vm_flags & VM_EXEC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 583 | |
James Hogan | 6d758bf | 2016-07-13 14:12:51 +0100 | [diff] [blame] | 584 | if (!has_valid_asid(vma->vm_mm, R4K_INDEX)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 585 | return; |
| 586 | |
James Hogan | b2a3c5b | 2016-01-22 10:58:25 +0000 | [diff] [blame] | 587 | /* |
| 588 | * If dcache can alias, we must blast it since mapping is changing. |
| 589 | * If executable, we must ensure any dirty lines are written back far |
| 590 | * enough to be visible to icache. |
| 591 | */ |
| 592 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) |
| 593 | r4k_blast_dcache(); |
| 594 | /* If executable, blast stale lines from icache */ |
Ralf Baechle | 2eaa7ec | 2008-02-11 14:51:40 +0000 | [diff] [blame] | 595 | if (exec) |
| 596 | r4k_blast_icache(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 597 | } |
| 598 | |
| 599 | static void r4k_flush_cache_range(struct vm_area_struct *vma, |
| 600 | unsigned long start, unsigned long end) |
| 601 | { |
Ralf Baechle | 2eaa7ec | 2008-02-11 14:51:40 +0000 | [diff] [blame] | 602 | int exec = vma->vm_flags & VM_EXEC; |
Atsushi Nemoto | 0550d9d | 2006-08-22 21:15:47 +0900 | [diff] [blame] | 603 | |
James Hogan | b2a3c5b | 2016-01-22 10:58:25 +0000 | [diff] [blame] | 604 | if (cpu_has_dc_aliases || exec) |
James Hogan | d374d93 | 2016-07-13 14:12:50 +0100 | [diff] [blame] | 605 | r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_range, vma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 606 | } |
| 607 | |
| 608 | static inline void local_r4k_flush_cache_mm(void * args) |
| 609 | { |
| 610 | struct mm_struct *mm = args; |
| 611 | |
James Hogan | 6d758bf | 2016-07-13 14:12:51 +0100 | [diff] [blame] | 612 | if (!has_valid_asid(mm, R4K_INDEX)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 613 | return; |
| 614 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 615 | /* |
| 616 | * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we |
Joshua Kinard | 3057739 | 2015-01-21 07:59:45 -0500 | [diff] [blame] | 617 | * only flush the primary caches but R1x000 behave sane ... |
Ralf Baechle | 617667b | 2006-11-30 01:14:48 +0000 | [diff] [blame] | 618 | * R4000SC and R4400SC indexed S-cache ops also invalidate primary |
| 619 | * caches, so we can bail out early. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 620 | */ |
Ralf Baechle | 10cc352 | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 621 | if (current_cpu_type() == CPU_R4000SC || |
| 622 | current_cpu_type() == CPU_R4000MC || |
| 623 | current_cpu_type() == CPU_R4400SC || |
| 624 | current_cpu_type() == CPU_R4400MC) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 625 | r4k_blast_scache(); |
Ralf Baechle | 617667b | 2006-11-30 01:14:48 +0000 | [diff] [blame] | 626 | return; |
| 627 | } |
| 628 | |
| 629 | r4k_blast_dcache(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 630 | } |
| 631 | |
| 632 | static void r4k_flush_cache_mm(struct mm_struct *mm) |
| 633 | { |
| 634 | if (!cpu_has_dc_aliases) |
| 635 | return; |
| 636 | |
James Hogan | d374d93 | 2016-07-13 14:12:50 +0100 | [diff] [blame] | 637 | r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_mm, mm); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 638 | } |
| 639 | |
| 640 | struct flush_cache_page_args { |
| 641 | struct vm_area_struct *vma; |
Ralf Baechle | 6ec2580 | 2005-10-12 00:02:34 +0100 | [diff] [blame] | 642 | unsigned long addr; |
Atsushi Nemoto | de62893 | 2006-03-13 18:23:03 +0900 | [diff] [blame] | 643 | unsigned long pfn; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 644 | }; |
| 645 | |
| 646 | static inline void local_r4k_flush_cache_page(void *args) |
| 647 | { |
| 648 | struct flush_cache_page_args *fcp_args = args; |
| 649 | struct vm_area_struct *vma = fcp_args->vma; |
Ralf Baechle | 6ec2580 | 2005-10-12 00:02:34 +0100 | [diff] [blame] | 650 | unsigned long addr = fcp_args->addr; |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 651 | struct page *page = pfn_to_page(fcp_args->pfn); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 652 | int exec = vma->vm_flags & VM_EXEC; |
| 653 | struct mm_struct *mm = vma->vm_mm; |
Ralf Baechle | c9c5023 | 2008-06-14 22:22:08 +0100 | [diff] [blame] | 654 | int map_coherent = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 655 | pmd_t *pmdp; |
| 656 | pte_t *ptep; |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 657 | void *vaddr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 658 | |
Ralf Baechle | 79acf83 | 2005-02-10 13:54:37 +0000 | [diff] [blame] | 659 | /* |
James Hogan | 6d758bf | 2016-07-13 14:12:51 +0100 | [diff] [blame] | 660 | * If owns no valid ASID yet, cannot possibly have gotten |
Ralf Baechle | 79acf83 | 2005-02-10 13:54:37 +0000 | [diff] [blame] | 661 | * this page into the cache. |
| 662 | */ |
James Hogan | 6d758bf | 2016-07-13 14:12:51 +0100 | [diff] [blame] | 663 | if (!has_valid_asid(mm, R4K_HIT)) |
Ralf Baechle | 79acf83 | 2005-02-10 13:54:37 +0000 | [diff] [blame] | 664 | return; |
| 665 | |
Ralf Baechle | 6ec2580 | 2005-10-12 00:02:34 +0100 | [diff] [blame] | 666 | addr &= PAGE_MASK; |
Mike Rapoport | e05c7b1 | 2020-06-08 21:33:05 -0700 | [diff] [blame] | 667 | pmdp = pmd_off(mm, addr); |
| 668 | ptep = pte_offset_kernel(pmdp, addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 669 | |
| 670 | /* |
| 671 | * If the page isn't marked valid, the page cannot possibly be |
| 672 | * in the cache. |
| 673 | */ |
Ralf Baechle | 526af35 | 2008-01-29 10:14:55 +0000 | [diff] [blame] | 674 | if (!(pte_present(*ptep))) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 675 | return; |
| 676 | |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 677 | if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) |
| 678 | vaddr = NULL; |
| 679 | else { |
| 680 | /* |
| 681 | * Use kmap_coherent or kmap_atomic to do flushes for |
| 682 | * another ASID than the current one. |
| 683 | */ |
Ralf Baechle | c9c5023 | 2008-06-14 22:22:08 +0100 | [diff] [blame] | 684 | map_coherent = (cpu_has_dc_aliases && |
Kirill A. Shutemov | e1534ae | 2016-01-15 16:53:46 -0800 | [diff] [blame] | 685 | page_mapcount(page) && |
| 686 | !Page_dcache_dirty(page)); |
Ralf Baechle | c9c5023 | 2008-06-14 22:22:08 +0100 | [diff] [blame] | 687 | if (map_coherent) |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 688 | vaddr = kmap_coherent(page, addr); |
| 689 | else |
Cong Wang | 9c02048 | 2011-11-25 23:14:15 +0800 | [diff] [blame] | 690 | vaddr = kmap_atomic(page); |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 691 | addr = (unsigned long)vaddr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 692 | } |
| 693 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 694 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { |
Markos Chandras | 80ca69f | 2014-01-16 13:11:08 +0000 | [diff] [blame] | 695 | vaddr ? r4k_blast_dcache_page(addr) : |
| 696 | r4k_blast_dcache_user_page(addr); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 697 | if (exec && !cpu_icache_snoops_remote_store) |
| 698 | r4k_blast_scache_page(addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 699 | } |
| 700 | if (exec) { |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 701 | if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { |
Paul Burton | c9b2a3d | 2019-02-02 01:43:19 +0000 | [diff] [blame] | 702 | drop_mmu_context(mm); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 703 | } else |
Markos Chandras | 80ca69f | 2014-01-16 13:11:08 +0000 | [diff] [blame] | 704 | vaddr ? r4k_blast_icache_page(addr) : |
| 705 | r4k_blast_icache_user_page(addr); |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 706 | } |
| 707 | |
| 708 | if (vaddr) { |
Ralf Baechle | c9c5023 | 2008-06-14 22:22:08 +0100 | [diff] [blame] | 709 | if (map_coherent) |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 710 | kunmap_coherent(); |
| 711 | else |
Cong Wang | 9c02048 | 2011-11-25 23:14:15 +0800 | [diff] [blame] | 712 | kunmap_atomic(vaddr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 713 | } |
| 714 | } |
| 715 | |
Ralf Baechle | 6ec2580 | 2005-10-12 00:02:34 +0100 | [diff] [blame] | 716 | static void r4k_flush_cache_page(struct vm_area_struct *vma, |
| 717 | unsigned long addr, unsigned long pfn) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 718 | { |
| 719 | struct flush_cache_page_args args; |
| 720 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 721 | args.vma = vma; |
Ralf Baechle | 6ec2580 | 2005-10-12 00:02:34 +0100 | [diff] [blame] | 722 | args.addr = addr; |
Atsushi Nemoto | de62893 | 2006-03-13 18:23:03 +0900 | [diff] [blame] | 723 | args.pfn = pfn; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 724 | |
James Hogan | d374d93 | 2016-07-13 14:12:50 +0100 | [diff] [blame] | 725 | r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_page, &args); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 726 | } |
| 727 | |
| 728 | static inline void local_r4k_flush_data_cache_page(void * addr) |
| 729 | { |
| 730 | r4k_blast_dcache_page((unsigned long) addr); |
| 731 | } |
| 732 | |
| 733 | static void r4k_flush_data_cache_page(unsigned long addr) |
| 734 | { |
Ralf Baechle | a754f70 | 2007-11-03 01:01:37 +0000 | [diff] [blame] | 735 | if (in_atomic()) |
| 736 | local_r4k_flush_data_cache_page((void *)addr); |
| 737 | else |
James Hogan | d374d93 | 2016-07-13 14:12:50 +0100 | [diff] [blame] | 738 | r4k_on_each_cpu(R4K_HIT, local_r4k_flush_data_cache_page, |
| 739 | (void *) addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 740 | } |
| 741 | |
| 742 | struct flush_icache_range_args { |
Atsushi Nemoto | d4264f1 | 2006-01-29 02:27:51 +0900 | [diff] [blame] | 743 | unsigned long start; |
| 744 | unsigned long end; |
James Hogan | 27b93d9 | 2016-07-13 14:12:54 +0100 | [diff] [blame] | 745 | unsigned int type; |
James Hogan | b2ff717 | 2016-09-01 17:30:15 +0100 | [diff] [blame] | 746 | bool user; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 747 | }; |
| 748 | |
James Hogan | 27b93d9 | 2016-07-13 14:12:54 +0100 | [diff] [blame] | 749 | static inline void __local_r4k_flush_icache_range(unsigned long start, |
| 750 | unsigned long end, |
James Hogan | b2ff717 | 2016-09-01 17:30:15 +0100 | [diff] [blame] | 751 | unsigned int type, |
| 752 | bool user) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 753 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 754 | if (!cpu_has_ic_fills_f_dc) { |
James Hogan | 27b93d9 | 2016-07-13 14:12:54 +0100 | [diff] [blame] | 755 | if (type == R4K_INDEX || |
| 756 | (type & R4K_INDEX && end - start >= dcache_size)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 757 | r4k_blast_dcache(); |
| 758 | } else { |
Thiemo Seufer | 10a3dab | 2005-09-09 20:26:54 +0000 | [diff] [blame] | 759 | R4600_HIT_CACHEOP_WAR_IMPL; |
James Hogan | b2ff717 | 2016-09-01 17:30:15 +0100 | [diff] [blame] | 760 | if (user) |
| 761 | protected_blast_dcache_range(start, end); |
| 762 | else |
| 763 | blast_dcache_range(start, end); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 764 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 765 | } |
| 766 | |
James Hogan | 27b93d9 | 2016-07-13 14:12:54 +0100 | [diff] [blame] | 767 | if (type == R4K_INDEX || |
| 768 | (type & R4K_INDEX && end - start > icache_size)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 769 | r4k_blast_icache(); |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 770 | else { |
| 771 | switch (boot_cpu_type()) { |
Jiaxun Yang | 268a2d6 | 2019-10-20 22:43:13 +0800 | [diff] [blame] | 772 | case CPU_LOONGSON2EF: |
Huacai Chen | bad009f | 2014-01-14 17:56:37 -0800 | [diff] [blame] | 773 | protected_loongson2_blast_icache_range(start, end); |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 774 | break; |
| 775 | |
| 776 | default: |
James Hogan | b2ff717 | 2016-09-01 17:30:15 +0100 | [diff] [blame] | 777 | if (user) |
| 778 | protected_blast_icache_range(start, end); |
| 779 | else |
| 780 | blast_icache_range(start, end); |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 781 | break; |
| 782 | } |
| 783 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 784 | } |
| 785 | |
James Hogan | 27b93d9 | 2016-07-13 14:12:54 +0100 | [diff] [blame] | 786 | static inline void local_r4k_flush_icache_range(unsigned long start, |
| 787 | unsigned long end) |
| 788 | { |
James Hogan | b2ff717 | 2016-09-01 17:30:15 +0100 | [diff] [blame] | 789 | __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, false); |
| 790 | } |
| 791 | |
| 792 | static inline void local_r4k_flush_icache_user_range(unsigned long start, |
| 793 | unsigned long end) |
| 794 | { |
| 795 | __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, true); |
James Hogan | 27b93d9 | 2016-07-13 14:12:54 +0100 | [diff] [blame] | 796 | } |
| 797 | |
Thomas Bogendoerfer | e0cee3e | 2008-08-04 20:53:57 +0200 | [diff] [blame] | 798 | static inline void local_r4k_flush_icache_range_ipi(void *args) |
| 799 | { |
| 800 | struct flush_icache_range_args *fir_args = args; |
| 801 | unsigned long start = fir_args->start; |
| 802 | unsigned long end = fir_args->end; |
James Hogan | 27b93d9 | 2016-07-13 14:12:54 +0100 | [diff] [blame] | 803 | unsigned int type = fir_args->type; |
James Hogan | b2ff717 | 2016-09-01 17:30:15 +0100 | [diff] [blame] | 804 | bool user = fir_args->user; |
Thomas Bogendoerfer | e0cee3e | 2008-08-04 20:53:57 +0200 | [diff] [blame] | 805 | |
James Hogan | b2ff717 | 2016-09-01 17:30:15 +0100 | [diff] [blame] | 806 | __local_r4k_flush_icache_range(start, end, type, user); |
Thomas Bogendoerfer | e0cee3e | 2008-08-04 20:53:57 +0200 | [diff] [blame] | 807 | } |
| 808 | |
James Hogan | b2ff717 | 2016-09-01 17:30:15 +0100 | [diff] [blame] | 809 | static void __r4k_flush_icache_range(unsigned long start, unsigned long end, |
| 810 | bool user) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 811 | { |
| 812 | struct flush_icache_range_args args; |
James Hogan | f70ddc0 | 2016-07-13 14:12:55 +0100 | [diff] [blame] | 813 | unsigned long size, cache_size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 814 | |
| 815 | args.start = start; |
| 816 | args.end = end; |
James Hogan | 27b93d9 | 2016-07-13 14:12:54 +0100 | [diff] [blame] | 817 | args.type = R4K_HIT | R4K_INDEX; |
James Hogan | b2ff717 | 2016-09-01 17:30:15 +0100 | [diff] [blame] | 818 | args.user = user; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 819 | |
James Hogan | f70ddc0 | 2016-07-13 14:12:55 +0100 | [diff] [blame] | 820 | /* |
| 821 | * Indexed cache ops require an SMP call. |
| 822 | * Consider if that can or should be avoided. |
| 823 | */ |
| 824 | preempt_disable(); |
| 825 | if (r4k_op_needs_ipi(R4K_INDEX) && !r4k_op_needs_ipi(R4K_HIT)) { |
| 826 | /* |
| 827 | * If address-based cache ops don't require an SMP call, then |
| 828 | * use them exclusively for small flushes. |
| 829 | */ |
Paul Burton | 801f823 | 2016-09-05 15:24:54 +0100 | [diff] [blame] | 830 | size = end - start; |
James Hogan | f70ddc0 | 2016-07-13 14:12:55 +0100 | [diff] [blame] | 831 | cache_size = icache_size; |
| 832 | if (!cpu_has_ic_fills_f_dc) { |
| 833 | size *= 2; |
| 834 | cache_size += dcache_size; |
| 835 | } |
| 836 | if (size <= cache_size) |
| 837 | args.type &= ~R4K_INDEX; |
| 838 | } |
James Hogan | 27b93d9 | 2016-07-13 14:12:54 +0100 | [diff] [blame] | 839 | r4k_on_each_cpu(args.type, local_r4k_flush_icache_range_ipi, &args); |
James Hogan | f70ddc0 | 2016-07-13 14:12:55 +0100 | [diff] [blame] | 840 | preempt_enable(); |
Ralf Baechle | cc61c1f | 2005-07-12 18:35:38 +0000 | [diff] [blame] | 841 | instruction_hazard(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 842 | } |
| 843 | |
James Hogan | b2ff717 | 2016-09-01 17:30:15 +0100 | [diff] [blame] | 844 | static void r4k_flush_icache_range(unsigned long start, unsigned long end) |
| 845 | { |
| 846 | return __r4k_flush_icache_range(start, end, false); |
| 847 | } |
| 848 | |
| 849 | static void r4k_flush_icache_user_range(unsigned long start, unsigned long end) |
| 850 | { |
| 851 | return __r4k_flush_icache_range(start, end, true); |
| 852 | } |
| 853 | |
Christoph Hellwig | 972dc3b | 2018-06-15 13:08:31 +0200 | [diff] [blame] | 854 | #ifdef CONFIG_DMA_NONCOHERENT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 855 | |
| 856 | static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) |
| 857 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 858 | /* Catch bad driver code */ |
Paul Burton | d4da0e9 | 2016-11-25 18:46:09 +0000 | [diff] [blame] | 859 | if (WARN_ON(size == 0)) |
| 860 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 861 | |
Ralf Baechle | ff52205 | 2013-09-17 12:44:31 +0200 | [diff] [blame] | 862 | preempt_disable(); |
Ralf Baechle | fc5d2d2 | 2006-07-06 13:04:01 +0100 | [diff] [blame] | 863 | if (cpu_has_inclusive_pcaches) { |
Huacai Chen | bb53fdf | 2018-11-15 15:53:53 +0800 | [diff] [blame] | 864 | if (size >= scache_size) { |
Jiaxun Yang | 268a2d6 | 2019-10-20 22:43:13 +0800 | [diff] [blame] | 865 | if (current_cpu_type() != CPU_LOONGSON64) |
Huacai Chen | bb53fdf | 2018-11-15 15:53:53 +0800 | [diff] [blame] | 866 | r4k_blast_scache(); |
| 867 | else |
| 868 | r4k_blast_scache_node(pa_to_nid(addr)); |
| 869 | } else { |
Atsushi Nemoto | 41700e7 | 2006-02-10 00:39:06 +0900 | [diff] [blame] | 870 | blast_scache_range(addr, addr + size); |
Huacai Chen | bb53fdf | 2018-11-15 15:53:53 +0800 | [diff] [blame] | 871 | } |
Yoichi Yuasa | 5596b0b | 2013-10-02 15:03:03 +0900 | [diff] [blame] | 872 | preempt_enable(); |
Kevin Cernekee | d0023c4 | 2010-09-06 21:03:46 -0700 | [diff] [blame] | 873 | __sync(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 874 | return; |
| 875 | } |
| 876 | |
| 877 | /* |
| 878 | * Either no secondary cache or the available caches don't have the |
| 879 | * subset property so we have to flush the primary caches |
NeilBrown | 55a2aa0 | 2018-04-27 09:28:34 +1000 | [diff] [blame] | 880 | * explicitly. |
| 881 | * If we would need IPI to perform an INDEX-type operation, then |
| 882 | * we have to use the HIT-type alternative as IPI cannot be used |
| 883 | * here due to interrupts possibly being disabled. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 884 | */ |
NeilBrown | 55a2aa0 | 2018-04-27 09:28:34 +1000 | [diff] [blame] | 885 | if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 886 | r4k_blast_dcache(); |
| 887 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 888 | R4600_HIT_CACHEOP_WAR_IMPL; |
Atsushi Nemoto | 41700e7 | 2006-02-10 00:39:06 +0900 | [diff] [blame] | 889 | blast_dcache_range(addr, addr + size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 890 | } |
Ralf Baechle | ff52205 | 2013-09-17 12:44:31 +0200 | [diff] [blame] | 891 | preempt_enable(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 892 | |
| 893 | bc_wback_inv(addr, size); |
Kevin Cernekee | d0023c4 | 2010-09-06 21:03:46 -0700 | [diff] [blame] | 894 | __sync(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 895 | } |
| 896 | |
Kamal Dasu | be28076 | 2020-02-07 17:33:07 -0500 | [diff] [blame] | 897 | static void prefetch_cache_inv(unsigned long addr, unsigned long size) |
| 898 | { |
| 899 | unsigned int linesz = cpu_scache_line_size(); |
| 900 | unsigned long addr0 = addr, addr1; |
| 901 | |
| 902 | addr0 &= ~(linesz - 1); |
| 903 | addr1 = (addr0 + size - 1) & ~(linesz - 1); |
| 904 | |
| 905 | protected_writeback_scache_line(addr0); |
| 906 | if (likely(addr1 != addr0)) |
| 907 | protected_writeback_scache_line(addr1); |
| 908 | else |
| 909 | return; |
| 910 | |
| 911 | addr0 += linesz; |
| 912 | if (likely(addr1 != addr0)) |
| 913 | protected_writeback_scache_line(addr0); |
| 914 | else |
| 915 | return; |
| 916 | |
| 917 | addr1 -= linesz; |
| 918 | if (likely(addr1 > addr0)) |
| 919 | protected_writeback_scache_line(addr0); |
| 920 | } |
| 921 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 922 | static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) |
| 923 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 924 | /* Catch bad driver code */ |
Paul Burton | d4da0e9 | 2016-11-25 18:46:09 +0000 | [diff] [blame] | 925 | if (WARN_ON(size == 0)) |
| 926 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 927 | |
Ralf Baechle | ff52205 | 2013-09-17 12:44:31 +0200 | [diff] [blame] | 928 | preempt_disable(); |
Kamal Dasu | be28076 | 2020-02-07 17:33:07 -0500 | [diff] [blame] | 929 | |
| 930 | if (current_cpu_type() == CPU_BMIPS5000) |
| 931 | prefetch_cache_inv(addr, size); |
| 932 | |
Ralf Baechle | fc5d2d2 | 2006-07-06 13:04:01 +0100 | [diff] [blame] | 933 | if (cpu_has_inclusive_pcaches) { |
Huacai Chen | bb53fdf | 2018-11-15 15:53:53 +0800 | [diff] [blame] | 934 | if (size >= scache_size) { |
Jiaxun Yang | 268a2d6 | 2019-10-20 22:43:13 +0800 | [diff] [blame] | 935 | if (current_cpu_type() != CPU_LOONGSON64) |
Huacai Chen | bb53fdf | 2018-11-15 15:53:53 +0800 | [diff] [blame] | 936 | r4k_blast_scache(); |
| 937 | else |
| 938 | r4k_blast_scache_node(pa_to_nid(addr)); |
| 939 | } else { |
Ralf Baechle | a8ca8b6 | 2009-01-11 18:44:49 +0000 | [diff] [blame] | 940 | /* |
| 941 | * There is no clearly documented alignment requirement |
| 942 | * for the cache instruction on MIPS processors and |
| 943 | * some processors, among them the RM5200 and RM7000 |
| 944 | * QED processors will throw an address error for cache |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 945 | * hit ops with insufficient alignment. Solved by |
Ralf Baechle | a8ca8b6 | 2009-01-11 18:44:49 +0000 | [diff] [blame] | 946 | * aligning the address to cache line size. |
| 947 | */ |
Thomas Bogendoerfer | e9c3357 | 2007-11-26 23:40:01 +0100 | [diff] [blame] | 948 | blast_inv_scache_range(addr, addr + size); |
Ralf Baechle | a8ca8b6 | 2009-01-11 18:44:49 +0000 | [diff] [blame] | 949 | } |
Yoichi Yuasa | 5596b0b | 2013-10-02 15:03:03 +0900 | [diff] [blame] | 950 | preempt_enable(); |
Kevin Cernekee | d0023c4 | 2010-09-06 21:03:46 -0700 | [diff] [blame] | 951 | __sync(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 952 | return; |
| 953 | } |
| 954 | |
NeilBrown | 55a2aa0 | 2018-04-27 09:28:34 +1000 | [diff] [blame] | 955 | if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 956 | r4k_blast_dcache(); |
| 957 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 958 | R4600_HIT_CACHEOP_WAR_IMPL; |
Thomas Bogendoerfer | e9c3357 | 2007-11-26 23:40:01 +0100 | [diff] [blame] | 959 | blast_inv_dcache_range(addr, addr + size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 960 | } |
Ralf Baechle | ff52205 | 2013-09-17 12:44:31 +0200 | [diff] [blame] | 961 | preempt_enable(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 962 | |
| 963 | bc_inv(addr, size); |
Kevin Cernekee | d0023c4 | 2010-09-06 21:03:46 -0700 | [diff] [blame] | 964 | __sync(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 965 | } |
Christoph Hellwig | 972dc3b | 2018-06-15 13:08:31 +0200 | [diff] [blame] | 966 | #endif /* CONFIG_DMA_NONCOHERENT */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 967 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 968 | static void r4k_flush_icache_all(void) |
| 969 | { |
| 970 | if (cpu_has_vtag_icache) |
| 971 | r4k_blast_icache(); |
| 972 | } |
| 973 | |
Ralf Baechle | d9cdc901 | 2011-06-17 16:20:28 +0100 | [diff] [blame] | 974 | struct flush_kernel_vmap_range_args { |
| 975 | unsigned long vaddr; |
| 976 | int size; |
| 977 | }; |
| 978 | |
James Hogan | a9341ae | 2016-07-13 14:12:53 +0100 | [diff] [blame] | 979 | static inline void local_r4k_flush_kernel_vmap_range_index(void *args) |
| 980 | { |
| 981 | /* |
| 982 | * Aliases only affect the primary caches so don't bother with |
| 983 | * S-caches or T-caches. |
| 984 | */ |
| 985 | r4k_blast_dcache(); |
| 986 | } |
| 987 | |
Ralf Baechle | d9cdc901 | 2011-06-17 16:20:28 +0100 | [diff] [blame] | 988 | static inline void local_r4k_flush_kernel_vmap_range(void *args) |
| 989 | { |
| 990 | struct flush_kernel_vmap_range_args *vmra = args; |
| 991 | unsigned long vaddr = vmra->vaddr; |
| 992 | int size = vmra->size; |
| 993 | |
| 994 | /* |
| 995 | * Aliases only affect the primary caches so don't bother with |
| 996 | * S-caches or T-caches. |
| 997 | */ |
James Hogan | a9341ae | 2016-07-13 14:12:53 +0100 | [diff] [blame] | 998 | R4600_HIT_CACHEOP_WAR_IMPL; |
| 999 | blast_dcache_range(vaddr, vaddr + size); |
Ralf Baechle | d9cdc901 | 2011-06-17 16:20:28 +0100 | [diff] [blame] | 1000 | } |
| 1001 | |
| 1002 | static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size) |
| 1003 | { |
| 1004 | struct flush_kernel_vmap_range_args args; |
| 1005 | |
| 1006 | args.vaddr = (unsigned long) vaddr; |
| 1007 | args.size = size; |
| 1008 | |
James Hogan | a9341ae | 2016-07-13 14:12:53 +0100 | [diff] [blame] | 1009 | if (size >= dcache_size) |
| 1010 | r4k_on_each_cpu(R4K_INDEX, |
| 1011 | local_r4k_flush_kernel_vmap_range_index, NULL); |
| 1012 | else |
| 1013 | r4k_on_each_cpu(R4K_HIT, local_r4k_flush_kernel_vmap_range, |
| 1014 | &args); |
Ralf Baechle | d9cdc901 | 2011-06-17 16:20:28 +0100 | [diff] [blame] | 1015 | } |
| 1016 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1017 | static inline void rm7k_erratum31(void) |
| 1018 | { |
| 1019 | const unsigned long ic_lsize = 32; |
| 1020 | unsigned long addr; |
| 1021 | |
| 1022 | /* RM7000 erratum #31. The icache is screwed at startup. */ |
| 1023 | write_c0_taglo(0); |
| 1024 | write_c0_taghi(0); |
| 1025 | |
| 1026 | for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { |
| 1027 | __asm__ __volatile__ ( |
Thiemo Seufer | d8748a3 | 2005-09-02 09:56:12 +0000 | [diff] [blame] | 1028 | ".set push\n\t" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1029 | ".set noreorder\n\t" |
| 1030 | ".set mips3\n\t" |
| 1031 | "cache\t%1, 0(%0)\n\t" |
| 1032 | "cache\t%1, 0x1000(%0)\n\t" |
| 1033 | "cache\t%1, 0x2000(%0)\n\t" |
| 1034 | "cache\t%1, 0x3000(%0)\n\t" |
| 1035 | "cache\t%2, 0(%0)\n\t" |
| 1036 | "cache\t%2, 0x1000(%0)\n\t" |
| 1037 | "cache\t%2, 0x2000(%0)\n\t" |
| 1038 | "cache\t%2, 0x3000(%0)\n\t" |
| 1039 | "cache\t%1, 0(%0)\n\t" |
| 1040 | "cache\t%1, 0x1000(%0)\n\t" |
| 1041 | "cache\t%1, 0x2000(%0)\n\t" |
| 1042 | "cache\t%1, 0x3000(%0)\n\t" |
Thiemo Seufer | d8748a3 | 2005-09-02 09:56:12 +0000 | [diff] [blame] | 1043 | ".set pop\n" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1044 | : |
Huacai Chen | a44f830 | 2020-04-26 19:09:52 +0800 | [diff] [blame] | 1045 | : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill_I)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1046 | } |
| 1047 | } |
| 1048 | |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 1049 | static inline int alias_74k_erratum(struct cpuinfo_mips *c) |
Steven J. Hill | 006a851 | 2012-06-26 04:11:03 +0000 | [diff] [blame] | 1050 | { |
Maciej W. Rozycki | 9213ad7 | 2013-09-18 19:08:15 +0100 | [diff] [blame] | 1051 | unsigned int imp = c->processor_id & PRID_IMP_MASK; |
| 1052 | unsigned int rev = c->processor_id & PRID_REV_MASK; |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 1053 | int present = 0; |
Maciej W. Rozycki | 9213ad7 | 2013-09-18 19:08:15 +0100 | [diff] [blame] | 1054 | |
Steven J. Hill | 006a851 | 2012-06-26 04:11:03 +0000 | [diff] [blame] | 1055 | /* |
| 1056 | * Early versions of the 74K do not update the cache tags on a |
| 1057 | * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 1058 | * aliases. In this case it is better to treat the cache as always |
| 1059 | * having aliases. Also disable the synonym tag update feature |
| 1060 | * where available. In this case no opportunistic tag update will |
| 1061 | * happen where a load causes a virtual address miss but a physical |
| 1062 | * address hit during a D-cache look-up. |
Steven J. Hill | 006a851 | 2012-06-26 04:11:03 +0000 | [diff] [blame] | 1063 | */ |
Maciej W. Rozycki | 9213ad7 | 2013-09-18 19:08:15 +0100 | [diff] [blame] | 1064 | switch (imp) { |
| 1065 | case PRID_IMP_74K: |
| 1066 | if (rev <= PRID_REV_ENCODE_332(2, 4, 0)) |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 1067 | present = 1; |
Maciej W. Rozycki | 9213ad7 | 2013-09-18 19:08:15 +0100 | [diff] [blame] | 1068 | if (rev == PRID_REV_ENCODE_332(2, 4, 0)) |
Huacai Chen | 8267e78 | 2020-05-23 15:51:45 +0800 | [diff] [blame] | 1069 | write_c0_config6(read_c0_config6() | MIPS_CONF6_MTI_SYND); |
Maciej W. Rozycki | 9213ad7 | 2013-09-18 19:08:15 +0100 | [diff] [blame] | 1070 | break; |
| 1071 | case PRID_IMP_1074K: |
| 1072 | if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) { |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 1073 | present = 1; |
Huacai Chen | 8267e78 | 2020-05-23 15:51:45 +0800 | [diff] [blame] | 1074 | write_c0_config6(read_c0_config6() | MIPS_CONF6_MTI_SYND); |
Maciej W. Rozycki | 9213ad7 | 2013-09-18 19:08:15 +0100 | [diff] [blame] | 1075 | } |
| 1076 | break; |
| 1077 | default: |
| 1078 | BUG(); |
Steven J. Hill | 006a851 | 2012-06-26 04:11:03 +0000 | [diff] [blame] | 1079 | } |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 1080 | |
| 1081 | return present; |
Steven J. Hill | 006a851 | 2012-06-26 04:11:03 +0000 | [diff] [blame] | 1082 | } |
| 1083 | |
Kevin Cernekee | d74b017 | 2014-10-20 21:28:00 -0700 | [diff] [blame] | 1084 | static void b5k_instruction_hazard(void) |
| 1085 | { |
| 1086 | __sync(); |
| 1087 | __sync(); |
| 1088 | __asm__ __volatile__( |
| 1089 | " nop; nop; nop; nop; nop; nop; nop; nop\n" |
| 1090 | " nop; nop; nop; nop; nop; nop; nop; nop\n" |
| 1091 | " nop; nop; nop; nop; nop; nop; nop; nop\n" |
| 1092 | " nop; nop; nop; nop; nop; nop; nop; nop\n" |
| 1093 | : : : "memory"); |
| 1094 | } |
| 1095 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1096 | static char *way_string[] = { NULL, "direct mapped", "2-way", |
Paul Burton | 1e18ac7 | 2015-07-09 10:40:41 +0100 | [diff] [blame] | 1097 | "3-way", "4-way", "5-way", "6-way", "7-way", "8-way", |
| 1098 | "9-way", "10-way", "11-way", "12-way", |
| 1099 | "13-way", "14-way", "15-way", "16-way", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1100 | }; |
| 1101 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1102 | static void probe_pcache(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1103 | { |
| 1104 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 1105 | unsigned int config = read_c0_config(); |
| 1106 | unsigned int prid = read_c0_prid(); |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 1107 | int has_74k_erratum = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1108 | unsigned long config1; |
| 1109 | unsigned int lsize; |
| 1110 | |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 1111 | switch (current_cpu_type()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1112 | case CPU_R4600: /* QED style two way caches? */ |
| 1113 | case CPU_R4700: |
| 1114 | case CPU_R5000: |
| 1115 | case CPU_NEVADA: |
| 1116 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); |
| 1117 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); |
| 1118 | c->icache.ways = 2; |
Atsushi Nemoto | 3c68da7 | 2006-04-08 01:33:31 +0900 | [diff] [blame] | 1119 | c->icache.waybit = __ffs(icache_size/2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1120 | |
| 1121 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); |
| 1122 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); |
| 1123 | c->dcache.ways = 2; |
Atsushi Nemoto | 3c68da7 | 2006-04-08 01:33:31 +0900 | [diff] [blame] | 1124 | c->dcache.waybit= __ffs(dcache_size/2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1125 | |
| 1126 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
| 1127 | break; |
| 1128 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1129 | case CPU_R5500: |
| 1130 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); |
| 1131 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); |
| 1132 | c->icache.ways = 2; |
| 1133 | c->icache.waybit= 0; |
| 1134 | |
| 1135 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); |
| 1136 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); |
| 1137 | c->dcache.ways = 2; |
| 1138 | c->dcache.waybit = 0; |
| 1139 | |
Shinya Kuribayashi | 5864810 | 2009-03-18 09:04:01 +0900 | [diff] [blame] | 1140 | c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1141 | break; |
| 1142 | |
| 1143 | case CPU_TX49XX: |
| 1144 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); |
| 1145 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); |
| 1146 | c->icache.ways = 4; |
| 1147 | c->icache.waybit= 0; |
| 1148 | |
| 1149 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); |
| 1150 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); |
| 1151 | c->dcache.ways = 4; |
| 1152 | c->dcache.waybit = 0; |
| 1153 | |
| 1154 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
Atsushi Nemoto | de862b4 | 2006-03-17 12:59:22 +0900 | [diff] [blame] | 1155 | c->options |= MIPS_CPU_PREFETCH; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1156 | break; |
| 1157 | |
| 1158 | case CPU_R4000PC: |
| 1159 | case CPU_R4000SC: |
| 1160 | case CPU_R4000MC: |
| 1161 | case CPU_R4400PC: |
| 1162 | case CPU_R4400SC: |
| 1163 | case CPU_R4400MC: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1164 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); |
| 1165 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); |
| 1166 | c->icache.ways = 1; |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1167 | c->icache.waybit = 0; /* doesn't matter */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1168 | |
| 1169 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); |
| 1170 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); |
| 1171 | c->dcache.ways = 1; |
| 1172 | c->dcache.waybit = 0; /* does not matter */ |
| 1173 | |
| 1174 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
| 1175 | break; |
| 1176 | |
| 1177 | case CPU_R10000: |
| 1178 | case CPU_R12000: |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 1179 | case CPU_R14000: |
Joshua Kinard | 3057739 | 2015-01-21 07:59:45 -0500 | [diff] [blame] | 1180 | case CPU_R16000: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1181 | icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); |
| 1182 | c->icache.linesz = 64; |
| 1183 | c->icache.ways = 2; |
| 1184 | c->icache.waybit = 0; |
| 1185 | |
| 1186 | dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); |
| 1187 | c->dcache.linesz = 32; |
| 1188 | c->dcache.ways = 2; |
| 1189 | c->dcache.waybit = 0; |
| 1190 | |
| 1191 | c->options |= MIPS_CPU_PREFETCH; |
| 1192 | break; |
| 1193 | |
| 1194 | case CPU_VR4133: |
Yoichi Yuasa | 2874fe5 | 2006-07-08 00:42:12 +0900 | [diff] [blame] | 1195 | write_c0_config(config & ~VR41_CONF_P4K); |
Liangliang Huang | c9b0299 | 2020-05-04 16:51:29 +0800 | [diff] [blame] | 1196 | fallthrough; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1197 | case CPU_VR4131: |
| 1198 | /* Workaround for cache instruction bug of VR4131 */ |
| 1199 | if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || |
| 1200 | c->processor_id == 0x0c82U) { |
Yoichi Yuasa | 4e8ab36 | 2006-07-04 22:59:41 +0900 | [diff] [blame] | 1201 | config |= 0x00400000U; |
| 1202 | if (c->processor_id == 0x0c80U) |
| 1203 | config |= VR41_CONF_BP; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1204 | write_c0_config(config); |
Yoichi Yuasa | 1058ecd | 2006-07-08 00:42:01 +0900 | [diff] [blame] | 1205 | } else |
| 1206 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
| 1207 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1208 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); |
| 1209 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); |
| 1210 | c->icache.ways = 2; |
Atsushi Nemoto | 3c68da7 | 2006-04-08 01:33:31 +0900 | [diff] [blame] | 1211 | c->icache.waybit = __ffs(icache_size/2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1212 | |
| 1213 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); |
| 1214 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); |
| 1215 | c->dcache.ways = 2; |
Atsushi Nemoto | 3c68da7 | 2006-04-08 01:33:31 +0900 | [diff] [blame] | 1216 | c->dcache.waybit = __ffs(dcache_size/2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1217 | break; |
| 1218 | |
| 1219 | case CPU_VR41XX: |
| 1220 | case CPU_VR4111: |
| 1221 | case CPU_VR4121: |
| 1222 | case CPU_VR4122: |
| 1223 | case CPU_VR4181: |
| 1224 | case CPU_VR4181A: |
| 1225 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); |
| 1226 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); |
| 1227 | c->icache.ways = 1; |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1228 | c->icache.waybit = 0; /* doesn't matter */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1229 | |
| 1230 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); |
| 1231 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); |
| 1232 | c->dcache.ways = 1; |
| 1233 | c->dcache.waybit = 0; /* does not matter */ |
| 1234 | |
| 1235 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
| 1236 | break; |
| 1237 | |
| 1238 | case CPU_RM7000: |
| 1239 | rm7k_erratum31(); |
| 1240 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1241 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); |
| 1242 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); |
| 1243 | c->icache.ways = 4; |
Atsushi Nemoto | 3c68da7 | 2006-04-08 01:33:31 +0900 | [diff] [blame] | 1244 | c->icache.waybit = __ffs(icache_size / c->icache.ways); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1245 | |
| 1246 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); |
| 1247 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); |
| 1248 | c->dcache.ways = 4; |
Atsushi Nemoto | 3c68da7 | 2006-04-08 01:33:31 +0900 | [diff] [blame] | 1249 | c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1250 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1251 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1252 | c->options |= MIPS_CPU_PREFETCH; |
| 1253 | break; |
| 1254 | |
Jiaxun Yang | 268a2d6 | 2019-10-20 22:43:13 +0800 | [diff] [blame] | 1255 | case CPU_LOONGSON2EF: |
Fuxin Zhang | 2a21c73 | 2007-06-06 14:52:43 +0800 | [diff] [blame] | 1256 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); |
| 1257 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); |
| 1258 | if (prid & 0x3) |
| 1259 | c->icache.ways = 4; |
| 1260 | else |
| 1261 | c->icache.ways = 2; |
| 1262 | c->icache.waybit = 0; |
| 1263 | |
| 1264 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); |
| 1265 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); |
| 1266 | if (prid & 0x3) |
| 1267 | c->dcache.ways = 4; |
| 1268 | else |
| 1269 | c->dcache.ways = 2; |
| 1270 | c->dcache.waybit = 0; |
| 1271 | break; |
| 1272 | |
Jiaxun Yang | 268a2d6 | 2019-10-20 22:43:13 +0800 | [diff] [blame] | 1273 | case CPU_LOONGSON64: |
Huacai Chen | c579d31 | 2014-03-21 18:44:00 +0800 | [diff] [blame] | 1274 | config1 = read_c0_config1(); |
| 1275 | lsize = (config1 >> 19) & 7; |
| 1276 | if (lsize) |
| 1277 | c->icache.linesz = 2 << lsize; |
| 1278 | else |
| 1279 | c->icache.linesz = 0; |
| 1280 | c->icache.sets = 64 << ((config1 >> 22) & 7); |
| 1281 | c->icache.ways = 1 + ((config1 >> 16) & 7); |
| 1282 | icache_size = c->icache.sets * |
| 1283 | c->icache.ways * |
| 1284 | c->icache.linesz; |
| 1285 | c->icache.waybit = 0; |
| 1286 | |
| 1287 | lsize = (config1 >> 10) & 7; |
| 1288 | if (lsize) |
| 1289 | c->dcache.linesz = 2 << lsize; |
| 1290 | else |
| 1291 | c->dcache.linesz = 0; |
| 1292 | c->dcache.sets = 64 << ((config1 >> 13) & 7); |
| 1293 | c->dcache.ways = 1 + ((config1 >> 7) & 7); |
| 1294 | dcache_size = c->dcache.sets * |
| 1295 | c->dcache.ways * |
| 1296 | c->dcache.linesz; |
| 1297 | c->dcache.waybit = 0; |
Huacai Chen | 7507445 | 2019-09-21 21:50:27 +0800 | [diff] [blame] | 1298 | if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >= |
Jiaxun Yang | 0cf2ea1 | 2020-04-22 22:43:44 +0800 | [diff] [blame] | 1299 | (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0) || |
| 1300 | (c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R) |
Huacai Chen | 1e820da3 | 2016-03-03 09:45:13 +0800 | [diff] [blame] | 1301 | c->options |= MIPS_CPU_PREFETCH; |
Huacai Chen | c579d31 | 2014-03-21 18:44:00 +0800 | [diff] [blame] | 1302 | break; |
| 1303 | |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 1304 | case CPU_CAVIUM_OCTEON3: |
| 1305 | /* For now lie about the number of ways. */ |
| 1306 | c->icache.linesz = 128; |
| 1307 | c->icache.sets = 16; |
| 1308 | c->icache.ways = 8; |
| 1309 | c->icache.flags |= MIPS_CACHE_VTAG; |
| 1310 | icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; |
| 1311 | |
| 1312 | c->dcache.linesz = 128; |
| 1313 | c->dcache.ways = 8; |
| 1314 | c->dcache.sets = 8; |
| 1315 | dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; |
| 1316 | c->options |= MIPS_CPU_PREFETCH; |
| 1317 | break; |
| 1318 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1319 | default: |
| 1320 | if (!(config & MIPS_CONF_M)) |
| 1321 | panic("Don't know how to probe P-caches on this cpu."); |
| 1322 | |
| 1323 | /* |
| 1324 | * So we seem to be a MIPS32 or MIPS64 CPU |
| 1325 | * So let's probe the I-cache ... |
| 1326 | */ |
| 1327 | config1 = read_c0_config1(); |
| 1328 | |
Markos Chandras | 175cba8 | 2013-09-19 18:18:41 +0100 | [diff] [blame] | 1329 | lsize = (config1 >> 19) & 7; |
| 1330 | |
| 1331 | /* IL == 7 is reserved */ |
| 1332 | if (lsize == 7) |
| 1333 | panic("Invalid icache line size"); |
| 1334 | |
| 1335 | c->icache.linesz = lsize ? 2 << lsize : 0; |
| 1336 | |
Douglas Leung | dc34b05 | 2012-07-19 09:11:13 +0200 | [diff] [blame] | 1337 | c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1338 | c->icache.ways = 1 + ((config1 >> 16) & 7); |
| 1339 | |
| 1340 | icache_size = c->icache.sets * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1341 | c->icache.ways * |
| 1342 | c->icache.linesz; |
Atsushi Nemoto | 3c68da7 | 2006-04-08 01:33:31 +0900 | [diff] [blame] | 1343 | c->icache.waybit = __ffs(icache_size/c->icache.ways); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1344 | |
James Hogan | 4b34bca | 2016-06-15 19:29:59 +0100 | [diff] [blame] | 1345 | if (config & MIPS_CONF_VI) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1346 | c->icache.flags |= MIPS_CACHE_VTAG; |
| 1347 | |
| 1348 | /* |
| 1349 | * Now probe the MIPS32 / MIPS64 data cache. |
| 1350 | */ |
| 1351 | c->dcache.flags = 0; |
| 1352 | |
Markos Chandras | 175cba8 | 2013-09-19 18:18:41 +0100 | [diff] [blame] | 1353 | lsize = (config1 >> 10) & 7; |
| 1354 | |
| 1355 | /* DL == 7 is reserved */ |
| 1356 | if (lsize == 7) |
| 1357 | panic("Invalid dcache line size"); |
| 1358 | |
| 1359 | c->dcache.linesz = lsize ? 2 << lsize : 0; |
| 1360 | |
Douglas Leung | dc34b05 | 2012-07-19 09:11:13 +0200 | [diff] [blame] | 1361 | c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1362 | c->dcache.ways = 1 + ((config1 >> 7) & 7); |
| 1363 | |
| 1364 | dcache_size = c->dcache.sets * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1365 | c->dcache.ways * |
| 1366 | c->dcache.linesz; |
Atsushi Nemoto | 3c68da7 | 2006-04-08 01:33:31 +0900 | [diff] [blame] | 1367 | c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1368 | |
| 1369 | c->options |= MIPS_CPU_PREFETCH; |
| 1370 | break; |
| 1371 | } |
| 1372 | |
| 1373 | /* |
| 1374 | * Processor configuration sanity check for the R4000SC erratum |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1375 | * #5. With page sizes larger than 32kB there is no possibility |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1376 | * to get a VCE exception anymore so we don't care about this |
| 1377 | * misconfiguration. The case is rather theoretical anyway; |
| 1378 | * presumably no vendor is shipping his hardware in the "bad" |
| 1379 | * configuration. |
| 1380 | */ |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1381 | if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 && |
| 1382 | (prid & PRID_REV_MASK) < PRID_REV_R4400 && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1383 | !(config & CONF_SC) && c->icache.linesz != 16 && |
| 1384 | PAGE_SIZE <= 0x8000) |
| 1385 | panic("Improper R4000SC processor configuration detected"); |
| 1386 | |
| 1387 | /* compute a couple of other cache variables */ |
| 1388 | c->icache.waysize = icache_size / c->icache.ways; |
| 1389 | c->dcache.waysize = dcache_size / c->dcache.ways; |
| 1390 | |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 1391 | c->icache.sets = c->icache.linesz ? |
| 1392 | icache_size / (c->icache.linesz * c->icache.ways) : 0; |
| 1393 | c->dcache.sets = c->dcache.linesz ? |
| 1394 | dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1395 | |
| 1396 | /* |
Joshua Kinard | 3057739 | 2015-01-21 07:59:45 -0500 | [diff] [blame] | 1397 | * R1x000 P-caches are odd in a positive way. They're 32kB 2-way |
| 1398 | * virtually indexed so normally would suffer from aliases. So |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1399 | * normally they'd suffer from aliases but magic in the hardware deals |
| 1400 | * with that for us so we don't need to take care ourselves. |
| 1401 | */ |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 1402 | switch (current_cpu_type()) { |
Ralf Baechle | a95970f | 2005-02-07 21:41:32 +0000 | [diff] [blame] | 1403 | case CPU_20KC: |
Ralf Baechle | 505403b | 2005-02-07 21:53:39 +0000 | [diff] [blame] | 1404 | case CPU_25KF: |
Paul Burton | 819da1e | 2016-08-19 18:13:34 +0100 | [diff] [blame] | 1405 | case CPU_I6400: |
Paul Burton | 859aeb1 | 2017-06-02 12:39:04 -0700 | [diff] [blame] | 1406 | case CPU_I6500: |
Ralf Baechle | 641e97f | 2007-10-11 23:46:05 +0100 | [diff] [blame] | 1407 | case CPU_SB1: |
| 1408 | case CPU_SB1A: |
Jayachandran C | efa0f81 | 2011-05-07 01:36:21 +0530 | [diff] [blame] | 1409 | case CPU_XLR: |
Atsushi Nemoto | de62893 | 2006-03-13 18:23:03 +0900 | [diff] [blame] | 1410 | c->dcache.flags |= MIPS_CACHE_PINDEX; |
Ralf Baechle | 641e97f | 2007-10-11 23:46:05 +0100 | [diff] [blame] | 1411 | break; |
| 1412 | |
Ralf Baechle | d1e344e | 2005-02-04 15:51:26 +0000 | [diff] [blame] | 1413 | case CPU_R10000: |
| 1414 | case CPU_R12000: |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 1415 | case CPU_R14000: |
Joshua Kinard | 3057739 | 2015-01-21 07:59:45 -0500 | [diff] [blame] | 1416 | case CPU_R16000: |
Ralf Baechle | d1e344e | 2005-02-04 15:51:26 +0000 | [diff] [blame] | 1417 | break; |
Ralf Baechle | 641e97f | 2007-10-11 23:46:05 +0100 | [diff] [blame] | 1418 | |
Maciej W. Rozycki | bf4aac0 | 2014-06-28 23:28:08 +0100 | [diff] [blame] | 1419 | case CPU_74K: |
| 1420 | case CPU_1074K: |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 1421 | has_74k_erratum = alias_74k_erratum(c); |
Liangliang Huang | c9b0299 | 2020-05-04 16:51:29 +0800 | [diff] [blame] | 1422 | fallthrough; |
Steven J. Hill | 113c62d | 2012-07-06 23:56:00 +0200 | [diff] [blame] | 1423 | case CPU_M14KC: |
Steven J. Hill | f8fa481 | 2012-12-07 03:51:35 +0000 | [diff] [blame] | 1424 | case CPU_M14KEC: |
Ralf Baechle | d1e344e | 2005-02-04 15:51:26 +0000 | [diff] [blame] | 1425 | case CPU_24K: |
Nigel Stephens | 98a41de | 2006-04-27 15:50:32 +0100 | [diff] [blame] | 1426 | case CPU_34K: |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 1427 | case CPU_1004K: |
Leonid Yegoshin | 26ab96d | 2013-11-27 10:07:53 +0000 | [diff] [blame] | 1428 | case CPU_INTERAPTIV: |
James Hogan | aced4cb | 2014-01-22 16:19:38 +0000 | [diff] [blame] | 1429 | case CPU_P5600: |
Leonid Yegoshin | 708ac4b | 2013-11-14 16:12:27 +0000 | [diff] [blame] | 1430 | case CPU_PROAPTIV: |
Leonid Yegoshin | f36c472 | 2014-03-04 13:34:43 +0000 | [diff] [blame] | 1431 | case CPU_M5150: |
Leonid Yegoshin | 4695089 | 2014-11-24 12:59:01 +0000 | [diff] [blame] | 1432 | case CPU_QEMU_GENERIC: |
Paul Burton | 1091bfa | 2016-02-03 03:26:38 +0000 | [diff] [blame] | 1433 | case CPU_P6600: |
Paul Burton | 1dbf6a8 | 2016-02-03 16:17:29 +0000 | [diff] [blame] | 1434 | case CPU_M6250: |
Markos Chandras | 02dc6bf | 2014-01-30 17:21:29 +0000 | [diff] [blame] | 1435 | if (!(read_c0_config7() & MIPS_CONF7_IAR) && |
| 1436 | (c->icache.waysize > PAGE_SIZE)) |
| 1437 | c->icache.flags |= MIPS_CACHE_ALIASES; |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 1438 | if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) { |
Markos Chandras | 02dc6bf | 2014-01-30 17:21:29 +0000 | [diff] [blame] | 1439 | /* |
| 1440 | * Effectively physically indexed dcache, |
| 1441 | * thus no virtual aliases. |
| 1442 | */ |
Ralf Baechle | beab375 | 2006-06-19 21:56:25 +0100 | [diff] [blame] | 1443 | c->dcache.flags |= MIPS_CACHE_PINDEX; |
| 1444 | break; |
| 1445 | } |
Liangliang Huang | c9b0299 | 2020-05-04 16:51:29 +0800 | [diff] [blame] | 1446 | fallthrough; |
Ralf Baechle | d1e344e | 2005-02-04 15:51:26 +0000 | [diff] [blame] | 1447 | default: |
Maciej W. Rozycki | e2e7f29 | 2014-11-16 01:02:29 +0000 | [diff] [blame] | 1448 | if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE) |
Ralf Baechle | beab375 | 2006-06-19 21:56:25 +0100 | [diff] [blame] | 1449 | c->dcache.flags |= MIPS_CACHE_ALIASES; |
Ralf Baechle | d1e344e | 2005-02-04 15:51:26 +0000 | [diff] [blame] | 1450 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1451 | |
Paul Burton | d66f99b | 2016-08-19 18:13:35 +0100 | [diff] [blame] | 1452 | /* Physically indexed caches don't suffer from virtual aliasing */ |
| 1453 | if (c->dcache.flags & MIPS_CACHE_PINDEX) |
| 1454 | c->dcache.flags &= ~MIPS_CACHE_ALIASES; |
| 1455 | |
Paul Burton | d1c5872 | 2017-06-02 15:17:25 -0700 | [diff] [blame] | 1456 | /* |
| 1457 | * In systems with CM the icache fills from L2 or closer caches, and |
| 1458 | * thus sees remote stores without needing to write them back any |
| 1459 | * further than that. |
| 1460 | */ |
| 1461 | if (mips_cm_present()) |
| 1462 | c->icache.flags |= MIPS_IC_SNOOPS_REMOTE; |
| 1463 | |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 1464 | switch (current_cpu_type()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1465 | case CPU_20KC: |
| 1466 | /* |
| 1467 | * Some older 20Kc chips doesn't have the 'VI' bit in |
| 1468 | * the config register. |
| 1469 | */ |
| 1470 | c->icache.flags |= MIPS_CACHE_VTAG; |
| 1471 | break; |
| 1472 | |
Manuel Lauss | 270717a | 2009-03-25 17:49:28 +0100 | [diff] [blame] | 1473 | case CPU_ALCHEMY: |
James Hogan | 47f2ac5 | 2016-01-22 10:58:26 +0000 | [diff] [blame] | 1474 | case CPU_I6400: |
Paul Burton | 859aeb1 | 2017-06-02 12:39:04 -0700 | [diff] [blame] | 1475 | case CPU_I6500: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1476 | c->icache.flags |= MIPS_CACHE_IC_F_DC; |
| 1477 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1478 | |
Florian Fainelli | c130d2f | 2016-04-04 10:55:34 -0700 | [diff] [blame] | 1479 | case CPU_BMIPS5000: |
| 1480 | c->icache.flags |= MIPS_CACHE_IC_F_DC; |
Florian Fainelli | 73c4ca047 | 2016-04-04 10:55:35 -0700 | [diff] [blame] | 1481 | /* Cache aliases are handled in hardware; allow HIGHMEM */ |
| 1482 | c->dcache.flags &= ~MIPS_CACHE_ALIASES; |
Florian Fainelli | c130d2f | 2016-04-04 10:55:34 -0700 | [diff] [blame] | 1483 | break; |
| 1484 | |
Jiaxun Yang | 268a2d6 | 2019-10-20 22:43:13 +0800 | [diff] [blame] | 1485 | case CPU_LOONGSON2EF: |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 1486 | /* |
| 1487 | * LOONGSON2 has 4 way icache, but when using indexed cache op, |
| 1488 | * one op will act on all 4 ways |
| 1489 | */ |
| 1490 | c->icache.ways = 1; |
| 1491 | } |
Fuxin Zhang | 2a21c73 | 2007-06-06 14:52:43 +0800 | [diff] [blame] | 1492 | |
Oleksij Rempel | bea176f | 2020-02-28 06:52:38 +0100 | [diff] [blame] | 1493 | pr_info("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", |
| 1494 | icache_size >> 10, |
| 1495 | c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", |
| 1496 | way_string[c->icache.ways], c->icache.linesz); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1497 | |
Oleksij Rempel | bea176f | 2020-02-28 06:52:38 +0100 | [diff] [blame] | 1498 | pr_info("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", |
| 1499 | dcache_size >> 10, way_string[c->dcache.ways], |
| 1500 | (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", |
| 1501 | (c->dcache.flags & MIPS_CACHE_ALIASES) ? |
Ralf Baechle | 64bfca5 | 2007-10-15 16:35:45 +0100 | [diff] [blame] | 1502 | "cache aliases" : "no aliases", |
Oleksij Rempel | bea176f | 2020-02-28 06:52:38 +0100 | [diff] [blame] | 1503 | c->dcache.linesz); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1504 | } |
| 1505 | |
Huacai Chen | b2edcfc | 2016-03-03 09:45:09 +0800 | [diff] [blame] | 1506 | static void probe_vcache(void) |
| 1507 | { |
| 1508 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 1509 | unsigned int config2, lsize; |
| 1510 | |
Jiaxun Yang | 268a2d6 | 2019-10-20 22:43:13 +0800 | [diff] [blame] | 1511 | if (current_cpu_type() != CPU_LOONGSON64) |
Huacai Chen | b2edcfc | 2016-03-03 09:45:09 +0800 | [diff] [blame] | 1512 | return; |
| 1513 | |
| 1514 | config2 = read_c0_config2(); |
| 1515 | if ((lsize = ((config2 >> 20) & 15))) |
| 1516 | c->vcache.linesz = 2 << lsize; |
| 1517 | else |
| 1518 | c->vcache.linesz = lsize; |
| 1519 | |
| 1520 | c->vcache.sets = 64 << ((config2 >> 24) & 15); |
| 1521 | c->vcache.ways = 1 + ((config2 >> 16) & 15); |
| 1522 | |
| 1523 | vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz; |
| 1524 | |
| 1525 | c->vcache.waybit = 0; |
Huacai Chen | 0be032c | 2017-03-16 21:00:29 +0800 | [diff] [blame] | 1526 | c->vcache.waysize = vcache_size / c->vcache.ways; |
Huacai Chen | b2edcfc | 2016-03-03 09:45:09 +0800 | [diff] [blame] | 1527 | |
| 1528 | pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n", |
| 1529 | vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz); |
| 1530 | } |
| 1531 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1532 | /* |
| 1533 | * If you even _breathe_ on this function, look at the gcc output and make sure |
| 1534 | * it does not pop things on and off the stack for the cache sizing loop that |
| 1535 | * executes in KSEG1 space or else you will crash and burn badly. You have |
| 1536 | * been warned. |
| 1537 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1538 | static int probe_scache(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1539 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1540 | unsigned long flags, addr, begin, end, pow2; |
| 1541 | unsigned int config = read_c0_config(); |
| 1542 | struct cpuinfo_mips *c = ¤t_cpu_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1543 | |
| 1544 | if (config & CONF_SC) |
| 1545 | return 0; |
| 1546 | |
Ralf Baechle | e001e52 | 2007-07-28 12:45:47 +0100 | [diff] [blame] | 1547 | begin = (unsigned long) &_stext; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1548 | begin &= ~((4 * 1024 * 1024) - 1); |
| 1549 | end = begin + (4 * 1024 * 1024); |
| 1550 | |
| 1551 | /* |
| 1552 | * This is such a bitch, you'd think they would make it easy to do |
| 1553 | * this. Away you daemons of stupidity! |
| 1554 | */ |
| 1555 | local_irq_save(flags); |
| 1556 | |
| 1557 | /* Fill each size-multiple cache line with a valid tag. */ |
| 1558 | pow2 = (64 * 1024); |
| 1559 | for (addr = begin; addr < end; addr = (begin + pow2)) { |
| 1560 | unsigned long *p = (unsigned long *) addr; |
| 1561 | __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ |
| 1562 | pow2 <<= 1; |
| 1563 | } |
| 1564 | |
| 1565 | /* Load first line with zero (therefore invalid) tag. */ |
| 1566 | write_c0_taglo(0); |
| 1567 | write_c0_taghi(0); |
| 1568 | __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ |
| 1569 | cache_op(Index_Store_Tag_I, begin); |
| 1570 | cache_op(Index_Store_Tag_D, begin); |
| 1571 | cache_op(Index_Store_Tag_SD, begin); |
| 1572 | |
| 1573 | /* Now search for the wrap around point. */ |
| 1574 | pow2 = (128 * 1024); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1575 | for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { |
| 1576 | cache_op(Index_Load_Tag_SD, addr); |
| 1577 | __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ |
| 1578 | if (!read_c0_taglo()) |
| 1579 | break; |
| 1580 | pow2 <<= 1; |
| 1581 | } |
| 1582 | local_irq_restore(flags); |
| 1583 | addr -= begin; |
| 1584 | |
| 1585 | scache_size = addr; |
| 1586 | c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); |
| 1587 | c->scache.ways = 1; |
Joshua Kinard | 755af33 | 2015-06-02 16:55:22 -0400 | [diff] [blame] | 1588 | c->scache.waybit = 0; /* does not matter */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1589 | |
| 1590 | return 1; |
| 1591 | } |
| 1592 | |
Fuxin Zhang | 2a21c73 | 2007-06-06 14:52:43 +0800 | [diff] [blame] | 1593 | static void __init loongson2_sc_init(void) |
| 1594 | { |
| 1595 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 1596 | |
| 1597 | scache_size = 512*1024; |
| 1598 | c->scache.linesz = 32; |
| 1599 | c->scache.ways = 4; |
| 1600 | c->scache.waybit = 0; |
| 1601 | c->scache.waysize = scache_size / (c->scache.ways); |
| 1602 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); |
| 1603 | pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", |
| 1604 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); |
| 1605 | |
| 1606 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; |
| 1607 | } |
Fuxin Zhang | 2a21c73 | 2007-06-06 14:52:43 +0800 | [diff] [blame] | 1608 | |
Huacai Chen | c579d31 | 2014-03-21 18:44:00 +0800 | [diff] [blame] | 1609 | static void __init loongson3_sc_init(void) |
| 1610 | { |
| 1611 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 1612 | unsigned int config2, lsize; |
| 1613 | |
| 1614 | config2 = read_c0_config2(); |
| 1615 | lsize = (config2 >> 4) & 15; |
| 1616 | if (lsize) |
| 1617 | c->scache.linesz = 2 << lsize; |
| 1618 | else |
| 1619 | c->scache.linesz = 0; |
| 1620 | c->scache.sets = 64 << ((config2 >> 8) & 15); |
| 1621 | c->scache.ways = 1 + (config2 & 15); |
| 1622 | |
| 1623 | scache_size = c->scache.sets * |
| 1624 | c->scache.ways * |
| 1625 | c->scache.linesz; |
Jiaxun Yang | 0cf2ea1 | 2020-04-22 22:43:44 +0800 | [diff] [blame] | 1626 | |
| 1627 | /* Loongson-3 has 4-Scache banks, while Loongson-2K have only 2 banks */ |
| 1628 | if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R) |
| 1629 | scache_size *= 2; |
| 1630 | else |
| 1631 | scache_size *= 4; |
| 1632 | |
Huacai Chen | c579d31 | 2014-03-21 18:44:00 +0800 | [diff] [blame] | 1633 | c->scache.waybit = 0; |
Huacai Chen | 0be032c | 2017-03-16 21:00:29 +0800 | [diff] [blame] | 1634 | c->scache.waysize = scache_size / c->scache.ways; |
Huacai Chen | c579d31 | 2014-03-21 18:44:00 +0800 | [diff] [blame] | 1635 | pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", |
| 1636 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); |
| 1637 | if (scache_size) |
| 1638 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; |
| 1639 | return; |
| 1640 | } |
| 1641 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1642 | extern int r5k_sc_init(void); |
| 1643 | extern int rm7k_sc_init(void); |
Chris Dearman | 9318c51 | 2006-06-20 17:15:20 +0100 | [diff] [blame] | 1644 | extern int mips_sc_init(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1645 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1646 | static void setup_scache(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1647 | { |
| 1648 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 1649 | unsigned int config = read_c0_config(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1650 | int sc_present = 0; |
| 1651 | |
| 1652 | /* |
| 1653 | * Do the probing thing on R4000SC and R4400SC processors. Other |
| 1654 | * processors don't have a S-cache that would be relevant to the |
Joe Perches | 603e82e | 2008-02-03 16:54:53 +0200 | [diff] [blame] | 1655 | * Linux memory management. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1656 | */ |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 1657 | switch (current_cpu_type()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1658 | case CPU_R4000SC: |
| 1659 | case CPU_R4000MC: |
| 1660 | case CPU_R4400SC: |
| 1661 | case CPU_R4400MC: |
Thiemo Seufer | ba5187d | 2005-04-25 16:36:23 +0000 | [diff] [blame] | 1662 | sc_present = run_uncached(probe_scache); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1663 | if (sc_present) |
| 1664 | c->options |= MIPS_CPU_CACHE_CDEX_S; |
| 1665 | break; |
| 1666 | |
| 1667 | case CPU_R10000: |
| 1668 | case CPU_R12000: |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 1669 | case CPU_R14000: |
Joshua Kinard | 3057739 | 2015-01-21 07:59:45 -0500 | [diff] [blame] | 1670 | case CPU_R16000: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1671 | scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); |
| 1672 | c->scache.linesz = 64 << ((config >> 13) & 1); |
| 1673 | c->scache.ways = 2; |
| 1674 | c->scache.waybit= 0; |
| 1675 | sc_present = 1; |
| 1676 | break; |
| 1677 | |
| 1678 | case CPU_R5000: |
| 1679 | case CPU_NEVADA: |
| 1680 | #ifdef CONFIG_R5000_CPU_SCACHE |
| 1681 | r5k_sc_init(); |
| 1682 | #endif |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1683 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1684 | |
| 1685 | case CPU_RM7000: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1686 | #ifdef CONFIG_RM7000_CPU_SCACHE |
| 1687 | rm7k_sc_init(); |
| 1688 | #endif |
| 1689 | return; |
| 1690 | |
Jiaxun Yang | 268a2d6 | 2019-10-20 22:43:13 +0800 | [diff] [blame] | 1691 | case CPU_LOONGSON2EF: |
Fuxin Zhang | 2a21c73 | 2007-06-06 14:52:43 +0800 | [diff] [blame] | 1692 | loongson2_sc_init(); |
| 1693 | return; |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 1694 | |
Jiaxun Yang | 268a2d6 | 2019-10-20 22:43:13 +0800 | [diff] [blame] | 1695 | case CPU_LOONGSON64: |
Huacai Chen | c579d31 | 2014-03-21 18:44:00 +0800 | [diff] [blame] | 1696 | loongson3_sc_init(); |
| 1697 | return; |
| 1698 | |
David Daney | 18a8cd6 | 2014-05-28 23:52:09 +0200 | [diff] [blame] | 1699 | case CPU_CAVIUM_OCTEON3: |
Jayachandran C | a3d4fb2 | 2011-11-16 00:21:20 +0000 | [diff] [blame] | 1700 | case CPU_XLP: |
| 1701 | /* don't need to worry about L2, fully coherent */ |
| 1702 | return; |
Fuxin Zhang | 2a21c73 | 2007-06-06 14:52:43 +0800 | [diff] [blame] | 1703 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1704 | default: |
Serge Semin | ab7c01f | 2020-05-21 17:07:14 +0300 | [diff] [blame] | 1705 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | |
| 1706 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | |
| 1707 | MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 | |
| 1708 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { |
Chris Dearman | 9318c51 | 2006-06-20 17:15:20 +0100 | [diff] [blame] | 1709 | #ifdef CONFIG_MIPS_CPU_SCACHE |
| 1710 | if (mips_sc_init ()) { |
| 1711 | scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; |
| 1712 | printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", |
| 1713 | scache_size >> 10, |
| 1714 | way_string[c->scache.ways], c->scache.linesz); |
| 1715 | } |
| 1716 | #else |
| 1717 | if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) |
| 1718 | panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); |
| 1719 | #endif |
| 1720 | return; |
| 1721 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1722 | sc_present = 0; |
| 1723 | } |
| 1724 | |
| 1725 | if (!sc_present) |
| 1726 | return; |
| 1727 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1728 | /* compute a couple of other cache variables */ |
| 1729 | c->scache.waysize = scache_size / c->scache.ways; |
| 1730 | |
| 1731 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); |
| 1732 | |
| 1733 | printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", |
| 1734 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); |
| 1735 | |
Ralf Baechle | fc5d2d2 | 2006-07-06 13:04:01 +0100 | [diff] [blame] | 1736 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1737 | } |
| 1738 | |
Sergei Shtylyov | 9370b35 | 2006-05-26 19:44:54 +0400 | [diff] [blame] | 1739 | void au1x00_fixup_config_od(void) |
| 1740 | { |
| 1741 | /* |
| 1742 | * c0_config.od (bit 19) was write only (and read as 0) |
| 1743 | * on the early revisions of Alchemy SOCs. It disables the bus |
| 1744 | * transaction overlapping and needs to be set to fix various errata. |
| 1745 | */ |
| 1746 | switch (read_c0_prid()) { |
| 1747 | case 0x00030100: /* Au1000 DA */ |
| 1748 | case 0x00030201: /* Au1000 HA */ |
| 1749 | case 0x00030202: /* Au1000 HB */ |
| 1750 | case 0x01030200: /* Au1500 AB */ |
| 1751 | /* |
| 1752 | * Au1100 errata actually keeps silence about this bit, so we set it |
| 1753 | * just in case for those revisions that require it to be set according |
Manuel Lauss | 270717a | 2009-03-25 17:49:28 +0100 | [diff] [blame] | 1754 | * to the (now gone) cpu table. |
Sergei Shtylyov | 9370b35 | 2006-05-26 19:44:54 +0400 | [diff] [blame] | 1755 | */ |
| 1756 | case 0x02030200: /* Au1100 AB */ |
| 1757 | case 0x02030201: /* Au1100 BA */ |
| 1758 | case 0x02030202: /* Au1100 BC */ |
| 1759 | set_c0_config(1 << 19); |
| 1760 | break; |
| 1761 | } |
| 1762 | } |
| 1763 | |
Ralf Baechle | 89052bd | 2008-06-12 17:26:02 +0100 | [diff] [blame] | 1764 | /* CP0 hazard avoidance. */ |
| 1765 | #define NXP_BARRIER() \ |
| 1766 | __asm__ __volatile__( \ |
| 1767 | ".set noreorder\n\t" \ |
| 1768 | "nop; nop; nop; nop; nop; nop;\n\t" \ |
| 1769 | ".set reorder\n\t") |
| 1770 | |
| 1771 | static void nxp_pr4450_fixup_config(void) |
| 1772 | { |
| 1773 | unsigned long config0; |
| 1774 | |
| 1775 | config0 = read_c0_config(); |
| 1776 | |
| 1777 | /* clear all three cache coherency fields */ |
| 1778 | config0 &= ~(0x7 | (7 << 25) | (7 << 28)); |
| 1779 | config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) | |
| 1780 | ((_page_cachable_default >> _CACHE_SHIFT) << 25) | |
| 1781 | ((_page_cachable_default >> _CACHE_SHIFT) << 28)); |
| 1782 | write_c0_config(config0); |
| 1783 | NXP_BARRIER(); |
| 1784 | } |
| 1785 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1786 | static int cca = -1; |
Chris Dearman | 3513369 | 2007-09-19 00:58:24 +0100 | [diff] [blame] | 1787 | |
| 1788 | static int __init cca_setup(char *str) |
| 1789 | { |
| 1790 | get_option(&str, &cca); |
| 1791 | |
Shane McDonald | b5b64f2 | 2012-06-14 02:26:40 +0000 | [diff] [blame] | 1792 | return 0; |
Chris Dearman | 3513369 | 2007-09-19 00:58:24 +0100 | [diff] [blame] | 1793 | } |
| 1794 | |
Shane McDonald | b5b64f2 | 2012-06-14 02:26:40 +0000 | [diff] [blame] | 1795 | early_param("cca", cca_setup); |
Chris Dearman | 3513369 | 2007-09-19 00:58:24 +0100 | [diff] [blame] | 1796 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1797 | static void coherency_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1798 | { |
Chris Dearman | 3513369 | 2007-09-19 00:58:24 +0100 | [diff] [blame] | 1799 | if (cca < 0 || cca > 7) |
| 1800 | cca = read_c0_config() & CONF_CM_CMASK; |
| 1801 | _page_cachable_default = cca << _CACHE_SHIFT; |
| 1802 | |
| 1803 | pr_debug("Using cache attribute %d\n", cca); |
| 1804 | change_c0_config(CONF_CM_CMASK, cca); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1805 | |
| 1806 | /* |
| 1807 | * c0_status.cu=0 specifies that updates by the sc instruction use |
| 1808 | * the coherency mode specified by the TLB; 1 means cachable |
| 1809 | * coherent update on write will be used. Not all processors have |
| 1810 | * this bit and; some wire it to zero, others like Toshiba had the |
| 1811 | * silly idea of putting something else there ... |
| 1812 | */ |
Ralf Baechle | 10cc352 | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1813 | switch (current_cpu_type()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1814 | case CPU_R4000PC: |
| 1815 | case CPU_R4000SC: |
| 1816 | case CPU_R4000MC: |
| 1817 | case CPU_R4400PC: |
| 1818 | case CPU_R4400SC: |
| 1819 | case CPU_R4400MC: |
| 1820 | clear_c0_config(CONF_CU); |
| 1821 | break; |
Sergei Shtylyov | 9370b35 | 2006-05-26 19:44:54 +0400 | [diff] [blame] | 1822 | /* |
Ralf Baechle | df586d5 | 2006-08-01 23:42:30 +0100 | [diff] [blame] | 1823 | * We need to catch the early Alchemy SOCs with |
Manuel Lauss | 270717a | 2009-03-25 17:49:28 +0100 | [diff] [blame] | 1824 | * the write-only co_config.od bit and set it back to one on: |
| 1825 | * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB |
Sergei Shtylyov | 9370b35 | 2006-05-26 19:44:54 +0400 | [diff] [blame] | 1826 | */ |
Manuel Lauss | 270717a | 2009-03-25 17:49:28 +0100 | [diff] [blame] | 1827 | case CPU_ALCHEMY: |
Sergei Shtylyov | 9370b35 | 2006-05-26 19:44:54 +0400 | [diff] [blame] | 1828 | au1x00_fixup_config_od(); |
| 1829 | break; |
Ralf Baechle | 89052bd | 2008-06-12 17:26:02 +0100 | [diff] [blame] | 1830 | |
| 1831 | case PRID_IMP_PR4450: |
| 1832 | nxp_pr4450_fixup_config(); |
| 1833 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1834 | } |
| 1835 | } |
| 1836 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1837 | static void r4k_cache_error_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1838 | { |
Ralf Baechle | 641e97f | 2007-10-11 23:46:05 +0100 | [diff] [blame] | 1839 | extern char __weak except_vec2_generic; |
| 1840 | extern char __weak except_vec2_sb1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1841 | |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 1842 | switch (current_cpu_type()) { |
Ralf Baechle | 641e97f | 2007-10-11 23:46:05 +0100 | [diff] [blame] | 1843 | case CPU_SB1: |
| 1844 | case CPU_SB1A: |
| 1845 | set_uncached_handler(0x100, &except_vec2_sb1, 0x80); |
| 1846 | break; |
| 1847 | |
| 1848 | default: |
| 1849 | set_uncached_handler(0x100, &except_vec2_generic, 0x80); |
| 1850 | break; |
| 1851 | } |
David Daney | 9cd9669b | 2012-05-15 00:04:49 -0700 | [diff] [blame] | 1852 | } |
| 1853 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1854 | void r4k_cache_init(void) |
David Daney | 9cd9669b | 2012-05-15 00:04:49 -0700 | [diff] [blame] | 1855 | { |
| 1856 | extern void build_clear_page(void); |
| 1857 | extern void build_copy_page(void); |
| 1858 | struct cpuinfo_mips *c = ¤t_cpu_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1859 | |
| 1860 | probe_pcache(); |
Huacai Chen | b2edcfc | 2016-03-03 09:45:09 +0800 | [diff] [blame] | 1861 | probe_vcache(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1862 | setup_scache(); |
| 1863 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1864 | r4k_blast_dcache_page_setup(); |
| 1865 | r4k_blast_dcache_page_indexed_setup(); |
| 1866 | r4k_blast_dcache_setup(); |
| 1867 | r4k_blast_icache_page_setup(); |
| 1868 | r4k_blast_icache_page_indexed_setup(); |
| 1869 | r4k_blast_icache_setup(); |
| 1870 | r4k_blast_scache_page_setup(); |
| 1871 | r4k_blast_scache_page_indexed_setup(); |
| 1872 | r4k_blast_scache_setup(); |
Huacai Chen | bb53fdf | 2018-11-15 15:53:53 +0800 | [diff] [blame] | 1873 | r4k_blast_scache_node_setup(); |
Leonid Yegoshin | 4caa906 | 2014-01-15 14:47:28 +0000 | [diff] [blame] | 1874 | #ifdef CONFIG_EVA |
| 1875 | r4k_blast_dcache_user_page_setup(); |
| 1876 | r4k_blast_icache_user_page_setup(); |
| 1877 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1878 | |
| 1879 | /* |
| 1880 | * Some MIPS32 and MIPS64 processors have physically indexed caches. |
| 1881 | * This code supports virtually indexed processors and will be |
| 1882 | * unnecessarily inefficient on physically indexed processors. |
| 1883 | */ |
Leonid Yegoshin | cb80b2a | 2015-11-19 17:38:21 -0800 | [diff] [blame] | 1884 | if (c->dcache.linesz && cpu_has_dc_aliases) |
Chris Dearman | 73f4035 | 2006-06-20 18:06:52 +0100 | [diff] [blame] | 1885 | shm_align_mask = max_t( unsigned long, |
| 1886 | c->dcache.sets * c->dcache.linesz - 1, |
| 1887 | PAGE_SIZE - 1); |
| 1888 | else |
| 1889 | shm_align_mask = PAGE_SIZE-1; |
Ralf Baechle | 9c5a3d7 | 2008-04-05 15:13:23 +0100 | [diff] [blame] | 1890 | |
| 1891 | __flush_cache_vmap = r4k__flush_cache_vmap; |
| 1892 | __flush_cache_vunmap = r4k__flush_cache_vunmap; |
| 1893 | |
Ralf Baechle | db813fe | 2007-09-27 18:26:43 +0100 | [diff] [blame] | 1894 | flush_cache_all = cache_noop; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1895 | __flush_cache_all = r4k___flush_cache_all; |
| 1896 | flush_cache_mm = r4k_flush_cache_mm; |
| 1897 | flush_cache_page = r4k_flush_cache_page; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1898 | flush_cache_range = r4k_flush_cache_range; |
| 1899 | |
Ralf Baechle | d9cdc901 | 2011-06-17 16:20:28 +0100 | [diff] [blame] | 1900 | __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range; |
| 1901 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1902 | flush_icache_all = r4k_flush_icache_all; |
Ralf Baechle | 7e3bfc7 | 2006-04-05 20:42:04 +0100 | [diff] [blame] | 1903 | local_flush_data_cache_page = local_r4k_flush_data_cache_page; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1904 | flush_data_cache_page = r4k_flush_data_cache_page; |
| 1905 | flush_icache_range = r4k_flush_icache_range; |
Thomas Bogendoerfer | e0cee3e | 2008-08-04 20:53:57 +0200 | [diff] [blame] | 1906 | local_flush_icache_range = local_r4k_flush_icache_range; |
James Hogan | b2ff717 | 2016-09-01 17:30:15 +0100 | [diff] [blame] | 1907 | __flush_icache_user_range = r4k_flush_icache_user_range; |
| 1908 | __local_flush_icache_user_range = local_r4k_flush_icache_user_range; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1909 | |
Christoph Hellwig | 5748e1b | 2018-08-16 16:47:53 +0300 | [diff] [blame] | 1910 | #ifdef CONFIG_DMA_NONCOHERENT |
| 1911 | #ifdef CONFIG_DMA_MAYBE_COHERENT |
| 1912 | if (coherentio == IO_COHERENCE_ENABLED || |
| 1913 | (coherentio == IO_COHERENCE_DEFAULT && hw_coherentio)) { |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 1914 | _dma_cache_wback_inv = (void *)cache_noop; |
| 1915 | _dma_cache_wback = (void *)cache_noop; |
| 1916 | _dma_cache_inv = (void *)cache_noop; |
Christoph Hellwig | 5748e1b | 2018-08-16 16:47:53 +0300 | [diff] [blame] | 1917 | } else |
| 1918 | #endif /* CONFIG_DMA_MAYBE_COHERENT */ |
| 1919 | { |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 1920 | _dma_cache_wback_inv = r4k_dma_cache_wback_inv; |
| 1921 | _dma_cache_wback = r4k_dma_cache_wback_inv; |
| 1922 | _dma_cache_inv = r4k_dma_cache_inv; |
| 1923 | } |
Christoph Hellwig | 5748e1b | 2018-08-16 16:47:53 +0300 | [diff] [blame] | 1924 | #endif /* CONFIG_DMA_NONCOHERENT */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1925 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1926 | build_clear_page(); |
| 1927 | build_copy_page(); |
Steven J. Hill | b6d92b4 | 2013-03-25 13:47:29 -0500 | [diff] [blame] | 1928 | |
| 1929 | /* |
| 1930 | * We want to run CMP kernels on core with and without coherent |
| 1931 | * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether |
| 1932 | * or not to flush caches. |
| 1933 | */ |
Ralf Baechle | 1d40cfc | 2005-07-15 15:23:23 +0000 | [diff] [blame] | 1934 | local_r4k___flush_cache_all(NULL); |
Steven J. Hill | b6d92b4 | 2013-03-25 13:47:29 -0500 | [diff] [blame] | 1935 | |
Ralf Baechle | 1d40cfc | 2005-07-15 15:23:23 +0000 | [diff] [blame] | 1936 | coherency_setup(); |
David Daney | 9cd9669b | 2012-05-15 00:04:49 -0700 | [diff] [blame] | 1937 | board_cache_error_setup = r4k_cache_error_setup; |
Kevin Cernekee | d74b017 | 2014-10-20 21:28:00 -0700 | [diff] [blame] | 1938 | |
| 1939 | /* |
| 1940 | * Per-CPU overrides |
| 1941 | */ |
| 1942 | switch (current_cpu_type()) { |
| 1943 | case CPU_BMIPS4350: |
| 1944 | case CPU_BMIPS4380: |
| 1945 | /* No IPI is needed because all CPUs share the same D$ */ |
| 1946 | flush_data_cache_page = r4k_blast_dcache_page; |
| 1947 | break; |
| 1948 | case CPU_BMIPS5000: |
| 1949 | /* We lose our superpowers if L2 is disabled */ |
| 1950 | if (c->scache.flags & MIPS_CACHE_NOT_PRESENT) |
| 1951 | break; |
| 1952 | |
| 1953 | /* I$ fills from D$ just by emptying the write buffers */ |
| 1954 | flush_cache_page = (void *)b5k_instruction_hazard; |
| 1955 | flush_cache_range = (void *)b5k_instruction_hazard; |
Kevin Cernekee | d74b017 | 2014-10-20 21:28:00 -0700 | [diff] [blame] | 1956 | local_flush_data_cache_page = (void *)b5k_instruction_hazard; |
| 1957 | flush_data_cache_page = (void *)b5k_instruction_hazard; |
| 1958 | flush_icache_range = (void *)b5k_instruction_hazard; |
| 1959 | local_flush_icache_range = (void *)b5k_instruction_hazard; |
| 1960 | |
Kevin Cernekee | d74b017 | 2014-10-20 21:28:00 -0700 | [diff] [blame] | 1961 | |
| 1962 | /* Optimization: an L2 flush implicitly flushes the L1 */ |
| 1963 | current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES; |
| 1964 | break; |
Jiaxun Yang | 268a2d6 | 2019-10-20 22:43:13 +0800 | [diff] [blame] | 1965 | case CPU_LOONGSON64: |
Huacai Chen | 37fbe8f | 2016-03-03 09:45:10 +0800 | [diff] [blame] | 1966 | /* Loongson-3 maintains cache coherency by hardware */ |
| 1967 | __flush_cache_all = cache_noop; |
| 1968 | __flush_cache_vmap = cache_noop; |
| 1969 | __flush_cache_vunmap = cache_noop; |
| 1970 | __flush_kernel_vmap_range = (void *)cache_noop; |
| 1971 | flush_cache_mm = (void *)cache_noop; |
| 1972 | flush_cache_page = (void *)cache_noop; |
| 1973 | flush_cache_range = (void *)cache_noop; |
Huacai Chen | 37fbe8f | 2016-03-03 09:45:10 +0800 | [diff] [blame] | 1974 | flush_icache_all = (void *)cache_noop; |
| 1975 | flush_data_cache_page = (void *)cache_noop; |
| 1976 | local_flush_data_cache_page = (void *)cache_noop; |
| 1977 | break; |
Kevin Cernekee | d74b017 | 2014-10-20 21:28:00 -0700 | [diff] [blame] | 1978 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1979 | } |
James Hogan | 61d7304 | 2014-03-04 10:23:57 +0000 | [diff] [blame] | 1980 | |
| 1981 | static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd, |
| 1982 | void *v) |
| 1983 | { |
| 1984 | switch (cmd) { |
| 1985 | case CPU_PM_ENTER_FAILED: |
| 1986 | case CPU_PM_EXIT: |
| 1987 | coherency_setup(); |
| 1988 | break; |
| 1989 | } |
| 1990 | |
| 1991 | return NOTIFY_OK; |
| 1992 | } |
| 1993 | |
| 1994 | static struct notifier_block r4k_cache_pm_notifier_block = { |
| 1995 | .notifier_call = r4k_cache_pm_notifier, |
| 1996 | }; |
| 1997 | |
| 1998 | int __init r4k_cache_init_pm(void) |
| 1999 | { |
| 2000 | return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block); |
| 2001 | } |
| 2002 | arch_initcall(r4k_cache_init_pm); |