blob: 49569e5666d7accaac99c209b4a3ea25d84e116b [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
Justin P. Mattock79add622011-04-04 14:15:29 -07006 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */
James Hogan61d73042014-03-04 10:23:57 +000010#include <linux/cpu_pm.h>
Ralf Baechlea754f702007-11-03 01:01:37 +000011#include <linux/hardirq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#include <linux/init.h>
Ralf Baechledb813fe2007-09-27 18:26:43 +010013#include <linux/highmem.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/kernel.h>
Ralf Baechle641e97f2007-10-11 23:46:05 +010015#include <linux/linkage.h>
Ralf Baechleff522052013-09-17 12:44:31 +020016#include <linux/preempt.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/sched.h>
Ralf Baechle631330f2009-06-19 14:05:26 +010018#include <linux/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <linux/mm.h>
Paul Gortmakerd9ba5772016-08-21 15:58:14 -040020#include <linux/export.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <linux/bitops.h>
22
23#include <asm/bcache.h>
24#include <asm/bootinfo.h>
Ralf Baechleec74e362005-07-13 11:48:45 +000025#include <asm/cache.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <asm/cacheops.h>
27#include <asm/cpu.h>
28#include <asm/cpu-features.h>
Ralf Baechle69f24d12013-09-17 10:25:47 +020029#include <asm/cpu-type.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070030#include <asm/io.h>
31#include <asm/page.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070032#include <asm/r4kcache.h>
Ralf Baechlee001e522007-07-28 12:45:47 +010033#include <asm/sections.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#include <asm/mmu_context.h>
35#include <asm/war.h>
Thiemo Seuferba5187d2005-04-25 16:36:23 +000036#include <asm/cacheflush.h> /* for run_uncached() */
David Daney9cd9669b2012-05-15 00:04:49 -070037#include <asm/traps.h>
Steven J. Hillb6d92b42013-03-25 13:47:29 -050038#include <asm/dma-coherence.h>
Paul Burtone83f7e02017-08-12 19:49:41 -070039#include <asm/mips-cps.h>
Ralf Baechle7f3f1d02006-05-12 13:20:06 +010040
41/*
James Hogand374d932016-07-13 14:12:50 +010042 * Bits describing what cache ops an SMP callback function may perform.
43 *
44 * R4K_HIT - Virtual user or kernel address based cache operations. The
45 * active_mm must be checked before using user addresses, falling
46 * back to kmap.
47 * R4K_INDEX - Index based cache operations.
48 */
49
50#define R4K_HIT BIT(0)
51#define R4K_INDEX BIT(1)
52
53/**
54 * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
55 * @type: Type of cache operations (R4K_HIT or R4K_INDEX).
56 *
57 * Decides whether a cache op needs to be performed on every core in the system.
James Hogan640511a2016-07-13 14:12:52 +010058 * This may change depending on the @type of cache operation, as well as the set
59 * of online CPUs, so preemption should be disabled by the caller to prevent CPU
60 * hotplug from changing the result.
James Hogand374d932016-07-13 14:12:50 +010061 *
62 * Returns: 1 if the cache operation @type should be done on every core in
63 * the system.
64 * 0 if the cache operation @type is globalized and only needs to
65 * be performed on a simple CPU.
66 */
67static inline bool r4k_op_needs_ipi(unsigned int type)
68{
69 /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */
James Hogan11f76902016-07-13 14:12:56 +010070 if (type == R4K_HIT && mips_cm_present())
James Hogand374d932016-07-13 14:12:50 +010071 return false;
72
73 /*
74 * Hardware doesn't globalize the required cache ops, so SMP calls may
James Hogan640511a2016-07-13 14:12:52 +010075 * be needed, but only if there are foreign CPUs (non-siblings with
76 * separate caches).
James Hogand374d932016-07-13 14:12:50 +010077 */
James Hogan640511a2016-07-13 14:12:52 +010078 /* cpu_foreign_map[] undeclared when !CONFIG_SMP */
79#ifdef CONFIG_SMP
80 return !cpumask_empty(&cpu_foreign_map[0]);
81#else
82 return false;
83#endif
James Hogand374d932016-07-13 14:12:50 +010084}
85
86/*
Ralf Baechle7f3f1d02006-05-12 13:20:06 +010087 * Special Variant of smp_call_function for use by cache functions:
88 *
89 * o No return value
90 * o collapses to normal function call on UP kernels
91 * o collapses to normal function call on systems with a single shared
92 * primary cache.
Ralf Baechlec8c5f3f2010-10-29 19:08:25 +010093 * o doesn't disable interrupts on the local CPU
Ralf Baechle7f3f1d02006-05-12 13:20:06 +010094 */
James Hogand374d932016-07-13 14:12:50 +010095static inline void r4k_on_each_cpu(unsigned int type,
96 void (*func)(void *info), void *info)
Ralf Baechle7f3f1d02006-05-12 13:20:06 +010097{
98 preempt_disable();
James Hogand374d932016-07-13 14:12:50 +010099 if (r4k_op_needs_ipi(type))
James Hogan640511a2016-07-13 14:12:52 +0100100 smp_call_function_many(&cpu_foreign_map[smp_processor_id()],
101 func, info, 1);
Ralf Baechle7f3f1d02006-05-12 13:20:06 +0100102 func(info);
103 preempt_enable();
104}
105
Ralf Baechleec74e362005-07-13 11:48:45 +0000106/*
107 * Must die.
108 */
109static unsigned long icache_size __read_mostly;
110static unsigned long dcache_size __read_mostly;
Huacai Chenb2edcfc2016-03-03 09:45:09 +0800111static unsigned long vcache_size __read_mostly;
Ralf Baechleec74e362005-07-13 11:48:45 +0000112static unsigned long scache_size __read_mostly;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113
114/*
115 * Dummy cache handling routines for machines without boardcaches
116 */
Chris Dearman73f40352006-06-20 18:06:52 +0100117static void cache_noop(void) {}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118
119static struct bcache_ops no_sc_ops = {
Chris Dearman73f40352006-06-20 18:06:52 +0100120 .bc_enable = (void *)cache_noop,
121 .bc_disable = (void *)cache_noop,
122 .bc_wback_inv = (void *)cache_noop,
123 .bc_inv = (void *)cache_noop
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124};
125
126struct bcache_ops *bcops = &no_sc_ops;
127
Thiemo Seufer330cfe02005-09-01 18:33:58 +0000128#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
129#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130
131#define R4600_HIT_CACHEOP_WAR_IMPL \
132do { \
133 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
134 *(volatile unsigned long *)CKSEG1; \
135 if (R4600_V1_HIT_CACHEOP_WAR) \
136 __asm__ __volatile__("nop;nop;nop;nop"); \
137} while (0)
138
139static void (*r4k_blast_dcache_page)(unsigned long addr);
140
141static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
142{
143 R4600_HIT_CACHEOP_WAR_IMPL;
144 blast_dcache32_page(addr);
145}
146
Kevin Cernekee605b7ef2009-04-23 17:36:53 -0700147static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
148{
Kevin Cernekee605b7ef2009-04-23 17:36:53 -0700149 blast_dcache64_page(addr);
150}
151
David Daney18a8cd62014-05-28 23:52:09 +0200152static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
153{
154 blast_dcache128_page(addr);
155}
156
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000157static void r4k_blast_dcache_page_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158{
159 unsigned long dc_lsize = cpu_dcache_line_size();
160
David Daney18a8cd62014-05-28 23:52:09 +0200161 switch (dc_lsize) {
162 case 0:
Chris Dearman73f40352006-06-20 18:06:52 +0100163 r4k_blast_dcache_page = (void *)cache_noop;
David Daney18a8cd62014-05-28 23:52:09 +0200164 break;
165 case 16:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166 r4k_blast_dcache_page = blast_dcache16_page;
David Daney18a8cd62014-05-28 23:52:09 +0200167 break;
168 case 32:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
David Daney18a8cd62014-05-28 23:52:09 +0200170 break;
171 case 64:
Kevin Cernekee605b7ef2009-04-23 17:36:53 -0700172 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
David Daney18a8cd62014-05-28 23:52:09 +0200173 break;
174 case 128:
175 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
176 break;
177 default:
178 break;
179 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180}
181
Leonid Yegoshin4caa9062014-01-15 14:47:28 +0000182#ifndef CONFIG_EVA
183#define r4k_blast_dcache_user_page r4k_blast_dcache_page
184#else
185
186static void (*r4k_blast_dcache_user_page)(unsigned long addr);
187
188static void r4k_blast_dcache_user_page_setup(void)
189{
190 unsigned long dc_lsize = cpu_dcache_line_size();
191
192 if (dc_lsize == 0)
193 r4k_blast_dcache_user_page = (void *)cache_noop;
194 else if (dc_lsize == 16)
195 r4k_blast_dcache_user_page = blast_dcache16_user_page;
196 else if (dc_lsize == 32)
197 r4k_blast_dcache_user_page = blast_dcache32_user_page;
198 else if (dc_lsize == 64)
199 r4k_blast_dcache_user_page = blast_dcache64_user_page;
200}
201
202#endif
203
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
205
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000206static void r4k_blast_dcache_page_indexed_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207{
208 unsigned long dc_lsize = cpu_dcache_line_size();
209
Chris Dearman73f40352006-06-20 18:06:52 +0100210 if (dc_lsize == 0)
211 r4k_blast_dcache_page_indexed = (void *)cache_noop;
212 else if (dc_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
214 else if (dc_lsize == 32)
215 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
Kevin Cernekee605b7ef2009-04-23 17:36:53 -0700216 else if (dc_lsize == 64)
217 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
David Daney18a8cd62014-05-28 23:52:09 +0200218 else if (dc_lsize == 128)
219 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220}
221
Sanjay Lalf2e36562012-11-21 18:34:10 -0800222void (* r4k_blast_dcache)(void);
223EXPORT_SYMBOL(r4k_blast_dcache);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000225static void r4k_blast_dcache_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226{
227 unsigned long dc_lsize = cpu_dcache_line_size();
228
Chris Dearman73f40352006-06-20 18:06:52 +0100229 if (dc_lsize == 0)
230 r4k_blast_dcache = (void *)cache_noop;
231 else if (dc_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232 r4k_blast_dcache = blast_dcache16;
233 else if (dc_lsize == 32)
234 r4k_blast_dcache = blast_dcache32;
Kevin Cernekee605b7ef2009-04-23 17:36:53 -0700235 else if (dc_lsize == 64)
236 r4k_blast_dcache = blast_dcache64;
David Daney18a8cd62014-05-28 23:52:09 +0200237 else if (dc_lsize == 128)
238 r4k_blast_dcache = blast_dcache128;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239}
240
241/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
242#define JUMP_TO_ALIGN(order) \
243 __asm__ __volatile__( \
244 "b\t1f\n\t" \
245 ".align\t" #order "\n\t" \
246 "1:\n\t" \
247 )
248#define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
Ralf Baechle70342282013-01-22 12:59:30 +0100249#define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250
251static inline void blast_r4600_v1_icache32(void)
252{
253 unsigned long flags;
254
255 local_irq_save(flags);
256 blast_icache32();
257 local_irq_restore(flags);
258}
259
260static inline void tx49_blast_icache32(void)
261{
262 unsigned long start = INDEX_BASE;
263 unsigned long end = start + current_cpu_data.icache.waysize;
264 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
265 unsigned long ws_end = current_cpu_data.icache.ways <<
Ralf Baechle70342282013-01-22 12:59:30 +0100266 current_cpu_data.icache.waybit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267 unsigned long ws, addr;
268
269 CACHE32_UNROLL32_ALIGN2;
270 /* I'm in even chunk. blast odd chunks */
Ralf Baechle42a3b4f22005-09-03 15:56:17 -0700271 for (ws = 0; ws < ws_end; ws += ws_inc)
272 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
Paul Burton6baaead2019-10-08 18:22:00 +0000273 cache_unroll(32, kernel_cache, Index_Invalidate_I,
274 addr | ws, 32);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275 CACHE32_UNROLL32_ALIGN;
276 /* I'm in odd chunk. blast even chunks */
Ralf Baechle42a3b4f22005-09-03 15:56:17 -0700277 for (ws = 0; ws < ws_end; ws += ws_inc)
278 for (addr = start; addr < end; addr += 0x400 * 2)
Paul Burton6baaead2019-10-08 18:22:00 +0000279 cache_unroll(32, kernel_cache, Index_Invalidate_I,
280 addr | ws, 32);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281}
282
283static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
284{
285 unsigned long flags;
286
287 local_irq_save(flags);
288 blast_icache32_page_indexed(page);
289 local_irq_restore(flags);
290}
291
292static inline void tx49_blast_icache32_page_indexed(unsigned long page)
293{
Atsushi Nemoto67a3f6de2006-04-04 17:34:14 +0900294 unsigned long indexmask = current_cpu_data.icache.waysize - 1;
295 unsigned long start = INDEX_BASE + (page & indexmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700296 unsigned long end = start + PAGE_SIZE;
297 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
298 unsigned long ws_end = current_cpu_data.icache.ways <<
Ralf Baechle70342282013-01-22 12:59:30 +0100299 current_cpu_data.icache.waybit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300 unsigned long ws, addr;
301
302 CACHE32_UNROLL32_ALIGN2;
303 /* I'm in even chunk. blast odd chunks */
Ralf Baechle42a3b4f22005-09-03 15:56:17 -0700304 for (ws = 0; ws < ws_end; ws += ws_inc)
305 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
Paul Burton6baaead2019-10-08 18:22:00 +0000306 cache_unroll(32, kernel_cache, Index_Invalidate_I,
307 addr | ws, 32);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308 CACHE32_UNROLL32_ALIGN;
309 /* I'm in odd chunk. blast even chunks */
Ralf Baechle42a3b4f22005-09-03 15:56:17 -0700310 for (ws = 0; ws < ws_end; ws += ws_inc)
311 for (addr = start; addr < end; addr += 0x400 * 2)
Paul Burton6baaead2019-10-08 18:22:00 +0000312 cache_unroll(32, kernel_cache, Index_Invalidate_I,
313 addr | ws, 32);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700314}
315
316static void (* r4k_blast_icache_page)(unsigned long addr);
317
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000318static void r4k_blast_icache_page_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319{
320 unsigned long ic_lsize = cpu_icache_line_size();
321
Chris Dearman73f40352006-06-20 18:06:52 +0100322 if (ic_lsize == 0)
323 r4k_blast_icache_page = (void *)cache_noop;
324 else if (ic_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325 r4k_blast_icache_page = blast_icache16_page;
Jiaxun Yang268a2d62019-10-20 22:43:13 +0800326 else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2EF)
Aaro Koskinen43a06842014-01-14 17:56:38 -0800327 r4k_blast_icache_page = loongson2_blast_icache32_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700328 else if (ic_lsize == 32)
329 r4k_blast_icache_page = blast_icache32_page;
330 else if (ic_lsize == 64)
331 r4k_blast_icache_page = blast_icache64_page;
David Daney18a8cd62014-05-28 23:52:09 +0200332 else if (ic_lsize == 128)
333 r4k_blast_icache_page = blast_icache128_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334}
335
Leonid Yegoshin4caa9062014-01-15 14:47:28 +0000336#ifndef CONFIG_EVA
337#define r4k_blast_icache_user_page r4k_blast_icache_page
338#else
339
340static void (*r4k_blast_icache_user_page)(unsigned long addr);
341
Paul Gortmaker9a8f4ea2015-04-27 18:47:57 -0400342static void r4k_blast_icache_user_page_setup(void)
Leonid Yegoshin4caa9062014-01-15 14:47:28 +0000343{
344 unsigned long ic_lsize = cpu_icache_line_size();
345
346 if (ic_lsize == 0)
347 r4k_blast_icache_user_page = (void *)cache_noop;
348 else if (ic_lsize == 16)
349 r4k_blast_icache_user_page = blast_icache16_user_page;
350 else if (ic_lsize == 32)
351 r4k_blast_icache_user_page = blast_icache32_user_page;
352 else if (ic_lsize == 64)
353 r4k_blast_icache_user_page = blast_icache64_user_page;
354}
355
356#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357
358static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
359
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000360static void r4k_blast_icache_page_indexed_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361{
362 unsigned long ic_lsize = cpu_icache_line_size();
363
Chris Dearman73f40352006-06-20 18:06:52 +0100364 if (ic_lsize == 0)
365 r4k_blast_icache_page_indexed = (void *)cache_noop;
366 else if (ic_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
368 else if (ic_lsize == 32) {
Thiemo Seufer02fe2c92005-09-09 19:45:41 +0000369 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370 r4k_blast_icache_page_indexed =
371 blast_icache32_r4600_v1_page_indexed;
Thiemo Seufer02fe2c92005-09-09 19:45:41 +0000372 else if (TX49XX_ICACHE_INDEX_INV_WAR)
373 r4k_blast_icache_page_indexed =
374 tx49_blast_icache32_page_indexed;
Jiaxun Yang268a2d62019-10-20 22:43:13 +0800375 else if (current_cpu_type() == CPU_LOONGSON2EF)
Aaro Koskinen43a06842014-01-14 17:56:38 -0800376 r4k_blast_icache_page_indexed =
377 loongson2_blast_icache32_page_indexed;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378 else
379 r4k_blast_icache_page_indexed =
380 blast_icache32_page_indexed;
381 } else if (ic_lsize == 64)
382 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
383}
384
Sanjay Lalf2e36562012-11-21 18:34:10 -0800385void (* r4k_blast_icache)(void);
386EXPORT_SYMBOL(r4k_blast_icache);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000388static void r4k_blast_icache_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389{
390 unsigned long ic_lsize = cpu_icache_line_size();
391
Chris Dearman73f40352006-06-20 18:06:52 +0100392 if (ic_lsize == 0)
393 r4k_blast_icache = (void *)cache_noop;
394 else if (ic_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395 r4k_blast_icache = blast_icache16;
396 else if (ic_lsize == 32) {
397 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
398 r4k_blast_icache = blast_r4600_v1_icache32;
399 else if (TX49XX_ICACHE_INDEX_INV_WAR)
400 r4k_blast_icache = tx49_blast_icache32;
Jiaxun Yang268a2d62019-10-20 22:43:13 +0800401 else if (current_cpu_type() == CPU_LOONGSON2EF)
Aaro Koskinen43a06842014-01-14 17:56:38 -0800402 r4k_blast_icache = loongson2_blast_icache32;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403 else
404 r4k_blast_icache = blast_icache32;
405 } else if (ic_lsize == 64)
406 r4k_blast_icache = blast_icache64;
David Daney18a8cd62014-05-28 23:52:09 +0200407 else if (ic_lsize == 128)
408 r4k_blast_icache = blast_icache128;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700409}
410
411static void (* r4k_blast_scache_page)(unsigned long addr);
412
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000413static void r4k_blast_scache_page_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414{
415 unsigned long sc_lsize = cpu_scache_line_size();
416
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000417 if (scache_size == 0)
Chris Dearman73f40352006-06-20 18:06:52 +0100418 r4k_blast_scache_page = (void *)cache_noop;
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000419 else if (sc_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420 r4k_blast_scache_page = blast_scache16_page;
421 else if (sc_lsize == 32)
422 r4k_blast_scache_page = blast_scache32_page;
423 else if (sc_lsize == 64)
424 r4k_blast_scache_page = blast_scache64_page;
425 else if (sc_lsize == 128)
426 r4k_blast_scache_page = blast_scache128_page;
427}
428
429static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
430
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000431static void r4k_blast_scache_page_indexed_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432{
433 unsigned long sc_lsize = cpu_scache_line_size();
434
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000435 if (scache_size == 0)
Chris Dearman73f40352006-06-20 18:06:52 +0100436 r4k_blast_scache_page_indexed = (void *)cache_noop;
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000437 else if (sc_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
439 else if (sc_lsize == 32)
440 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
441 else if (sc_lsize == 64)
442 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
443 else if (sc_lsize == 128)
444 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
445}
446
447static void (* r4k_blast_scache)(void);
448
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000449static void r4k_blast_scache_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450{
451 unsigned long sc_lsize = cpu_scache_line_size();
452
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000453 if (scache_size == 0)
Chris Dearman73f40352006-06-20 18:06:52 +0100454 r4k_blast_scache = (void *)cache_noop;
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000455 else if (sc_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456 r4k_blast_scache = blast_scache16;
457 else if (sc_lsize == 32)
458 r4k_blast_scache = blast_scache32;
459 else if (sc_lsize == 64)
460 r4k_blast_scache = blast_scache64;
461 else if (sc_lsize == 128)
462 r4k_blast_scache = blast_scache128;
463}
464
Huacai Chenbb53fdf2018-11-15 15:53:53 +0800465static void (*r4k_blast_scache_node)(long node);
466
467static void r4k_blast_scache_node_setup(void)
468{
469 unsigned long sc_lsize = cpu_scache_line_size();
470
Jiaxun Yang268a2d62019-10-20 22:43:13 +0800471 if (current_cpu_type() != CPU_LOONGSON64)
Huacai Chenbb53fdf2018-11-15 15:53:53 +0800472 r4k_blast_scache_node = (void *)cache_noop;
473 else if (sc_lsize == 16)
474 r4k_blast_scache_node = blast_scache16_node;
475 else if (sc_lsize == 32)
476 r4k_blast_scache_node = blast_scache32_node;
477 else if (sc_lsize == 64)
478 r4k_blast_scache_node = blast_scache64_node;
479 else if (sc_lsize == 128)
480 r4k_blast_scache_node = blast_scache128_node;
481}
482
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483static inline void local_r4k___flush_cache_all(void * args)
484{
Ralf Baechle10cc3522007-10-11 23:46:15 +0100485 switch (current_cpu_type()) {
Jiaxun Yang268a2d62019-10-20 22:43:13 +0800486 case CPU_LOONGSON2EF:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487 case CPU_R4000SC:
488 case CPU_R4000MC:
489 case CPU_R4400SC:
490 case CPU_R4400MC:
491 case CPU_R10000:
492 case CPU_R12000:
Kumba44d921b2006-05-16 22:23:59 -0400493 case CPU_R14000:
Joshua Kinard30577392015-01-21 07:59:45 -0500494 case CPU_R16000:
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200495 /*
496 * These caches are inclusive caches, that is, if something
497 * is not cached in the S-cache, we know it also won't be
498 * in one of the primary caches.
499 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700500 r4k_blast_scache();
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200501 break;
502
Jiaxun Yang268a2d62019-10-20 22:43:13 +0800503 case CPU_LOONGSON64:
Huacai Chenbb53fdf2018-11-15 15:53:53 +0800504 /* Use get_ebase_cpunum() for both NUMA=y/n */
505 r4k_blast_scache_node(get_ebase_cpunum() >> 2);
506 break;
507
Florian Fainellif6758432016-04-04 10:55:36 -0700508 case CPU_BMIPS5000:
509 r4k_blast_scache();
510 __sync();
511 break;
512
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200513 default:
514 r4k_blast_dcache();
515 r4k_blast_icache();
516 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517 }
518}
519
520static void r4k___flush_cache_all(void)
521{
James Hogand374d932016-07-13 14:12:50 +0100522 r4k_on_each_cpu(R4K_INDEX, local_r4k___flush_cache_all, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523}
524
James Hogan6d758bf2016-07-13 14:12:51 +0100525/**
526 * has_valid_asid() - Determine if an mm already has an ASID.
527 * @mm: Memory map.
528 * @type: R4K_HIT or R4K_INDEX, type of cache op.
529 *
530 * Determines whether @mm already has an ASID on any of the CPUs which cache ops
531 * of type @type within an r4k_on_each_cpu() call will affect. If
532 * r4k_on_each_cpu() does an SMP call to a single VPE in each core, then the
533 * scope of the operation is confined to sibling CPUs, otherwise all online CPUs
534 * will need to be checked.
535 *
536 * Must be called in non-preemptive context.
537 *
538 * Returns: 1 if the CPUs affected by @type cache ops have an ASID for @mm.
539 * 0 otherwise.
540 */
541static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type)
Ralf Baechlea76ab5c2007-10-08 16:38:37 +0100542{
James Hogan6d758bf2016-07-13 14:12:51 +0100543 unsigned int i;
544 const cpumask_t *mask = cpu_present_mask;
Ralf Baechlea76ab5c2007-10-08 16:38:37 +0100545
Paul Burtonc8790d62019-02-02 01:43:28 +0000546 if (cpu_has_mmid)
547 return cpu_context(0, mm) != 0;
548
James Hogan6d758bf2016-07-13 14:12:51 +0100549 /* cpu_sibling_map[] undeclared when !CONFIG_SMP */
550#ifdef CONFIG_SMP
551 /*
552 * If r4k_on_each_cpu does SMP calls, it does them to a single VPE in
553 * each foreign core, so we only need to worry about siblings.
554 * Otherwise we need to worry about all present CPUs.
555 */
556 if (r4k_op_needs_ipi(type))
557 mask = &cpu_sibling_map[smp_processor_id()];
558#endif
559 for_each_cpu(i, mask)
Ralf Baechlea76ab5c2007-10-08 16:38:37 +0100560 if (cpu_context(i, mm))
561 return 1;
Ralf Baechlea76ab5c2007-10-08 16:38:37 +0100562 return 0;
Ralf Baechlea76ab5c2007-10-08 16:38:37 +0100563}
564
Ralf Baechle9c5a3d72008-04-05 15:13:23 +0100565static void r4k__flush_cache_vmap(void)
566{
567 r4k_blast_dcache();
568}
569
570static void r4k__flush_cache_vunmap(void)
571{
572 r4k_blast_dcache();
573}
574
James Hogana05c3922016-07-13 14:12:44 +0100575/*
576 * Note: flush_tlb_range() assumes flush_cache_range() sufficiently flushes
577 * whole caches when vma is executable.
578 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700579static inline void local_r4k_flush_cache_range(void * args)
580{
581 struct vm_area_struct *vma = args;
Ralf Baechle2eaa7ec2008-02-11 14:51:40 +0000582 int exec = vma->vm_flags & VM_EXEC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700583
James Hogan6d758bf2016-07-13 14:12:51 +0100584 if (!has_valid_asid(vma->vm_mm, R4K_INDEX))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700585 return;
586
James Hoganb2a3c5b2016-01-22 10:58:25 +0000587 /*
588 * If dcache can alias, we must blast it since mapping is changing.
589 * If executable, we must ensure any dirty lines are written back far
590 * enough to be visible to icache.
591 */
592 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
593 r4k_blast_dcache();
594 /* If executable, blast stale lines from icache */
Ralf Baechle2eaa7ec2008-02-11 14:51:40 +0000595 if (exec)
596 r4k_blast_icache();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700597}
598
599static void r4k_flush_cache_range(struct vm_area_struct *vma,
600 unsigned long start, unsigned long end)
601{
Ralf Baechle2eaa7ec2008-02-11 14:51:40 +0000602 int exec = vma->vm_flags & VM_EXEC;
Atsushi Nemoto0550d9d2006-08-22 21:15:47 +0900603
James Hoganb2a3c5b2016-01-22 10:58:25 +0000604 if (cpu_has_dc_aliases || exec)
James Hogand374d932016-07-13 14:12:50 +0100605 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_range, vma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700606}
607
608static inline void local_r4k_flush_cache_mm(void * args)
609{
610 struct mm_struct *mm = args;
611
James Hogan6d758bf2016-07-13 14:12:51 +0100612 if (!has_valid_asid(mm, R4K_INDEX))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700613 return;
614
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615 /*
616 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
Joshua Kinard30577392015-01-21 07:59:45 -0500617 * only flush the primary caches but R1x000 behave sane ...
Ralf Baechle617667b2006-11-30 01:14:48 +0000618 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
619 * caches, so we can bail out early.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620 */
Ralf Baechle10cc3522007-10-11 23:46:15 +0100621 if (current_cpu_type() == CPU_R4000SC ||
622 current_cpu_type() == CPU_R4000MC ||
623 current_cpu_type() == CPU_R4400SC ||
624 current_cpu_type() == CPU_R4400MC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700625 r4k_blast_scache();
Ralf Baechle617667b2006-11-30 01:14:48 +0000626 return;
627 }
628
629 r4k_blast_dcache();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700630}
631
632static void r4k_flush_cache_mm(struct mm_struct *mm)
633{
634 if (!cpu_has_dc_aliases)
635 return;
636
James Hogand374d932016-07-13 14:12:50 +0100637 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_mm, mm);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638}
639
640struct flush_cache_page_args {
641 struct vm_area_struct *vma;
Ralf Baechle6ec25802005-10-12 00:02:34 +0100642 unsigned long addr;
Atsushi Nemotode628932006-03-13 18:23:03 +0900643 unsigned long pfn;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700644};
645
646static inline void local_r4k_flush_cache_page(void *args)
647{
648 struct flush_cache_page_args *fcp_args = args;
649 struct vm_area_struct *vma = fcp_args->vma;
Ralf Baechle6ec25802005-10-12 00:02:34 +0100650 unsigned long addr = fcp_args->addr;
Ralf Baechledb813fe2007-09-27 18:26:43 +0100651 struct page *page = pfn_to_page(fcp_args->pfn);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652 int exec = vma->vm_flags & VM_EXEC;
653 struct mm_struct *mm = vma->vm_mm;
Ralf Baechlec9c50232008-06-14 22:22:08 +0100654 int map_coherent = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655 pmd_t *pmdp;
656 pte_t *ptep;
Ralf Baechledb813fe2007-09-27 18:26:43 +0100657 void *vaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700658
Ralf Baechle79acf832005-02-10 13:54:37 +0000659 /*
James Hogan6d758bf2016-07-13 14:12:51 +0100660 * If owns no valid ASID yet, cannot possibly have gotten
Ralf Baechle79acf832005-02-10 13:54:37 +0000661 * this page into the cache.
662 */
James Hogan6d758bf2016-07-13 14:12:51 +0100663 if (!has_valid_asid(mm, R4K_HIT))
Ralf Baechle79acf832005-02-10 13:54:37 +0000664 return;
665
Ralf Baechle6ec25802005-10-12 00:02:34 +0100666 addr &= PAGE_MASK;
Mike Rapoporte05c7b12020-06-08 21:33:05 -0700667 pmdp = pmd_off(mm, addr);
668 ptep = pte_offset_kernel(pmdp, addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669
670 /*
671 * If the page isn't marked valid, the page cannot possibly be
672 * in the cache.
673 */
Ralf Baechle526af352008-01-29 10:14:55 +0000674 if (!(pte_present(*ptep)))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675 return;
676
Ralf Baechledb813fe2007-09-27 18:26:43 +0100677 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
678 vaddr = NULL;
679 else {
680 /*
681 * Use kmap_coherent or kmap_atomic to do flushes for
682 * another ASID than the current one.
683 */
Ralf Baechlec9c50232008-06-14 22:22:08 +0100684 map_coherent = (cpu_has_dc_aliases &&
Kirill A. Shutemove1534ae2016-01-15 16:53:46 -0800685 page_mapcount(page) &&
686 !Page_dcache_dirty(page));
Ralf Baechlec9c50232008-06-14 22:22:08 +0100687 if (map_coherent)
Ralf Baechledb813fe2007-09-27 18:26:43 +0100688 vaddr = kmap_coherent(page, addr);
689 else
Cong Wang9c020482011-11-25 23:14:15 +0800690 vaddr = kmap_atomic(page);
Ralf Baechledb813fe2007-09-27 18:26:43 +0100691 addr = (unsigned long)vaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692 }
693
Linus Torvalds1da177e2005-04-16 15:20:36 -0700694 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
Markos Chandras80ca69f2014-01-16 13:11:08 +0000695 vaddr ? r4k_blast_dcache_page(addr) :
696 r4k_blast_dcache_user_page(addr);
Ralf Baechle39b8d522008-04-28 17:14:26 +0100697 if (exec && !cpu_icache_snoops_remote_store)
698 r4k_blast_scache_page(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699 }
700 if (exec) {
Ralf Baechledb813fe2007-09-27 18:26:43 +0100701 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
Paul Burtonc9b2a3d2019-02-02 01:43:19 +0000702 drop_mmu_context(mm);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703 } else
Markos Chandras80ca69f2014-01-16 13:11:08 +0000704 vaddr ? r4k_blast_icache_page(addr) :
705 r4k_blast_icache_user_page(addr);
Ralf Baechledb813fe2007-09-27 18:26:43 +0100706 }
707
708 if (vaddr) {
Ralf Baechlec9c50232008-06-14 22:22:08 +0100709 if (map_coherent)
Ralf Baechledb813fe2007-09-27 18:26:43 +0100710 kunmap_coherent();
711 else
Cong Wang9c020482011-11-25 23:14:15 +0800712 kunmap_atomic(vaddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700713 }
714}
715
Ralf Baechle6ec25802005-10-12 00:02:34 +0100716static void r4k_flush_cache_page(struct vm_area_struct *vma,
717 unsigned long addr, unsigned long pfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718{
719 struct flush_cache_page_args args;
720
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721 args.vma = vma;
Ralf Baechle6ec25802005-10-12 00:02:34 +0100722 args.addr = addr;
Atsushi Nemotode628932006-03-13 18:23:03 +0900723 args.pfn = pfn;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700724
James Hogand374d932016-07-13 14:12:50 +0100725 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_page, &args);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726}
727
728static inline void local_r4k_flush_data_cache_page(void * addr)
729{
730 r4k_blast_dcache_page((unsigned long) addr);
731}
732
733static void r4k_flush_data_cache_page(unsigned long addr)
734{
Ralf Baechlea754f702007-11-03 01:01:37 +0000735 if (in_atomic())
736 local_r4k_flush_data_cache_page((void *)addr);
737 else
James Hogand374d932016-07-13 14:12:50 +0100738 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_data_cache_page,
739 (void *) addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700740}
741
742struct flush_icache_range_args {
Atsushi Nemotod4264f12006-01-29 02:27:51 +0900743 unsigned long start;
744 unsigned long end;
James Hogan27b93d92016-07-13 14:12:54 +0100745 unsigned int type;
James Hoganb2ff7172016-09-01 17:30:15 +0100746 bool user;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747};
748
James Hogan27b93d92016-07-13 14:12:54 +0100749static inline void __local_r4k_flush_icache_range(unsigned long start,
750 unsigned long end,
James Hoganb2ff7172016-09-01 17:30:15 +0100751 unsigned int type,
752 bool user)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700753{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700754 if (!cpu_has_ic_fills_f_dc) {
James Hogan27b93d92016-07-13 14:12:54 +0100755 if (type == R4K_INDEX ||
756 (type & R4K_INDEX && end - start >= dcache_size)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700757 r4k_blast_dcache();
758 } else {
Thiemo Seufer10a3dab2005-09-09 20:26:54 +0000759 R4600_HIT_CACHEOP_WAR_IMPL;
James Hoganb2ff7172016-09-01 17:30:15 +0100760 if (user)
761 protected_blast_dcache_range(start, end);
762 else
763 blast_dcache_range(start, end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700764 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700765 }
766
James Hogan27b93d92016-07-13 14:12:54 +0100767 if (type == R4K_INDEX ||
768 (type & R4K_INDEX && end - start > icache_size))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700769 r4k_blast_icache();
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200770 else {
771 switch (boot_cpu_type()) {
Jiaxun Yang268a2d62019-10-20 22:43:13 +0800772 case CPU_LOONGSON2EF:
Huacai Chenbad009f2014-01-14 17:56:37 -0800773 protected_loongson2_blast_icache_range(start, end);
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200774 break;
775
776 default:
James Hoganb2ff7172016-09-01 17:30:15 +0100777 if (user)
778 protected_blast_icache_range(start, end);
779 else
780 blast_icache_range(start, end);
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200781 break;
782 }
783 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700784}
785
James Hogan27b93d92016-07-13 14:12:54 +0100786static inline void local_r4k_flush_icache_range(unsigned long start,
787 unsigned long end)
788{
James Hoganb2ff7172016-09-01 17:30:15 +0100789 __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, false);
790}
791
792static inline void local_r4k_flush_icache_user_range(unsigned long start,
793 unsigned long end)
794{
795 __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, true);
James Hogan27b93d92016-07-13 14:12:54 +0100796}
797
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +0200798static inline void local_r4k_flush_icache_range_ipi(void *args)
799{
800 struct flush_icache_range_args *fir_args = args;
801 unsigned long start = fir_args->start;
802 unsigned long end = fir_args->end;
James Hogan27b93d92016-07-13 14:12:54 +0100803 unsigned int type = fir_args->type;
James Hoganb2ff7172016-09-01 17:30:15 +0100804 bool user = fir_args->user;
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +0200805
James Hoganb2ff7172016-09-01 17:30:15 +0100806 __local_r4k_flush_icache_range(start, end, type, user);
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +0200807}
808
James Hoganb2ff7172016-09-01 17:30:15 +0100809static void __r4k_flush_icache_range(unsigned long start, unsigned long end,
810 bool user)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700811{
812 struct flush_icache_range_args args;
James Hoganf70ddc02016-07-13 14:12:55 +0100813 unsigned long size, cache_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814
815 args.start = start;
816 args.end = end;
James Hogan27b93d92016-07-13 14:12:54 +0100817 args.type = R4K_HIT | R4K_INDEX;
James Hoganb2ff7172016-09-01 17:30:15 +0100818 args.user = user;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700819
James Hoganf70ddc02016-07-13 14:12:55 +0100820 /*
821 * Indexed cache ops require an SMP call.
822 * Consider if that can or should be avoided.
823 */
824 preempt_disable();
825 if (r4k_op_needs_ipi(R4K_INDEX) && !r4k_op_needs_ipi(R4K_HIT)) {
826 /*
827 * If address-based cache ops don't require an SMP call, then
828 * use them exclusively for small flushes.
829 */
Paul Burton801f8232016-09-05 15:24:54 +0100830 size = end - start;
James Hoganf70ddc02016-07-13 14:12:55 +0100831 cache_size = icache_size;
832 if (!cpu_has_ic_fills_f_dc) {
833 size *= 2;
834 cache_size += dcache_size;
835 }
836 if (size <= cache_size)
837 args.type &= ~R4K_INDEX;
838 }
James Hogan27b93d92016-07-13 14:12:54 +0100839 r4k_on_each_cpu(args.type, local_r4k_flush_icache_range_ipi, &args);
James Hoganf70ddc02016-07-13 14:12:55 +0100840 preempt_enable();
Ralf Baechlecc61c1f2005-07-12 18:35:38 +0000841 instruction_hazard();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842}
843
James Hoganb2ff7172016-09-01 17:30:15 +0100844static void r4k_flush_icache_range(unsigned long start, unsigned long end)
845{
846 return __r4k_flush_icache_range(start, end, false);
847}
848
849static void r4k_flush_icache_user_range(unsigned long start, unsigned long end)
850{
851 return __r4k_flush_icache_range(start, end, true);
852}
853
Christoph Hellwig972dc3b2018-06-15 13:08:31 +0200854#ifdef CONFIG_DMA_NONCOHERENT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700855
856static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
857{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858 /* Catch bad driver code */
Paul Burtond4da0e92016-11-25 18:46:09 +0000859 if (WARN_ON(size == 0))
860 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700861
Ralf Baechleff522052013-09-17 12:44:31 +0200862 preempt_disable();
Ralf Baechlefc5d2d22006-07-06 13:04:01 +0100863 if (cpu_has_inclusive_pcaches) {
Huacai Chenbb53fdf2018-11-15 15:53:53 +0800864 if (size >= scache_size) {
Jiaxun Yang268a2d62019-10-20 22:43:13 +0800865 if (current_cpu_type() != CPU_LOONGSON64)
Huacai Chenbb53fdf2018-11-15 15:53:53 +0800866 r4k_blast_scache();
867 else
868 r4k_blast_scache_node(pa_to_nid(addr));
869 } else {
Atsushi Nemoto41700e72006-02-10 00:39:06 +0900870 blast_scache_range(addr, addr + size);
Huacai Chenbb53fdf2018-11-15 15:53:53 +0800871 }
Yoichi Yuasa5596b0b2013-10-02 15:03:03 +0900872 preempt_enable();
Kevin Cernekeed0023c42010-09-06 21:03:46 -0700873 __sync();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874 return;
875 }
876
877 /*
878 * Either no secondary cache or the available caches don't have the
879 * subset property so we have to flush the primary caches
NeilBrown55a2aa02018-04-27 09:28:34 +1000880 * explicitly.
881 * If we would need IPI to perform an INDEX-type operation, then
882 * we have to use the HIT-type alternative as IPI cannot be used
883 * here due to interrupts possibly being disabled.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700884 */
NeilBrown55a2aa02018-04-27 09:28:34 +1000885 if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700886 r4k_blast_dcache();
887 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700888 R4600_HIT_CACHEOP_WAR_IMPL;
Atsushi Nemoto41700e72006-02-10 00:39:06 +0900889 blast_dcache_range(addr, addr + size);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890 }
Ralf Baechleff522052013-09-17 12:44:31 +0200891 preempt_enable();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892
893 bc_wback_inv(addr, size);
Kevin Cernekeed0023c42010-09-06 21:03:46 -0700894 __sync();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700895}
896
Kamal Dasube280762020-02-07 17:33:07 -0500897static void prefetch_cache_inv(unsigned long addr, unsigned long size)
898{
899 unsigned int linesz = cpu_scache_line_size();
900 unsigned long addr0 = addr, addr1;
901
902 addr0 &= ~(linesz - 1);
903 addr1 = (addr0 + size - 1) & ~(linesz - 1);
904
905 protected_writeback_scache_line(addr0);
906 if (likely(addr1 != addr0))
907 protected_writeback_scache_line(addr1);
908 else
909 return;
910
911 addr0 += linesz;
912 if (likely(addr1 != addr0))
913 protected_writeback_scache_line(addr0);
914 else
915 return;
916
917 addr1 -= linesz;
918 if (likely(addr1 > addr0))
919 protected_writeback_scache_line(addr0);
920}
921
Linus Torvalds1da177e2005-04-16 15:20:36 -0700922static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
923{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924 /* Catch bad driver code */
Paul Burtond4da0e92016-11-25 18:46:09 +0000925 if (WARN_ON(size == 0))
926 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700927
Ralf Baechleff522052013-09-17 12:44:31 +0200928 preempt_disable();
Kamal Dasube280762020-02-07 17:33:07 -0500929
930 if (current_cpu_type() == CPU_BMIPS5000)
931 prefetch_cache_inv(addr, size);
932
Ralf Baechlefc5d2d22006-07-06 13:04:01 +0100933 if (cpu_has_inclusive_pcaches) {
Huacai Chenbb53fdf2018-11-15 15:53:53 +0800934 if (size >= scache_size) {
Jiaxun Yang268a2d62019-10-20 22:43:13 +0800935 if (current_cpu_type() != CPU_LOONGSON64)
Huacai Chenbb53fdf2018-11-15 15:53:53 +0800936 r4k_blast_scache();
937 else
938 r4k_blast_scache_node(pa_to_nid(addr));
939 } else {
Ralf Baechlea8ca8b62009-01-11 18:44:49 +0000940 /*
941 * There is no clearly documented alignment requirement
942 * for the cache instruction on MIPS processors and
943 * some processors, among them the RM5200 and RM7000
944 * QED processors will throw an address error for cache
Ralf Baechle70342282013-01-22 12:59:30 +0100945 * hit ops with insufficient alignment. Solved by
Ralf Baechlea8ca8b62009-01-11 18:44:49 +0000946 * aligning the address to cache line size.
947 */
Thomas Bogendoerfere9c33572007-11-26 23:40:01 +0100948 blast_inv_scache_range(addr, addr + size);
Ralf Baechlea8ca8b62009-01-11 18:44:49 +0000949 }
Yoichi Yuasa5596b0b2013-10-02 15:03:03 +0900950 preempt_enable();
Kevin Cernekeed0023c42010-09-06 21:03:46 -0700951 __sync();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700952 return;
953 }
954
NeilBrown55a2aa02018-04-27 09:28:34 +1000955 if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700956 r4k_blast_dcache();
957 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700958 R4600_HIT_CACHEOP_WAR_IMPL;
Thomas Bogendoerfere9c33572007-11-26 23:40:01 +0100959 blast_inv_dcache_range(addr, addr + size);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700960 }
Ralf Baechleff522052013-09-17 12:44:31 +0200961 preempt_enable();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700962
963 bc_inv(addr, size);
Kevin Cernekeed0023c42010-09-06 21:03:46 -0700964 __sync();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700965}
Christoph Hellwig972dc3b2018-06-15 13:08:31 +0200966#endif /* CONFIG_DMA_NONCOHERENT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700967
Linus Torvalds1da177e2005-04-16 15:20:36 -0700968static void r4k_flush_icache_all(void)
969{
970 if (cpu_has_vtag_icache)
971 r4k_blast_icache();
972}
973
Ralf Baechled9cdc9012011-06-17 16:20:28 +0100974struct flush_kernel_vmap_range_args {
975 unsigned long vaddr;
976 int size;
977};
978
James Hogana9341ae2016-07-13 14:12:53 +0100979static inline void local_r4k_flush_kernel_vmap_range_index(void *args)
980{
981 /*
982 * Aliases only affect the primary caches so don't bother with
983 * S-caches or T-caches.
984 */
985 r4k_blast_dcache();
986}
987
Ralf Baechled9cdc9012011-06-17 16:20:28 +0100988static inline void local_r4k_flush_kernel_vmap_range(void *args)
989{
990 struct flush_kernel_vmap_range_args *vmra = args;
991 unsigned long vaddr = vmra->vaddr;
992 int size = vmra->size;
993
994 /*
995 * Aliases only affect the primary caches so don't bother with
996 * S-caches or T-caches.
997 */
James Hogana9341ae2016-07-13 14:12:53 +0100998 R4600_HIT_CACHEOP_WAR_IMPL;
999 blast_dcache_range(vaddr, vaddr + size);
Ralf Baechled9cdc9012011-06-17 16:20:28 +01001000}
1001
1002static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
1003{
1004 struct flush_kernel_vmap_range_args args;
1005
1006 args.vaddr = (unsigned long) vaddr;
1007 args.size = size;
1008
James Hogana9341ae2016-07-13 14:12:53 +01001009 if (size >= dcache_size)
1010 r4k_on_each_cpu(R4K_INDEX,
1011 local_r4k_flush_kernel_vmap_range_index, NULL);
1012 else
1013 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_kernel_vmap_range,
1014 &args);
Ralf Baechled9cdc9012011-06-17 16:20:28 +01001015}
1016
Linus Torvalds1da177e2005-04-16 15:20:36 -07001017static inline void rm7k_erratum31(void)
1018{
1019 const unsigned long ic_lsize = 32;
1020 unsigned long addr;
1021
1022 /* RM7000 erratum #31. The icache is screwed at startup. */
1023 write_c0_taglo(0);
1024 write_c0_taghi(0);
1025
1026 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
1027 __asm__ __volatile__ (
Thiemo Seuferd8748a32005-09-02 09:56:12 +00001028 ".set push\n\t"
Linus Torvalds1da177e2005-04-16 15:20:36 -07001029 ".set noreorder\n\t"
1030 ".set mips3\n\t"
1031 "cache\t%1, 0(%0)\n\t"
1032 "cache\t%1, 0x1000(%0)\n\t"
1033 "cache\t%1, 0x2000(%0)\n\t"
1034 "cache\t%1, 0x3000(%0)\n\t"
1035 "cache\t%2, 0(%0)\n\t"
1036 "cache\t%2, 0x1000(%0)\n\t"
1037 "cache\t%2, 0x2000(%0)\n\t"
1038 "cache\t%2, 0x3000(%0)\n\t"
1039 "cache\t%1, 0(%0)\n\t"
1040 "cache\t%1, 0x1000(%0)\n\t"
1041 "cache\t%1, 0x2000(%0)\n\t"
1042 "cache\t%1, 0x3000(%0)\n\t"
Thiemo Seuferd8748a32005-09-02 09:56:12 +00001043 ".set pop\n"
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044 :
Huacai Chena44f8302020-04-26 19:09:52 +08001045 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill_I));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046 }
1047}
1048
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001049static inline int alias_74k_erratum(struct cpuinfo_mips *c)
Steven J. Hill006a8512012-06-26 04:11:03 +00001050{
Maciej W. Rozycki9213ad72013-09-18 19:08:15 +01001051 unsigned int imp = c->processor_id & PRID_IMP_MASK;
1052 unsigned int rev = c->processor_id & PRID_REV_MASK;
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001053 int present = 0;
Maciej W. Rozycki9213ad72013-09-18 19:08:15 +01001054
Steven J. Hill006a8512012-06-26 04:11:03 +00001055 /*
1056 * Early versions of the 74K do not update the cache tags on a
1057 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001058 * aliases. In this case it is better to treat the cache as always
1059 * having aliases. Also disable the synonym tag update feature
1060 * where available. In this case no opportunistic tag update will
1061 * happen where a load causes a virtual address miss but a physical
1062 * address hit during a D-cache look-up.
Steven J. Hill006a8512012-06-26 04:11:03 +00001063 */
Maciej W. Rozycki9213ad72013-09-18 19:08:15 +01001064 switch (imp) {
1065 case PRID_IMP_74K:
1066 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001067 present = 1;
Maciej W. Rozycki9213ad72013-09-18 19:08:15 +01001068 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
Huacai Chen8267e782020-05-23 15:51:45 +08001069 write_c0_config6(read_c0_config6() | MIPS_CONF6_MTI_SYND);
Maciej W. Rozycki9213ad72013-09-18 19:08:15 +01001070 break;
1071 case PRID_IMP_1074K:
1072 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001073 present = 1;
Huacai Chen8267e782020-05-23 15:51:45 +08001074 write_c0_config6(read_c0_config6() | MIPS_CONF6_MTI_SYND);
Maciej W. Rozycki9213ad72013-09-18 19:08:15 +01001075 }
1076 break;
1077 default:
1078 BUG();
Steven J. Hill006a8512012-06-26 04:11:03 +00001079 }
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001080
1081 return present;
Steven J. Hill006a8512012-06-26 04:11:03 +00001082}
1083
Kevin Cernekeed74b0172014-10-20 21:28:00 -07001084static void b5k_instruction_hazard(void)
1085{
1086 __sync();
1087 __sync();
1088 __asm__ __volatile__(
1089 " nop; nop; nop; nop; nop; nop; nop; nop\n"
1090 " nop; nop; nop; nop; nop; nop; nop; nop\n"
1091 " nop; nop; nop; nop; nop; nop; nop; nop\n"
1092 " nop; nop; nop; nop; nop; nop; nop; nop\n"
1093 : : : "memory");
1094}
1095
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001096static char *way_string[] = { NULL, "direct mapped", "2-way",
Paul Burton1e18ac72015-07-09 10:40:41 +01001097 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
1098 "9-way", "10-way", "11-way", "12-way",
1099 "13-way", "14-way", "15-way", "16-way",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100};
1101
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001102static void probe_pcache(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103{
1104 struct cpuinfo_mips *c = &current_cpu_data;
1105 unsigned int config = read_c0_config();
1106 unsigned int prid = read_c0_prid();
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001107 int has_74k_erratum = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001108 unsigned long config1;
1109 unsigned int lsize;
1110
Ralf Baechle69f24d12013-09-17 10:25:47 +02001111 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001112 case CPU_R4600: /* QED style two way caches? */
1113 case CPU_R4700:
1114 case CPU_R5000:
1115 case CPU_NEVADA:
1116 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1117 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1118 c->icache.ways = 2;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001119 c->icache.waybit = __ffs(icache_size/2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001120
1121 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1122 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1123 c->dcache.ways = 2;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001124 c->dcache.waybit= __ffs(dcache_size/2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001125
1126 c->options |= MIPS_CPU_CACHE_CDEX_P;
1127 break;
1128
Linus Torvalds1da177e2005-04-16 15:20:36 -07001129 case CPU_R5500:
1130 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1131 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1132 c->icache.ways = 2;
1133 c->icache.waybit= 0;
1134
1135 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1136 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1137 c->dcache.ways = 2;
1138 c->dcache.waybit = 0;
1139
Shinya Kuribayashi58648102009-03-18 09:04:01 +09001140 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001141 break;
1142
1143 case CPU_TX49XX:
1144 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1145 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1146 c->icache.ways = 4;
1147 c->icache.waybit= 0;
1148
1149 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1150 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1151 c->dcache.ways = 4;
1152 c->dcache.waybit = 0;
1153
1154 c->options |= MIPS_CPU_CACHE_CDEX_P;
Atsushi Nemotode862b42006-03-17 12:59:22 +09001155 c->options |= MIPS_CPU_PREFETCH;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001156 break;
1157
1158 case CPU_R4000PC:
1159 case CPU_R4000SC:
1160 case CPU_R4000MC:
1161 case CPU_R4400PC:
1162 case CPU_R4400SC:
1163 case CPU_R4400MC:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001164 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1165 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1166 c->icache.ways = 1;
Ralf Baechle70342282013-01-22 12:59:30 +01001167 c->icache.waybit = 0; /* doesn't matter */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001168
1169 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1170 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1171 c->dcache.ways = 1;
1172 c->dcache.waybit = 0; /* does not matter */
1173
1174 c->options |= MIPS_CPU_CACHE_CDEX_P;
1175 break;
1176
1177 case CPU_R10000:
1178 case CPU_R12000:
Kumba44d921b2006-05-16 22:23:59 -04001179 case CPU_R14000:
Joshua Kinard30577392015-01-21 07:59:45 -05001180 case CPU_R16000:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001181 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
1182 c->icache.linesz = 64;
1183 c->icache.ways = 2;
1184 c->icache.waybit = 0;
1185
1186 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
1187 c->dcache.linesz = 32;
1188 c->dcache.ways = 2;
1189 c->dcache.waybit = 0;
1190
1191 c->options |= MIPS_CPU_PREFETCH;
1192 break;
1193
1194 case CPU_VR4133:
Yoichi Yuasa2874fe52006-07-08 00:42:12 +09001195 write_c0_config(config & ~VR41_CONF_P4K);
Liangliang Huangc9b02992020-05-04 16:51:29 +08001196 fallthrough;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001197 case CPU_VR4131:
1198 /* Workaround for cache instruction bug of VR4131 */
1199 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
1200 c->processor_id == 0x0c82U) {
Yoichi Yuasa4e8ab362006-07-04 22:59:41 +09001201 config |= 0x00400000U;
1202 if (c->processor_id == 0x0c80U)
1203 config |= VR41_CONF_BP;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001204 write_c0_config(config);
Yoichi Yuasa1058ecd2006-07-08 00:42:01 +09001205 } else
1206 c->options |= MIPS_CPU_CACHE_CDEX_P;
1207
Linus Torvalds1da177e2005-04-16 15:20:36 -07001208 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1209 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1210 c->icache.ways = 2;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001211 c->icache.waybit = __ffs(icache_size/2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001212
1213 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1214 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1215 c->dcache.ways = 2;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001216 c->dcache.waybit = __ffs(dcache_size/2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001217 break;
1218
1219 case CPU_VR41XX:
1220 case CPU_VR4111:
1221 case CPU_VR4121:
1222 case CPU_VR4122:
1223 case CPU_VR4181:
1224 case CPU_VR4181A:
1225 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1226 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1227 c->icache.ways = 1;
Ralf Baechle70342282013-01-22 12:59:30 +01001228 c->icache.waybit = 0; /* doesn't matter */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001229
1230 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1231 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1232 c->dcache.ways = 1;
1233 c->dcache.waybit = 0; /* does not matter */
1234
1235 c->options |= MIPS_CPU_CACHE_CDEX_P;
1236 break;
1237
1238 case CPU_RM7000:
1239 rm7k_erratum31();
1240
Linus Torvalds1da177e2005-04-16 15:20:36 -07001241 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1242 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1243 c->icache.ways = 4;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001244 c->icache.waybit = __ffs(icache_size / c->icache.ways);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001245
1246 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1247 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1248 c->dcache.ways = 4;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001249 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001250
Linus Torvalds1da177e2005-04-16 15:20:36 -07001251 c->options |= MIPS_CPU_CACHE_CDEX_P;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001252 c->options |= MIPS_CPU_PREFETCH;
1253 break;
1254
Jiaxun Yang268a2d62019-10-20 22:43:13 +08001255 case CPU_LOONGSON2EF:
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001256 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1257 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1258 if (prid & 0x3)
1259 c->icache.ways = 4;
1260 else
1261 c->icache.ways = 2;
1262 c->icache.waybit = 0;
1263
1264 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1265 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1266 if (prid & 0x3)
1267 c->dcache.ways = 4;
1268 else
1269 c->dcache.ways = 2;
1270 c->dcache.waybit = 0;
1271 break;
1272
Jiaxun Yang268a2d62019-10-20 22:43:13 +08001273 case CPU_LOONGSON64:
Huacai Chenc579d312014-03-21 18:44:00 +08001274 config1 = read_c0_config1();
1275 lsize = (config1 >> 19) & 7;
1276 if (lsize)
1277 c->icache.linesz = 2 << lsize;
1278 else
1279 c->icache.linesz = 0;
1280 c->icache.sets = 64 << ((config1 >> 22) & 7);
1281 c->icache.ways = 1 + ((config1 >> 16) & 7);
1282 icache_size = c->icache.sets *
1283 c->icache.ways *
1284 c->icache.linesz;
1285 c->icache.waybit = 0;
1286
1287 lsize = (config1 >> 10) & 7;
1288 if (lsize)
1289 c->dcache.linesz = 2 << lsize;
1290 else
1291 c->dcache.linesz = 0;
1292 c->dcache.sets = 64 << ((config1 >> 13) & 7);
1293 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1294 dcache_size = c->dcache.sets *
1295 c->dcache.ways *
1296 c->dcache.linesz;
1297 c->dcache.waybit = 0;
Huacai Chen75074452019-09-21 21:50:27 +08001298 if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >=
Jiaxun Yang0cf2ea12020-04-22 22:43:44 +08001299 (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0) ||
1300 (c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
Huacai Chen1e820da32016-03-03 09:45:13 +08001301 c->options |= MIPS_CPU_PREFETCH;
Huacai Chenc579d312014-03-21 18:44:00 +08001302 break;
1303
David Daney18a8cd62014-05-28 23:52:09 +02001304 case CPU_CAVIUM_OCTEON3:
1305 /* For now lie about the number of ways. */
1306 c->icache.linesz = 128;
1307 c->icache.sets = 16;
1308 c->icache.ways = 8;
1309 c->icache.flags |= MIPS_CACHE_VTAG;
1310 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
1311
1312 c->dcache.linesz = 128;
1313 c->dcache.ways = 8;
1314 c->dcache.sets = 8;
1315 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
1316 c->options |= MIPS_CPU_PREFETCH;
1317 break;
1318
Linus Torvalds1da177e2005-04-16 15:20:36 -07001319 default:
1320 if (!(config & MIPS_CONF_M))
1321 panic("Don't know how to probe P-caches on this cpu.");
1322
1323 /*
1324 * So we seem to be a MIPS32 or MIPS64 CPU
1325 * So let's probe the I-cache ...
1326 */
1327 config1 = read_c0_config1();
1328
Markos Chandras175cba82013-09-19 18:18:41 +01001329 lsize = (config1 >> 19) & 7;
1330
1331 /* IL == 7 is reserved */
1332 if (lsize == 7)
1333 panic("Invalid icache line size");
1334
1335 c->icache.linesz = lsize ? 2 << lsize : 0;
1336
Douglas Leungdc34b052012-07-19 09:11:13 +02001337 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001338 c->icache.ways = 1 + ((config1 >> 16) & 7);
1339
1340 icache_size = c->icache.sets *
Ralf Baechle70342282013-01-22 12:59:30 +01001341 c->icache.ways *
1342 c->icache.linesz;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001343 c->icache.waybit = __ffs(icache_size/c->icache.ways);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001344
James Hogan4b34bca2016-06-15 19:29:59 +01001345 if (config & MIPS_CONF_VI)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001346 c->icache.flags |= MIPS_CACHE_VTAG;
1347
1348 /*
1349 * Now probe the MIPS32 / MIPS64 data cache.
1350 */
1351 c->dcache.flags = 0;
1352
Markos Chandras175cba82013-09-19 18:18:41 +01001353 lsize = (config1 >> 10) & 7;
1354
1355 /* DL == 7 is reserved */
1356 if (lsize == 7)
1357 panic("Invalid dcache line size");
1358
1359 c->dcache.linesz = lsize ? 2 << lsize : 0;
1360
Douglas Leungdc34b052012-07-19 09:11:13 +02001361 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001362 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1363
1364 dcache_size = c->dcache.sets *
Ralf Baechle70342282013-01-22 12:59:30 +01001365 c->dcache.ways *
1366 c->dcache.linesz;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001367 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001368
1369 c->options |= MIPS_CPU_PREFETCH;
1370 break;
1371 }
1372
1373 /*
1374 * Processor configuration sanity check for the R4000SC erratum
Ralf Baechle70342282013-01-22 12:59:30 +01001375 * #5. With page sizes larger than 32kB there is no possibility
Linus Torvalds1da177e2005-04-16 15:20:36 -07001376 * to get a VCE exception anymore so we don't care about this
1377 * misconfiguration. The case is rather theoretical anyway;
1378 * presumably no vendor is shipping his hardware in the "bad"
1379 * configuration.
1380 */
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001381 if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1382 (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07001383 !(config & CONF_SC) && c->icache.linesz != 16 &&
1384 PAGE_SIZE <= 0x8000)
1385 panic("Improper R4000SC processor configuration detected");
1386
1387 /* compute a couple of other cache variables */
1388 c->icache.waysize = icache_size / c->icache.ways;
1389 c->dcache.waysize = dcache_size / c->dcache.ways;
1390
Chris Dearman73f40352006-06-20 18:06:52 +01001391 c->icache.sets = c->icache.linesz ?
1392 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1393 c->dcache.sets = c->dcache.linesz ?
1394 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001395
1396 /*
Joshua Kinard30577392015-01-21 07:59:45 -05001397 * R1x000 P-caches are odd in a positive way. They're 32kB 2-way
1398 * virtually indexed so normally would suffer from aliases. So
Linus Torvalds1da177e2005-04-16 15:20:36 -07001399 * normally they'd suffer from aliases but magic in the hardware deals
1400 * with that for us so we don't need to take care ourselves.
1401 */
Ralf Baechle69f24d12013-09-17 10:25:47 +02001402 switch (current_cpu_type()) {
Ralf Baechlea95970f2005-02-07 21:41:32 +00001403 case CPU_20KC:
Ralf Baechle505403b2005-02-07 21:53:39 +00001404 case CPU_25KF:
Paul Burton819da1e2016-08-19 18:13:34 +01001405 case CPU_I6400:
Paul Burton859aeb12017-06-02 12:39:04 -07001406 case CPU_I6500:
Ralf Baechle641e97f2007-10-11 23:46:05 +01001407 case CPU_SB1:
1408 case CPU_SB1A:
Jayachandran Cefa0f812011-05-07 01:36:21 +05301409 case CPU_XLR:
Atsushi Nemotode628932006-03-13 18:23:03 +09001410 c->dcache.flags |= MIPS_CACHE_PINDEX;
Ralf Baechle641e97f2007-10-11 23:46:05 +01001411 break;
1412
Ralf Baechled1e344e2005-02-04 15:51:26 +00001413 case CPU_R10000:
1414 case CPU_R12000:
Kumba44d921b2006-05-16 22:23:59 -04001415 case CPU_R14000:
Joshua Kinard30577392015-01-21 07:59:45 -05001416 case CPU_R16000:
Ralf Baechled1e344e2005-02-04 15:51:26 +00001417 break;
Ralf Baechle641e97f2007-10-11 23:46:05 +01001418
Maciej W. Rozyckibf4aac02014-06-28 23:28:08 +01001419 case CPU_74K:
1420 case CPU_1074K:
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001421 has_74k_erratum = alias_74k_erratum(c);
Liangliang Huangc9b02992020-05-04 16:51:29 +08001422 fallthrough;
Steven J. Hill113c62d2012-07-06 23:56:00 +02001423 case CPU_M14KC:
Steven J. Hillf8fa4812012-12-07 03:51:35 +00001424 case CPU_M14KEC:
Ralf Baechled1e344e2005-02-04 15:51:26 +00001425 case CPU_24K:
Nigel Stephens98a41de2006-04-27 15:50:32 +01001426 case CPU_34K:
Ralf Baechle39b8d522008-04-28 17:14:26 +01001427 case CPU_1004K:
Leonid Yegoshin26ab96d2013-11-27 10:07:53 +00001428 case CPU_INTERAPTIV:
James Hoganaced4cb2014-01-22 16:19:38 +00001429 case CPU_P5600:
Leonid Yegoshin708ac4b2013-11-14 16:12:27 +00001430 case CPU_PROAPTIV:
Leonid Yegoshinf36c4722014-03-04 13:34:43 +00001431 case CPU_M5150:
Leonid Yegoshin46950892014-11-24 12:59:01 +00001432 case CPU_QEMU_GENERIC:
Paul Burton1091bfa2016-02-03 03:26:38 +00001433 case CPU_P6600:
Paul Burton1dbf6a82016-02-03 16:17:29 +00001434 case CPU_M6250:
Markos Chandras02dc6bf2014-01-30 17:21:29 +00001435 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
1436 (c->icache.waysize > PAGE_SIZE))
1437 c->icache.flags |= MIPS_CACHE_ALIASES;
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001438 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) {
Markos Chandras02dc6bf2014-01-30 17:21:29 +00001439 /*
1440 * Effectively physically indexed dcache,
1441 * thus no virtual aliases.
1442 */
Ralf Baechlebeab3752006-06-19 21:56:25 +01001443 c->dcache.flags |= MIPS_CACHE_PINDEX;
1444 break;
1445 }
Liangliang Huangc9b02992020-05-04 16:51:29 +08001446 fallthrough;
Ralf Baechled1e344e2005-02-04 15:51:26 +00001447 default:
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001448 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
Ralf Baechlebeab3752006-06-19 21:56:25 +01001449 c->dcache.flags |= MIPS_CACHE_ALIASES;
Ralf Baechled1e344e2005-02-04 15:51:26 +00001450 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001451
Paul Burtond66f99b2016-08-19 18:13:35 +01001452 /* Physically indexed caches don't suffer from virtual aliasing */
1453 if (c->dcache.flags & MIPS_CACHE_PINDEX)
1454 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1455
Paul Burtond1c58722017-06-02 15:17:25 -07001456 /*
1457 * In systems with CM the icache fills from L2 or closer caches, and
1458 * thus sees remote stores without needing to write them back any
1459 * further than that.
1460 */
1461 if (mips_cm_present())
1462 c->icache.flags |= MIPS_IC_SNOOPS_REMOTE;
1463
Ralf Baechle69f24d12013-09-17 10:25:47 +02001464 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001465 case CPU_20KC:
1466 /*
1467 * Some older 20Kc chips doesn't have the 'VI' bit in
1468 * the config register.
1469 */
1470 c->icache.flags |= MIPS_CACHE_VTAG;
1471 break;
1472
Manuel Lauss270717a2009-03-25 17:49:28 +01001473 case CPU_ALCHEMY:
James Hogan47f2ac52016-01-22 10:58:26 +00001474 case CPU_I6400:
Paul Burton859aeb12017-06-02 12:39:04 -07001475 case CPU_I6500:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001476 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1477 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001478
Florian Fainellic130d2f2016-04-04 10:55:34 -07001479 case CPU_BMIPS5000:
1480 c->icache.flags |= MIPS_CACHE_IC_F_DC;
Florian Fainelli73c4ca0472016-04-04 10:55:35 -07001481 /* Cache aliases are handled in hardware; allow HIGHMEM */
1482 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
Florian Fainellic130d2f2016-04-04 10:55:34 -07001483 break;
1484
Jiaxun Yang268a2d62019-10-20 22:43:13 +08001485 case CPU_LOONGSON2EF:
Ralf Baechle14bd8c02013-09-25 18:21:26 +02001486 /*
1487 * LOONGSON2 has 4 way icache, but when using indexed cache op,
1488 * one op will act on all 4 ways
1489 */
1490 c->icache.ways = 1;
1491 }
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001492
Oleksij Rempelbea176f2020-02-28 06:52:38 +01001493 pr_info("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1494 icache_size >> 10,
1495 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1496 way_string[c->icache.ways], c->icache.linesz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001497
Oleksij Rempelbea176f2020-02-28 06:52:38 +01001498 pr_info("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1499 dcache_size >> 10, way_string[c->dcache.ways],
1500 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1501 (c->dcache.flags & MIPS_CACHE_ALIASES) ?
Ralf Baechle64bfca52007-10-15 16:35:45 +01001502 "cache aliases" : "no aliases",
Oleksij Rempelbea176f2020-02-28 06:52:38 +01001503 c->dcache.linesz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001504}
1505
Huacai Chenb2edcfc2016-03-03 09:45:09 +08001506static void probe_vcache(void)
1507{
1508 struct cpuinfo_mips *c = &current_cpu_data;
1509 unsigned int config2, lsize;
1510
Jiaxun Yang268a2d62019-10-20 22:43:13 +08001511 if (current_cpu_type() != CPU_LOONGSON64)
Huacai Chenb2edcfc2016-03-03 09:45:09 +08001512 return;
1513
1514 config2 = read_c0_config2();
1515 if ((lsize = ((config2 >> 20) & 15)))
1516 c->vcache.linesz = 2 << lsize;
1517 else
1518 c->vcache.linesz = lsize;
1519
1520 c->vcache.sets = 64 << ((config2 >> 24) & 15);
1521 c->vcache.ways = 1 + ((config2 >> 16) & 15);
1522
1523 vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz;
1524
1525 c->vcache.waybit = 0;
Huacai Chen0be032c2017-03-16 21:00:29 +08001526 c->vcache.waysize = vcache_size / c->vcache.ways;
Huacai Chenb2edcfc2016-03-03 09:45:09 +08001527
1528 pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n",
1529 vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz);
1530}
1531
Linus Torvalds1da177e2005-04-16 15:20:36 -07001532/*
1533 * If you even _breathe_ on this function, look at the gcc output and make sure
1534 * it does not pop things on and off the stack for the cache sizing loop that
1535 * executes in KSEG1 space or else you will crash and burn badly. You have
1536 * been warned.
1537 */
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001538static int probe_scache(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001539{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001540 unsigned long flags, addr, begin, end, pow2;
1541 unsigned int config = read_c0_config();
1542 struct cpuinfo_mips *c = &current_cpu_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001543
1544 if (config & CONF_SC)
1545 return 0;
1546
Ralf Baechlee001e522007-07-28 12:45:47 +01001547 begin = (unsigned long) &_stext;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001548 begin &= ~((4 * 1024 * 1024) - 1);
1549 end = begin + (4 * 1024 * 1024);
1550
1551 /*
1552 * This is such a bitch, you'd think they would make it easy to do
1553 * this. Away you daemons of stupidity!
1554 */
1555 local_irq_save(flags);
1556
1557 /* Fill each size-multiple cache line with a valid tag. */
1558 pow2 = (64 * 1024);
1559 for (addr = begin; addr < end; addr = (begin + pow2)) {
1560 unsigned long *p = (unsigned long *) addr;
1561 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1562 pow2 <<= 1;
1563 }
1564
1565 /* Load first line with zero (therefore invalid) tag. */
1566 write_c0_taglo(0);
1567 write_c0_taghi(0);
1568 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1569 cache_op(Index_Store_Tag_I, begin);
1570 cache_op(Index_Store_Tag_D, begin);
1571 cache_op(Index_Store_Tag_SD, begin);
1572
1573 /* Now search for the wrap around point. */
1574 pow2 = (128 * 1024);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001575 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1576 cache_op(Index_Load_Tag_SD, addr);
1577 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1578 if (!read_c0_taglo())
1579 break;
1580 pow2 <<= 1;
1581 }
1582 local_irq_restore(flags);
1583 addr -= begin;
1584
1585 scache_size = addr;
1586 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1587 c->scache.ways = 1;
Joshua Kinard755af332015-06-02 16:55:22 -04001588 c->scache.waybit = 0; /* does not matter */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001589
1590 return 1;
1591}
1592
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001593static void __init loongson2_sc_init(void)
1594{
1595 struct cpuinfo_mips *c = &current_cpu_data;
1596
1597 scache_size = 512*1024;
1598 c->scache.linesz = 32;
1599 c->scache.ways = 4;
1600 c->scache.waybit = 0;
1601 c->scache.waysize = scache_size / (c->scache.ways);
1602 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1603 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1604 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1605
1606 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1607}
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001608
Huacai Chenc579d312014-03-21 18:44:00 +08001609static void __init loongson3_sc_init(void)
1610{
1611 struct cpuinfo_mips *c = &current_cpu_data;
1612 unsigned int config2, lsize;
1613
1614 config2 = read_c0_config2();
1615 lsize = (config2 >> 4) & 15;
1616 if (lsize)
1617 c->scache.linesz = 2 << lsize;
1618 else
1619 c->scache.linesz = 0;
1620 c->scache.sets = 64 << ((config2 >> 8) & 15);
1621 c->scache.ways = 1 + (config2 & 15);
1622
1623 scache_size = c->scache.sets *
1624 c->scache.ways *
1625 c->scache.linesz;
Jiaxun Yang0cf2ea12020-04-22 22:43:44 +08001626
1627 /* Loongson-3 has 4-Scache banks, while Loongson-2K have only 2 banks */
1628 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
1629 scache_size *= 2;
1630 else
1631 scache_size *= 4;
1632
Huacai Chenc579d312014-03-21 18:44:00 +08001633 c->scache.waybit = 0;
Huacai Chen0be032c2017-03-16 21:00:29 +08001634 c->scache.waysize = scache_size / c->scache.ways;
Huacai Chenc579d312014-03-21 18:44:00 +08001635 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1636 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1637 if (scache_size)
1638 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1639 return;
1640}
1641
Linus Torvalds1da177e2005-04-16 15:20:36 -07001642extern int r5k_sc_init(void);
1643extern int rm7k_sc_init(void);
Chris Dearman9318c512006-06-20 17:15:20 +01001644extern int mips_sc_init(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001645
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001646static void setup_scache(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001647{
1648 struct cpuinfo_mips *c = &current_cpu_data;
1649 unsigned int config = read_c0_config();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001650 int sc_present = 0;
1651
1652 /*
1653 * Do the probing thing on R4000SC and R4400SC processors. Other
1654 * processors don't have a S-cache that would be relevant to the
Joe Perches603e82e2008-02-03 16:54:53 +02001655 * Linux memory management.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001656 */
Ralf Baechle69f24d12013-09-17 10:25:47 +02001657 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001658 case CPU_R4000SC:
1659 case CPU_R4000MC:
1660 case CPU_R4400SC:
1661 case CPU_R4400MC:
Thiemo Seuferba5187d2005-04-25 16:36:23 +00001662 sc_present = run_uncached(probe_scache);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001663 if (sc_present)
1664 c->options |= MIPS_CPU_CACHE_CDEX_S;
1665 break;
1666
1667 case CPU_R10000:
1668 case CPU_R12000:
Kumba44d921b2006-05-16 22:23:59 -04001669 case CPU_R14000:
Joshua Kinard30577392015-01-21 07:59:45 -05001670 case CPU_R16000:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001671 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1672 c->scache.linesz = 64 << ((config >> 13) & 1);
1673 c->scache.ways = 2;
1674 c->scache.waybit= 0;
1675 sc_present = 1;
1676 break;
1677
1678 case CPU_R5000:
1679 case CPU_NEVADA:
1680#ifdef CONFIG_R5000_CPU_SCACHE
1681 r5k_sc_init();
1682#endif
Ralf Baechle70342282013-01-22 12:59:30 +01001683 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001684
1685 case CPU_RM7000:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001686#ifdef CONFIG_RM7000_CPU_SCACHE
1687 rm7k_sc_init();
1688#endif
1689 return;
1690
Jiaxun Yang268a2d62019-10-20 22:43:13 +08001691 case CPU_LOONGSON2EF:
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001692 loongson2_sc_init();
1693 return;
Ralf Baechle14bd8c02013-09-25 18:21:26 +02001694
Jiaxun Yang268a2d62019-10-20 22:43:13 +08001695 case CPU_LOONGSON64:
Huacai Chenc579d312014-03-21 18:44:00 +08001696 loongson3_sc_init();
1697 return;
1698
David Daney18a8cd62014-05-28 23:52:09 +02001699 case CPU_CAVIUM_OCTEON3:
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001700 case CPU_XLP:
1701 /* don't need to worry about L2, fully coherent */
1702 return;
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001703
Linus Torvalds1da177e2005-04-16 15:20:36 -07001704 default:
Serge Seminab7c01f2020-05-21 17:07:14 +03001705 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
1706 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
1707 MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
1708 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
Chris Dearman9318c512006-06-20 17:15:20 +01001709#ifdef CONFIG_MIPS_CPU_SCACHE
1710 if (mips_sc_init ()) {
1711 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1712 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1713 scache_size >> 10,
1714 way_string[c->scache.ways], c->scache.linesz);
1715 }
1716#else
1717 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1718 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1719#endif
1720 return;
1721 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001722 sc_present = 0;
1723 }
1724
1725 if (!sc_present)
1726 return;
1727
Linus Torvalds1da177e2005-04-16 15:20:36 -07001728 /* compute a couple of other cache variables */
1729 c->scache.waysize = scache_size / c->scache.ways;
1730
1731 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1732
1733 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1734 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1735
Ralf Baechlefc5d2d22006-07-06 13:04:01 +01001736 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001737}
1738
Sergei Shtylyov9370b352006-05-26 19:44:54 +04001739void au1x00_fixup_config_od(void)
1740{
1741 /*
1742 * c0_config.od (bit 19) was write only (and read as 0)
1743 * on the early revisions of Alchemy SOCs. It disables the bus
1744 * transaction overlapping and needs to be set to fix various errata.
1745 */
1746 switch (read_c0_prid()) {
1747 case 0x00030100: /* Au1000 DA */
1748 case 0x00030201: /* Au1000 HA */
1749 case 0x00030202: /* Au1000 HB */
1750 case 0x01030200: /* Au1500 AB */
1751 /*
1752 * Au1100 errata actually keeps silence about this bit, so we set it
1753 * just in case for those revisions that require it to be set according
Manuel Lauss270717a2009-03-25 17:49:28 +01001754 * to the (now gone) cpu table.
Sergei Shtylyov9370b352006-05-26 19:44:54 +04001755 */
1756 case 0x02030200: /* Au1100 AB */
1757 case 0x02030201: /* Au1100 BA */
1758 case 0x02030202: /* Au1100 BC */
1759 set_c0_config(1 << 19);
1760 break;
1761 }
1762}
1763
Ralf Baechle89052bd2008-06-12 17:26:02 +01001764/* CP0 hazard avoidance. */
1765#define NXP_BARRIER() \
1766 __asm__ __volatile__( \
1767 ".set noreorder\n\t" \
1768 "nop; nop; nop; nop; nop; nop;\n\t" \
1769 ".set reorder\n\t")
1770
1771static void nxp_pr4450_fixup_config(void)
1772{
1773 unsigned long config0;
1774
1775 config0 = read_c0_config();
1776
1777 /* clear all three cache coherency fields */
1778 config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1779 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) |
1780 ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1781 ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1782 write_c0_config(config0);
1783 NXP_BARRIER();
1784}
1785
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001786static int cca = -1;
Chris Dearman35133692007-09-19 00:58:24 +01001787
1788static int __init cca_setup(char *str)
1789{
1790 get_option(&str, &cca);
1791
Shane McDonaldb5b64f22012-06-14 02:26:40 +00001792 return 0;
Chris Dearman35133692007-09-19 00:58:24 +01001793}
1794
Shane McDonaldb5b64f22012-06-14 02:26:40 +00001795early_param("cca", cca_setup);
Chris Dearman35133692007-09-19 00:58:24 +01001796
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001797static void coherency_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001798{
Chris Dearman35133692007-09-19 00:58:24 +01001799 if (cca < 0 || cca > 7)
1800 cca = read_c0_config() & CONF_CM_CMASK;
1801 _page_cachable_default = cca << _CACHE_SHIFT;
1802
1803 pr_debug("Using cache attribute %d\n", cca);
1804 change_c0_config(CONF_CM_CMASK, cca);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001805
1806 /*
1807 * c0_status.cu=0 specifies that updates by the sc instruction use
1808 * the coherency mode specified by the TLB; 1 means cachable
1809 * coherent update on write will be used. Not all processors have
1810 * this bit and; some wire it to zero, others like Toshiba had the
1811 * silly idea of putting something else there ...
1812 */
Ralf Baechle10cc3522007-10-11 23:46:15 +01001813 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001814 case CPU_R4000PC:
1815 case CPU_R4000SC:
1816 case CPU_R4000MC:
1817 case CPU_R4400PC:
1818 case CPU_R4400SC:
1819 case CPU_R4400MC:
1820 clear_c0_config(CONF_CU);
1821 break;
Sergei Shtylyov9370b352006-05-26 19:44:54 +04001822 /*
Ralf Baechledf586d52006-08-01 23:42:30 +01001823 * We need to catch the early Alchemy SOCs with
Manuel Lauss270717a2009-03-25 17:49:28 +01001824 * the write-only co_config.od bit and set it back to one on:
1825 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
Sergei Shtylyov9370b352006-05-26 19:44:54 +04001826 */
Manuel Lauss270717a2009-03-25 17:49:28 +01001827 case CPU_ALCHEMY:
Sergei Shtylyov9370b352006-05-26 19:44:54 +04001828 au1x00_fixup_config_od();
1829 break;
Ralf Baechle89052bd2008-06-12 17:26:02 +01001830
1831 case PRID_IMP_PR4450:
1832 nxp_pr4450_fixup_config();
1833 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001834 }
1835}
1836
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001837static void r4k_cache_error_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001838{
Ralf Baechle641e97f2007-10-11 23:46:05 +01001839 extern char __weak except_vec2_generic;
1840 extern char __weak except_vec2_sb1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001841
Ralf Baechle69f24d12013-09-17 10:25:47 +02001842 switch (current_cpu_type()) {
Ralf Baechle641e97f2007-10-11 23:46:05 +01001843 case CPU_SB1:
1844 case CPU_SB1A:
1845 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1846 break;
1847
1848 default:
1849 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1850 break;
1851 }
David Daney9cd9669b2012-05-15 00:04:49 -07001852}
1853
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001854void r4k_cache_init(void)
David Daney9cd9669b2012-05-15 00:04:49 -07001855{
1856 extern void build_clear_page(void);
1857 extern void build_copy_page(void);
1858 struct cpuinfo_mips *c = &current_cpu_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001859
1860 probe_pcache();
Huacai Chenb2edcfc2016-03-03 09:45:09 +08001861 probe_vcache();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001862 setup_scache();
1863
Linus Torvalds1da177e2005-04-16 15:20:36 -07001864 r4k_blast_dcache_page_setup();
1865 r4k_blast_dcache_page_indexed_setup();
1866 r4k_blast_dcache_setup();
1867 r4k_blast_icache_page_setup();
1868 r4k_blast_icache_page_indexed_setup();
1869 r4k_blast_icache_setup();
1870 r4k_blast_scache_page_setup();
1871 r4k_blast_scache_page_indexed_setup();
1872 r4k_blast_scache_setup();
Huacai Chenbb53fdf2018-11-15 15:53:53 +08001873 r4k_blast_scache_node_setup();
Leonid Yegoshin4caa9062014-01-15 14:47:28 +00001874#ifdef CONFIG_EVA
1875 r4k_blast_dcache_user_page_setup();
1876 r4k_blast_icache_user_page_setup();
1877#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001878
1879 /*
1880 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1881 * This code supports virtually indexed processors and will be
1882 * unnecessarily inefficient on physically indexed processors.
1883 */
Leonid Yegoshincb80b2a2015-11-19 17:38:21 -08001884 if (c->dcache.linesz && cpu_has_dc_aliases)
Chris Dearman73f40352006-06-20 18:06:52 +01001885 shm_align_mask = max_t( unsigned long,
1886 c->dcache.sets * c->dcache.linesz - 1,
1887 PAGE_SIZE - 1);
1888 else
1889 shm_align_mask = PAGE_SIZE-1;
Ralf Baechle9c5a3d72008-04-05 15:13:23 +01001890
1891 __flush_cache_vmap = r4k__flush_cache_vmap;
1892 __flush_cache_vunmap = r4k__flush_cache_vunmap;
1893
Ralf Baechledb813fe2007-09-27 18:26:43 +01001894 flush_cache_all = cache_noop;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001895 __flush_cache_all = r4k___flush_cache_all;
1896 flush_cache_mm = r4k_flush_cache_mm;
1897 flush_cache_page = r4k_flush_cache_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001898 flush_cache_range = r4k_flush_cache_range;
1899
Ralf Baechled9cdc9012011-06-17 16:20:28 +01001900 __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1901
Linus Torvalds1da177e2005-04-16 15:20:36 -07001902 flush_icache_all = r4k_flush_icache_all;
Ralf Baechle7e3bfc72006-04-05 20:42:04 +01001903 local_flush_data_cache_page = local_r4k_flush_data_cache_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001904 flush_data_cache_page = r4k_flush_data_cache_page;
1905 flush_icache_range = r4k_flush_icache_range;
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02001906 local_flush_icache_range = local_r4k_flush_icache_range;
James Hoganb2ff7172016-09-01 17:30:15 +01001907 __flush_icache_user_range = r4k_flush_icache_user_range;
1908 __local_flush_icache_user_range = local_r4k_flush_icache_user_range;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001909
Christoph Hellwig5748e1b2018-08-16 16:47:53 +03001910#ifdef CONFIG_DMA_NONCOHERENT
1911#ifdef CONFIG_DMA_MAYBE_COHERENT
1912 if (coherentio == IO_COHERENCE_ENABLED ||
1913 (coherentio == IO_COHERENCE_DEFAULT && hw_coherentio)) {
Ralf Baechle39b8d522008-04-28 17:14:26 +01001914 _dma_cache_wback_inv = (void *)cache_noop;
1915 _dma_cache_wback = (void *)cache_noop;
1916 _dma_cache_inv = (void *)cache_noop;
Christoph Hellwig5748e1b2018-08-16 16:47:53 +03001917 } else
1918#endif /* CONFIG_DMA_MAYBE_COHERENT */
1919 {
Ralf Baechle39b8d522008-04-28 17:14:26 +01001920 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1921 _dma_cache_wback = r4k_dma_cache_wback_inv;
1922 _dma_cache_inv = r4k_dma_cache_inv;
1923 }
Christoph Hellwig5748e1b2018-08-16 16:47:53 +03001924#endif /* CONFIG_DMA_NONCOHERENT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001925
Linus Torvalds1da177e2005-04-16 15:20:36 -07001926 build_clear_page();
1927 build_copy_page();
Steven J. Hillb6d92b42013-03-25 13:47:29 -05001928
1929 /*
1930 * We want to run CMP kernels on core with and without coherent
1931 * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1932 * or not to flush caches.
1933 */
Ralf Baechle1d40cfc2005-07-15 15:23:23 +00001934 local_r4k___flush_cache_all(NULL);
Steven J. Hillb6d92b42013-03-25 13:47:29 -05001935
Ralf Baechle1d40cfc2005-07-15 15:23:23 +00001936 coherency_setup();
David Daney9cd9669b2012-05-15 00:04:49 -07001937 board_cache_error_setup = r4k_cache_error_setup;
Kevin Cernekeed74b0172014-10-20 21:28:00 -07001938
1939 /*
1940 * Per-CPU overrides
1941 */
1942 switch (current_cpu_type()) {
1943 case CPU_BMIPS4350:
1944 case CPU_BMIPS4380:
1945 /* No IPI is needed because all CPUs share the same D$ */
1946 flush_data_cache_page = r4k_blast_dcache_page;
1947 break;
1948 case CPU_BMIPS5000:
1949 /* We lose our superpowers if L2 is disabled */
1950 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
1951 break;
1952
1953 /* I$ fills from D$ just by emptying the write buffers */
1954 flush_cache_page = (void *)b5k_instruction_hazard;
1955 flush_cache_range = (void *)b5k_instruction_hazard;
Kevin Cernekeed74b0172014-10-20 21:28:00 -07001956 local_flush_data_cache_page = (void *)b5k_instruction_hazard;
1957 flush_data_cache_page = (void *)b5k_instruction_hazard;
1958 flush_icache_range = (void *)b5k_instruction_hazard;
1959 local_flush_icache_range = (void *)b5k_instruction_hazard;
1960
Kevin Cernekeed74b0172014-10-20 21:28:00 -07001961
1962 /* Optimization: an L2 flush implicitly flushes the L1 */
1963 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
1964 break;
Jiaxun Yang268a2d62019-10-20 22:43:13 +08001965 case CPU_LOONGSON64:
Huacai Chen37fbe8f2016-03-03 09:45:10 +08001966 /* Loongson-3 maintains cache coherency by hardware */
1967 __flush_cache_all = cache_noop;
1968 __flush_cache_vmap = cache_noop;
1969 __flush_cache_vunmap = cache_noop;
1970 __flush_kernel_vmap_range = (void *)cache_noop;
1971 flush_cache_mm = (void *)cache_noop;
1972 flush_cache_page = (void *)cache_noop;
1973 flush_cache_range = (void *)cache_noop;
Huacai Chen37fbe8f2016-03-03 09:45:10 +08001974 flush_icache_all = (void *)cache_noop;
1975 flush_data_cache_page = (void *)cache_noop;
1976 local_flush_data_cache_page = (void *)cache_noop;
1977 break;
Kevin Cernekeed74b0172014-10-20 21:28:00 -07001978 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001979}
James Hogan61d73042014-03-04 10:23:57 +00001980
1981static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
1982 void *v)
1983{
1984 switch (cmd) {
1985 case CPU_PM_ENTER_FAILED:
1986 case CPU_PM_EXIT:
1987 coherency_setup();
1988 break;
1989 }
1990
1991 return NOTIFY_OK;
1992}
1993
1994static struct notifier_block r4k_cache_pm_notifier_block = {
1995 .notifier_call = r4k_cache_pm_notifier,
1996};
1997
1998int __init r4k_cache_init_pm(void)
1999{
2000 return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block);
2001}
2002arch_initcall(r4k_cache_init_pm);