Jeff Kirsher | ae06c70 | 2018-03-22 10:08:48 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Jeff Kirsher | 51dce24 | 2018-04-26 08:08:09 -0700 | [diff] [blame] | 2 | /* Copyright(c) 1999 - 2018 Intel Corporation. */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4 | /* 82562G 10/100 Network Connection |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5 | * 82562G-2 10/100 Network Connection |
| 6 | * 82562GT 10/100 Network Connection |
| 7 | * 82562GT-2 10/100 Network Connection |
| 8 | * 82562V 10/100 Network Connection |
| 9 | * 82562V-2 10/100 Network Connection |
| 10 | * 82566DC-2 Gigabit Network Connection |
| 11 | * 82566DC Gigabit Network Connection |
| 12 | * 82566DM-2 Gigabit Network Connection |
| 13 | * 82566DM Gigabit Network Connection |
| 14 | * 82566MC Gigabit Network Connection |
| 15 | * 82566MM Gigabit Network Connection |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 16 | * 82567LM Gigabit Network Connection |
| 17 | * 82567LF Gigabit Network Connection |
Bruce Allan | 1605927f | 2008-11-21 16:51:06 -0800 | [diff] [blame] | 18 | * 82567V Gigabit Network Connection |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 19 | * 82567LM-2 Gigabit Network Connection |
| 20 | * 82567LF-2 Gigabit Network Connection |
| 21 | * 82567V-2 Gigabit Network Connection |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 22 | * 82567LF-3 Gigabit Network Connection |
| 23 | * 82567LM-3 Gigabit Network Connection |
Bruce Allan | 2f15f9d | 2008-08-26 18:36:36 -0700 | [diff] [blame] | 24 | * 82567LM-4 Gigabit Network Connection |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 25 | * 82577LM Gigabit Network Connection |
| 26 | * 82577LC Gigabit Network Connection |
| 27 | * 82578DM Gigabit Network Connection |
| 28 | * 82578DC Gigabit Network Connection |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 29 | * 82579LM Gigabit Network Connection |
| 30 | * 82579V Gigabit Network Connection |
David Ertman | 3b70d4f | 2014-02-05 01:09:54 +0000 | [diff] [blame] | 31 | * Ethernet Connection I217-LM |
| 32 | * Ethernet Connection I217-V |
| 33 | * Ethernet Connection I218-V |
| 34 | * Ethernet Connection I218-LM |
| 35 | * Ethernet Connection (2) I218-LM |
| 36 | * Ethernet Connection (2) I218-V |
| 37 | * Ethernet Connection (3) I218-LM |
| 38 | * Ethernet Connection (3) I218-V |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 39 | */ |
| 40 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 41 | #include "e1000.h" |
| 42 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 43 | /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ |
| 44 | /* Offset 04h HSFSTS */ |
| 45 | union ich8_hws_flash_status { |
| 46 | struct ich8_hsfsts { |
Bruce Allan | 362e20c | 2013-02-20 04:05:45 +0000 | [diff] [blame] | 47 | u16 flcdone:1; /* bit 0 Flash Cycle Done */ |
| 48 | u16 flcerr:1; /* bit 1 Flash Cycle Error */ |
| 49 | u16 dael:1; /* bit 2 Direct Access error Log */ |
| 50 | u16 berasesz:2; /* bit 4:3 Sector Erase Size */ |
| 51 | u16 flcinprog:1; /* bit 5 flash cycle in Progress */ |
| 52 | u16 reserved1:2; /* bit 13:6 Reserved */ |
| 53 | u16 reserved2:6; /* bit 13:6 Reserved */ |
| 54 | u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ |
| 55 | u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 56 | } hsf_status; |
| 57 | u16 regval; |
| 58 | }; |
| 59 | |
| 60 | /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ |
| 61 | /* Offset 06h FLCTL */ |
| 62 | union ich8_hws_flash_ctrl { |
| 63 | struct ich8_hsflctl { |
Bruce Allan | 362e20c | 2013-02-20 04:05:45 +0000 | [diff] [blame] | 64 | u16 flcgo:1; /* 0 Flash Cycle Go */ |
| 65 | u16 flcycle:2; /* 2:1 Flash Cycle */ |
| 66 | u16 reserved:5; /* 7:3 Reserved */ |
| 67 | u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ |
| 68 | u16 flockdn:6; /* 15:10 Reserved */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 69 | } hsf_ctrl; |
| 70 | u16 regval; |
| 71 | }; |
| 72 | |
| 73 | /* ICH Flash Region Access Permissions */ |
| 74 | union ich8_hws_flash_regacc { |
| 75 | struct ich8_flracc { |
Bruce Allan | 362e20c | 2013-02-20 04:05:45 +0000 | [diff] [blame] | 76 | u32 grra:8; /* 0:7 GbE region Read Access */ |
| 77 | u32 grwa:8; /* 8:15 GbE region Write Access */ |
| 78 | u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ |
| 79 | u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 80 | } hsf_flregacc; |
| 81 | u16 regval; |
| 82 | }; |
| 83 | |
Bruce Allan | 4a77035 | 2008-10-01 17:18:35 -0700 | [diff] [blame] | 84 | /* ICH Flash Protected Region */ |
| 85 | union ich8_flash_protected_range { |
| 86 | struct ich8_pr { |
Bruce Allan | e80bd1d | 2013-05-01 01:19:46 +0000 | [diff] [blame] | 87 | u32 base:13; /* 0:12 Protected Range Base */ |
| 88 | u32 reserved1:2; /* 13:14 Reserved */ |
| 89 | u32 rpe:1; /* 15 Read Protection Enable */ |
| 90 | u32 limit:13; /* 16:28 Protected Range Limit */ |
| 91 | u32 reserved2:2; /* 29:30 Reserved */ |
| 92 | u32 wpe:1; /* 31 Write Protection Enable */ |
Bruce Allan | 4a77035 | 2008-10-01 17:18:35 -0700 | [diff] [blame] | 93 | } range; |
| 94 | u32 regval; |
| 95 | }; |
| 96 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 97 | static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); |
| 98 | static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 99 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); |
| 100 | static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, |
| 101 | u32 offset, u8 byte); |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 102 | static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, |
| 103 | u8 *data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 104 | static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, |
| 105 | u16 *data); |
| 106 | static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, |
| 107 | u8 size, u16 *data); |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 108 | static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, |
| 109 | u32 *data); |
| 110 | static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, |
| 111 | u32 offset, u32 *data); |
| 112 | static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, |
| 113 | u32 offset, u32 data); |
| 114 | static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, |
| 115 | u32 offset, u32 dword); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 116 | static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 117 | static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); |
| 118 | static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); |
| 119 | static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); |
| 120 | static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); |
| 121 | static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); |
| 122 | static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); |
| 123 | static s32 e1000_led_on_pchlan(struct e1000_hw *hw); |
| 124 | static s32 e1000_led_off_pchlan(struct e1000_hw *hw); |
Bruce Allan | fa2ce13 | 2009-10-26 11:23:25 +0000 | [diff] [blame] | 125 | static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); |
Bruce Allan | 17f208d | 2009-12-01 15:47:22 +0000 | [diff] [blame] | 126 | static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 127 | static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); |
Bruce Allan | 1f96012d | 2013-01-05 03:06:54 +0000 | [diff] [blame] | 128 | static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); |
Bruce Allan | fddaa1a | 2010-01-13 01:52:49 +0000 | [diff] [blame] | 129 | static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); |
Bruce Allan | eb7700d | 2010-06-16 13:27:05 +0000 | [diff] [blame] | 130 | static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); |
| 131 | static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); |
David Ertman | b3e5bf1 | 2014-05-06 03:50:17 +0000 | [diff] [blame] | 132 | static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); |
| 133 | static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); |
| 134 | static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw); |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 135 | static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); |
Bruce Allan | 605c82b | 2010-09-22 17:17:01 +0000 | [diff] [blame] | 136 | static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 137 | static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); |
Bruce Allan | ea8179a | 2013-03-06 09:02:47 +0000 | [diff] [blame] | 138 | static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 139 | static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 140 | |
| 141 | static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) |
| 142 | { |
| 143 | return readw(hw->flash_address + reg); |
| 144 | } |
| 145 | |
| 146 | static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) |
| 147 | { |
| 148 | return readl(hw->flash_address + reg); |
| 149 | } |
| 150 | |
| 151 | static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) |
| 152 | { |
| 153 | writew(val, hw->flash_address + reg); |
| 154 | } |
| 155 | |
| 156 | static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) |
| 157 | { |
| 158 | writel(val, hw->flash_address + reg); |
| 159 | } |
| 160 | |
| 161 | #define er16flash(reg) __er16flash(hw, (reg)) |
| 162 | #define er32flash(reg) __er32flash(hw, (reg)) |
Bruce Allan | 0e15df4 | 2012-01-31 06:37:11 +0000 | [diff] [blame] | 163 | #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) |
| 164 | #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 165 | |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 166 | /** |
| 167 | * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers |
| 168 | * @hw: pointer to the HW structure |
| 169 | * |
| 170 | * Test access to the PHY registers by reading the PHY ID registers. If |
| 171 | * the PHY ID is already known (e.g. resume path) compare it with known ID, |
| 172 | * otherwise assume the read PHY ID is correct if it is valid. |
| 173 | * |
| 174 | * Assumes the sw/fw/hw semaphore is already acquired. |
| 175 | **/ |
| 176 | static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 177 | { |
Bruce Allan | a52359b | 2012-07-14 04:23:58 +0000 | [diff] [blame] | 178 | u16 phy_reg = 0; |
| 179 | u32 phy_id = 0; |
David Ertman | 2c98262 | 2014-05-01 02:19:03 +0000 | [diff] [blame] | 180 | s32 ret_val = 0; |
Bruce Allan | a52359b | 2012-07-14 04:23:58 +0000 | [diff] [blame] | 181 | u16 retry_count; |
Bruce Allan | 16b095a | 2013-06-29 07:42:39 +0000 | [diff] [blame] | 182 | u32 mac_reg = 0; |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 183 | |
Bruce Allan | a52359b | 2012-07-14 04:23:58 +0000 | [diff] [blame] | 184 | for (retry_count = 0; retry_count < 2; retry_count++) { |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 185 | ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); |
Bruce Allan | a52359b | 2012-07-14 04:23:58 +0000 | [diff] [blame] | 186 | if (ret_val || (phy_reg == 0xFFFF)) |
| 187 | continue; |
| 188 | phy_id = (u32)(phy_reg << 16); |
| 189 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 190 | ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); |
Bruce Allan | a52359b | 2012-07-14 04:23:58 +0000 | [diff] [blame] | 191 | if (ret_val || (phy_reg == 0xFFFF)) { |
| 192 | phy_id = 0; |
| 193 | continue; |
| 194 | } |
| 195 | phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); |
| 196 | break; |
| 197 | } |
Bruce Allan | 62bc813 | 2012-03-20 03:47:57 +0000 | [diff] [blame] | 198 | |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 199 | if (hw->phy.id) { |
| 200 | if (hw->phy.id == phy_id) |
Bruce Allan | 16b095a | 2013-06-29 07:42:39 +0000 | [diff] [blame] | 201 | goto out; |
Bruce Allan | a52359b | 2012-07-14 04:23:58 +0000 | [diff] [blame] | 202 | } else if (phy_id) { |
| 203 | hw->phy.id = phy_id; |
| 204 | hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); |
Bruce Allan | 16b095a | 2013-06-29 07:42:39 +0000 | [diff] [blame] | 205 | goto out; |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 206 | } |
| 207 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 208 | /* In case the PHY needs to be in mdio slow mode, |
Bruce Allan | a52359b | 2012-07-14 04:23:58 +0000 | [diff] [blame] | 209 | * set slow mode and try to get the PHY id again. |
| 210 | */ |
David Ertman | 2c98262 | 2014-05-01 02:19:03 +0000 | [diff] [blame] | 211 | if (hw->mac.type < e1000_pch_lpt) { |
| 212 | hw->phy.ops.release(hw); |
| 213 | ret_val = e1000_set_mdio_slow_mode_hv(hw); |
| 214 | if (!ret_val) |
| 215 | ret_val = e1000e_get_phy_id(hw); |
| 216 | hw->phy.ops.acquire(hw); |
| 217 | } |
Bruce Allan | a52359b | 2012-07-14 04:23:58 +0000 | [diff] [blame] | 218 | |
Bruce Allan | 16b095a | 2013-06-29 07:42:39 +0000 | [diff] [blame] | 219 | if (ret_val) |
| 220 | return false; |
| 221 | out: |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 222 | if (hw->mac.type >= e1000_pch_lpt) { |
Yanir Lubetkin | beee807 | 2015-06-10 01:15:51 +0300 | [diff] [blame] | 223 | /* Only unforce SMBus if ME is not active */ |
| 224 | if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { |
Vitaly Lifshits | 6dbdd4d | 2024-01-04 16:16:52 +0200 | [diff] [blame] | 225 | /* Switching PHY interface always returns MDI error |
| 226 | * so disable retry mechanism to avoid wasting time |
| 227 | */ |
| 228 | e1000e_disable_phy_retry(hw); |
| 229 | |
Yanir Lubetkin | beee807 | 2015-06-10 01:15:51 +0300 | [diff] [blame] | 230 | /* Unforce SMBus mode in PHY */ |
| 231 | e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); |
| 232 | phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; |
| 233 | e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); |
Bruce Allan | 16b095a | 2013-06-29 07:42:39 +0000 | [diff] [blame] | 234 | |
Vitaly Lifshits | 6dbdd4d | 2024-01-04 16:16:52 +0200 | [diff] [blame] | 235 | e1000e_enable_phy_retry(hw); |
| 236 | |
Yanir Lubetkin | beee807 | 2015-06-10 01:15:51 +0300 | [diff] [blame] | 237 | /* Unforce SMBus mode in MAC */ |
| 238 | mac_reg = er32(CTRL_EXT); |
| 239 | mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; |
| 240 | ew32(CTRL_EXT, mac_reg); |
| 241 | } |
Bruce Allan | 16b095a | 2013-06-29 07:42:39 +0000 | [diff] [blame] | 242 | } |
| 243 | |
| 244 | return true; |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 245 | } |
| 246 | |
| 247 | /** |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 248 | * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value |
| 249 | * @hw: pointer to the HW structure |
| 250 | * |
| 251 | * Toggling the LANPHYPC pin value fully power-cycles the PHY and is |
| 252 | * used to reset the PHY to a quiescent state when necessary. |
| 253 | **/ |
| 254 | static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) |
| 255 | { |
| 256 | u32 mac_reg; |
| 257 | |
| 258 | /* Set Phy Config Counter to 50msec */ |
| 259 | mac_reg = er32(FEXTNVM3); |
| 260 | mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; |
| 261 | mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; |
| 262 | ew32(FEXTNVM3, mac_reg); |
| 263 | |
| 264 | /* Toggle LANPHYPC Value bit */ |
| 265 | mac_reg = er32(CTRL); |
| 266 | mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; |
| 267 | mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; |
| 268 | ew32(CTRL, mac_reg); |
| 269 | e1e_flush(); |
| 270 | usleep_range(10, 20); |
| 271 | mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; |
| 272 | ew32(CTRL, mac_reg); |
| 273 | e1e_flush(); |
| 274 | |
| 275 | if (hw->mac.type < e1000_pch_lpt) { |
| 276 | msleep(50); |
| 277 | } else { |
| 278 | u16 count = 20; |
| 279 | |
| 280 | do { |
Arjan van de Ven | ab6973a | 2019-06-14 17:29:35 -0700 | [diff] [blame] | 281 | usleep_range(5000, 6000); |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 282 | } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); |
| 283 | |
| 284 | msleep(30); |
| 285 | } |
| 286 | } |
| 287 | |
| 288 | /** |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 289 | * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds |
| 290 | * @hw: pointer to the HW structure |
| 291 | * |
| 292 | * Workarounds/flow necessary for PHY initialization during driver load |
| 293 | * and resume paths. |
| 294 | **/ |
| 295 | static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) |
| 296 | { |
David Ertman | f7235ef6 | 2014-01-23 06:29:13 +0000 | [diff] [blame] | 297 | struct e1000_adapter *adapter = hw->adapter; |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 298 | u32 mac_reg, fwsm = er32(FWSM); |
| 299 | s32 ret_val; |
| 300 | |
Bruce Allan | 6e928b7 | 2012-12-12 04:45:51 +0000 | [diff] [blame] | 301 | /* Gate automatic PHY configuration by hardware on managed and |
| 302 | * non-managed 82579 and newer adapters. |
| 303 | */ |
| 304 | e1000_gate_hw_phy_config_ich8lan(hw, true); |
| 305 | |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 306 | /* It is not possible to be certain of the current state of ULP |
| 307 | * so forcibly disable it. |
| 308 | */ |
| 309 | hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; |
Kai-Heng Feng | 0c80cdb | 2020-05-07 14:25:45 +0800 | [diff] [blame] | 310 | ret_val = e1000_disable_ulp_lpt_lp(hw, true); |
Aaron Ma | 1050242 | 2020-06-18 14:54:53 +0800 | [diff] [blame] | 311 | if (ret_val) |
Kai-Heng Feng | 0c80cdb | 2020-05-07 14:25:45 +0800 | [diff] [blame] | 312 | e_warn("Failed to disable ULP\n"); |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 313 | |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 314 | ret_val = hw->phy.ops.acquire(hw); |
| 315 | if (ret_val) { |
| 316 | e_dbg("Failed to initialize PHY flow\n"); |
Bruce Allan | 6e928b7 | 2012-12-12 04:45:51 +0000 | [diff] [blame] | 317 | goto out; |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 318 | } |
| 319 | |
Vitaly Lifshits | 6dbdd4d | 2024-01-04 16:16:52 +0200 | [diff] [blame] | 320 | /* There is no guarantee that the PHY is accessible at this time |
| 321 | * so disable retry mechanism to avoid wasting time |
| 322 | */ |
| 323 | e1000e_disable_phy_retry(hw); |
| 324 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 325 | /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 326 | * inaccessible and resetting the PHY is not blocked, toggle the |
| 327 | * LANPHYPC Value bit to force the interconnect to PCIe mode. |
| 328 | */ |
| 329 | switch (hw->mac.type) { |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 330 | case e1000_pch_lpt: |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 331 | case e1000_pch_spt: |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 332 | case e1000_pch_cnp: |
Sasha Neftin | fb776f5 | 2019-10-16 11:08:38 +0300 | [diff] [blame] | 333 | case e1000_pch_tgp: |
Sasha Neftin | 59e4668 | 2020-01-19 13:57:13 +0200 | [diff] [blame] | 334 | case e1000_pch_adp: |
Sasha Neftin | cc23f4f | 2020-08-13 11:34:06 +0300 | [diff] [blame] | 335 | case e1000_pch_mtp: |
Sasha Neftin | 820b8ff | 2021-03-04 09:38:13 +0200 | [diff] [blame] | 336 | case e1000_pch_lnp: |
Sasha Neftin | 0c9183c | 2022-09-29 11:08:59 +0300 | [diff] [blame] | 337 | case e1000_pch_ptp: |
Sasha Neftin | 1fe4f45 | 2023-07-18 19:28:57 +0300 | [diff] [blame] | 338 | case e1000_pch_nvp: |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 339 | if (e1000_phy_is_accessible_pchlan(hw)) |
| 340 | break; |
| 341 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 342 | /* Before toggling LANPHYPC, see if PHY is accessible by |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 343 | * forcing MAC to SMBus mode first. |
| 344 | */ |
| 345 | mac_reg = er32(CTRL_EXT); |
| 346 | mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; |
| 347 | ew32(CTRL_EXT, mac_reg); |
| 348 | |
Bruce Allan | 16b095a | 2013-06-29 07:42:39 +0000 | [diff] [blame] | 349 | /* Wait 50 milliseconds for MAC to finish any retries |
| 350 | * that it might be trying to perform from previous |
| 351 | * attempts to acknowledge any phy read requests. |
| 352 | */ |
| 353 | msleep(50); |
| 354 | |
Jeff Kirsher | 5463fce6 | 2020-06-03 20:07:26 -0700 | [diff] [blame] | 355 | fallthrough; |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 356 | case e1000_pch2lan: |
Bruce Allan | 16b095a | 2013-06-29 07:42:39 +0000 | [diff] [blame] | 357 | if (e1000_phy_is_accessible_pchlan(hw)) |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 358 | break; |
| 359 | |
Jeff Kirsher | 5463fce6 | 2020-06-03 20:07:26 -0700 | [diff] [blame] | 360 | fallthrough; |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 361 | case e1000_pchlan: |
| 362 | if ((hw->mac.type == e1000_pchlan) && |
| 363 | (fwsm & E1000_ICH_FWSM_FW_VALID)) |
| 364 | break; |
| 365 | |
| 366 | if (hw->phy.ops.check_reset_block(hw)) { |
| 367 | e_dbg("Required LANPHYPC toggle blocked by ME\n"); |
Bruce Allan | 16b095a | 2013-06-29 07:42:39 +0000 | [diff] [blame] | 368 | ret_val = -E1000_ERR_PHY; |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 369 | break; |
| 370 | } |
| 371 | |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 372 | /* Toggle LANPHYPC Value bit */ |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 373 | e1000_toggle_lanphypc_pch_lpt(hw); |
| 374 | if (hw->mac.type >= e1000_pch_lpt) { |
Bruce Allan | 16b095a | 2013-06-29 07:42:39 +0000 | [diff] [blame] | 375 | if (e1000_phy_is_accessible_pchlan(hw)) |
| 376 | break; |
| 377 | |
| 378 | /* Toggling LANPHYPC brings the PHY out of SMBus mode |
| 379 | * so ensure that the MAC is also out of SMBus mode |
| 380 | */ |
| 381 | mac_reg = er32(CTRL_EXT); |
| 382 | mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; |
| 383 | ew32(CTRL_EXT, mac_reg); |
| 384 | |
| 385 | if (e1000_phy_is_accessible_pchlan(hw)) |
| 386 | break; |
| 387 | |
| 388 | ret_val = -E1000_ERR_PHY; |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 389 | } |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 390 | break; |
| 391 | default: |
| 392 | break; |
| 393 | } |
| 394 | |
Vitaly Lifshits | 6dbdd4d | 2024-01-04 16:16:52 +0200 | [diff] [blame] | 395 | e1000e_enable_phy_retry(hw); |
| 396 | |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 397 | hw->phy.ops.release(hw); |
Bruce Allan | 16b095a | 2013-06-29 07:42:39 +0000 | [diff] [blame] | 398 | if (!ret_val) { |
David Ertman | f7235ef6 | 2014-01-23 06:29:13 +0000 | [diff] [blame] | 399 | |
| 400 | /* Check to see if able to reset PHY. Print error if not */ |
| 401 | if (hw->phy.ops.check_reset_block(hw)) { |
| 402 | e_err("Reset blocked by ME\n"); |
| 403 | goto out; |
| 404 | } |
| 405 | |
Bruce Allan | 16b095a | 2013-06-29 07:42:39 +0000 | [diff] [blame] | 406 | /* Reset the PHY before any access to it. Doing so, ensures |
| 407 | * that the PHY is in a known good state before we read/write |
| 408 | * PHY registers. The generic reset is sufficient here, |
| 409 | * because we haven't determined the PHY type yet. |
| 410 | */ |
| 411 | ret_val = e1000e_phy_hw_reset_generic(hw); |
David Ertman | f7235ef6 | 2014-01-23 06:29:13 +0000 | [diff] [blame] | 412 | if (ret_val) |
| 413 | goto out; |
| 414 | |
| 415 | /* On a successful reset, possibly need to wait for the PHY |
| 416 | * to quiesce to an accessible state before returning control |
| 417 | * to the calling function. If the PHY does not quiesce, then |
| 418 | * return E1000E_BLK_PHY_RESET, as this is the condition that |
| 419 | * the PHY is in. |
| 420 | */ |
| 421 | ret_val = hw->phy.ops.check_reset_block(hw); |
| 422 | if (ret_val) |
| 423 | e_err("ME blocked access to PHY after reset\n"); |
Bruce Allan | 16b095a | 2013-06-29 07:42:39 +0000 | [diff] [blame] | 424 | } |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 425 | |
Bruce Allan | 6e928b7 | 2012-12-12 04:45:51 +0000 | [diff] [blame] | 426 | out: |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 427 | /* Ungate automatic PHY configuration on non-managed 82579 */ |
| 428 | if ((hw->mac.type == e1000_pch2lan) && |
| 429 | !(fwsm & E1000_ICH_FWSM_FW_VALID)) { |
Arjan van de Ven | ab6973a | 2019-06-14 17:29:35 -0700 | [diff] [blame] | 430 | usleep_range(10000, 11000); |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 431 | e1000_gate_hw_phy_config_ich8lan(hw, false); |
| 432 | } |
| 433 | |
| 434 | return ret_val; |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 435 | } |
| 436 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 437 | /** |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 438 | * e1000_init_phy_params_pchlan - Initialize PHY function pointers |
| 439 | * @hw: pointer to the HW structure |
| 440 | * |
| 441 | * Initialize family-specific PHY parameters and function pointers. |
| 442 | **/ |
| 443 | static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) |
| 444 | { |
| 445 | struct e1000_phy_info *phy = &hw->phy; |
Bruce Allan | 70806a7 | 2013-01-05 05:08:37 +0000 | [diff] [blame] | 446 | s32 ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 447 | |
Bruce Allan | e80bd1d | 2013-05-01 01:19:46 +0000 | [diff] [blame] | 448 | phy->addr = 1; |
| 449 | phy->reset_delay_us = 100; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 450 | |
Bruce Allan | e80bd1d | 2013-05-01 01:19:46 +0000 | [diff] [blame] | 451 | phy->ops.set_page = e1000_set_page_igp; |
| 452 | phy->ops.read_reg = e1000_read_phy_reg_hv; |
| 453 | phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; |
| 454 | phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; |
| 455 | phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; |
| 456 | phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; |
| 457 | phy->ops.write_reg = e1000_write_phy_reg_hv; |
| 458 | phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; |
| 459 | phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; |
| 460 | phy->ops.power_up = e1000_power_up_phy_copper; |
| 461 | phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; |
| 462 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 463 | |
| 464 | phy->id = e1000_phy_unknown; |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 465 | |
Vitaly Lifshits | 6dbdd4d | 2024-01-04 16:16:52 +0200 | [diff] [blame] | 466 | if (hw->mac.type == e1000_pch_mtp) { |
| 467 | phy->retry_count = 2; |
| 468 | e1000e_enable_phy_retry(hw); |
| 469 | } |
| 470 | |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 471 | ret_val = e1000_init_phy_workarounds_pchlan(hw); |
| 472 | if (ret_val) |
| 473 | return ret_val; |
| 474 | |
| 475 | if (phy->id == e1000_phy_unknown) |
| 476 | switch (hw->mac.type) { |
| 477 | default: |
| 478 | ret_val = e1000e_get_phy_id(hw); |
| 479 | if (ret_val) |
| 480 | return ret_val; |
| 481 | if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) |
| 482 | break; |
Jeff Kirsher | 5463fce6 | 2020-06-03 20:07:26 -0700 | [diff] [blame] | 483 | fallthrough; |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 484 | case e1000_pch2lan: |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 485 | case e1000_pch_lpt: |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 486 | case e1000_pch_spt: |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 487 | case e1000_pch_cnp: |
Sasha Neftin | fb776f5 | 2019-10-16 11:08:38 +0300 | [diff] [blame] | 488 | case e1000_pch_tgp: |
Sasha Neftin | 59e4668 | 2020-01-19 13:57:13 +0200 | [diff] [blame] | 489 | case e1000_pch_adp: |
Sasha Neftin | cc23f4f | 2020-08-13 11:34:06 +0300 | [diff] [blame] | 490 | case e1000_pch_mtp: |
Sasha Neftin | 820b8ff | 2021-03-04 09:38:13 +0200 | [diff] [blame] | 491 | case e1000_pch_lnp: |
Sasha Neftin | 0c9183c | 2022-09-29 11:08:59 +0300 | [diff] [blame] | 492 | case e1000_pch_ptp: |
Sasha Neftin | 1fe4f45 | 2023-07-18 19:28:57 +0300 | [diff] [blame] | 493 | case e1000_pch_nvp: |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 494 | /* In case the PHY needs to be in mdio slow mode, |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 495 | * set slow mode and try to get the PHY id again. |
| 496 | */ |
| 497 | ret_val = e1000_set_mdio_slow_mode_hv(hw); |
| 498 | if (ret_val) |
| 499 | return ret_val; |
| 500 | ret_val = e1000e_get_phy_id(hw); |
| 501 | if (ret_val) |
| 502 | return ret_val; |
Bruce Allan | 664dc87 | 2010-11-24 06:01:46 +0000 | [diff] [blame] | 503 | break; |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 504 | } |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 505 | phy->type = e1000e_get_phy_type_from_id(phy->id); |
| 506 | |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 507 | switch (phy->type) { |
| 508 | case e1000_phy_82577: |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 509 | case e1000_phy_82579: |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 510 | case e1000_phy_i217: |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 511 | phy->ops.check_polarity = e1000_check_polarity_82577; |
| 512 | phy->ops.force_speed_duplex = |
Bruce Allan | 6cc7aae | 2011-02-25 06:25:18 +0000 | [diff] [blame] | 513 | e1000_phy_force_speed_duplex_82577; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 514 | phy->ops.get_cable_length = e1000_get_cable_length_82577; |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 515 | phy->ops.get_info = e1000_get_phy_info_82577; |
| 516 | phy->ops.commit = e1000e_phy_sw_reset; |
Bruce Allan | eab50ff | 2010-05-10 15:01:30 +0000 | [diff] [blame] | 517 | break; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 518 | case e1000_phy_82578: |
| 519 | phy->ops.check_polarity = e1000_check_polarity_m88; |
| 520 | phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; |
| 521 | phy->ops.get_cable_length = e1000e_get_cable_length_m88; |
| 522 | phy->ops.get_info = e1000e_get_phy_info_m88; |
| 523 | break; |
| 524 | default: |
| 525 | ret_val = -E1000_ERR_PHY; |
| 526 | break; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 527 | } |
| 528 | |
| 529 | return ret_val; |
| 530 | } |
| 531 | |
| 532 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 533 | * e1000_init_phy_params_ich8lan - Initialize PHY function pointers |
| 534 | * @hw: pointer to the HW structure |
| 535 | * |
| 536 | * Initialize family-specific PHY parameters and function pointers. |
| 537 | **/ |
| 538 | static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) |
| 539 | { |
| 540 | struct e1000_phy_info *phy = &hw->phy; |
| 541 | s32 ret_val; |
| 542 | u16 i = 0; |
| 543 | |
Bruce Allan | e80bd1d | 2013-05-01 01:19:46 +0000 | [diff] [blame] | 544 | phy->addr = 1; |
| 545 | phy->reset_delay_us = 100; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 546 | |
Bruce Allan | e80bd1d | 2013-05-01 01:19:46 +0000 | [diff] [blame] | 547 | phy->ops.power_up = e1000_power_up_phy_copper; |
| 548 | phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; |
Bruce Allan | 17f208d | 2009-12-01 15:47:22 +0000 | [diff] [blame] | 549 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 550 | /* We may need to do this twice - once for IGP and if that fails, |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 551 | * we'll set BM func pointers and try again |
| 552 | */ |
| 553 | ret_val = e1000e_determine_phy_address(hw); |
| 554 | if (ret_val) { |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 555 | phy->ops.write_reg = e1000e_write_phy_reg_bm; |
Bruce Allan | e80bd1d | 2013-05-01 01:19:46 +0000 | [diff] [blame] | 556 | phy->ops.read_reg = e1000e_read_phy_reg_bm; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 557 | ret_val = e1000e_determine_phy_address(hw); |
Bruce Allan | 9b71b41 | 2009-12-01 15:53:07 +0000 | [diff] [blame] | 558 | if (ret_val) { |
| 559 | e_dbg("Cannot determine PHY addr. Erroring out\n"); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 560 | return ret_val; |
Bruce Allan | 9b71b41 | 2009-12-01 15:53:07 +0000 | [diff] [blame] | 561 | } |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 562 | } |
| 563 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 564 | phy->id = 0; |
| 565 | while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && |
| 566 | (i++ < 100)) { |
Arjan van de Ven | ab6973a | 2019-06-14 17:29:35 -0700 | [diff] [blame] | 567 | usleep_range(1000, 1100); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 568 | ret_val = e1000e_get_phy_id(hw); |
| 569 | if (ret_val) |
| 570 | return ret_val; |
| 571 | } |
| 572 | |
| 573 | /* Verify phy id */ |
| 574 | switch (phy->id) { |
| 575 | case IGP03E1000_E_PHY_ID: |
| 576 | phy->type = e1000_phy_igp_3; |
| 577 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 578 | phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; |
| 579 | phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 580 | phy->ops.get_info = e1000e_get_phy_info_igp; |
| 581 | phy->ops.check_polarity = e1000_check_polarity_igp; |
| 582 | phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 583 | break; |
| 584 | case IFE_E_PHY_ID: |
| 585 | case IFE_PLUS_E_PHY_ID: |
| 586 | case IFE_C_E_PHY_ID: |
| 587 | phy->type = e1000_phy_ife; |
| 588 | phy->autoneg_mask = E1000_ALL_NOT_GIG; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 589 | phy->ops.get_info = e1000_get_phy_info_ife; |
| 590 | phy->ops.check_polarity = e1000_check_polarity_ife; |
| 591 | phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 592 | break; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 593 | case BME1000_E_PHY_ID: |
| 594 | phy->type = e1000_phy_bm; |
| 595 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 596 | phy->ops.read_reg = e1000e_read_phy_reg_bm; |
| 597 | phy->ops.write_reg = e1000e_write_phy_reg_bm; |
| 598 | phy->ops.commit = e1000e_phy_sw_reset; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 599 | phy->ops.get_info = e1000e_get_phy_info_m88; |
| 600 | phy->ops.check_polarity = e1000_check_polarity_m88; |
| 601 | phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 602 | break; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 603 | default: |
| 604 | return -E1000_ERR_PHY; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 605 | } |
| 606 | |
| 607 | return 0; |
| 608 | } |
| 609 | |
| 610 | /** |
| 611 | * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers |
| 612 | * @hw: pointer to the HW structure |
| 613 | * |
| 614 | * Initialize family-specific NVM parameters and function |
| 615 | * pointers. |
| 616 | **/ |
| 617 | static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) |
| 618 | { |
| 619 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 620 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
Bruce Allan | 148675a | 2009-08-07 07:41:56 +0000 | [diff] [blame] | 621 | u32 gfpreg, sector_base_addr, sector_end_addr; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 622 | u16 i; |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 623 | u32 nvm_size; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 624 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 625 | nvm->type = e1000_nvm_flash_sw; |
Yanir Lubetkin | 9d17ce4 | 2015-02-28 10:09:34 +0000 | [diff] [blame] | 626 | |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 627 | if (hw->mac.type >= e1000_pch_spt) { |
Yanir Lubetkin | 9d17ce4 | 2015-02-28 10:09:34 +0000 | [diff] [blame] | 628 | /* in SPT, gfpreg doesn't exist. NVM size is taken from the |
| 629 | * STRAP register. This is because in SPT the GbE Flash region |
| 630 | * is no longer accessed through the flash registers. Instead, |
| 631 | * the mechanism has changed, and the Flash region access |
| 632 | * registers are now implemented in GbE memory space. |
| 633 | */ |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 634 | nvm->flash_base_addr = 0; |
| 635 | nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1) |
| 636 | * NVM_SIZE_MULTIPLIER; |
| 637 | nvm->flash_bank_size = nvm_size / 2; |
| 638 | /* Adjust to word count */ |
| 639 | nvm->flash_bank_size /= sizeof(u16); |
| 640 | /* Set the base address for flash register access */ |
| 641 | hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; |
| 642 | } else { |
Yanir Lubetkin | 9d17ce4 | 2015-02-28 10:09:34 +0000 | [diff] [blame] | 643 | /* Can't read flash registers if register set isn't mapped. */ |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 644 | if (!hw->flash_address) { |
| 645 | e_dbg("ERROR: Flash registers not mapped\n"); |
| 646 | return -E1000_ERR_CONFIG; |
| 647 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 648 | |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 649 | gfpreg = er32flash(ICH_FLASH_GFPREG); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 650 | |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 651 | /* sector_X_addr is a "sector"-aligned address (4096 bytes) |
| 652 | * Add 1 to sector_end_addr since this sector is included in |
| 653 | * the overall size. |
| 654 | */ |
| 655 | sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; |
| 656 | sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; |
| 657 | |
| 658 | /* flash_base_addr is byte-aligned */ |
| 659 | nvm->flash_base_addr = sector_base_addr |
| 660 | << FLASH_SECTOR_ADDR_SHIFT; |
| 661 | |
| 662 | /* find total size of the NVM, then cut in half since the total |
| 663 | * size represents two separate NVM banks. |
| 664 | */ |
| 665 | nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) |
| 666 | << FLASH_SECTOR_ADDR_SHIFT); |
| 667 | nvm->flash_bank_size /= 2; |
| 668 | /* Adjust to word count */ |
| 669 | nvm->flash_bank_size /= sizeof(u16); |
| 670 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 671 | |
| 672 | nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; |
| 673 | |
| 674 | /* Clear shadow ram */ |
| 675 | for (i = 0; i < nvm->word_size; i++) { |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 676 | dev_spec->shadow_ram[i].modified = false; |
Bruce Allan | e80bd1d | 2013-05-01 01:19:46 +0000 | [diff] [blame] | 677 | dev_spec->shadow_ram[i].value = 0xFFFF; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 678 | } |
| 679 | |
| 680 | return 0; |
| 681 | } |
| 682 | |
| 683 | /** |
| 684 | * e1000_init_mac_params_ich8lan - Initialize MAC function pointers |
| 685 | * @hw: pointer to the HW structure |
| 686 | * |
| 687 | * Initialize family-specific MAC parameters and function |
| 688 | * pointers. |
| 689 | **/ |
Bruce Allan | ec34c17 | 2012-02-01 10:53:05 +0000 | [diff] [blame] | 690 | static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 691 | { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 692 | struct e1000_mac_info *mac = &hw->mac; |
| 693 | |
| 694 | /* Set media type function pointer */ |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 695 | hw->phy.media_type = e1000_media_type_copper; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 696 | |
| 697 | /* Set mta register count */ |
| 698 | mac->mta_reg_count = 32; |
| 699 | /* Set rar entry count */ |
| 700 | mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; |
| 701 | if (mac->type == e1000_ich8lan) |
| 702 | mac->rar_entry_count--; |
Bruce Allan | a65a4a0 | 2010-05-10 15:01:51 +0000 | [diff] [blame] | 703 | /* FWSM register */ |
| 704 | mac->has_fwsm = true; |
| 705 | /* ARC subsystem not supported */ |
| 706 | mac->arc_subsystem_valid = false; |
Bruce Allan | f464ba8 | 2010-01-07 16:31:35 +0000 | [diff] [blame] | 707 | /* Adaptive IFS supported */ |
| 708 | mac->adaptive_ifs = true; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 709 | |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 710 | /* LED and other operations */ |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 711 | switch (mac->type) { |
| 712 | case e1000_ich8lan: |
| 713 | case e1000_ich9lan: |
| 714 | case e1000_ich10lan: |
Bruce Allan | eb7700d | 2010-06-16 13:27:05 +0000 | [diff] [blame] | 715 | /* check management mode */ |
| 716 | mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 717 | /* ID LED init */ |
Bruce Allan | d1964eb | 2012-02-22 09:02:21 +0000 | [diff] [blame] | 718 | mac->ops.id_led_init = e1000e_id_led_init_generic; |
Bruce Allan | dbf80dc | 2011-04-16 00:34:40 +0000 | [diff] [blame] | 719 | /* blink LED */ |
| 720 | mac->ops.blink_led = e1000e_blink_led_generic; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 721 | /* setup LED */ |
| 722 | mac->ops.setup_led = e1000e_setup_led_generic; |
| 723 | /* cleanup LED */ |
| 724 | mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; |
| 725 | /* turn on/off LED */ |
| 726 | mac->ops.led_on = e1000_led_on_ich8lan; |
| 727 | mac->ops.led_off = e1000_led_off_ich8lan; |
| 728 | break; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 729 | case e1000_pch2lan: |
Bruce Allan | 69e1e01 | 2012-04-14 03:28:50 +0000 | [diff] [blame] | 730 | mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; |
| 731 | mac->ops.rar_set = e1000_rar_set_pch2lan; |
Jeff Kirsher | 5463fce6 | 2020-06-03 20:07:26 -0700 | [diff] [blame] | 732 | fallthrough; |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 733 | case e1000_pch_lpt: |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 734 | case e1000_pch_spt: |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 735 | case e1000_pch_cnp: |
Sasha Neftin | fb776f5 | 2019-10-16 11:08:38 +0300 | [diff] [blame] | 736 | case e1000_pch_tgp: |
Sasha Neftin | 59e4668 | 2020-01-19 13:57:13 +0200 | [diff] [blame] | 737 | case e1000_pch_adp: |
Sasha Neftin | cc23f4f | 2020-08-13 11:34:06 +0300 | [diff] [blame] | 738 | case e1000_pch_mtp: |
Sasha Neftin | 820b8ff | 2021-03-04 09:38:13 +0200 | [diff] [blame] | 739 | case e1000_pch_lnp: |
Sasha Neftin | 0c9183c | 2022-09-29 11:08:59 +0300 | [diff] [blame] | 740 | case e1000_pch_ptp: |
Sasha Neftin | 1fe4f45 | 2023-07-18 19:28:57 +0300 | [diff] [blame] | 741 | case e1000_pch_nvp: |
Bruce Allan | 69e1e01 | 2012-04-14 03:28:50 +0000 | [diff] [blame] | 742 | case e1000_pchlan: |
Bruce Allan | eb7700d | 2010-06-16 13:27:05 +0000 | [diff] [blame] | 743 | /* check management mode */ |
| 744 | mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 745 | /* ID LED init */ |
| 746 | mac->ops.id_led_init = e1000_id_led_init_pchlan; |
| 747 | /* setup LED */ |
| 748 | mac->ops.setup_led = e1000_setup_led_pchlan; |
| 749 | /* cleanup LED */ |
| 750 | mac->ops.cleanup_led = e1000_cleanup_led_pchlan; |
| 751 | /* turn on/off LED */ |
| 752 | mac->ops.led_on = e1000_led_on_pchlan; |
| 753 | mac->ops.led_off = e1000_led_off_pchlan; |
| 754 | break; |
| 755 | default: |
| 756 | break; |
| 757 | } |
| 758 | |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 759 | if (mac->type >= e1000_pch_lpt) { |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 760 | mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; |
| 761 | mac->ops.rar_set = e1000_rar_set_pch_lpt; |
Bruce Allan | ea8179a | 2013-03-06 09:02:47 +0000 | [diff] [blame] | 762 | mac->ops.setup_physical_interface = |
| 763 | e1000_setup_copper_link_pch_lpt; |
David Ertman | b3e5bf1 | 2014-05-06 03:50:17 +0000 | [diff] [blame] | 764 | mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 765 | } |
| 766 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 767 | /* Enable PCS Lock-loss workaround for ICH8 */ |
| 768 | if (mac->type == e1000_ich8lan) |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 769 | e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 770 | |
| 771 | return 0; |
| 772 | } |
| 773 | |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 774 | /** |
Bruce Allan | 4ddc48a | 2012-12-05 06:25:58 +0000 | [diff] [blame] | 775 | * __e1000_access_emi_reg_locked - Read/write EMI register |
| 776 | * @hw: pointer to the HW structure |
Jesse Brandeburg | b50f7bc | 2020-09-25 15:24:37 -0700 | [diff] [blame] | 777 | * @address: EMI address to program |
Bruce Allan | 4ddc48a | 2012-12-05 06:25:58 +0000 | [diff] [blame] | 778 | * @data: pointer to value to read/write from/to the EMI address |
| 779 | * @read: boolean flag to indicate read or write |
| 780 | * |
| 781 | * This helper function assumes the SW/FW/HW Semaphore is already acquired. |
| 782 | **/ |
| 783 | static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, |
| 784 | u16 *data, bool read) |
| 785 | { |
Bruce Allan | 70806a7 | 2013-01-05 05:08:37 +0000 | [diff] [blame] | 786 | s32 ret_val; |
Bruce Allan | 4ddc48a | 2012-12-05 06:25:58 +0000 | [diff] [blame] | 787 | |
| 788 | ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); |
| 789 | if (ret_val) |
| 790 | return ret_val; |
| 791 | |
| 792 | if (read) |
| 793 | ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); |
| 794 | else |
| 795 | ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); |
| 796 | |
| 797 | return ret_val; |
| 798 | } |
| 799 | |
| 800 | /** |
| 801 | * e1000_read_emi_reg_locked - Read Extended Management Interface register |
| 802 | * @hw: pointer to the HW structure |
| 803 | * @addr: EMI address to program |
| 804 | * @data: value to be read from the EMI address |
| 805 | * |
| 806 | * Assumes the SW/FW/HW Semaphore is already acquired. |
| 807 | **/ |
Bruce Allan | 203e4151 | 2012-12-05 08:40:59 +0000 | [diff] [blame] | 808 | s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) |
Bruce Allan | 4ddc48a | 2012-12-05 06:25:58 +0000 | [diff] [blame] | 809 | { |
| 810 | return __e1000_access_emi_reg_locked(hw, addr, data, true); |
| 811 | } |
| 812 | |
| 813 | /** |
| 814 | * e1000_write_emi_reg_locked - Write Extended Management Interface register |
| 815 | * @hw: pointer to the HW structure |
| 816 | * @addr: EMI address to program |
| 817 | * @data: value to be written to the EMI address |
| 818 | * |
| 819 | * Assumes the SW/FW/HW Semaphore is already acquired. |
| 820 | **/ |
Bruce Allan | d495bcb | 2013-03-20 07:23:11 +0000 | [diff] [blame] | 821 | s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) |
Bruce Allan | 4ddc48a | 2012-12-05 06:25:58 +0000 | [diff] [blame] | 822 | { |
| 823 | return __e1000_access_emi_reg_locked(hw, addr, &data, false); |
| 824 | } |
| 825 | |
| 826 | /** |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 827 | * e1000_set_eee_pchlan - Enable/disable EEE support |
| 828 | * @hw: pointer to the HW structure |
| 829 | * |
Bruce Allan | 3d4d575 | 2012-12-05 06:26:08 +0000 | [diff] [blame] | 830 | * Enable/disable EEE based on setting in dev_spec structure, the duplex of |
| 831 | * the link and the EEE capabilities of the link partner. The LPI Control |
| 832 | * register bits will remain set only if/when link is up. |
David Ertman | a03206e | 2014-01-24 23:07:48 +0000 | [diff] [blame] | 833 | * |
| 834 | * EEE LPI must not be asserted earlier than one second after link is up. |
| 835 | * On 82579, EEE LPI should not be enabled until such time otherwise there |
| 836 | * can be link issues with some switches. Other devices can have EEE LPI |
| 837 | * enabled immediately upon link up since they have a timer in hardware which |
| 838 | * prevents LPI from being asserted too early. |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 839 | **/ |
David Ertman | a03206e | 2014-01-24 23:07:48 +0000 | [diff] [blame] | 840 | s32 e1000_set_eee_pchlan(struct e1000_hw *hw) |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 841 | { |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 842 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
Bruce Allan | 3d4d575 | 2012-12-05 06:26:08 +0000 | [diff] [blame] | 843 | s32 ret_val; |
Bruce Allan | d495bcb | 2013-03-20 07:23:11 +0000 | [diff] [blame] | 844 | u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 845 | |
Bruce Allan | d495bcb | 2013-03-20 07:23:11 +0000 | [diff] [blame] | 846 | switch (hw->phy.type) { |
| 847 | case e1000_phy_82579: |
| 848 | lpa = I82579_EEE_LP_ABILITY; |
| 849 | pcs_status = I82579_EEE_PCS_STATUS; |
| 850 | adv_addr = I82579_EEE_ADVERTISEMENT; |
| 851 | break; |
| 852 | case e1000_phy_i217: |
| 853 | lpa = I217_EEE_LP_ABILITY; |
| 854 | pcs_status = I217_EEE_PCS_STATUS; |
| 855 | adv_addr = I217_EEE_ADVERTISEMENT; |
| 856 | break; |
| 857 | default: |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 858 | return 0; |
Bruce Allan | d495bcb | 2013-03-20 07:23:11 +0000 | [diff] [blame] | 859 | } |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 860 | |
Bruce Allan | 3d4d575 | 2012-12-05 06:26:08 +0000 | [diff] [blame] | 861 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 862 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 863 | return ret_val; |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 864 | |
Bruce Allan | 3d4d575 | 2012-12-05 06:26:08 +0000 | [diff] [blame] | 865 | ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 866 | if (ret_val) |
Bruce Allan | 3d4d575 | 2012-12-05 06:26:08 +0000 | [diff] [blame] | 867 | goto release; |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 868 | |
Bruce Allan | 3d4d575 | 2012-12-05 06:26:08 +0000 | [diff] [blame] | 869 | /* Clear bits that enable EEE in various speeds */ |
| 870 | lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; |
| 871 | |
| 872 | /* Enable EEE if not disabled by user */ |
| 873 | if (!dev_spec->eee_disable) { |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 874 | /* Save off link partner's EEE ability */ |
Bruce Allan | 3d4d575 | 2012-12-05 06:26:08 +0000 | [diff] [blame] | 875 | ret_val = e1000_read_emi_reg_locked(hw, lpa, |
Bruce Allan | 4ddc48a | 2012-12-05 06:25:58 +0000 | [diff] [blame] | 876 | &dev_spec->eee_lp_ability); |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 877 | if (ret_val) |
| 878 | goto release; |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 879 | |
Bruce Allan | d495bcb | 2013-03-20 07:23:11 +0000 | [diff] [blame] | 880 | /* Read EEE advertisement */ |
| 881 | ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); |
| 882 | if (ret_val) |
| 883 | goto release; |
| 884 | |
Bruce Allan | 3d4d575 | 2012-12-05 06:26:08 +0000 | [diff] [blame] | 885 | /* Enable EEE only for speeds in which the link partner is |
Bruce Allan | d495bcb | 2013-03-20 07:23:11 +0000 | [diff] [blame] | 886 | * EEE capable and for which we advertise EEE. |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 887 | */ |
Bruce Allan | d495bcb | 2013-03-20 07:23:11 +0000 | [diff] [blame] | 888 | if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) |
Bruce Allan | 3d4d575 | 2012-12-05 06:26:08 +0000 | [diff] [blame] | 889 | lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; |
| 890 | |
Bruce Allan | d495bcb | 2013-03-20 07:23:11 +0000 | [diff] [blame] | 891 | if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 892 | e1e_rphy_locked(hw, MII_LPA, &data); |
| 893 | if (data & LPA_100FULL) |
Bruce Allan | 3d4d575 | 2012-12-05 06:26:08 +0000 | [diff] [blame] | 894 | lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; |
| 895 | else |
| 896 | /* EEE is not supported in 100Half, so ignore |
| 897 | * partner's EEE in 100 ability if full-duplex |
| 898 | * is not advertised. |
| 899 | */ |
| 900 | dev_spec->eee_lp_ability &= |
| 901 | ~I82579_EEE_100_SUPPORTED; |
| 902 | } |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 903 | } |
| 904 | |
David Ertman | 7142a55 | 2014-05-01 01:22:26 +0000 | [diff] [blame] | 905 | if (hw->phy.type == e1000_phy_82579) { |
| 906 | ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, |
| 907 | &data); |
| 908 | if (ret_val) |
| 909 | goto release; |
| 910 | |
| 911 | data &= ~I82579_LPI_100_PLL_SHUT; |
| 912 | ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, |
| 913 | data); |
| 914 | } |
| 915 | |
Bruce Allan | d495bcb | 2013-03-20 07:23:11 +0000 | [diff] [blame] | 916 | /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ |
| 917 | ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); |
| 918 | if (ret_val) |
| 919 | goto release; |
| 920 | |
Bruce Allan | 3d4d575 | 2012-12-05 06:26:08 +0000 | [diff] [blame] | 921 | ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); |
| 922 | release: |
| 923 | hw->phy.ops.release(hw); |
| 924 | |
| 925 | return ret_val; |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 926 | } |
| 927 | |
| 928 | /** |
Bruce Allan | e08f626 | 2013-02-20 03:06:34 +0000 | [diff] [blame] | 929 | * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP |
| 930 | * @hw: pointer to the HW structure |
| 931 | * @link: link up bool flag |
| 932 | * |
| 933 | * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications |
| 934 | * preventing further DMA write requests. Workaround the issue by disabling |
| 935 | * the de-assertion of the clock request when in 1Gpbs mode. |
Bruce Allan | e0236ad | 2013-06-21 09:07:13 +0000 | [diff] [blame] | 936 | * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link |
| 937 | * speeds in order to avoid Tx hangs. |
Bruce Allan | e08f626 | 2013-02-20 03:06:34 +0000 | [diff] [blame] | 938 | **/ |
| 939 | static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) |
| 940 | { |
| 941 | u32 fextnvm6 = er32(FEXTNVM6); |
Bruce Allan | e0236ad | 2013-06-21 09:07:13 +0000 | [diff] [blame] | 942 | u32 status = er32(STATUS); |
Bruce Allan | e08f626 | 2013-02-20 03:06:34 +0000 | [diff] [blame] | 943 | s32 ret_val = 0; |
Bruce Allan | e0236ad | 2013-06-21 09:07:13 +0000 | [diff] [blame] | 944 | u16 reg; |
Bruce Allan | e08f626 | 2013-02-20 03:06:34 +0000 | [diff] [blame] | 945 | |
Bruce Allan | e0236ad | 2013-06-21 09:07:13 +0000 | [diff] [blame] | 946 | if (link && (status & E1000_STATUS_SPEED_1000)) { |
Bruce Allan | e08f626 | 2013-02-20 03:06:34 +0000 | [diff] [blame] | 947 | ret_val = hw->phy.ops.acquire(hw); |
| 948 | if (ret_val) |
| 949 | return ret_val; |
| 950 | |
| 951 | ret_val = |
| 952 | e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, |
Bruce Allan | e0236ad | 2013-06-21 09:07:13 +0000 | [diff] [blame] | 953 | ®); |
Bruce Allan | e08f626 | 2013-02-20 03:06:34 +0000 | [diff] [blame] | 954 | if (ret_val) |
| 955 | goto release; |
| 956 | |
| 957 | ret_val = |
| 958 | e1000e_write_kmrn_reg_locked(hw, |
| 959 | E1000_KMRNCTRLSTA_K1_CONFIG, |
Bruce Allan | e0236ad | 2013-06-21 09:07:13 +0000 | [diff] [blame] | 960 | reg & |
Bruce Allan | e08f626 | 2013-02-20 03:06:34 +0000 | [diff] [blame] | 961 | ~E1000_KMRNCTRLSTA_K1_ENABLE); |
| 962 | if (ret_val) |
| 963 | goto release; |
| 964 | |
| 965 | usleep_range(10, 20); |
| 966 | |
| 967 | ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); |
| 968 | |
| 969 | ret_val = |
| 970 | e1000e_write_kmrn_reg_locked(hw, |
| 971 | E1000_KMRNCTRLSTA_K1_CONFIG, |
Bruce Allan | e0236ad | 2013-06-21 09:07:13 +0000 | [diff] [blame] | 972 | reg); |
Bruce Allan | e08f626 | 2013-02-20 03:06:34 +0000 | [diff] [blame] | 973 | release: |
| 974 | hw->phy.ops.release(hw); |
| 975 | } else { |
| 976 | /* clear FEXTNVM6 bit 8 on link down or 10/100 */ |
Bruce Allan | e0236ad | 2013-06-21 09:07:13 +0000 | [diff] [blame] | 977 | fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; |
| 978 | |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 979 | if ((hw->phy.revision > 5) || !link || |
| 980 | ((status & E1000_STATUS_SPEED_100) && |
| 981 | (status & E1000_STATUS_FD))) |
Bruce Allan | e0236ad | 2013-06-21 09:07:13 +0000 | [diff] [blame] | 982 | goto update_fextnvm6; |
| 983 | |
| 984 | ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®); |
| 985 | if (ret_val) |
| 986 | return ret_val; |
| 987 | |
| 988 | /* Clear link status transmit timeout */ |
| 989 | reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; |
| 990 | |
| 991 | if (status & E1000_STATUS_SPEED_100) { |
| 992 | /* Set inband Tx timeout to 5x10us for 100Half */ |
| 993 | reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; |
| 994 | |
| 995 | /* Do not extend the K1 entry latency for 100Half */ |
| 996 | fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; |
| 997 | } else { |
| 998 | /* Set inband Tx timeout to 50x10us for 10Full/Half */ |
| 999 | reg |= 50 << |
| 1000 | I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; |
| 1001 | |
| 1002 | /* Extend the K1 entry latency for 10 Mbps */ |
| 1003 | fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; |
| 1004 | } |
| 1005 | |
| 1006 | ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg); |
| 1007 | if (ret_val) |
| 1008 | return ret_val; |
| 1009 | |
| 1010 | update_fextnvm6: |
| 1011 | ew32(FEXTNVM6, fextnvm6); |
Bruce Allan | e08f626 | 2013-02-20 03:06:34 +0000 | [diff] [blame] | 1012 | } |
| 1013 | |
| 1014 | return ret_val; |
| 1015 | } |
| 1016 | |
| 1017 | /** |
Bruce Allan | cf8fb73 | 2013-03-06 09:03:02 +0000 | [diff] [blame] | 1018 | * e1000_platform_pm_pch_lpt - Set platform power management values |
| 1019 | * @hw: pointer to the HW structure |
| 1020 | * @link: bool indicating link status |
| 1021 | * |
| 1022 | * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" |
| 1023 | * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed |
| 1024 | * when link is up (which must not exceed the maximum latency supported |
| 1025 | * by the platform), otherwise specify there is no LTR requirement. |
| 1026 | * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop |
| 1027 | * latencies in the LTR Extended Capability Structure in the PCIe Extended |
| 1028 | * Capability register set, on this device LTR is set by writing the |
| 1029 | * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and |
| 1030 | * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) |
| 1031 | * message to the PMC. |
| 1032 | **/ |
| 1033 | static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) |
| 1034 | { |
| 1035 | u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | |
| 1036 | link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; |
Sasha Neftin | 04ebaa1 | 2022-04-05 18:56:01 +0300 | [diff] [blame] | 1037 | u32 max_ltr_enc_d = 0; /* maximum LTR decoded by platform */ |
| 1038 | u32 lat_enc_d = 0; /* latency decoded */ |
Bruce Allan | cf8fb73 | 2013-03-06 09:03:02 +0000 | [diff] [blame] | 1039 | u16 lat_enc = 0; /* latency encoded */ |
| 1040 | |
| 1041 | if (link) { |
| 1042 | u16 speed, duplex, scale = 0; |
| 1043 | u16 max_snoop, max_nosnoop; |
| 1044 | u16 max_ltr_enc; /* max LTR latency encoded */ |
Jeff Kirsher | 30544af | 2015-05-02 01:20:04 -0700 | [diff] [blame] | 1045 | u64 value; |
Bruce Allan | cf8fb73 | 2013-03-06 09:03:02 +0000 | [diff] [blame] | 1046 | u32 rxa; |
| 1047 | |
| 1048 | if (!hw->adapter->max_frame_size) { |
| 1049 | e_dbg("max_frame_size not set.\n"); |
| 1050 | return -E1000_ERR_CONFIG; |
| 1051 | } |
| 1052 | |
| 1053 | hw->mac.ops.get_link_up_info(hw, &speed, &duplex); |
| 1054 | if (!speed) { |
| 1055 | e_dbg("Speed not set.\n"); |
| 1056 | return -E1000_ERR_CONFIG; |
| 1057 | } |
| 1058 | |
| 1059 | /* Rx Packet Buffer Allocation size (KB) */ |
| 1060 | rxa = er32(PBA) & E1000_PBA_RXA_MASK; |
| 1061 | |
| 1062 | /* Determine the maximum latency tolerated by the device. |
| 1063 | * |
| 1064 | * Per the PCIe spec, the tolerated latencies are encoded as |
| 1065 | * a 3-bit encoded scale (only 0-5 are valid) multiplied by |
| 1066 | * a 10-bit value (0-1023) to provide a range from 1 ns to |
| 1067 | * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, |
| 1068 | * 1=2^5ns, 2=2^10ns,...5=2^25ns. |
| 1069 | */ |
Yanir Lubetkin | bfc9473 | 2015-04-22 05:55:43 +0300 | [diff] [blame] | 1070 | rxa *= 512; |
| 1071 | value = (rxa > hw->adapter->max_frame_size) ? |
| 1072 | (rxa - hw->adapter->max_frame_size) * (16000 / speed) : |
| 1073 | 0; |
Bruce Allan | cf8fb73 | 2013-03-06 09:03:02 +0000 | [diff] [blame] | 1074 | |
Bruce Allan | cf8fb73 | 2013-03-06 09:03:02 +0000 | [diff] [blame] | 1075 | while (value > PCI_LTR_VALUE_MASK) { |
| 1076 | scale++; |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 1077 | value = DIV_ROUND_UP(value, BIT(5)); |
Bruce Allan | cf8fb73 | 2013-03-06 09:03:02 +0000 | [diff] [blame] | 1078 | } |
| 1079 | if (scale > E1000_LTRV_SCALE_MAX) { |
| 1080 | e_dbg("Invalid LTR latency scale %d\n", scale); |
| 1081 | return -E1000_ERR_CONFIG; |
| 1082 | } |
| 1083 | lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value); |
| 1084 | |
| 1085 | /* Determine the maximum latency tolerated by the platform */ |
| 1086 | pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, |
| 1087 | &max_snoop); |
| 1088 | pci_read_config_word(hw->adapter->pdev, |
| 1089 | E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); |
| 1090 | max_ltr_enc = max_t(u16, max_snoop, max_nosnoop); |
| 1091 | |
Sasha Neftin | 44a13a5 | 2021-07-04 10:11:41 +0300 | [diff] [blame] | 1092 | lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) * |
| 1093 | (1U << (E1000_LTRV_SCALE_FACTOR * |
Jesse Brandeburg | b9a4525 | 2023-12-05 17:01:08 -0800 | [diff] [blame] | 1094 | FIELD_GET(E1000_LTRV_SCALE_MASK, lat_enc))); |
Sasha Neftin | 44a13a5 | 2021-07-04 10:11:41 +0300 | [diff] [blame] | 1095 | |
| 1096 | max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) * |
Jesse Brandeburg | b9a4525 | 2023-12-05 17:01:08 -0800 | [diff] [blame] | 1097 | (1U << (E1000_LTRV_SCALE_FACTOR * |
| 1098 | FIELD_GET(E1000_LTRV_SCALE_MASK, max_ltr_enc))); |
Sasha Neftin | 44a13a5 | 2021-07-04 10:11:41 +0300 | [diff] [blame] | 1099 | |
| 1100 | if (lat_enc_d > max_ltr_enc_d) |
Bruce Allan | cf8fb73 | 2013-03-06 09:03:02 +0000 | [diff] [blame] | 1101 | lat_enc = max_ltr_enc; |
| 1102 | } |
| 1103 | |
| 1104 | /* Set Snoop and No-Snoop latencies the same */ |
| 1105 | reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); |
| 1106 | ew32(LTRV, reg); |
| 1107 | |
| 1108 | return 0; |
| 1109 | } |
| 1110 | |
| 1111 | /** |
Vitaly Lifshits | 76a0a3f | 2024-07-09 13:31:22 -0700 | [diff] [blame] | 1112 | * e1000e_force_smbus - Force interfaces to transition to SMBUS mode. |
| 1113 | * @hw: pointer to the HW structure |
| 1114 | * |
| 1115 | * Force the MAC and the PHY to SMBUS mode. Assumes semaphore already |
| 1116 | * acquired. |
| 1117 | * |
| 1118 | * Return: 0 on success, negative errno on failure. |
| 1119 | **/ |
| 1120 | static s32 e1000e_force_smbus(struct e1000_hw *hw) |
| 1121 | { |
| 1122 | u16 smb_ctrl = 0; |
| 1123 | u32 ctrl_ext; |
| 1124 | s32 ret_val; |
| 1125 | |
| 1126 | /* Switching PHY interface always returns MDI error |
| 1127 | * so disable retry mechanism to avoid wasting time |
| 1128 | */ |
| 1129 | e1000e_disable_phy_retry(hw); |
| 1130 | |
| 1131 | /* Force SMBus mode in the PHY */ |
| 1132 | ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &smb_ctrl); |
| 1133 | if (ret_val) { |
| 1134 | e1000e_enable_phy_retry(hw); |
| 1135 | return ret_val; |
| 1136 | } |
| 1137 | |
| 1138 | smb_ctrl |= CV_SMB_CTRL_FORCE_SMBUS; |
| 1139 | e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, smb_ctrl); |
| 1140 | |
| 1141 | e1000e_enable_phy_retry(hw); |
| 1142 | |
| 1143 | /* Force SMBus mode in the MAC */ |
| 1144 | ctrl_ext = er32(CTRL_EXT); |
| 1145 | ctrl_ext |= E1000_CTRL_EXT_FORCE_SMBUS; |
| 1146 | ew32(CTRL_EXT, ctrl_ext); |
| 1147 | |
| 1148 | return 0; |
| 1149 | } |
| 1150 | |
| 1151 | /** |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 1152 | * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP |
| 1153 | * @hw: pointer to the HW structure |
| 1154 | * @to_sx: boolean indicating a system power state transition to Sx |
| 1155 | * |
| 1156 | * When link is down, configure ULP mode to significantly reduce the power |
| 1157 | * to the PHY. If on a Manageability Engine (ME) enabled system, tell the |
| 1158 | * ME firmware to start the ULP configuration. If not on an ME enabled |
| 1159 | * system, configure the ULP mode by software. |
| 1160 | */ |
| 1161 | s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) |
| 1162 | { |
| 1163 | u32 mac_reg; |
| 1164 | s32 ret_val = 0; |
| 1165 | u16 phy_reg; |
Yanir Lubetkin | 6607c99 | 2015-06-10 01:15:55 +0300 | [diff] [blame] | 1166 | u16 oem_reg = 0; |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 1167 | |
| 1168 | if ((hw->mac.type < e1000_pch_lpt) || |
| 1169 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || |
| 1170 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || |
| 1171 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || |
| 1172 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || |
| 1173 | (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) |
| 1174 | return 0; |
| 1175 | |
| 1176 | if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { |
| 1177 | /* Request ME configure ULP mode in the PHY */ |
| 1178 | mac_reg = er32(H2ME); |
| 1179 | mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; |
| 1180 | ew32(H2ME, mac_reg); |
| 1181 | |
| 1182 | goto out; |
| 1183 | } |
| 1184 | |
| 1185 | if (!to_sx) { |
| 1186 | int i = 0; |
| 1187 | |
| 1188 | /* Poll up to 5 seconds for Cable Disconnected indication */ |
| 1189 | while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) { |
| 1190 | /* Bail if link is re-acquired */ |
| 1191 | if (er32(STATUS) & E1000_STATUS_LU) |
| 1192 | return -E1000_ERR_PHY; |
| 1193 | |
| 1194 | if (i++ == 100) |
| 1195 | break; |
| 1196 | |
| 1197 | msleep(50); |
| 1198 | } |
| 1199 | e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n", |
| 1200 | (er32(FEXT) & |
| 1201 | E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50); |
| 1202 | } |
| 1203 | |
| 1204 | ret_val = hw->phy.ops.acquire(hw); |
| 1205 | if (ret_val) |
| 1206 | goto out; |
| 1207 | |
Vitaly Lifshits | 76a0a3f | 2024-07-09 13:31:22 -0700 | [diff] [blame] | 1208 | if (hw->mac.type != e1000_pch_mtp) { |
| 1209 | ret_val = e1000e_force_smbus(hw); |
| 1210 | if (ret_val) { |
| 1211 | e_dbg("Failed to force SMBUS: %d\n", ret_val); |
| 1212 | goto release; |
| 1213 | } |
| 1214 | } |
| 1215 | |
Yanir Lubetkin | 6607c99 | 2015-06-10 01:15:55 +0300 | [diff] [blame] | 1216 | /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable |
| 1217 | * LPLU and disable Gig speed when entering ULP |
| 1218 | */ |
| 1219 | if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { |
| 1220 | ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, |
| 1221 | &oem_reg); |
| 1222 | if (ret_val) |
| 1223 | goto release; |
| 1224 | |
| 1225 | phy_reg = oem_reg; |
| 1226 | phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS; |
| 1227 | |
| 1228 | ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, |
| 1229 | phy_reg); |
| 1230 | |
| 1231 | if (ret_val) |
| 1232 | goto release; |
| 1233 | } |
| 1234 | |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 1235 | /* Set Inband ULP Exit, Reset to SMBus mode and |
| 1236 | * Disable SMBus Release on PERST# in PHY |
| 1237 | */ |
| 1238 | ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); |
| 1239 | if (ret_val) |
| 1240 | goto release; |
| 1241 | phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | |
| 1242 | I218_ULP_CONFIG1_DISABLE_SMB_PERST); |
| 1243 | if (to_sx) { |
| 1244 | if (er32(WUFC) & E1000_WUFC_LNKC) |
| 1245 | phy_reg |= I218_ULP_CONFIG1_WOL_HOST; |
Yanir Lubetkin | 6607c99 | 2015-06-10 01:15:55 +0300 | [diff] [blame] | 1246 | else |
| 1247 | phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 1248 | |
| 1249 | phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; |
Yanir Lubetkin | 6607c99 | 2015-06-10 01:15:55 +0300 | [diff] [blame] | 1250 | phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT; |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 1251 | } else { |
| 1252 | phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; |
Yanir Lubetkin | 6607c99 | 2015-06-10 01:15:55 +0300 | [diff] [blame] | 1253 | phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP; |
| 1254 | phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 1255 | } |
| 1256 | e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); |
| 1257 | |
| 1258 | /* Set Disable SMBus Release on PERST# in MAC */ |
| 1259 | mac_reg = er32(FEXTNVM7); |
| 1260 | mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; |
| 1261 | ew32(FEXTNVM7, mac_reg); |
| 1262 | |
| 1263 | /* Commit ULP changes in PHY by starting auto ULP configuration */ |
| 1264 | phy_reg |= I218_ULP_CONFIG1_START; |
| 1265 | e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); |
Yanir Lubetkin | 6607c99 | 2015-06-10 01:15:55 +0300 | [diff] [blame] | 1266 | |
| 1267 | if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && |
| 1268 | to_sx && (er32(STATUS) & E1000_STATUS_LU)) { |
| 1269 | ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, |
| 1270 | oem_reg); |
| 1271 | if (ret_val) |
| 1272 | goto release; |
| 1273 | } |
| 1274 | |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 1275 | release: |
Vitaly Lifshits | 76a0a3f | 2024-07-09 13:31:22 -0700 | [diff] [blame] | 1276 | if (hw->mac.type == e1000_pch_mtp) { |
| 1277 | ret_val = e1000e_force_smbus(hw); |
| 1278 | if (ret_val) |
| 1279 | e_dbg("Failed to force SMBUS over MTL system: %d\n", |
| 1280 | ret_val); |
Hui Wang | bfd546a | 2024-05-28 15:06:04 -0700 | [diff] [blame] | 1281 | } |
Hui Wang | bfd546a | 2024-05-28 15:06:04 -0700 | [diff] [blame] | 1282 | |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 1283 | hw->phy.ops.release(hw); |
| 1284 | out: |
| 1285 | if (ret_val) |
| 1286 | e_dbg("Error in ULP enable flow: %d\n", ret_val); |
| 1287 | else |
| 1288 | hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; |
| 1289 | |
| 1290 | return ret_val; |
| 1291 | } |
| 1292 | |
| 1293 | /** |
| 1294 | * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP |
| 1295 | * @hw: pointer to the HW structure |
| 1296 | * @force: boolean indicating whether or not to force disabling ULP |
| 1297 | * |
| 1298 | * Un-configure ULP mode when link is up, the system is transitioned from |
| 1299 | * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled |
| 1300 | * system, poll for an indication from ME that ULP has been un-configured. |
| 1301 | * If not on an ME enabled system, un-configure the ULP mode by software. |
| 1302 | * |
| 1303 | * During nominal operation, this function is called when link is acquired |
| 1304 | * to disable ULP mode (force=false); otherwise, for example when unloading |
| 1305 | * the driver or during Sx->S0 transitions, this is called with force=true |
| 1306 | * to forcibly disable ULP. |
| 1307 | */ |
| 1308 | static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) |
| 1309 | { |
| 1310 | s32 ret_val = 0; |
| 1311 | u32 mac_reg; |
| 1312 | u16 phy_reg; |
| 1313 | int i = 0; |
| 1314 | |
| 1315 | if ((hw->mac.type < e1000_pch_lpt) || |
| 1316 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || |
| 1317 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || |
| 1318 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || |
| 1319 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || |
| 1320 | (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) |
| 1321 | return 0; |
| 1322 | |
| 1323 | if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { |
Mario Limonciello | 3cf31b1 | 2020-12-14 13:29:33 -0600 | [diff] [blame] | 1324 | struct e1000_adapter *adapter = hw->adapter; |
| 1325 | bool firmware_bug = false; |
| 1326 | |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 1327 | if (force) { |
| 1328 | /* Request ME un-configure ULP mode in the PHY */ |
| 1329 | mac_reg = er32(H2ME); |
| 1330 | mac_reg &= ~E1000_H2ME_ULP; |
| 1331 | mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; |
| 1332 | ew32(H2ME, mac_reg); |
| 1333 | } |
| 1334 | |
Mario Limonciello | 3cf31b1 | 2020-12-14 13:29:33 -0600 | [diff] [blame] | 1335 | /* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE. |
| 1336 | * If this takes more than 1 second, show a warning indicating a |
| 1337 | * firmware bug |
| 1338 | */ |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 1339 | while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) { |
Mario Limonciello | 3cf31b1 | 2020-12-14 13:29:33 -0600 | [diff] [blame] | 1340 | if (i++ == 250) { |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 1341 | ret_val = -E1000_ERR_PHY; |
| 1342 | goto out; |
| 1343 | } |
Mario Limonciello | 3cf31b1 | 2020-12-14 13:29:33 -0600 | [diff] [blame] | 1344 | if (i > 100 && !firmware_bug) |
| 1345 | firmware_bug = true; |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 1346 | |
Arjan van de Ven | ab6973a | 2019-06-14 17:29:35 -0700 | [diff] [blame] | 1347 | usleep_range(10000, 11000); |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 1348 | } |
Mario Limonciello | 3cf31b1 | 2020-12-14 13:29:33 -0600 | [diff] [blame] | 1349 | if (firmware_bug) |
Sasha Neftin | ade4162 | 2021-06-16 07:19:30 +0300 | [diff] [blame] | 1350 | e_warn("ULP_CONFIG_DONE took %d msec. This is a firmware bug\n", |
| 1351 | i * 10); |
Mario Limonciello | 3cf31b1 | 2020-12-14 13:29:33 -0600 | [diff] [blame] | 1352 | else |
Sasha Neftin | ade4162 | 2021-06-16 07:19:30 +0300 | [diff] [blame] | 1353 | e_dbg("ULP_CONFIG_DONE cleared after %d msec\n", |
| 1354 | i * 10); |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 1355 | |
| 1356 | if (force) { |
| 1357 | mac_reg = er32(H2ME); |
| 1358 | mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; |
| 1359 | ew32(H2ME, mac_reg); |
| 1360 | } else { |
| 1361 | /* Clear H2ME.ULP after ME ULP configuration */ |
| 1362 | mac_reg = er32(H2ME); |
| 1363 | mac_reg &= ~E1000_H2ME_ULP; |
| 1364 | ew32(H2ME, mac_reg); |
| 1365 | } |
| 1366 | |
| 1367 | goto out; |
| 1368 | } |
| 1369 | |
| 1370 | ret_val = hw->phy.ops.acquire(hw); |
| 1371 | if (ret_val) |
| 1372 | goto out; |
| 1373 | |
| 1374 | if (force) |
| 1375 | /* Toggle LANPHYPC Value bit */ |
| 1376 | e1000_toggle_lanphypc_pch_lpt(hw); |
| 1377 | |
Vitaly Lifshits | 6dbdd4d | 2024-01-04 16:16:52 +0200 | [diff] [blame] | 1378 | /* Switching PHY interface always returns MDI error |
| 1379 | * so disable retry mechanism to avoid wasting time |
| 1380 | */ |
| 1381 | e1000e_disable_phy_retry(hw); |
| 1382 | |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 1383 | /* Unforce SMBus mode in PHY */ |
| 1384 | ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); |
| 1385 | if (ret_val) { |
| 1386 | /* The MAC might be in PCIe mode, so temporarily force to |
| 1387 | * SMBus mode in order to access the PHY. |
| 1388 | */ |
| 1389 | mac_reg = er32(CTRL_EXT); |
| 1390 | mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; |
| 1391 | ew32(CTRL_EXT, mac_reg); |
| 1392 | |
| 1393 | msleep(50); |
| 1394 | |
| 1395 | ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, |
| 1396 | &phy_reg); |
| 1397 | if (ret_val) |
| 1398 | goto release; |
| 1399 | } |
| 1400 | phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; |
| 1401 | e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); |
| 1402 | |
Vitaly Lifshits | 6dbdd4d | 2024-01-04 16:16:52 +0200 | [diff] [blame] | 1403 | e1000e_enable_phy_retry(hw); |
| 1404 | |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 1405 | /* Unforce SMBus mode in MAC */ |
| 1406 | mac_reg = er32(CTRL_EXT); |
| 1407 | mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; |
| 1408 | ew32(CTRL_EXT, mac_reg); |
| 1409 | |
| 1410 | /* When ULP mode was previously entered, K1 was disabled by the |
| 1411 | * hardware. Re-Enable K1 in the PHY when exiting ULP. |
| 1412 | */ |
| 1413 | ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); |
| 1414 | if (ret_val) |
| 1415 | goto release; |
| 1416 | phy_reg |= HV_PM_CTRL_K1_ENABLE; |
| 1417 | e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); |
| 1418 | |
| 1419 | /* Clear ULP enabled configuration */ |
| 1420 | ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); |
| 1421 | if (ret_val) |
| 1422 | goto release; |
| 1423 | phy_reg &= ~(I218_ULP_CONFIG1_IND | |
| 1424 | I218_ULP_CONFIG1_STICKY_ULP | |
| 1425 | I218_ULP_CONFIG1_RESET_TO_SMBUS | |
| 1426 | I218_ULP_CONFIG1_WOL_HOST | |
| 1427 | I218_ULP_CONFIG1_INBAND_EXIT | |
Raanan Avargil | c5c6d077 | 2015-12-22 15:35:04 +0200 | [diff] [blame] | 1428 | I218_ULP_CONFIG1_EN_ULP_LANPHYPC | |
| 1429 | I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | |
David Ertman | 74f350e | 2014-02-22 03:15:17 +0000 | [diff] [blame] | 1430 | I218_ULP_CONFIG1_DISABLE_SMB_PERST); |
| 1431 | e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); |
| 1432 | |
| 1433 | /* Commit ULP changes by starting auto ULP configuration */ |
| 1434 | phy_reg |= I218_ULP_CONFIG1_START; |
| 1435 | e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); |
| 1436 | |
| 1437 | /* Clear Disable SMBus Release on PERST# in MAC */ |
| 1438 | mac_reg = er32(FEXTNVM7); |
| 1439 | mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; |
| 1440 | ew32(FEXTNVM7, mac_reg); |
| 1441 | |
| 1442 | release: |
| 1443 | hw->phy.ops.release(hw); |
| 1444 | if (force) { |
| 1445 | e1000_phy_hw_reset(hw); |
| 1446 | msleep(50); |
| 1447 | } |
| 1448 | out: |
| 1449 | if (ret_val) |
| 1450 | e_dbg("Error in ULP disable flow: %d\n", ret_val); |
| 1451 | else |
| 1452 | hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; |
| 1453 | |
| 1454 | return ret_val; |
| 1455 | } |
| 1456 | |
| 1457 | /** |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 1458 | * e1000_check_for_copper_link_ich8lan - Check for link (Copper) |
| 1459 | * @hw: pointer to the HW structure |
| 1460 | * |
| 1461 | * Checks to see of the link status of the hardware has changed. If a |
| 1462 | * change in link status has been detected, then we read the PHY registers |
| 1463 | * to get the current speed/duplex if link exists. |
| 1464 | **/ |
| 1465 | static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) |
| 1466 | { |
| 1467 | struct e1000_mac_info *mac = &hw->mac; |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 1468 | s32 ret_val, tipg_reg = 0; |
| 1469 | u16 emi_addr, emi_val = 0; |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 1470 | bool link; |
Bruce Allan | 1d2101a7 | 2011-07-22 06:21:56 +0000 | [diff] [blame] | 1471 | u16 phy_reg; |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 1472 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1473 | /* We only want to go out to the PHY registers to see if Auto-Neg |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 1474 | * has completed and/or if our link status has changed. The |
| 1475 | * get_link_status flag is set upon receiving a Link Status |
| 1476 | * Change or Rx Sequence Error interrupt. |
| 1477 | */ |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1478 | if (!mac->get_link_status) |
Benjamin Poirier | 3016e0a | 2018-03-06 10:55:52 +0900 | [diff] [blame] | 1479 | return 0; |
Benjamin Poirier | e2710db | 2018-03-06 10:55:53 +0900 | [diff] [blame] | 1480 | mac->get_link_status = false; |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 1481 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1482 | /* First we want to see if the MII Status Register reports |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 1483 | * link. If so, then we want to get the current speed/duplex |
| 1484 | * of the PHY. |
| 1485 | */ |
| 1486 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
| 1487 | if (ret_val) |
Benjamin Poirier | e2710db | 2018-03-06 10:55:53 +0900 | [diff] [blame] | 1488 | goto out; |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 1489 | |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1490 | if (hw->mac.type == e1000_pchlan) { |
| 1491 | ret_val = e1000_k1_gig_workaround_hv(hw, link); |
| 1492 | if (ret_val) |
Benjamin Poirier | e2710db | 2018-03-06 10:55:53 +0900 | [diff] [blame] | 1493 | goto out; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1494 | } |
| 1495 | |
David Ertman | fbb9ab1 | 2014-04-22 05:48:54 +0000 | [diff] [blame] | 1496 | /* When connected at 10Mbps half-duplex, some parts are excessively |
Bruce Allan | 772d05c | 2013-03-06 09:02:36 +0000 | [diff] [blame] | 1497 | * aggressive resulting in many collisions. To avoid this, increase |
| 1498 | * the IPG and reduce Rx latency in the PHY. |
| 1499 | */ |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 1500 | if ((hw->mac.type >= e1000_pch2lan) && link) { |
Yanir Lubetkin | 69cfbc9 | 2015-06-10 01:15:57 +0300 | [diff] [blame] | 1501 | u16 speed, duplex; |
David Ertman | 6cf08d1 | 2014-04-05 06:07:00 +0000 | [diff] [blame] | 1502 | |
Yanir Lubetkin | 69cfbc9 | 2015-06-10 01:15:57 +0300 | [diff] [blame] | 1503 | e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex); |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 1504 | tipg_reg = er32(TIPG); |
| 1505 | tipg_reg &= ~E1000_TIPG_IPGT_MASK; |
| 1506 | |
Yanir Lubetkin | 69cfbc9 | 2015-06-10 01:15:57 +0300 | [diff] [blame] | 1507 | if (duplex == HALF_DUPLEX && speed == SPEED_10) { |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 1508 | tipg_reg |= 0xFF; |
Bruce Allan | 772d05c | 2013-03-06 09:02:36 +0000 | [diff] [blame] | 1509 | /* Reduce Rx latency in analog PHY */ |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 1510 | emi_val = 0; |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 1511 | } else if (hw->mac.type >= e1000_pch_spt && |
Yanir Lubetkin | 69cfbc9 | 2015-06-10 01:15:57 +0300 | [diff] [blame] | 1512 | duplex == FULL_DUPLEX && speed != SPEED_1000) { |
| 1513 | tipg_reg |= 0xC; |
| 1514 | emi_val = 1; |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 1515 | } else { |
Bruce Allan | 772d05c | 2013-03-06 09:02:36 +0000 | [diff] [blame] | 1516 | |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 1517 | /* Roll back the default values */ |
| 1518 | tipg_reg |= 0x08; |
| 1519 | emi_val = 1; |
Bruce Allan | 772d05c | 2013-03-06 09:02:36 +0000 | [diff] [blame] | 1520 | } |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 1521 | |
| 1522 | ew32(TIPG, tipg_reg); |
| 1523 | |
| 1524 | ret_val = hw->phy.ops.acquire(hw); |
| 1525 | if (ret_val) |
Benjamin Poirier | e2710db | 2018-03-06 10:55:53 +0900 | [diff] [blame] | 1526 | goto out; |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 1527 | |
| 1528 | if (hw->mac.type == e1000_pch2lan) |
| 1529 | emi_addr = I82579_RX_CONFIG; |
| 1530 | else |
| 1531 | emi_addr = I217_RX_CONFIG; |
| 1532 | ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); |
| 1533 | |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 1534 | if (hw->mac.type >= e1000_pch_lpt) { |
Raanan Avargil | 74f3129 | 2015-12-22 15:35:02 +0200 | [diff] [blame] | 1535 | u16 phy_reg; |
| 1536 | |
| 1537 | e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg); |
| 1538 | phy_reg &= ~I217_PLL_CLOCK_GATE_MASK; |
| 1539 | if (speed == SPEED_100 || speed == SPEED_10) |
| 1540 | phy_reg |= 0x3E8; |
| 1541 | else |
| 1542 | phy_reg |= 0xFA; |
| 1543 | e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg); |
Kai-Heng Feng | e5e9a2e | 2019-07-08 12:55:45 +0800 | [diff] [blame] | 1544 | |
| 1545 | if (speed == SPEED_1000) { |
| 1546 | hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, |
| 1547 | &phy_reg); |
| 1548 | |
| 1549 | phy_reg |= HV_PM_CTRL_K1_CLK_REQ; |
| 1550 | |
| 1551 | hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, |
| 1552 | phy_reg); |
| 1553 | } |
Raanan Avargil | 74f3129 | 2015-12-22 15:35:02 +0200 | [diff] [blame] | 1554 | } |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 1555 | hw->phy.ops.release(hw); |
| 1556 | |
| 1557 | if (ret_val) |
Benjamin Poirier | e2710db | 2018-03-06 10:55:53 +0900 | [diff] [blame] | 1558 | goto out; |
Yanir Lubetkin | 93cbfc7 | 2015-06-10 01:16:01 +0300 | [diff] [blame] | 1559 | |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 1560 | if (hw->mac.type >= e1000_pch_spt) { |
Yanir Lubetkin | 93cbfc7 | 2015-06-10 01:16:01 +0300 | [diff] [blame] | 1561 | u16 data; |
| 1562 | u16 ptr_gap; |
| 1563 | |
| 1564 | if (speed == SPEED_1000) { |
| 1565 | ret_val = hw->phy.ops.acquire(hw); |
| 1566 | if (ret_val) |
Benjamin Poirier | e2710db | 2018-03-06 10:55:53 +0900 | [diff] [blame] | 1567 | goto out; |
Yanir Lubetkin | 93cbfc7 | 2015-06-10 01:16:01 +0300 | [diff] [blame] | 1568 | |
| 1569 | ret_val = e1e_rphy_locked(hw, |
| 1570 | PHY_REG(776, 20), |
| 1571 | &data); |
| 1572 | if (ret_val) { |
| 1573 | hw->phy.ops.release(hw); |
Benjamin Poirier | e2710db | 2018-03-06 10:55:53 +0900 | [diff] [blame] | 1574 | goto out; |
Yanir Lubetkin | 93cbfc7 | 2015-06-10 01:16:01 +0300 | [diff] [blame] | 1575 | } |
| 1576 | |
| 1577 | ptr_gap = (data & (0x3FF << 2)) >> 2; |
| 1578 | if (ptr_gap < 0x18) { |
| 1579 | data &= ~(0x3FF << 2); |
| 1580 | data |= (0x18 << 2); |
| 1581 | ret_val = |
| 1582 | e1e_wphy_locked(hw, |
| 1583 | PHY_REG(776, 20), |
| 1584 | data); |
| 1585 | } |
| 1586 | hw->phy.ops.release(hw); |
| 1587 | if (ret_val) |
Benjamin Poirier | e2710db | 2018-03-06 10:55:53 +0900 | [diff] [blame] | 1588 | goto out; |
Raanan Avargil | c26f40d | 2015-12-22 15:35:03 +0200 | [diff] [blame] | 1589 | } else { |
| 1590 | ret_val = hw->phy.ops.acquire(hw); |
| 1591 | if (ret_val) |
Benjamin Poirier | e2710db | 2018-03-06 10:55:53 +0900 | [diff] [blame] | 1592 | goto out; |
Raanan Avargil | c26f40d | 2015-12-22 15:35:03 +0200 | [diff] [blame] | 1593 | |
| 1594 | ret_val = e1e_wphy_locked(hw, |
| 1595 | PHY_REG(776, 20), |
| 1596 | 0xC023); |
| 1597 | hw->phy.ops.release(hw); |
| 1598 | if (ret_val) |
Benjamin Poirier | e2710db | 2018-03-06 10:55:53 +0900 | [diff] [blame] | 1599 | goto out; |
Raanan Avargil | c26f40d | 2015-12-22 15:35:03 +0200 | [diff] [blame] | 1600 | |
Yanir Lubetkin | 93cbfc7 | 2015-06-10 01:16:01 +0300 | [diff] [blame] | 1601 | } |
| 1602 | } |
| 1603 | } |
| 1604 | |
| 1605 | /* I217 Packet Loss issue: |
| 1606 | * ensure that FEXTNVM4 Beacon Duration is set correctly |
| 1607 | * on power up. |
| 1608 | * Set the Beacon Duration for I217 to 8 usec |
| 1609 | */ |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 1610 | if (hw->mac.type >= e1000_pch_lpt) { |
Yanir Lubetkin | 93cbfc7 | 2015-06-10 01:16:01 +0300 | [diff] [blame] | 1611 | u32 mac_reg; |
| 1612 | |
| 1613 | mac_reg = er32(FEXTNVM4); |
| 1614 | mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; |
| 1615 | mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; |
| 1616 | ew32(FEXTNVM4, mac_reg); |
Bruce Allan | 772d05c | 2013-03-06 09:02:36 +0000 | [diff] [blame] | 1617 | } |
| 1618 | |
Bruce Allan | e08f626 | 2013-02-20 03:06:34 +0000 | [diff] [blame] | 1619 | /* Work-around I218 hang issue */ |
| 1620 | if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || |
Bruce Allan | 91a3d82 | 2013-06-29 01:15:16 +0000 | [diff] [blame] | 1621 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || |
| 1622 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || |
Yanir Lubetkin | 352f8ea | 2015-06-10 01:16:03 +0300 | [diff] [blame] | 1623 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { |
Bruce Allan | e08f626 | 2013-02-20 03:06:34 +0000 | [diff] [blame] | 1624 | ret_val = e1000_k1_workaround_lpt_lp(hw, link); |
| 1625 | if (ret_val) |
Benjamin Poirier | e2710db | 2018-03-06 10:55:53 +0900 | [diff] [blame] | 1626 | goto out; |
Bruce Allan | e08f626 | 2013-02-20 03:06:34 +0000 | [diff] [blame] | 1627 | } |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 1628 | if (hw->mac.type >= e1000_pch_lpt) { |
Bruce Allan | cf8fb73 | 2013-03-06 09:03:02 +0000 | [diff] [blame] | 1629 | /* Set platform power management values for |
| 1630 | * Latency Tolerance Reporting (LTR) |
| 1631 | */ |
| 1632 | ret_val = e1000_platform_pm_pch_lpt(hw, link); |
| 1633 | if (ret_val) |
Benjamin Poirier | e2710db | 2018-03-06 10:55:53 +0900 | [diff] [blame] | 1634 | goto out; |
Bruce Allan | cf8fb73 | 2013-03-06 09:03:02 +0000 | [diff] [blame] | 1635 | } |
| 1636 | |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 1637 | /* Clear link partner's EEE ability */ |
| 1638 | hw->dev_spec.ich8lan.eee_lp_ability = 0; |
| 1639 | |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 1640 | if (hw->mac.type >= e1000_pch_lpt) { |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 1641 | u32 fextnvm6 = er32(FEXTNVM6); |
| 1642 | |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 1643 | if (hw->mac.type == e1000_pch_spt) { |
| 1644 | /* FEXTNVM6 K1-off workaround - for SPT only */ |
| 1645 | u32 pcieanacfg = er32(PCIEANACFG); |
| 1646 | |
| 1647 | if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) |
| 1648 | fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE; |
| 1649 | else |
| 1650 | fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; |
| 1651 | } |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 1652 | |
| 1653 | ew32(FEXTNVM6, fextnvm6); |
| 1654 | } |
| 1655 | |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 1656 | if (!link) |
Benjamin Poirier | e2710db | 2018-03-06 10:55:53 +0900 | [diff] [blame] | 1657 | goto out; |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 1658 | |
Bruce Allan | 1d2101a7 | 2011-07-22 06:21:56 +0000 | [diff] [blame] | 1659 | switch (hw->mac.type) { |
| 1660 | case e1000_pch2lan: |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 1661 | ret_val = e1000_k1_workaround_lv(hw); |
| 1662 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1663 | return ret_val; |
Jeff Kirsher | 5463fce6 | 2020-06-03 20:07:26 -0700 | [diff] [blame] | 1664 | fallthrough; |
Bruce Allan | 1d2101a7 | 2011-07-22 06:21:56 +0000 | [diff] [blame] | 1665 | case e1000_pchlan: |
| 1666 | if (hw->phy.type == e1000_phy_82578) { |
| 1667 | ret_val = e1000_link_stall_workaround_hv(hw); |
| 1668 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1669 | return ret_val; |
Bruce Allan | 1d2101a7 | 2011-07-22 06:21:56 +0000 | [diff] [blame] | 1670 | } |
| 1671 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1672 | /* Workaround for PCHx parts in half-duplex: |
Bruce Allan | 1d2101a7 | 2011-07-22 06:21:56 +0000 | [diff] [blame] | 1673 | * Set the number of preambles removed from the packet |
| 1674 | * when it is passed from the PHY to the MAC to prevent |
| 1675 | * the MAC from misinterpreting the packet type. |
| 1676 | */ |
| 1677 | e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); |
| 1678 | phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; |
| 1679 | |
| 1680 | if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 1681 | phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); |
Bruce Allan | 1d2101a7 | 2011-07-22 06:21:56 +0000 | [diff] [blame] | 1682 | |
| 1683 | e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); |
| 1684 | break; |
| 1685 | default: |
| 1686 | break; |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 1687 | } |
| 1688 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1689 | /* Check if there was DownShift, must be checked |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 1690 | * immediately after link-up |
| 1691 | */ |
| 1692 | e1000e_check_downshift(hw); |
| 1693 | |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 1694 | /* Enable/Disable EEE after link up */ |
David Ertman | a03206e | 2014-01-24 23:07:48 +0000 | [diff] [blame] | 1695 | if (hw->phy.type > e1000_phy_82579) { |
| 1696 | ret_val = e1000_set_eee_pchlan(hw); |
| 1697 | if (ret_val) |
| 1698 | return ret_val; |
| 1699 | } |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 1700 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1701 | /* If we are forcing speed/duplex, then we simply return since |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 1702 | * we have already determined whether we have link or not. |
| 1703 | */ |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1704 | if (!mac->autoneg) |
Benjamin Poirier | 3016e0a | 2018-03-06 10:55:52 +0900 | [diff] [blame] | 1705 | return -E1000_ERR_CONFIG; |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 1706 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1707 | /* Auto-Neg is enabled. Auto Speed Detection takes care |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 1708 | * of MAC speed/duplex configuration. So we only need to |
| 1709 | * configure Collision Distance in the MAC. |
| 1710 | */ |
Bruce Allan | 57cde76 | 2012-02-22 09:02:58 +0000 | [diff] [blame] | 1711 | mac->ops.config_collision_dist(hw); |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 1712 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1713 | /* Configure Flow Control now that Auto-Neg has completed. |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 1714 | * First, we need to restore the desired flow control |
| 1715 | * settings because we may have had to re-autoneg with a |
| 1716 | * different link partner. |
| 1717 | */ |
| 1718 | ret_val = e1000e_config_fc_after_link_up(hw); |
Benjamin Poirier | 3016e0a | 2018-03-06 10:55:52 +0900 | [diff] [blame] | 1719 | if (ret_val) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1720 | e_dbg("Error configuring flow control\n"); |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 1721 | |
Benjamin Poirier | 3016e0a | 2018-03-06 10:55:52 +0900 | [diff] [blame] | 1722 | return ret_val; |
Benjamin Poirier | e2710db | 2018-03-06 10:55:53 +0900 | [diff] [blame] | 1723 | |
| 1724 | out: |
| 1725 | mac->get_link_status = true; |
| 1726 | return ret_val; |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 1727 | } |
| 1728 | |
Jeff Kirsher | 69e3fd8 | 2008-04-02 13:48:18 -0700 | [diff] [blame] | 1729 | static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1730 | { |
| 1731 | struct e1000_hw *hw = &adapter->hw; |
| 1732 | s32 rc; |
| 1733 | |
Bruce Allan | ec34c17 | 2012-02-01 10:53:05 +0000 | [diff] [blame] | 1734 | rc = e1000_init_mac_params_ich8lan(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1735 | if (rc) |
| 1736 | return rc; |
| 1737 | |
| 1738 | rc = e1000_init_nvm_params_ich8lan(hw); |
| 1739 | if (rc) |
| 1740 | return rc; |
| 1741 | |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1742 | switch (hw->mac.type) { |
| 1743 | case e1000_ich8lan: |
| 1744 | case e1000_ich9lan: |
| 1745 | case e1000_ich10lan: |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1746 | rc = e1000_init_phy_params_ich8lan(hw); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1747 | break; |
| 1748 | case e1000_pchlan: |
| 1749 | case e1000_pch2lan: |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 1750 | case e1000_pch_lpt: |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 1751 | case e1000_pch_spt: |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 1752 | case e1000_pch_cnp: |
Sasha Neftin | fb776f5 | 2019-10-16 11:08:38 +0300 | [diff] [blame] | 1753 | case e1000_pch_tgp: |
Sasha Neftin | 59e4668 | 2020-01-19 13:57:13 +0200 | [diff] [blame] | 1754 | case e1000_pch_adp: |
Sasha Neftin | cc23f4f | 2020-08-13 11:34:06 +0300 | [diff] [blame] | 1755 | case e1000_pch_mtp: |
Sasha Neftin | 820b8ff | 2021-03-04 09:38:13 +0200 | [diff] [blame] | 1756 | case e1000_pch_lnp: |
Sasha Neftin | 0c9183c | 2022-09-29 11:08:59 +0300 | [diff] [blame] | 1757 | case e1000_pch_ptp: |
Sasha Neftin | 1fe4f45 | 2023-07-18 19:28:57 +0300 | [diff] [blame] | 1758 | case e1000_pch_nvp: |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1759 | rc = e1000_init_phy_params_pchlan(hw); |
| 1760 | break; |
| 1761 | default: |
| 1762 | break; |
| 1763 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1764 | if (rc) |
| 1765 | return rc; |
| 1766 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1767 | /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or |
Bruce Allan | 23e4f06 | 2011-02-25 07:44:51 +0000 | [diff] [blame] | 1768 | * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). |
| 1769 | */ |
| 1770 | if ((adapter->hw.phy.type == e1000_phy_ife) || |
| 1771 | ((adapter->hw.mac.type >= e1000_pch2lan) && |
| 1772 | (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { |
Bruce Allan | 2adc55c | 2009-06-02 11:28:58 +0000 | [diff] [blame] | 1773 | adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; |
Alexander Duyck | 8084b86 | 2015-05-02 00:52:00 -0700 | [diff] [blame] | 1774 | adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; |
Bruce Allan | dbf80dc | 2011-04-16 00:34:40 +0000 | [diff] [blame] | 1775 | |
| 1776 | hw->mac.ops.blink_led = NULL; |
Bruce Allan | 2adc55c | 2009-06-02 11:28:58 +0000 | [diff] [blame] | 1777 | } |
| 1778 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1779 | if ((adapter->hw.mac.type == e1000_ich8lan) && |
Bruce Allan | 462d599 | 2011-09-30 08:07:11 +0000 | [diff] [blame] | 1780 | (adapter->hw.phy.type != e1000_phy_ife)) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1781 | adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; |
| 1782 | |
Bruce Allan | c6e7f51 | 2011-07-29 05:53:02 +0000 | [diff] [blame] | 1783 | /* Enable workaround for 82579 w/ ME enabled */ |
| 1784 | if ((adapter->hw.mac.type == e1000_pch2lan) && |
| 1785 | (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) |
| 1786 | adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; |
| 1787 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1788 | return 0; |
| 1789 | } |
| 1790 | |
Thomas Gleixner | 717d438 | 2008-10-02 16:33:40 -0700 | [diff] [blame] | 1791 | static DEFINE_MUTEX(nvm_mutex); |
Thomas Gleixner | 717d438 | 2008-10-02 16:33:40 -0700 | [diff] [blame] | 1792 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1793 | /** |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 1794 | * e1000_acquire_nvm_ich8lan - Acquire NVM mutex |
| 1795 | * @hw: pointer to the HW structure |
| 1796 | * |
| 1797 | * Acquires the mutex for performing NVM operations. |
| 1798 | **/ |
Bruce Allan | 8bb6286 | 2013-01-16 08:46:49 +0000 | [diff] [blame] | 1799 | static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 1800 | { |
| 1801 | mutex_lock(&nvm_mutex); |
| 1802 | |
| 1803 | return 0; |
| 1804 | } |
| 1805 | |
| 1806 | /** |
| 1807 | * e1000_release_nvm_ich8lan - Release NVM mutex |
| 1808 | * @hw: pointer to the HW structure |
| 1809 | * |
| 1810 | * Releases the mutex used while performing NVM operations. |
| 1811 | **/ |
Bruce Allan | 8bb6286 | 2013-01-16 08:46:49 +0000 | [diff] [blame] | 1812 | static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 1813 | { |
| 1814 | mutex_unlock(&nvm_mutex); |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 1815 | } |
| 1816 | |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 1817 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1818 | * e1000_acquire_swflag_ich8lan - Acquire software control flag |
| 1819 | * @hw: pointer to the HW structure |
| 1820 | * |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 1821 | * Acquires the software control flag for performing PHY and select |
| 1822 | * MAC CSR accesses. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1823 | **/ |
| 1824 | static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) |
| 1825 | { |
Bruce Allan | 373a88d | 2009-08-07 07:41:37 +0000 | [diff] [blame] | 1826 | u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; |
| 1827 | s32 ret_val = 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1828 | |
Bruce Allan | a90b412 | 2011-10-07 03:50:38 +0000 | [diff] [blame] | 1829 | if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, |
| 1830 | &hw->adapter->state)) { |
Bruce Allan | 34c9ef8 | 2011-10-21 04:33:47 +0000 | [diff] [blame] | 1831 | e_dbg("contention for Phy access\n"); |
Bruce Allan | a90b412 | 2011-10-07 03:50:38 +0000 | [diff] [blame] | 1832 | return -E1000_ERR_PHY; |
| 1833 | } |
Thomas Gleixner | 717d438 | 2008-10-02 16:33:40 -0700 | [diff] [blame] | 1834 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1835 | while (timeout) { |
| 1836 | extcnf_ctrl = er32(EXTCNF_CTRL); |
Bruce Allan | 373a88d | 2009-08-07 07:41:37 +0000 | [diff] [blame] | 1837 | if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) |
| 1838 | break; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1839 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1840 | mdelay(1); |
| 1841 | timeout--; |
| 1842 | } |
| 1843 | |
| 1844 | if (!timeout) { |
Bruce Allan | a90b412 | 2011-10-07 03:50:38 +0000 | [diff] [blame] | 1845 | e_dbg("SW has already locked the resource.\n"); |
Bruce Allan | 373a88d | 2009-08-07 07:41:37 +0000 | [diff] [blame] | 1846 | ret_val = -E1000_ERR_CONFIG; |
| 1847 | goto out; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1848 | } |
| 1849 | |
Bruce Allan | 53ac5a8 | 2009-10-26 11:23:06 +0000 | [diff] [blame] | 1850 | timeout = SW_FLAG_TIMEOUT; |
Bruce Allan | 373a88d | 2009-08-07 07:41:37 +0000 | [diff] [blame] | 1851 | |
| 1852 | extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; |
| 1853 | ew32(EXTCNF_CTRL, extcnf_ctrl); |
| 1854 | |
| 1855 | while (timeout) { |
| 1856 | extcnf_ctrl = er32(EXTCNF_CTRL); |
| 1857 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) |
| 1858 | break; |
| 1859 | |
| 1860 | mdelay(1); |
| 1861 | timeout--; |
| 1862 | } |
| 1863 | |
| 1864 | if (!timeout) { |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 1865 | e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", |
Bruce Allan | a90b412 | 2011-10-07 03:50:38 +0000 | [diff] [blame] | 1866 | er32(FWSM), extcnf_ctrl); |
Bruce Allan | 373a88d | 2009-08-07 07:41:37 +0000 | [diff] [blame] | 1867 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; |
| 1868 | ew32(EXTCNF_CTRL, extcnf_ctrl); |
| 1869 | ret_val = -E1000_ERR_CONFIG; |
| 1870 | goto out; |
| 1871 | } |
| 1872 | |
| 1873 | out: |
| 1874 | if (ret_val) |
Bruce Allan | a90b412 | 2011-10-07 03:50:38 +0000 | [diff] [blame] | 1875 | clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); |
Bruce Allan | 373a88d | 2009-08-07 07:41:37 +0000 | [diff] [blame] | 1876 | |
| 1877 | return ret_val; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1878 | } |
| 1879 | |
| 1880 | /** |
| 1881 | * e1000_release_swflag_ich8lan - Release software control flag |
| 1882 | * @hw: pointer to the HW structure |
| 1883 | * |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 1884 | * Releases the software control flag for performing PHY and select |
| 1885 | * MAC CSR accesses. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1886 | **/ |
| 1887 | static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) |
| 1888 | { |
| 1889 | u32 extcnf_ctrl; |
| 1890 | |
| 1891 | extcnf_ctrl = er32(EXTCNF_CTRL); |
Bruce Allan | c5caf48 | 2011-05-13 07:19:53 +0000 | [diff] [blame] | 1892 | |
| 1893 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { |
| 1894 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; |
| 1895 | ew32(EXTCNF_CTRL, extcnf_ctrl); |
| 1896 | } else { |
| 1897 | e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); |
| 1898 | } |
Thomas Gleixner | 717d438 | 2008-10-02 16:33:40 -0700 | [diff] [blame] | 1899 | |
Bruce Allan | a90b412 | 2011-10-07 03:50:38 +0000 | [diff] [blame] | 1900 | clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1901 | } |
| 1902 | |
| 1903 | /** |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 1904 | * e1000_check_mng_mode_ich8lan - Checks management mode |
| 1905 | * @hw: pointer to the HW structure |
| 1906 | * |
Bruce Allan | eb7700d | 2010-06-16 13:27:05 +0000 | [diff] [blame] | 1907 | * This checks if the adapter has any manageability enabled. |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 1908 | * This is a function pointer entry point only called by read/write |
| 1909 | * routines for the PHY and NVM parts. |
| 1910 | **/ |
| 1911 | static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) |
| 1912 | { |
Bruce Allan | a708dd8 | 2009-11-20 23:28:37 +0000 | [diff] [blame] | 1913 | u32 fwsm; |
| 1914 | |
| 1915 | fwsm = er32(FWSM); |
David Ertman | 261a7d1 | 2014-05-13 00:02:12 +0000 | [diff] [blame] | 1916 | return (fwsm & E1000_ICH_FWSM_FW_VALID) && |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 1917 | ((fwsm & E1000_FWSM_MODE_MASK) == |
David Ertman | 261a7d1 | 2014-05-13 00:02:12 +0000 | [diff] [blame] | 1918 | (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); |
Bruce Allan | eb7700d | 2010-06-16 13:27:05 +0000 | [diff] [blame] | 1919 | } |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 1920 | |
Bruce Allan | eb7700d | 2010-06-16 13:27:05 +0000 | [diff] [blame] | 1921 | /** |
| 1922 | * e1000_check_mng_mode_pchlan - Checks management mode |
| 1923 | * @hw: pointer to the HW structure |
| 1924 | * |
| 1925 | * This checks if the adapter has iAMT enabled. |
| 1926 | * This is a function pointer entry point only called by read/write |
| 1927 | * routines for the PHY and NVM parts. |
| 1928 | **/ |
| 1929 | static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) |
| 1930 | { |
| 1931 | u32 fwsm; |
| 1932 | |
| 1933 | fwsm = er32(FWSM); |
| 1934 | return (fwsm & E1000_ICH_FWSM_FW_VALID) && |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 1935 | (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 1936 | } |
| 1937 | |
| 1938 | /** |
Bruce Allan | 69e1e01 | 2012-04-14 03:28:50 +0000 | [diff] [blame] | 1939 | * e1000_rar_set_pch2lan - Set receive address register |
| 1940 | * @hw: pointer to the HW structure |
| 1941 | * @addr: pointer to the receive address |
| 1942 | * @index: receive address array register |
| 1943 | * |
| 1944 | * Sets the receive address array register at index to the address passed |
| 1945 | * in by addr. For 82579, RAR[0] is the base address register that is to |
| 1946 | * contain the MAC address but RAR[1-6] are reserved for manageability (ME). |
| 1947 | * Use SHRA[0-3] in place of those reserved for ME. |
| 1948 | **/ |
David Ertman | b3e5bf1 | 2014-05-06 03:50:17 +0000 | [diff] [blame] | 1949 | static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) |
Bruce Allan | 69e1e01 | 2012-04-14 03:28:50 +0000 | [diff] [blame] | 1950 | { |
| 1951 | u32 rar_low, rar_high; |
| 1952 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1953 | /* HW expects these in little endian so we reverse the byte order |
Bruce Allan | 69e1e01 | 2012-04-14 03:28:50 +0000 | [diff] [blame] | 1954 | * from network order (big endian) to little endian |
| 1955 | */ |
| 1956 | rar_low = ((u32)addr[0] | |
| 1957 | ((u32)addr[1] << 8) | |
| 1958 | ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); |
| 1959 | |
| 1960 | rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); |
| 1961 | |
| 1962 | /* If MAC address zero, no need to set the AV bit */ |
| 1963 | if (rar_low || rar_high) |
| 1964 | rar_high |= E1000_RAH_AV; |
| 1965 | |
| 1966 | if (index == 0) { |
| 1967 | ew32(RAL(index), rar_low); |
| 1968 | e1e_flush(); |
| 1969 | ew32(RAH(index), rar_high); |
| 1970 | e1e_flush(); |
David Ertman | b3e5bf1 | 2014-05-06 03:50:17 +0000 | [diff] [blame] | 1971 | return 0; |
Bruce Allan | 69e1e01 | 2012-04-14 03:28:50 +0000 | [diff] [blame] | 1972 | } |
| 1973 | |
David Ertman | c3a0dce | 2013-09-05 04:24:25 +0000 | [diff] [blame] | 1974 | /* RAR[1-6] are owned by manageability. Skip those and program the |
| 1975 | * next address into the SHRA register array. |
| 1976 | */ |
David Ertman | 96dee02 | 2014-03-05 07:50:46 +0000 | [diff] [blame] | 1977 | if (index < (u32)(hw->mac.rar_entry_count)) { |
Bruce Allan | 69e1e01 | 2012-04-14 03:28:50 +0000 | [diff] [blame] | 1978 | s32 ret_val; |
| 1979 | |
| 1980 | ret_val = e1000_acquire_swflag_ich8lan(hw); |
| 1981 | if (ret_val) |
| 1982 | goto out; |
| 1983 | |
| 1984 | ew32(SHRAL(index - 1), rar_low); |
| 1985 | e1e_flush(); |
| 1986 | ew32(SHRAH(index - 1), rar_high); |
| 1987 | e1e_flush(); |
| 1988 | |
| 1989 | e1000_release_swflag_ich8lan(hw); |
| 1990 | |
| 1991 | /* verify the register updates */ |
| 1992 | if ((er32(SHRAL(index - 1)) == rar_low) && |
| 1993 | (er32(SHRAH(index - 1)) == rar_high)) |
David Ertman | b3e5bf1 | 2014-05-06 03:50:17 +0000 | [diff] [blame] | 1994 | return 0; |
Bruce Allan | 69e1e01 | 2012-04-14 03:28:50 +0000 | [diff] [blame] | 1995 | |
| 1996 | e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", |
| 1997 | (index - 1), er32(FWSM)); |
| 1998 | } |
| 1999 | |
| 2000 | out: |
| 2001 | e_dbg("Failed to write receive address at index %d\n", index); |
David Ertman | b3e5bf1 | 2014-05-06 03:50:17 +0000 | [diff] [blame] | 2002 | return -E1000_ERR_CONFIG; |
| 2003 | } |
| 2004 | |
| 2005 | /** |
| 2006 | * e1000_rar_get_count_pch_lpt - Get the number of available SHRA |
| 2007 | * @hw: pointer to the HW structure |
| 2008 | * |
| 2009 | * Get the number of available receive registers that the Host can |
| 2010 | * program. SHRA[0-10] are the shared receive address registers |
| 2011 | * that are shared between the Host and manageability engine (ME). |
| 2012 | * ME can reserve any number of addresses and the host needs to be |
| 2013 | * able to tell how many available registers it has access to. |
| 2014 | **/ |
| 2015 | static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw) |
| 2016 | { |
| 2017 | u32 wlock_mac; |
| 2018 | u32 num_entries; |
| 2019 | |
| 2020 | wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; |
| 2021 | wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; |
| 2022 | |
| 2023 | switch (wlock_mac) { |
| 2024 | case 0: |
| 2025 | /* All SHRA[0..10] and RAR[0] available */ |
| 2026 | num_entries = hw->mac.rar_entry_count; |
| 2027 | break; |
| 2028 | case 1: |
| 2029 | /* Only RAR[0] available */ |
| 2030 | num_entries = 1; |
| 2031 | break; |
| 2032 | default: |
| 2033 | /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */ |
| 2034 | num_entries = wlock_mac + 1; |
| 2035 | break; |
| 2036 | } |
| 2037 | |
| 2038 | return num_entries; |
Bruce Allan | 69e1e01 | 2012-04-14 03:28:50 +0000 | [diff] [blame] | 2039 | } |
| 2040 | |
| 2041 | /** |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2042 | * e1000_rar_set_pch_lpt - Set receive address registers |
| 2043 | * @hw: pointer to the HW structure |
| 2044 | * @addr: pointer to the receive address |
| 2045 | * @index: receive address array register |
| 2046 | * |
| 2047 | * Sets the receive address register array at index to the address passed |
| 2048 | * in by addr. For LPT, RAR[0] is the base address register that is to |
| 2049 | * contain the MAC address. SHRA[0-10] are the shared receive address |
| 2050 | * registers that are shared between the Host and manageability engine (ME). |
| 2051 | **/ |
David Ertman | b3e5bf1 | 2014-05-06 03:50:17 +0000 | [diff] [blame] | 2052 | static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2053 | { |
| 2054 | u32 rar_low, rar_high; |
| 2055 | u32 wlock_mac; |
| 2056 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2057 | /* HW expects these in little endian so we reverse the byte order |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2058 | * from network order (big endian) to little endian |
| 2059 | */ |
| 2060 | rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | |
| 2061 | ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); |
| 2062 | |
| 2063 | rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); |
| 2064 | |
| 2065 | /* If MAC address zero, no need to set the AV bit */ |
| 2066 | if (rar_low || rar_high) |
| 2067 | rar_high |= E1000_RAH_AV; |
| 2068 | |
| 2069 | if (index == 0) { |
| 2070 | ew32(RAL(index), rar_low); |
| 2071 | e1e_flush(); |
| 2072 | ew32(RAH(index), rar_high); |
| 2073 | e1e_flush(); |
David Ertman | b3e5bf1 | 2014-05-06 03:50:17 +0000 | [diff] [blame] | 2074 | return 0; |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2075 | } |
| 2076 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2077 | /* The manageability engine (ME) can lock certain SHRAR registers that |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2078 | * it is using - those registers are unavailable for use. |
| 2079 | */ |
| 2080 | if (index < hw->mac.rar_entry_count) { |
| 2081 | wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; |
| 2082 | wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; |
| 2083 | |
| 2084 | /* Check if all SHRAR registers are locked */ |
| 2085 | if (wlock_mac == 1) |
| 2086 | goto out; |
| 2087 | |
| 2088 | if ((wlock_mac == 0) || (index <= wlock_mac)) { |
| 2089 | s32 ret_val; |
| 2090 | |
| 2091 | ret_val = e1000_acquire_swflag_ich8lan(hw); |
| 2092 | |
| 2093 | if (ret_val) |
| 2094 | goto out; |
| 2095 | |
| 2096 | ew32(SHRAL_PCH_LPT(index - 1), rar_low); |
| 2097 | e1e_flush(); |
| 2098 | ew32(SHRAH_PCH_LPT(index - 1), rar_high); |
| 2099 | e1e_flush(); |
| 2100 | |
| 2101 | e1000_release_swflag_ich8lan(hw); |
| 2102 | |
| 2103 | /* verify the register updates */ |
| 2104 | if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && |
| 2105 | (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) |
David Ertman | b3e5bf1 | 2014-05-06 03:50:17 +0000 | [diff] [blame] | 2106 | return 0; |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2107 | } |
| 2108 | } |
| 2109 | |
| 2110 | out: |
| 2111 | e_dbg("Failed to write receive address at index %d\n", index); |
David Ertman | b3e5bf1 | 2014-05-06 03:50:17 +0000 | [diff] [blame] | 2112 | return -E1000_ERR_CONFIG; |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2113 | } |
| 2114 | |
| 2115 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2116 | * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked |
| 2117 | * @hw: pointer to the HW structure |
| 2118 | * |
| 2119 | * Checks if firmware is blocking the reset of the PHY. |
| 2120 | * This is a function pointer entry point only called by |
| 2121 | * reset routines. |
| 2122 | **/ |
| 2123 | static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) |
| 2124 | { |
David Ertman | f7235ef6 | 2014-01-23 06:29:13 +0000 | [diff] [blame] | 2125 | bool blocked = false; |
| 2126 | int i = 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2127 | |
David Ertman | f7235ef6 | 2014-01-23 06:29:13 +0000 | [diff] [blame] | 2128 | while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) && |
Raanan Avargil | d17c786 | 2015-10-15 15:59:49 +0300 | [diff] [blame] | 2129 | (i++ < 30)) |
Arjan van de Ven | ab6973a | 2019-06-14 17:29:35 -0700 | [diff] [blame] | 2130 | usleep_range(10000, 11000); |
David Ertman | f7235ef6 | 2014-01-23 06:29:13 +0000 | [diff] [blame] | 2131 | return blocked ? E1000_BLK_PHY_RESET : 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2132 | } |
| 2133 | |
| 2134 | /** |
Bruce Allan | 8395ae8 | 2010-09-22 17:15:08 +0000 | [diff] [blame] | 2135 | * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states |
| 2136 | * @hw: pointer to the HW structure |
| 2137 | * |
| 2138 | * Assumes semaphore already acquired. |
| 2139 | * |
| 2140 | **/ |
| 2141 | static s32 e1000_write_smbus_addr(struct e1000_hw *hw) |
| 2142 | { |
| 2143 | u16 phy_data; |
| 2144 | u32 strap = er32(STRAP); |
Jesse Brandeburg | b9a4525 | 2023-12-05 17:01:08 -0800 | [diff] [blame] | 2145 | u32 freq = FIELD_GET(E1000_STRAP_SMT_FREQ_MASK, strap); |
Bruce Allan | 70806a7 | 2013-01-05 05:08:37 +0000 | [diff] [blame] | 2146 | s32 ret_val; |
Bruce Allan | 8395ae8 | 2010-09-22 17:15:08 +0000 | [diff] [blame] | 2147 | |
| 2148 | strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; |
| 2149 | |
| 2150 | ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); |
| 2151 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2152 | return ret_val; |
Bruce Allan | 8395ae8 | 2010-09-22 17:15:08 +0000 | [diff] [blame] | 2153 | |
| 2154 | phy_data &= ~HV_SMB_ADDR_MASK; |
| 2155 | phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); |
| 2156 | phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; |
Bruce Allan | 8395ae8 | 2010-09-22 17:15:08 +0000 | [diff] [blame] | 2157 | |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2158 | if (hw->phy.type == e1000_phy_i217) { |
| 2159 | /* Restore SMBus frequency */ |
| 2160 | if (freq--) { |
| 2161 | phy_data &= ~HV_SMB_ADDR_FREQ_MASK; |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 2162 | phy_data |= (freq & BIT(0)) << |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2163 | HV_SMB_ADDR_FREQ_LOW_SHIFT; |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 2164 | phy_data |= (freq & BIT(1)) << |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2165 | (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); |
| 2166 | } else { |
| 2167 | e_dbg("Unsupported SMB frequency in PHY\n"); |
| 2168 | } |
| 2169 | } |
| 2170 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2171 | return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); |
Bruce Allan | 8395ae8 | 2010-09-22 17:15:08 +0000 | [diff] [blame] | 2172 | } |
| 2173 | |
| 2174 | /** |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2175 | * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration |
| 2176 | * @hw: pointer to the HW structure |
| 2177 | * |
| 2178 | * SW should configure the LCD from the NVM extended configuration region |
| 2179 | * as a workaround for certain parts. |
| 2180 | **/ |
| 2181 | static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) |
| 2182 | { |
| 2183 | struct e1000_phy_info *phy = &hw->phy; |
| 2184 | u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 2185 | s32 ret_val = 0; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2186 | u16 word_addr, reg_data, reg_addr, phy_page = 0; |
| 2187 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2188 | /* Initialize the PHY from the NVM on ICH platforms. This |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2189 | * is needed due to an issue where the NVM configuration is |
| 2190 | * not properly autoloaded after power transitions. |
| 2191 | * Therefore, after each PHY reset, we will load the |
| 2192 | * configuration data out of the NVM manually. |
| 2193 | */ |
Bruce Allan | 3f0c16e | 2010-06-16 13:26:17 +0000 | [diff] [blame] | 2194 | switch (hw->mac.type) { |
| 2195 | case e1000_ich8lan: |
| 2196 | if (phy->type != e1000_phy_igp_3) |
| 2197 | return ret_val; |
| 2198 | |
Bruce Allan | 5f3eed6 | 2010-09-22 17:15:54 +0000 | [diff] [blame] | 2199 | if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || |
| 2200 | (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { |
Bruce Allan | 3f0c16e | 2010-06-16 13:26:17 +0000 | [diff] [blame] | 2201 | sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; |
| 2202 | break; |
| 2203 | } |
Jeff Kirsher | 5463fce6 | 2020-06-03 20:07:26 -0700 | [diff] [blame] | 2204 | fallthrough; |
Bruce Allan | 3f0c16e | 2010-06-16 13:26:17 +0000 | [diff] [blame] | 2205 | case e1000_pchlan: |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2206 | case e1000_pch2lan: |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2207 | case e1000_pch_lpt: |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 2208 | case e1000_pch_spt: |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 2209 | case e1000_pch_cnp: |
Sasha Neftin | fb776f5 | 2019-10-16 11:08:38 +0300 | [diff] [blame] | 2210 | case e1000_pch_tgp: |
Sasha Neftin | 59e4668 | 2020-01-19 13:57:13 +0200 | [diff] [blame] | 2211 | case e1000_pch_adp: |
Sasha Neftin | cc23f4f | 2020-08-13 11:34:06 +0300 | [diff] [blame] | 2212 | case e1000_pch_mtp: |
Sasha Neftin | 820b8ff | 2021-03-04 09:38:13 +0200 | [diff] [blame] | 2213 | case e1000_pch_lnp: |
Sasha Neftin | 0c9183c | 2022-09-29 11:08:59 +0300 | [diff] [blame] | 2214 | case e1000_pch_ptp: |
Sasha Neftin | 1fe4f45 | 2023-07-18 19:28:57 +0300 | [diff] [blame] | 2215 | case e1000_pch_nvp: |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 2216 | sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; |
Bruce Allan | 3f0c16e | 2010-06-16 13:26:17 +0000 | [diff] [blame] | 2217 | break; |
| 2218 | default: |
| 2219 | return ret_val; |
| 2220 | } |
| 2221 | |
| 2222 | ret_val = hw->phy.ops.acquire(hw); |
| 2223 | if (ret_val) |
| 2224 | return ret_val; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2225 | |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 2226 | data = er32(FEXTNVM); |
| 2227 | if (!(data & sw_cfg_mask)) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2228 | goto release; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2229 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2230 | /* Make sure HW does not configure LCD from PHY |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 2231 | * extended configuration before SW configuration |
| 2232 | */ |
| 2233 | data = er32(EXTCNF_CTRL); |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2234 | if ((hw->mac.type < e1000_pch2lan) && |
| 2235 | (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) |
| 2236 | goto release; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2237 | |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 2238 | cnf_size = er32(EXTCNF_SIZE); |
| 2239 | cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; |
| 2240 | cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; |
| 2241 | if (!cnf_size) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2242 | goto release; |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 2243 | |
| 2244 | cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; |
| 2245 | cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; |
| 2246 | |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2247 | if (((hw->mac.type == e1000_pchlan) && |
| 2248 | !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || |
| 2249 | (hw->mac.type > e1000_pchlan)) { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2250 | /* HW configures the SMBus address and LEDs when the |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 2251 | * OEM and LCD Write Enable bits are set in the NVM. |
| 2252 | * When both NVM bits are cleared, SW will configure |
| 2253 | * them instead. |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2254 | */ |
Bruce Allan | 8395ae8 | 2010-09-22 17:15:08 +0000 | [diff] [blame] | 2255 | ret_val = e1000_write_smbus_addr(hw); |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 2256 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2257 | goto release; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2258 | |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 2259 | data = er32(LEDCTL); |
| 2260 | ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, |
| 2261 | (u16)data); |
| 2262 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2263 | goto release; |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 2264 | } |
| 2265 | |
| 2266 | /* Configure LCD from extended configuration region. */ |
| 2267 | |
| 2268 | /* cnf_base_addr is in DWORD */ |
| 2269 | word_addr = (u16)(cnf_base_addr << 1); |
| 2270 | |
| 2271 | for (i = 0; i < cnf_size; i++) { |
Bruce Allan | e5fe254 | 2013-02-20 04:06:27 +0000 | [diff] [blame] | 2272 | ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data); |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 2273 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2274 | goto release; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2275 | |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 2276 | ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), |
| 2277 | 1, ®_addr); |
| 2278 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2279 | goto release; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2280 | |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 2281 | /* Save off the PHY page for future writes. */ |
| 2282 | if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { |
| 2283 | phy_page = reg_data; |
| 2284 | continue; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2285 | } |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2286 | |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 2287 | reg_addr &= PHY_REG_MASK; |
| 2288 | reg_addr |= phy_page; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2289 | |
Bruce Allan | f1430d6 | 2012-04-14 04:21:52 +0000 | [diff] [blame] | 2290 | ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 2291 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2292 | goto release; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2293 | } |
| 2294 | |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2295 | release: |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2296 | hw->phy.ops.release(hw); |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2297 | return ret_val; |
| 2298 | } |
| 2299 | |
| 2300 | /** |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2301 | * e1000_k1_gig_workaround_hv - K1 Si workaround |
| 2302 | * @hw: pointer to the HW structure |
| 2303 | * @link: link up bool flag |
| 2304 | * |
| 2305 | * If K1 is enabled for 1Gbps, the MAC might stall when transitioning |
| 2306 | * from a lower speed. This workaround disables K1 whenever link is at 1Gig |
| 2307 | * If link is down, the function will restore the default K1 setting located |
| 2308 | * in the NVM. |
| 2309 | **/ |
| 2310 | static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) |
| 2311 | { |
| 2312 | s32 ret_val = 0; |
| 2313 | u16 status_reg = 0; |
| 2314 | bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; |
| 2315 | |
| 2316 | if (hw->mac.type != e1000_pchlan) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2317 | return 0; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2318 | |
| 2319 | /* Wrap the whole flow with the sw flag */ |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2320 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2321 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2322 | return ret_val; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2323 | |
| 2324 | /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ |
| 2325 | if (link) { |
| 2326 | if (hw->phy.type == e1000_phy_82578) { |
Bruce Allan | f1430d6 | 2012-04-14 04:21:52 +0000 | [diff] [blame] | 2327 | ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, |
| 2328 | &status_reg); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2329 | if (ret_val) |
| 2330 | goto release; |
| 2331 | |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2332 | status_reg &= (BM_CS_STATUS_LINK_UP | |
| 2333 | BM_CS_STATUS_RESOLVED | |
| 2334 | BM_CS_STATUS_SPEED_MASK); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2335 | |
| 2336 | if (status_reg == (BM_CS_STATUS_LINK_UP | |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2337 | BM_CS_STATUS_RESOLVED | |
| 2338 | BM_CS_STATUS_SPEED_1000)) |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2339 | k1_enable = false; |
| 2340 | } |
| 2341 | |
| 2342 | if (hw->phy.type == e1000_phy_82577) { |
Bruce Allan | f1430d6 | 2012-04-14 04:21:52 +0000 | [diff] [blame] | 2343 | ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2344 | if (ret_val) |
| 2345 | goto release; |
| 2346 | |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2347 | status_reg &= (HV_M_STATUS_LINK_UP | |
| 2348 | HV_M_STATUS_AUTONEG_COMPLETE | |
| 2349 | HV_M_STATUS_SPEED_MASK); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2350 | |
| 2351 | if (status_reg == (HV_M_STATUS_LINK_UP | |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2352 | HV_M_STATUS_AUTONEG_COMPLETE | |
| 2353 | HV_M_STATUS_SPEED_1000)) |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2354 | k1_enable = false; |
| 2355 | } |
| 2356 | |
| 2357 | /* Link stall fix for link up */ |
Bruce Allan | f1430d6 | 2012-04-14 04:21:52 +0000 | [diff] [blame] | 2358 | ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2359 | if (ret_val) |
| 2360 | goto release; |
| 2361 | |
| 2362 | } else { |
| 2363 | /* Link stall fix for link down */ |
Bruce Allan | f1430d6 | 2012-04-14 04:21:52 +0000 | [diff] [blame] | 2364 | ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2365 | if (ret_val) |
| 2366 | goto release; |
| 2367 | } |
| 2368 | |
| 2369 | ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); |
| 2370 | |
| 2371 | release: |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2372 | hw->phy.ops.release(hw); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2373 | |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2374 | return ret_val; |
| 2375 | } |
| 2376 | |
| 2377 | /** |
| 2378 | * e1000_configure_k1_ich8lan - Configure K1 power state |
| 2379 | * @hw: pointer to the HW structure |
Jesse Brandeburg | b50f7bc | 2020-09-25 15:24:37 -0700 | [diff] [blame] | 2380 | * @k1_enable: K1 state to configure |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2381 | * |
| 2382 | * Configure the K1 power state based on the provided parameter. |
| 2383 | * Assumes semaphore already acquired. |
| 2384 | * |
| 2385 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
| 2386 | **/ |
Bruce Allan | bb436b2 | 2009-11-20 23:24:11 +0000 | [diff] [blame] | 2387 | s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2388 | { |
Bruce Allan | 70806a7 | 2013-01-05 05:08:37 +0000 | [diff] [blame] | 2389 | s32 ret_val; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2390 | u32 ctrl_reg = 0; |
| 2391 | u32 ctrl_ext = 0; |
| 2392 | u32 reg = 0; |
| 2393 | u16 kmrn_reg = 0; |
| 2394 | |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 2395 | ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, |
| 2396 | &kmrn_reg); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2397 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2398 | return ret_val; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2399 | |
| 2400 | if (k1_enable) |
| 2401 | kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; |
| 2402 | else |
| 2403 | kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; |
| 2404 | |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 2405 | ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, |
| 2406 | kmrn_reg); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2407 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2408 | return ret_val; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2409 | |
Bruce Allan | ce43a21 | 2013-02-20 04:06:32 +0000 | [diff] [blame] | 2410 | usleep_range(20, 40); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2411 | ctrl_ext = er32(CTRL_EXT); |
| 2412 | ctrl_reg = er32(CTRL); |
| 2413 | |
| 2414 | reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); |
| 2415 | reg |= E1000_CTRL_FRCSPD; |
| 2416 | ew32(CTRL, reg); |
| 2417 | |
| 2418 | ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); |
Jesse Brandeburg | 945a515 | 2011-07-20 00:56:21 +0000 | [diff] [blame] | 2419 | e1e_flush(); |
Bruce Allan | ce43a21 | 2013-02-20 04:06:32 +0000 | [diff] [blame] | 2420 | usleep_range(20, 40); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2421 | ew32(CTRL, ctrl_reg); |
| 2422 | ew32(CTRL_EXT, ctrl_ext); |
Jesse Brandeburg | 945a515 | 2011-07-20 00:56:21 +0000 | [diff] [blame] | 2423 | e1e_flush(); |
Bruce Allan | ce43a21 | 2013-02-20 04:06:32 +0000 | [diff] [blame] | 2424 | usleep_range(20, 40); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2425 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2426 | return 0; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2427 | } |
| 2428 | |
| 2429 | /** |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2430 | * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration |
| 2431 | * @hw: pointer to the HW structure |
| 2432 | * @d0_state: boolean if entering d0 or d3 device state |
| 2433 | * |
| 2434 | * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are |
| 2435 | * collectively called OEM bits. The OEM Write Enable bit and SW Config bit |
| 2436 | * in NVM determines whether HW should configure LPLU and Gbe Disable. |
| 2437 | **/ |
| 2438 | static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) |
| 2439 | { |
| 2440 | s32 ret_val = 0; |
| 2441 | u32 mac_reg; |
| 2442 | u16 oem_reg; |
| 2443 | |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2444 | if (hw->mac.type < e1000_pchlan) |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2445 | return ret_val; |
| 2446 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2447 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2448 | if (ret_val) |
| 2449 | return ret_val; |
| 2450 | |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2451 | if (hw->mac.type == e1000_pchlan) { |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2452 | mac_reg = er32(EXTCNF_CTRL); |
| 2453 | if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2454 | goto release; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2455 | } |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2456 | |
| 2457 | mac_reg = er32(FEXTNVM); |
| 2458 | if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2459 | goto release; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2460 | |
| 2461 | mac_reg = er32(PHY_CTRL); |
| 2462 | |
Bruce Allan | f1430d6 | 2012-04-14 04:21:52 +0000 | [diff] [blame] | 2463 | ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2464 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2465 | goto release; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2466 | |
| 2467 | oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); |
| 2468 | |
| 2469 | if (d0_state) { |
| 2470 | if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) |
| 2471 | oem_reg |= HV_OEM_BITS_GBE_DIS; |
| 2472 | |
| 2473 | if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) |
| 2474 | oem_reg |= HV_OEM_BITS_LPLU; |
| 2475 | } else { |
Bruce Allan | 03299e4 | 2011-09-30 08:07:05 +0000 | [diff] [blame] | 2476 | if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | |
| 2477 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2478 | oem_reg |= HV_OEM_BITS_GBE_DIS; |
| 2479 | |
Bruce Allan | 03299e4 | 2011-09-30 08:07:05 +0000 | [diff] [blame] | 2480 | if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | |
| 2481 | E1000_PHY_CTRL_NOND0A_LPLU)) |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2482 | oem_reg |= HV_OEM_BITS_LPLU; |
| 2483 | } |
Bruce Allan | 03299e4 | 2011-09-30 08:07:05 +0000 | [diff] [blame] | 2484 | |
Bruce Allan | 92fe173 | 2012-04-12 06:27:03 +0000 | [diff] [blame] | 2485 | /* Set Restart auto-neg to activate the bits */ |
| 2486 | if ((d0_state || (hw->mac.type != e1000_pchlan)) && |
| 2487 | !hw->phy.ops.check_reset_block(hw)) |
| 2488 | oem_reg |= HV_OEM_BITS_RESTART_AN; |
| 2489 | |
Bruce Allan | f1430d6 | 2012-04-14 04:21:52 +0000 | [diff] [blame] | 2490 | ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2491 | |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2492 | release: |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2493 | hw->phy.ops.release(hw); |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2494 | |
| 2495 | return ret_val; |
| 2496 | } |
| 2497 | |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2498 | /** |
Bruce Allan | fddaa1a | 2010-01-13 01:52:49 +0000 | [diff] [blame] | 2499 | * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode |
| 2500 | * @hw: pointer to the HW structure |
| 2501 | **/ |
| 2502 | static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) |
| 2503 | { |
| 2504 | s32 ret_val; |
| 2505 | u16 data; |
| 2506 | |
| 2507 | ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); |
| 2508 | if (ret_val) |
| 2509 | return ret_val; |
| 2510 | |
| 2511 | data |= HV_KMRN_MDIO_SLOW; |
| 2512 | |
| 2513 | ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); |
| 2514 | |
| 2515 | return ret_val; |
| 2516 | } |
| 2517 | |
| 2518 | /** |
Jesse Brandeburg | b50f7bc | 2020-09-25 15:24:37 -0700 | [diff] [blame] | 2519 | * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds |
| 2520 | * @hw: pointer to the HW structure |
| 2521 | * |
| 2522 | * A series of PHY workarounds to be done after every PHY reset. |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2523 | **/ |
| 2524 | static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) |
| 2525 | { |
| 2526 | s32 ret_val = 0; |
Bruce Allan | baf86c9 | 2010-01-13 01:53:08 +0000 | [diff] [blame] | 2527 | u16 phy_data; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2528 | |
| 2529 | if (hw->mac.type != e1000_pchlan) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2530 | return 0; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2531 | |
Bruce Allan | fddaa1a | 2010-01-13 01:52:49 +0000 | [diff] [blame] | 2532 | /* Set MDIO slow mode before any other MDIO access */ |
| 2533 | if (hw->phy.type == e1000_phy_82577) { |
| 2534 | ret_val = e1000_set_mdio_slow_mode_hv(hw); |
| 2535 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2536 | return ret_val; |
Bruce Allan | fddaa1a | 2010-01-13 01:52:49 +0000 | [diff] [blame] | 2537 | } |
| 2538 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2539 | if (((hw->phy.type == e1000_phy_82577) && |
| 2540 | ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || |
| 2541 | ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { |
| 2542 | /* Disable generation of early preamble */ |
| 2543 | ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); |
| 2544 | if (ret_val) |
| 2545 | return ret_val; |
| 2546 | |
| 2547 | /* Preamble tuning for SSC */ |
Bruce Allan | 1d2101a7 | 2011-07-22 06:21:56 +0000 | [diff] [blame] | 2548 | ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2549 | if (ret_val) |
| 2550 | return ret_val; |
| 2551 | } |
| 2552 | |
| 2553 | if (hw->phy.type == e1000_phy_82578) { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2554 | /* Return registers to default by doing a soft reset then |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2555 | * writing 0x3140 to the control register. |
| 2556 | */ |
| 2557 | if (hw->phy.revision < 2) { |
| 2558 | e1000e_phy_sw_reset(hw); |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 2559 | ret_val = e1e_wphy(hw, MII_BMCR, 0x3140); |
Gustavo A R Silva | d75372a | 2017-06-20 16:22:34 -0500 | [diff] [blame] | 2560 | if (ret_val) |
| 2561 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2562 | } |
| 2563 | } |
| 2564 | |
| 2565 | /* Select page 0 */ |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2566 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2567 | if (ret_val) |
| 2568 | return ret_val; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2569 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2570 | hw->phy.addr = 1; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2571 | ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); |
Bruce Allan | baf86c9 | 2010-01-13 01:53:08 +0000 | [diff] [blame] | 2572 | hw->phy.ops.release(hw); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2573 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2574 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2575 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2576 | /* Configure the K1 Si workaround during phy reset assuming there is |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2577 | * link so that it disables K1 if link is in 1Gbps. |
| 2578 | */ |
| 2579 | ret_val = e1000_k1_gig_workaround_hv(hw, true); |
Bruce Allan | baf86c9 | 2010-01-13 01:53:08 +0000 | [diff] [blame] | 2580 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2581 | return ret_val; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 2582 | |
Bruce Allan | baf86c9 | 2010-01-13 01:53:08 +0000 | [diff] [blame] | 2583 | /* Workaround for link disconnects on a busy hub in half duplex */ |
| 2584 | ret_val = hw->phy.ops.acquire(hw); |
| 2585 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2586 | return ret_val; |
Bruce Allan | f1430d6 | 2012-04-14 04:21:52 +0000 | [diff] [blame] | 2587 | ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); |
Bruce Allan | baf86c9 | 2010-01-13 01:53:08 +0000 | [diff] [blame] | 2588 | if (ret_val) |
| 2589 | goto release; |
Bruce Allan | f1430d6 | 2012-04-14 04:21:52 +0000 | [diff] [blame] | 2590 | ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); |
Bruce Allan | 651fb10 | 2012-12-05 06:26:03 +0000 | [diff] [blame] | 2591 | if (ret_val) |
| 2592 | goto release; |
| 2593 | |
| 2594 | /* set MSE higher to enable link to stay up when noise is high */ |
| 2595 | ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); |
Bruce Allan | baf86c9 | 2010-01-13 01:53:08 +0000 | [diff] [blame] | 2596 | release: |
| 2597 | hw->phy.ops.release(hw); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2598 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2599 | return ret_val; |
| 2600 | } |
| 2601 | |
| 2602 | /** |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2603 | * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY |
| 2604 | * @hw: pointer to the HW structure |
| 2605 | **/ |
| 2606 | void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) |
| 2607 | { |
| 2608 | u32 mac_reg; |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2609 | u16 i, phy_reg = 0; |
| 2610 | s32 ret_val; |
| 2611 | |
| 2612 | ret_val = hw->phy.ops.acquire(hw); |
| 2613 | if (ret_val) |
| 2614 | return; |
| 2615 | ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); |
| 2616 | if (ret_val) |
| 2617 | goto release; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2618 | |
David Ertman | c3a0dce | 2013-09-05 04:24:25 +0000 | [diff] [blame] | 2619 | /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */ |
| 2620 | for (i = 0; i < (hw->mac.rar_entry_count); i++) { |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2621 | mac_reg = er32(RAL(i)); |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2622 | hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), |
| 2623 | (u16)(mac_reg & 0xFFFF)); |
| 2624 | hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), |
| 2625 | (u16)((mac_reg >> 16) & 0xFFFF)); |
| 2626 | |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2627 | mac_reg = er32(RAH(i)); |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2628 | hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), |
| 2629 | (u16)(mac_reg & 0xFFFF)); |
| 2630 | hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), |
Sasha Neftin | ba54b1a | 2024-02-18 09:42:21 +0200 | [diff] [blame] | 2631 | (u16)((mac_reg & E1000_RAH_AV) >> 16)); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2632 | } |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2633 | |
| 2634 | e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); |
| 2635 | |
| 2636 | release: |
| 2637 | hw->phy.ops.release(hw); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2638 | } |
| 2639 | |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2640 | /** |
| 2641 | * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation |
| 2642 | * with 82579 PHY |
| 2643 | * @hw: pointer to the HW structure |
| 2644 | * @enable: flag to enable/disable workaround when enabling/disabling jumbos |
| 2645 | **/ |
| 2646 | s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) |
| 2647 | { |
| 2648 | s32 ret_val = 0; |
| 2649 | u16 phy_reg, data; |
| 2650 | u32 mac_reg; |
| 2651 | u16 i; |
| 2652 | |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2653 | if (hw->mac.type < e1000_pch2lan) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2654 | return 0; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2655 | |
| 2656 | /* disable Rx path while enabling/disabling workaround */ |
| 2657 | e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 2658 | ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14)); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2659 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2660 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2661 | |
| 2662 | if (enable) { |
David Ertman | c3a0dce | 2013-09-05 04:24:25 +0000 | [diff] [blame] | 2663 | /* Write Rx addresses (rar_entry_count for RAL/H, and |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2664 | * SHRAL/H) and initial CRC values to the MAC |
| 2665 | */ |
David Ertman | c3a0dce | 2013-09-05 04:24:25 +0000 | [diff] [blame] | 2666 | for (i = 0; i < hw->mac.rar_entry_count; i++) { |
Bruce Allan | 362e20c | 2013-02-20 04:05:45 +0000 | [diff] [blame] | 2667 | u8 mac_addr[ETH_ALEN] = { 0 }; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2668 | u32 addr_high, addr_low; |
| 2669 | |
| 2670 | addr_high = er32(RAH(i)); |
| 2671 | if (!(addr_high & E1000_RAH_AV)) |
| 2672 | continue; |
| 2673 | addr_low = er32(RAL(i)); |
| 2674 | mac_addr[0] = (addr_low & 0xFF); |
| 2675 | mac_addr[1] = ((addr_low >> 8) & 0xFF); |
| 2676 | mac_addr[2] = ((addr_low >> 16) & 0xFF); |
| 2677 | mac_addr[3] = ((addr_low >> 24) & 0xFF); |
| 2678 | mac_addr[4] = (addr_high & 0xFF); |
| 2679 | mac_addr[5] = ((addr_high >> 8) & 0xFF); |
| 2680 | |
Bruce Allan | fe46f58 | 2011-01-06 14:29:51 +0000 | [diff] [blame] | 2681 | ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2682 | } |
| 2683 | |
| 2684 | /* Write Rx addresses to the PHY */ |
| 2685 | e1000_copy_rx_addrs_to_phy_ich8lan(hw); |
| 2686 | |
| 2687 | /* Enable jumbo frame workaround in the MAC */ |
| 2688 | mac_reg = er32(FFLT_DBG); |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 2689 | mac_reg &= ~BIT(14); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2690 | mac_reg |= (7 << 15); |
| 2691 | ew32(FFLT_DBG, mac_reg); |
| 2692 | |
| 2693 | mac_reg = er32(RCTL); |
| 2694 | mac_reg |= E1000_RCTL_SECRC; |
| 2695 | ew32(RCTL, mac_reg); |
| 2696 | |
| 2697 | ret_val = e1000e_read_kmrn_reg(hw, |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 2698 | E1000_KMRNCTRLSTA_CTRL_OFFSET, |
| 2699 | &data); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2700 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2701 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2702 | ret_val = e1000e_write_kmrn_reg(hw, |
| 2703 | E1000_KMRNCTRLSTA_CTRL_OFFSET, |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 2704 | data | BIT(0)); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2705 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2706 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2707 | ret_val = e1000e_read_kmrn_reg(hw, |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 2708 | E1000_KMRNCTRLSTA_HD_CTRL, |
| 2709 | &data); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2710 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2711 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2712 | data &= ~(0xF << 8); |
| 2713 | data |= (0xB << 8); |
| 2714 | ret_val = e1000e_write_kmrn_reg(hw, |
| 2715 | E1000_KMRNCTRLSTA_HD_CTRL, |
| 2716 | data); |
| 2717 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2718 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2719 | |
| 2720 | /* Enable jumbo frame workaround in the PHY */ |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2721 | e1e_rphy(hw, PHY_REG(769, 23), &data); |
| 2722 | data &= ~(0x7F << 5); |
| 2723 | data |= (0x37 << 5); |
| 2724 | ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); |
| 2725 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2726 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2727 | e1e_rphy(hw, PHY_REG(769, 16), &data); |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 2728 | data &= ~BIT(13); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2729 | ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); |
| 2730 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2731 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2732 | e1e_rphy(hw, PHY_REG(776, 20), &data); |
| 2733 | data &= ~(0x3FF << 2); |
David Ertman | 493004d | 2014-07-04 01:44:32 +0000 | [diff] [blame] | 2734 | data |= (E1000_TX_PTR_GAP << 2); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2735 | ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); |
| 2736 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2737 | return ret_val; |
Bruce Allan | b64e9dd | 2011-09-30 08:07:00 +0000 | [diff] [blame] | 2738 | ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2739 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2740 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2741 | e1e_rphy(hw, HV_PM_CTRL, &data); |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 2742 | ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10)); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2743 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2744 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2745 | } else { |
| 2746 | /* Write MAC register values back to h/w defaults */ |
| 2747 | mac_reg = er32(FFLT_DBG); |
| 2748 | mac_reg &= ~(0xF << 14); |
| 2749 | ew32(FFLT_DBG, mac_reg); |
| 2750 | |
| 2751 | mac_reg = er32(RCTL); |
| 2752 | mac_reg &= ~E1000_RCTL_SECRC; |
Bruce Allan | a1ce647 | 2010-09-22 17:16:40 +0000 | [diff] [blame] | 2753 | ew32(RCTL, mac_reg); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2754 | |
| 2755 | ret_val = e1000e_read_kmrn_reg(hw, |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 2756 | E1000_KMRNCTRLSTA_CTRL_OFFSET, |
| 2757 | &data); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2758 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2759 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2760 | ret_val = e1000e_write_kmrn_reg(hw, |
| 2761 | E1000_KMRNCTRLSTA_CTRL_OFFSET, |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 2762 | data & ~BIT(0)); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2763 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2764 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2765 | ret_val = e1000e_read_kmrn_reg(hw, |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 2766 | E1000_KMRNCTRLSTA_HD_CTRL, |
| 2767 | &data); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2768 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2769 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2770 | data &= ~(0xF << 8); |
| 2771 | data |= (0xB << 8); |
| 2772 | ret_val = e1000e_write_kmrn_reg(hw, |
| 2773 | E1000_KMRNCTRLSTA_HD_CTRL, |
| 2774 | data); |
| 2775 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2776 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2777 | |
| 2778 | /* Write PHY register values back to h/w defaults */ |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2779 | e1e_rphy(hw, PHY_REG(769, 23), &data); |
| 2780 | data &= ~(0x7F << 5); |
| 2781 | ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); |
| 2782 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2783 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2784 | e1e_rphy(hw, PHY_REG(769, 16), &data); |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 2785 | data |= BIT(13); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2786 | ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); |
| 2787 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2788 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2789 | e1e_rphy(hw, PHY_REG(776, 20), &data); |
| 2790 | data &= ~(0x3FF << 2); |
| 2791 | data |= (0x8 << 2); |
| 2792 | ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); |
| 2793 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2794 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2795 | ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); |
| 2796 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2797 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2798 | e1e_rphy(hw, HV_PM_CTRL, &data); |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 2799 | ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10)); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2800 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2801 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2802 | } |
| 2803 | |
| 2804 | /* re-enable Rx path after enabling/disabling workaround */ |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 2805 | return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14)); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2806 | } |
| 2807 | |
| 2808 | /** |
Jesse Brandeburg | b50f7bc | 2020-09-25 15:24:37 -0700 | [diff] [blame] | 2809 | * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds |
| 2810 | * @hw: pointer to the HW structure |
| 2811 | * |
| 2812 | * A series of PHY workarounds to be done after every PHY reset. |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2813 | **/ |
| 2814 | static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) |
| 2815 | { |
| 2816 | s32 ret_val = 0; |
| 2817 | |
| 2818 | if (hw->mac.type != e1000_pch2lan) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2819 | return 0; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2820 | |
| 2821 | /* Set MDIO slow mode before any other MDIO access */ |
| 2822 | ret_val = e1000_set_mdio_slow_mode_hv(hw); |
Bruce Allan | 8e5ab42 | 2012-12-05 06:26:19 +0000 | [diff] [blame] | 2823 | if (ret_val) |
| 2824 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2825 | |
Bruce Allan | 4d24136 | 2011-12-16 00:46:06 +0000 | [diff] [blame] | 2826 | ret_val = hw->phy.ops.acquire(hw); |
| 2827 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2828 | return ret_val; |
Bruce Allan | 4d24136 | 2011-12-16 00:46:06 +0000 | [diff] [blame] | 2829 | /* set MSE higher to enable link to stay up when noise is high */ |
Bruce Allan | 4ddc48a | 2012-12-05 06:25:58 +0000 | [diff] [blame] | 2830 | ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); |
Bruce Allan | 4d24136 | 2011-12-16 00:46:06 +0000 | [diff] [blame] | 2831 | if (ret_val) |
| 2832 | goto release; |
| 2833 | /* drop link after 5 times MSE threshold was reached */ |
Bruce Allan | 4ddc48a | 2012-12-05 06:25:58 +0000 | [diff] [blame] | 2834 | ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); |
Bruce Allan | 4d24136 | 2011-12-16 00:46:06 +0000 | [diff] [blame] | 2835 | release: |
| 2836 | hw->phy.ops.release(hw); |
| 2837 | |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2838 | return ret_val; |
| 2839 | } |
| 2840 | |
| 2841 | /** |
Sasha Neftin | 39da2ca | 2021-03-14 15:59:20 +0200 | [diff] [blame] | 2842 | * e1000_k1_workaround_lv - K1 Si workaround |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 2843 | * @hw: pointer to the HW structure |
| 2844 | * |
David Ertman | 77e6114 | 2014-04-22 05:25:53 +0000 | [diff] [blame] | 2845 | * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps |
| 2846 | * Disable K1 in 1000Mbps and 100Mbps |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 2847 | **/ |
| 2848 | static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) |
| 2849 | { |
| 2850 | s32 ret_val = 0; |
| 2851 | u16 status_reg = 0; |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 2852 | |
| 2853 | if (hw->mac.type != e1000_pch2lan) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2854 | return 0; |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 2855 | |
David Ertman | 77e6114 | 2014-04-22 05:25:53 +0000 | [diff] [blame] | 2856 | /* Set K1 beacon duration based on 10Mbs speed */ |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 2857 | ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); |
| 2858 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2859 | return ret_val; |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 2860 | |
| 2861 | if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) |
| 2862 | == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { |
David Ertman | 77e6114 | 2014-04-22 05:25:53 +0000 | [diff] [blame] | 2863 | if (status_reg & |
| 2864 | (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) { |
Bruce Allan | 36ceeb4 | 2012-03-20 03:47:47 +0000 | [diff] [blame] | 2865 | u16 pm_phy_reg; |
| 2866 | |
David Ertman | 77e6114 | 2014-04-22 05:25:53 +0000 | [diff] [blame] | 2867 | /* LV 1G/100 Packet drop issue wa */ |
Bruce Allan | 36ceeb4 | 2012-03-20 03:47:47 +0000 | [diff] [blame] | 2868 | ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); |
| 2869 | if (ret_val) |
| 2870 | return ret_val; |
David Ertman | 77e6114 | 2014-04-22 05:25:53 +0000 | [diff] [blame] | 2871 | pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE; |
Bruce Allan | 36ceeb4 | 2012-03-20 03:47:47 +0000 | [diff] [blame] | 2872 | ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); |
| 2873 | if (ret_val) |
| 2874 | return ret_val; |
Bruce Allan | 0ed013e | 2011-07-29 05:52:56 +0000 | [diff] [blame] | 2875 | } else { |
David Ertman | 77e6114 | 2014-04-22 05:25:53 +0000 | [diff] [blame] | 2876 | u32 mac_reg; |
| 2877 | |
| 2878 | mac_reg = er32(FEXTNVM4); |
| 2879 | mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; |
Bruce Allan | 0ed013e | 2011-07-29 05:52:56 +0000 | [diff] [blame] | 2880 | mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; |
David Ertman | 77e6114 | 2014-04-22 05:25:53 +0000 | [diff] [blame] | 2881 | ew32(FEXTNVM4, mac_reg); |
Bruce Allan | 0ed013e | 2011-07-29 05:52:56 +0000 | [diff] [blame] | 2882 | } |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 2883 | } |
| 2884 | |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 2885 | return ret_val; |
| 2886 | } |
| 2887 | |
| 2888 | /** |
Bruce Allan | 605c82b | 2010-09-22 17:17:01 +0000 | [diff] [blame] | 2889 | * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware |
| 2890 | * @hw: pointer to the HW structure |
| 2891 | * @gate: boolean set to true to gate, false to ungate |
| 2892 | * |
| 2893 | * Gate/ungate the automatic PHY configuration via hardware; perform |
| 2894 | * the configuration via software instead. |
| 2895 | **/ |
| 2896 | static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) |
| 2897 | { |
| 2898 | u32 extcnf_ctrl; |
| 2899 | |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2900 | if (hw->mac.type < e1000_pch2lan) |
Bruce Allan | 605c82b | 2010-09-22 17:17:01 +0000 | [diff] [blame] | 2901 | return; |
| 2902 | |
| 2903 | extcnf_ctrl = er32(EXTCNF_CTRL); |
| 2904 | |
| 2905 | if (gate) |
| 2906 | extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; |
| 2907 | else |
| 2908 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; |
| 2909 | |
| 2910 | ew32(EXTCNF_CTRL, extcnf_ctrl); |
Bruce Allan | 605c82b | 2010-09-22 17:17:01 +0000 | [diff] [blame] | 2911 | } |
| 2912 | |
| 2913 | /** |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 2914 | * e1000_lan_init_done_ich8lan - Check for PHY config completion |
| 2915 | * @hw: pointer to the HW structure |
| 2916 | * |
| 2917 | * Check the appropriate indication the MAC has finished configuring the |
| 2918 | * PHY after a software reset. |
| 2919 | **/ |
| 2920 | static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) |
| 2921 | { |
| 2922 | u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; |
| 2923 | |
| 2924 | /* Wait for basic configuration completes before proceeding */ |
| 2925 | do { |
| 2926 | data = er32(STATUS); |
| 2927 | data &= E1000_STATUS_LAN_INIT_DONE; |
Bruce Allan | ce43a21 | 2013-02-20 04:06:32 +0000 | [diff] [blame] | 2928 | usleep_range(100, 200); |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 2929 | } while ((!data) && --loop); |
| 2930 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2931 | /* If basic configuration is incomplete before the above loop |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 2932 | * count reaches 0, loading the configuration from NVM will |
| 2933 | * leave the PHY in a bad state possibly resulting in no link. |
| 2934 | */ |
| 2935 | if (loop == 0) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 2936 | e_dbg("LAN_INIT_DONE not set, increase timeout\n"); |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 2937 | |
| 2938 | /* Clear the Init Done bit for the next init event */ |
| 2939 | data = er32(STATUS); |
| 2940 | data &= ~E1000_STATUS_LAN_INIT_DONE; |
| 2941 | ew32(STATUS, data); |
| 2942 | } |
| 2943 | |
| 2944 | /** |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 2945 | * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2946 | * @hw: pointer to the HW structure |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2947 | **/ |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 2948 | static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2949 | { |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2950 | s32 ret_val = 0; |
| 2951 | u16 reg; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2952 | |
Bruce Allan | 44abd5c | 2012-02-22 09:02:37 +0000 | [diff] [blame] | 2953 | if (hw->phy.ops.check_reset_block(hw)) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2954 | return 0; |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 2955 | |
Bruce Allan | 5f3eed6 | 2010-09-22 17:15:54 +0000 | [diff] [blame] | 2956 | /* Allow time for h/w to get to quiescent state after reset */ |
Arjan van de Ven | ab6973a | 2019-06-14 17:29:35 -0700 | [diff] [blame] | 2957 | usleep_range(10000, 11000); |
Bruce Allan | 5f3eed6 | 2010-09-22 17:15:54 +0000 | [diff] [blame] | 2958 | |
Bruce Allan | fddaa1a | 2010-01-13 01:52:49 +0000 | [diff] [blame] | 2959 | /* Perform any necessary post-reset workarounds */ |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 2960 | switch (hw->mac.type) { |
| 2961 | case e1000_pchlan: |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2962 | ret_val = e1000_hv_phy_workarounds_ich8lan(hw); |
| 2963 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2964 | return ret_val; |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 2965 | break; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2966 | case e1000_pch2lan: |
| 2967 | ret_val = e1000_lv_phy_workarounds_ich8lan(hw); |
| 2968 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2969 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2970 | break; |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 2971 | default: |
| 2972 | break; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2973 | } |
| 2974 | |
Bruce Allan | 3ebfc7c | 2011-05-13 07:20:14 +0000 | [diff] [blame] | 2975 | /* Clear the host wakeup bit after lcd reset */ |
| 2976 | if (hw->mac.type >= e1000_pchlan) { |
| 2977 | e1e_rphy(hw, BM_PORT_GEN_CFG, ®); |
| 2978 | reg &= ~BM_WUC_HOST_WU_BIT; |
| 2979 | e1e_wphy(hw, BM_PORT_GEN_CFG, reg); |
| 2980 | } |
Bruce Allan | db2932e | 2009-10-26 11:22:47 +0000 | [diff] [blame] | 2981 | |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2982 | /* Configure the LCD with the extended configuration region in NVM */ |
| 2983 | ret_val = e1000_sw_lcd_config_ich8lan(hw); |
| 2984 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2985 | return ret_val; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2986 | |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 2987 | /* Configure the LCD with the OEM bits in NVM */ |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 2988 | ret_val = e1000_oem_bits_config_ich8lan(hw, true); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2989 | |
Bruce Allan | 1effb45 | 2011-02-25 06:58:03 +0000 | [diff] [blame] | 2990 | if (hw->mac.type == e1000_pch2lan) { |
| 2991 | /* Ungate automatic PHY configuration on non-managed 82579 */ |
| 2992 | if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { |
Arjan van de Ven | ab6973a | 2019-06-14 17:29:35 -0700 | [diff] [blame] | 2993 | usleep_range(10000, 11000); |
Bruce Allan | 1effb45 | 2011-02-25 06:58:03 +0000 | [diff] [blame] | 2994 | e1000_gate_hw_phy_config_ich8lan(hw, false); |
| 2995 | } |
| 2996 | |
| 2997 | /* Set EEE LPI Update Timer to 200usec */ |
| 2998 | ret_val = hw->phy.ops.acquire(hw); |
| 2999 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3000 | return ret_val; |
Bruce Allan | 4ddc48a | 2012-12-05 06:25:58 +0000 | [diff] [blame] | 3001 | ret_val = e1000_write_emi_reg_locked(hw, |
| 3002 | I82579_LPI_UPDATE_TIMER, |
| 3003 | 0x1387); |
Bruce Allan | 1effb45 | 2011-02-25 06:58:03 +0000 | [diff] [blame] | 3004 | hw->phy.ops.release(hw); |
Bruce Allan | 605c82b | 2010-09-22 17:17:01 +0000 | [diff] [blame] | 3005 | } |
| 3006 | |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 3007 | return ret_val; |
| 3008 | } |
| 3009 | |
| 3010 | /** |
| 3011 | * e1000_phy_hw_reset_ich8lan - Performs a PHY reset |
| 3012 | * @hw: pointer to the HW structure |
| 3013 | * |
| 3014 | * Resets the PHY |
| 3015 | * This is a function pointer entry point called by drivers |
| 3016 | * or other shared routines. |
| 3017 | **/ |
| 3018 | static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) |
| 3019 | { |
| 3020 | s32 ret_val = 0; |
| 3021 | |
Bruce Allan | 605c82b | 2010-09-22 17:17:01 +0000 | [diff] [blame] | 3022 | /* Gate automatic PHY configuration by hardware on non-managed 82579 */ |
| 3023 | if ((hw->mac.type == e1000_pch2lan) && |
| 3024 | !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) |
| 3025 | e1000_gate_hw_phy_config_ich8lan(hw, true); |
| 3026 | |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 3027 | ret_val = e1000e_phy_hw_reset_generic(hw); |
| 3028 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3029 | return ret_val; |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 3030 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3031 | return e1000_post_phy_reset_ich8lan(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3032 | } |
| 3033 | |
| 3034 | /** |
Bruce Allan | fa2ce13 | 2009-10-26 11:23:25 +0000 | [diff] [blame] | 3035 | * e1000_set_lplu_state_pchlan - Set Low Power Link Up state |
| 3036 | * @hw: pointer to the HW structure |
| 3037 | * @active: true to enable LPLU, false to disable |
| 3038 | * |
| 3039 | * Sets the LPLU state according to the active flag. For PCH, if OEM write |
| 3040 | * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set |
| 3041 | * the phy speed. This function will manually set the LPLU bit and restart |
| 3042 | * auto-neg as hw would do. D3 and D0 LPLU will call the same function |
| 3043 | * since it configures the same bit. |
| 3044 | **/ |
| 3045 | static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) |
| 3046 | { |
Bruce Allan | 70806a7 | 2013-01-05 05:08:37 +0000 | [diff] [blame] | 3047 | s32 ret_val; |
Bruce Allan | fa2ce13 | 2009-10-26 11:23:25 +0000 | [diff] [blame] | 3048 | u16 oem_reg; |
| 3049 | |
| 3050 | ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); |
| 3051 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3052 | return ret_val; |
Bruce Allan | fa2ce13 | 2009-10-26 11:23:25 +0000 | [diff] [blame] | 3053 | |
| 3054 | if (active) |
| 3055 | oem_reg |= HV_OEM_BITS_LPLU; |
| 3056 | else |
| 3057 | oem_reg &= ~HV_OEM_BITS_LPLU; |
| 3058 | |
Bruce Allan | 44abd5c | 2012-02-22 09:02:37 +0000 | [diff] [blame] | 3059 | if (!hw->phy.ops.check_reset_block(hw)) |
Bruce Allan | 464c85e | 2011-12-16 00:46:49 +0000 | [diff] [blame] | 3060 | oem_reg |= HV_OEM_BITS_RESTART_AN; |
| 3061 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3062 | return e1e_wphy(hw, HV_OEM_BITS, oem_reg); |
Bruce Allan | fa2ce13 | 2009-10-26 11:23:25 +0000 | [diff] [blame] | 3063 | } |
| 3064 | |
| 3065 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3066 | * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state |
| 3067 | * @hw: pointer to the HW structure |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 3068 | * @active: true to enable LPLU, false to disable |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3069 | * |
| 3070 | * Sets the LPLU D0 state according to the active flag. When |
| 3071 | * activating LPLU this function also disables smart speed |
| 3072 | * and vice versa. LPLU will not be activated unless the |
| 3073 | * device autonegotiation advertisement meets standards of |
| 3074 | * either 10 or 10/100 or 10/100/1000 at all duplexes. |
| 3075 | * This is a function pointer entry point only called by |
| 3076 | * PHY setup routines. |
| 3077 | **/ |
| 3078 | static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) |
| 3079 | { |
| 3080 | struct e1000_phy_info *phy = &hw->phy; |
| 3081 | u32 phy_ctrl; |
| 3082 | s32 ret_val = 0; |
| 3083 | u16 data; |
| 3084 | |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 3085 | if (phy->type == e1000_phy_ife) |
Bruce Allan | 8260725 | 2012-02-08 02:55:09 +0000 | [diff] [blame] | 3086 | return 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3087 | |
| 3088 | phy_ctrl = er32(PHY_CTRL); |
| 3089 | |
| 3090 | if (active) { |
| 3091 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; |
| 3092 | ew32(PHY_CTRL, phy_ctrl); |
| 3093 | |
Bruce Allan | 60f1292 | 2009-07-01 13:28:14 +0000 | [diff] [blame] | 3094 | if (phy->type != e1000_phy_igp_3) |
| 3095 | return 0; |
| 3096 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 3097 | /* Call gig speed drop workaround on LPLU before accessing |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3098 | * any PHY registers |
| 3099 | */ |
Bruce Allan | 60f1292 | 2009-07-01 13:28:14 +0000 | [diff] [blame] | 3100 | if (hw->mac.type == e1000_ich8lan) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3101 | e1000e_gig_downshift_workaround_ich8lan(hw); |
| 3102 | |
| 3103 | /* When LPLU is enabled, we should disable SmartSpeed */ |
| 3104 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); |
Bruce Allan | 7dbbe5d | 2013-01-05 05:08:31 +0000 | [diff] [blame] | 3105 | if (ret_val) |
| 3106 | return ret_val; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3107 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 3108 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); |
| 3109 | if (ret_val) |
| 3110 | return ret_val; |
| 3111 | } else { |
| 3112 | phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; |
| 3113 | ew32(PHY_CTRL, phy_ctrl); |
| 3114 | |
Bruce Allan | 60f1292 | 2009-07-01 13:28:14 +0000 | [diff] [blame] | 3115 | if (phy->type != e1000_phy_igp_3) |
| 3116 | return 0; |
| 3117 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 3118 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3119 | * during Dx states where the power conservation is most |
| 3120 | * important. During driver activity we should enable |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3121 | * SmartSpeed, so performance is maintained. |
| 3122 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3123 | if (phy->smart_speed == e1000_smart_speed_on) { |
| 3124 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3125 | &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3126 | if (ret_val) |
| 3127 | return ret_val; |
| 3128 | |
| 3129 | data |= IGP01E1000_PSCFR_SMART_SPEED; |
| 3130 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3131 | data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3132 | if (ret_val) |
| 3133 | return ret_val; |
| 3134 | } else if (phy->smart_speed == e1000_smart_speed_off) { |
| 3135 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3136 | &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3137 | if (ret_val) |
| 3138 | return ret_val; |
| 3139 | |
| 3140 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 3141 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3142 | data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3143 | if (ret_val) |
| 3144 | return ret_val; |
| 3145 | } |
| 3146 | } |
| 3147 | |
| 3148 | return 0; |
| 3149 | } |
| 3150 | |
| 3151 | /** |
| 3152 | * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state |
| 3153 | * @hw: pointer to the HW structure |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 3154 | * @active: true to enable LPLU, false to disable |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3155 | * |
| 3156 | * Sets the LPLU D3 state according to the active flag. When |
| 3157 | * activating LPLU this function also disables smart speed |
| 3158 | * and vice versa. LPLU will not be activated unless the |
| 3159 | * device autonegotiation advertisement meets standards of |
| 3160 | * either 10 or 10/100 or 10/100/1000 at all duplexes. |
| 3161 | * This is a function pointer entry point only called by |
| 3162 | * PHY setup routines. |
| 3163 | **/ |
| 3164 | static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) |
| 3165 | { |
| 3166 | struct e1000_phy_info *phy = &hw->phy; |
| 3167 | u32 phy_ctrl; |
Bruce Allan | d7eb338 | 2012-02-08 02:55:14 +0000 | [diff] [blame] | 3168 | s32 ret_val = 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3169 | u16 data; |
| 3170 | |
| 3171 | phy_ctrl = er32(PHY_CTRL); |
| 3172 | |
| 3173 | if (!active) { |
| 3174 | phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; |
| 3175 | ew32(PHY_CTRL, phy_ctrl); |
Bruce Allan | 60f1292 | 2009-07-01 13:28:14 +0000 | [diff] [blame] | 3176 | |
| 3177 | if (phy->type != e1000_phy_igp_3) |
| 3178 | return 0; |
| 3179 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 3180 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3181 | * during Dx states where the power conservation is most |
| 3182 | * important. During driver activity we should enable |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3183 | * SmartSpeed, so performance is maintained. |
| 3184 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3185 | if (phy->smart_speed == e1000_smart_speed_on) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3186 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 3187 | &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3188 | if (ret_val) |
| 3189 | return ret_val; |
| 3190 | |
| 3191 | data |= IGP01E1000_PSCFR_SMART_SPEED; |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3192 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 3193 | data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3194 | if (ret_val) |
| 3195 | return ret_val; |
| 3196 | } else if (phy->smart_speed == e1000_smart_speed_off) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3197 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 3198 | &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3199 | if (ret_val) |
| 3200 | return ret_val; |
| 3201 | |
| 3202 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3203 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 3204 | data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3205 | if (ret_val) |
| 3206 | return ret_val; |
| 3207 | } |
| 3208 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || |
| 3209 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || |
| 3210 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { |
| 3211 | phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; |
| 3212 | ew32(PHY_CTRL, phy_ctrl); |
| 3213 | |
Bruce Allan | 60f1292 | 2009-07-01 13:28:14 +0000 | [diff] [blame] | 3214 | if (phy->type != e1000_phy_igp_3) |
| 3215 | return 0; |
| 3216 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 3217 | /* Call gig speed drop workaround on LPLU before accessing |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3218 | * any PHY registers |
| 3219 | */ |
Bruce Allan | 60f1292 | 2009-07-01 13:28:14 +0000 | [diff] [blame] | 3220 | if (hw->mac.type == e1000_ich8lan) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3221 | e1000e_gig_downshift_workaround_ich8lan(hw); |
| 3222 | |
| 3223 | /* When LPLU is enabled, we should disable SmartSpeed */ |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3224 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3225 | if (ret_val) |
| 3226 | return ret_val; |
| 3227 | |
| 3228 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3229 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3230 | } |
| 3231 | |
Bruce Allan | d7eb338 | 2012-02-08 02:55:14 +0000 | [diff] [blame] | 3232 | return ret_val; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3233 | } |
| 3234 | |
| 3235 | /** |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3236 | * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 |
| 3237 | * @hw: pointer to the HW structure |
| 3238 | * @bank: pointer to the variable that returns the active bank |
| 3239 | * |
| 3240 | * Reads signature byte from the NVM using the flash access registers. |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 3241 | * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3242 | **/ |
| 3243 | static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) |
| 3244 | { |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 3245 | u32 eecd; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3246 | struct e1000_nvm_info *nvm = &hw->nvm; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3247 | u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); |
| 3248 | u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; |
Raanan Avargil | f3ed935 | 2015-10-20 17:13:01 +0300 | [diff] [blame] | 3249 | u32 nvm_dword = 0; |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 3250 | u8 sig_byte = 0; |
Bruce Allan | f71dde6 | 2012-02-08 02:55:35 +0000 | [diff] [blame] | 3251 | s32 ret_val; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3252 | |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 3253 | switch (hw->mac.type) { |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3254 | case e1000_pch_spt: |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 3255 | case e1000_pch_cnp: |
Sasha Neftin | fb776f5 | 2019-10-16 11:08:38 +0300 | [diff] [blame] | 3256 | case e1000_pch_tgp: |
Sasha Neftin | 59e4668 | 2020-01-19 13:57:13 +0200 | [diff] [blame] | 3257 | case e1000_pch_adp: |
Sasha Neftin | cc23f4f | 2020-08-13 11:34:06 +0300 | [diff] [blame] | 3258 | case e1000_pch_mtp: |
Sasha Neftin | 820b8ff | 2021-03-04 09:38:13 +0200 | [diff] [blame] | 3259 | case e1000_pch_lnp: |
Sasha Neftin | 0c9183c | 2022-09-29 11:08:59 +0300 | [diff] [blame] | 3260 | case e1000_pch_ptp: |
Sasha Neftin | 1fe4f45 | 2023-07-18 19:28:57 +0300 | [diff] [blame] | 3261 | case e1000_pch_nvp: |
Raanan Avargil | f3ed935 | 2015-10-20 17:13:01 +0300 | [diff] [blame] | 3262 | bank1_offset = nvm->flash_bank_size; |
| 3263 | act_offset = E1000_ICH_NVM_SIG_WORD; |
| 3264 | |
| 3265 | /* set bank to 0 in case flash read fails */ |
| 3266 | *bank = 0; |
| 3267 | |
| 3268 | /* Check bank 0 */ |
| 3269 | ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, |
| 3270 | &nvm_dword); |
| 3271 | if (ret_val) |
| 3272 | return ret_val; |
Jesse Brandeburg | b9a4525 | 2023-12-05 17:01:08 -0800 | [diff] [blame] | 3273 | sig_byte = FIELD_GET(0xFF00, nvm_dword); |
Raanan Avargil | f3ed935 | 2015-10-20 17:13:01 +0300 | [diff] [blame] | 3274 | if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == |
| 3275 | E1000_ICH_NVM_SIG_VALUE) { |
| 3276 | *bank = 0; |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3277 | return 0; |
| 3278 | } |
Raanan Avargil | f3ed935 | 2015-10-20 17:13:01 +0300 | [diff] [blame] | 3279 | |
| 3280 | /* Check bank 1 */ |
| 3281 | ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + |
| 3282 | bank1_offset, |
| 3283 | &nvm_dword); |
| 3284 | if (ret_val) |
| 3285 | return ret_val; |
Jesse Brandeburg | b9a4525 | 2023-12-05 17:01:08 -0800 | [diff] [blame] | 3286 | sig_byte = FIELD_GET(0xFF00, nvm_dword); |
Raanan Avargil | f3ed935 | 2015-10-20 17:13:01 +0300 | [diff] [blame] | 3287 | if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == |
| 3288 | E1000_ICH_NVM_SIG_VALUE) { |
| 3289 | *bank = 1; |
| 3290 | return 0; |
| 3291 | } |
| 3292 | |
| 3293 | e_dbg("ERROR: No valid NVM bank present\n"); |
| 3294 | return -E1000_ERR_NVM; |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 3295 | case e1000_ich8lan: |
| 3296 | case e1000_ich9lan: |
| 3297 | eecd = er32(EECD); |
| 3298 | if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == |
| 3299 | E1000_EECD_SEC1VAL_VALID_MASK) { |
| 3300 | if (eecd & E1000_EECD_SEC1VAL) |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3301 | *bank = 1; |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 3302 | else |
| 3303 | *bank = 0; |
| 3304 | |
| 3305 | return 0; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3306 | } |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 3307 | e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); |
Jeff Kirsher | 5463fce6 | 2020-06-03 20:07:26 -0700 | [diff] [blame] | 3308 | fallthrough; |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 3309 | default: |
| 3310 | /* set bank to 0 in case flash read fails */ |
| 3311 | *bank = 0; |
| 3312 | |
| 3313 | /* Check bank 0 */ |
| 3314 | ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 3315 | &sig_byte); |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 3316 | if (ret_val) |
| 3317 | return ret_val; |
| 3318 | if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == |
| 3319 | E1000_ICH_NVM_SIG_VALUE) { |
| 3320 | *bank = 0; |
| 3321 | return 0; |
| 3322 | } |
| 3323 | |
| 3324 | /* Check bank 1 */ |
| 3325 | ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 3326 | bank1_offset, |
| 3327 | &sig_byte); |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 3328 | if (ret_val) |
| 3329 | return ret_val; |
| 3330 | if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == |
| 3331 | E1000_ICH_NVM_SIG_VALUE) { |
| 3332 | *bank = 1; |
| 3333 | return 0; |
| 3334 | } |
| 3335 | |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3336 | e_dbg("ERROR: No valid NVM bank present\n"); |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 3337 | return -E1000_ERR_NVM; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3338 | } |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3339 | } |
| 3340 | |
| 3341 | /** |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3342 | * e1000_read_nvm_spt - NVM access for SPT |
| 3343 | * @hw: pointer to the HW structure |
| 3344 | * @offset: The offset (in bytes) of the word(s) to read. |
| 3345 | * @words: Size of data to read in words. |
| 3346 | * @data: pointer to the word(s) to read at offset. |
| 3347 | * |
| 3348 | * Reads a word(s) from the NVM |
| 3349 | **/ |
| 3350 | static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, |
| 3351 | u16 *data) |
| 3352 | { |
| 3353 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 3354 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
| 3355 | u32 act_offset; |
| 3356 | s32 ret_val = 0; |
| 3357 | u32 bank = 0; |
| 3358 | u32 dword = 0; |
| 3359 | u16 offset_to_read; |
| 3360 | u16 i; |
| 3361 | |
| 3362 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || |
| 3363 | (words == 0)) { |
| 3364 | e_dbg("nvm parameter(s) out of bounds\n"); |
| 3365 | ret_val = -E1000_ERR_NVM; |
| 3366 | goto out; |
| 3367 | } |
| 3368 | |
| 3369 | nvm->ops.acquire(hw); |
| 3370 | |
| 3371 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
| 3372 | if (ret_val) { |
| 3373 | e_dbg("Could not detect valid bank, assuming bank 0\n"); |
| 3374 | bank = 0; |
| 3375 | } |
| 3376 | |
| 3377 | act_offset = (bank) ? nvm->flash_bank_size : 0; |
| 3378 | act_offset += offset; |
| 3379 | |
| 3380 | ret_val = 0; |
| 3381 | |
| 3382 | for (i = 0; i < words; i += 2) { |
| 3383 | if (words - i == 1) { |
| 3384 | if (dev_spec->shadow_ram[offset + i].modified) { |
| 3385 | data[i] = |
| 3386 | dev_spec->shadow_ram[offset + i].value; |
| 3387 | } else { |
| 3388 | offset_to_read = act_offset + i - |
| 3389 | ((act_offset + i) % 2); |
| 3390 | ret_val = |
| 3391 | e1000_read_flash_dword_ich8lan(hw, |
| 3392 | offset_to_read, |
| 3393 | &dword); |
| 3394 | if (ret_val) |
| 3395 | break; |
| 3396 | if ((act_offset + i) % 2 == 0) |
| 3397 | data[i] = (u16)(dword & 0xFFFF); |
| 3398 | else |
| 3399 | data[i] = (u16)((dword >> 16) & 0xFFFF); |
| 3400 | } |
| 3401 | } else { |
| 3402 | offset_to_read = act_offset + i; |
| 3403 | if (!(dev_spec->shadow_ram[offset + i].modified) || |
| 3404 | !(dev_spec->shadow_ram[offset + i + 1].modified)) { |
| 3405 | ret_val = |
| 3406 | e1000_read_flash_dword_ich8lan(hw, |
| 3407 | offset_to_read, |
| 3408 | &dword); |
| 3409 | if (ret_val) |
| 3410 | break; |
| 3411 | } |
| 3412 | if (dev_spec->shadow_ram[offset + i].modified) |
| 3413 | data[i] = |
| 3414 | dev_spec->shadow_ram[offset + i].value; |
| 3415 | else |
| 3416 | data[i] = (u16)(dword & 0xFFFF); |
| 3417 | if (dev_spec->shadow_ram[offset + i].modified) |
| 3418 | data[i + 1] = |
| 3419 | dev_spec->shadow_ram[offset + i + 1].value; |
| 3420 | else |
| 3421 | data[i + 1] = (u16)(dword >> 16 & 0xFFFF); |
| 3422 | } |
| 3423 | } |
| 3424 | |
| 3425 | nvm->ops.release(hw); |
| 3426 | |
| 3427 | out: |
| 3428 | if (ret_val) |
| 3429 | e_dbg("NVM read error: %d\n", ret_val); |
| 3430 | |
| 3431 | return ret_val; |
| 3432 | } |
| 3433 | |
| 3434 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3435 | * e1000_read_nvm_ich8lan - Read word(s) from the NVM |
| 3436 | * @hw: pointer to the HW structure |
| 3437 | * @offset: The offset (in bytes) of the word(s) to read. |
| 3438 | * @words: Size of data to read in words |
| 3439 | * @data: Pointer to the word(s) to read at offset. |
| 3440 | * |
| 3441 | * Reads a word(s) from the NVM using the flash access registers. |
| 3442 | **/ |
| 3443 | static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, |
| 3444 | u16 *data) |
| 3445 | { |
| 3446 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 3447 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
| 3448 | u32 act_offset; |
Bruce Allan | 148675a | 2009-08-07 07:41:56 +0000 | [diff] [blame] | 3449 | s32 ret_val = 0; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3450 | u32 bank = 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3451 | u16 i, word; |
| 3452 | |
| 3453 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || |
| 3454 | (words == 0)) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3455 | e_dbg("nvm parameter(s) out of bounds\n"); |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 3456 | ret_val = -E1000_ERR_NVM; |
| 3457 | goto out; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3458 | } |
| 3459 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 3460 | nvm->ops.acquire(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3461 | |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3462 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
Bruce Allan | 148675a | 2009-08-07 07:41:56 +0000 | [diff] [blame] | 3463 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3464 | e_dbg("Could not detect valid bank, assuming bank 0\n"); |
Bruce Allan | 148675a | 2009-08-07 07:41:56 +0000 | [diff] [blame] | 3465 | bank = 0; |
| 3466 | } |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3467 | |
| 3468 | act_offset = (bank) ? nvm->flash_bank_size : 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3469 | act_offset += offset; |
| 3470 | |
Bruce Allan | 148675a | 2009-08-07 07:41:56 +0000 | [diff] [blame] | 3471 | ret_val = 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3472 | for (i = 0; i < words; i++) { |
Bruce Allan | 362e20c | 2013-02-20 04:05:45 +0000 | [diff] [blame] | 3473 | if (dev_spec->shadow_ram[offset + i].modified) { |
| 3474 | data[i] = dev_spec->shadow_ram[offset + i].value; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3475 | } else { |
| 3476 | ret_val = e1000_read_flash_word_ich8lan(hw, |
| 3477 | act_offset + i, |
| 3478 | &word); |
| 3479 | if (ret_val) |
| 3480 | break; |
| 3481 | data[i] = word; |
| 3482 | } |
| 3483 | } |
| 3484 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 3485 | nvm->ops.release(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3486 | |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 3487 | out: |
| 3488 | if (ret_val) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3489 | e_dbg("NVM read error: %d\n", ret_val); |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 3490 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3491 | return ret_val; |
| 3492 | } |
| 3493 | |
| 3494 | /** |
| 3495 | * e1000_flash_cycle_init_ich8lan - Initialize flash |
| 3496 | * @hw: pointer to the HW structure |
| 3497 | * |
| 3498 | * This function does initial flash setup so that a new read/write/erase cycle |
| 3499 | * can be started. |
| 3500 | **/ |
| 3501 | static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) |
| 3502 | { |
| 3503 | union ich8_hws_flash_status hsfsts; |
| 3504 | s32 ret_val = -E1000_ERR_NVM; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3505 | |
| 3506 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
| 3507 | |
| 3508 | /* Check if the flash descriptor is valid */ |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 3509 | if (!hsfsts.hsf_status.fldesvalid) { |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 3510 | e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3511 | return -E1000_ERR_NVM; |
| 3512 | } |
| 3513 | |
| 3514 | /* Clear FCERR and DAEL in hw status by writing 1 */ |
| 3515 | hsfsts.hsf_status.flcerr = 1; |
| 3516 | hsfsts.hsf_status.dael = 1; |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 3517 | if (hw->mac.type >= e1000_pch_spt) |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3518 | ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); |
| 3519 | else |
| 3520 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3521 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 3522 | /* Either we should have a hardware SPI cycle in progress |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3523 | * bit to check against, in order to start a new cycle or |
| 3524 | * FDONE bit should be changed in the hardware so that it |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 3525 | * is 1 after hardware reset, which can then be used as an |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3526 | * indication whether a cycle is in progress or has been |
| 3527 | * completed. |
| 3528 | */ |
| 3529 | |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 3530 | if (!hsfsts.hsf_status.flcinprog) { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 3531 | /* There is no cycle running at present, |
Bruce Allan | 5ff5b66 | 2009-12-01 15:51:11 +0000 | [diff] [blame] | 3532 | * so we can start a cycle. |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3533 | * Begin by setting Flash Cycle Done. |
| 3534 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3535 | hsfsts.hsf_status.flcdone = 1; |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 3536 | if (hw->mac.type >= e1000_pch_spt) |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3537 | ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); |
| 3538 | else |
| 3539 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3540 | ret_val = 0; |
| 3541 | } else { |
Bruce Allan | f71dde6 | 2012-02-08 02:55:35 +0000 | [diff] [blame] | 3542 | s32 i; |
Bruce Allan | 90da066 | 2011-01-06 07:02:53 +0000 | [diff] [blame] | 3543 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 3544 | /* Otherwise poll for sometime so the current |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3545 | * cycle has a chance to end before giving up. |
| 3546 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3547 | for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { |
Bruce Allan | c8243ee | 2011-12-17 08:32:57 +0000 | [diff] [blame] | 3548 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 3549 | if (!hsfsts.hsf_status.flcinprog) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3550 | ret_val = 0; |
| 3551 | break; |
| 3552 | } |
| 3553 | udelay(1); |
| 3554 | } |
Bruce Allan | 9e2d765 | 2012-01-31 06:37:27 +0000 | [diff] [blame] | 3555 | if (!ret_val) { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 3556 | /* Successful in waiting for previous cycle to timeout, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3557 | * now set the Flash Cycle Done. |
| 3558 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3559 | hsfsts.hsf_status.flcdone = 1; |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 3560 | if (hw->mac.type >= e1000_pch_spt) |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3561 | ew32flash(ICH_FLASH_HSFSTS, |
| 3562 | hsfsts.regval & 0xFFFF); |
| 3563 | else |
| 3564 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3565 | } else { |
Joe Perches | 2c73e1f | 2010-03-26 20:16:59 +0000 | [diff] [blame] | 3566 | e_dbg("Flash controller busy, cannot get access\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3567 | } |
| 3568 | } |
| 3569 | |
| 3570 | return ret_val; |
| 3571 | } |
| 3572 | |
| 3573 | /** |
| 3574 | * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) |
| 3575 | * @hw: pointer to the HW structure |
| 3576 | * @timeout: maximum time to wait for completion |
| 3577 | * |
| 3578 | * This function starts a flash cycle and waits for its completion. |
| 3579 | **/ |
| 3580 | static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) |
| 3581 | { |
| 3582 | union ich8_hws_flash_ctrl hsflctl; |
| 3583 | union ich8_hws_flash_status hsfsts; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3584 | u32 i = 0; |
| 3585 | |
| 3586 | /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 3587 | if (hw->mac.type >= e1000_pch_spt) |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3588 | hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; |
| 3589 | else |
| 3590 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3591 | hsflctl.hsf_ctrl.flcgo = 1; |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3592 | |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 3593 | if (hw->mac.type >= e1000_pch_spt) |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3594 | ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); |
| 3595 | else |
| 3596 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3597 | |
| 3598 | /* wait till FDONE bit is set to 1 */ |
| 3599 | do { |
| 3600 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 3601 | if (hsfsts.hsf_status.flcdone) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3602 | break; |
| 3603 | udelay(1); |
| 3604 | } while (i++ < timeout); |
| 3605 | |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 3606 | if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3607 | return 0; |
| 3608 | |
Bruce Allan | 55920b5 | 2012-02-08 02:55:25 +0000 | [diff] [blame] | 3609 | return -E1000_ERR_NVM; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3610 | } |
| 3611 | |
| 3612 | /** |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3613 | * e1000_read_flash_dword_ich8lan - Read dword from flash |
| 3614 | * @hw: pointer to the HW structure |
| 3615 | * @offset: offset to data location |
| 3616 | * @data: pointer to the location for storing the data |
| 3617 | * |
| 3618 | * Reads the flash dword at offset into data. Offset is converted |
| 3619 | * to bytes before read. |
| 3620 | **/ |
| 3621 | static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, |
| 3622 | u32 *data) |
| 3623 | { |
| 3624 | /* Must convert word offset into bytes. */ |
| 3625 | offset <<= 1; |
| 3626 | return e1000_read_flash_data32_ich8lan(hw, offset, data); |
| 3627 | } |
| 3628 | |
| 3629 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3630 | * e1000_read_flash_word_ich8lan - Read word from flash |
| 3631 | * @hw: pointer to the HW structure |
| 3632 | * @offset: offset to data location |
| 3633 | * @data: pointer to the location for storing the data |
| 3634 | * |
| 3635 | * Reads the flash word at offset into data. Offset is converted |
| 3636 | * to bytes before read. |
| 3637 | **/ |
| 3638 | static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, |
| 3639 | u16 *data) |
| 3640 | { |
| 3641 | /* Must convert offset into bytes. */ |
| 3642 | offset <<= 1; |
| 3643 | |
| 3644 | return e1000_read_flash_data_ich8lan(hw, offset, 2, data); |
| 3645 | } |
| 3646 | |
| 3647 | /** |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3648 | * e1000_read_flash_byte_ich8lan - Read byte from flash |
| 3649 | * @hw: pointer to the HW structure |
| 3650 | * @offset: The offset of the byte to read. |
| 3651 | * @data: Pointer to a byte to store the value read. |
| 3652 | * |
| 3653 | * Reads a single byte from the NVM using the flash access registers. |
| 3654 | **/ |
| 3655 | static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, |
| 3656 | u8 *data) |
| 3657 | { |
| 3658 | s32 ret_val; |
| 3659 | u16 word = 0; |
| 3660 | |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3661 | /* In SPT, only 32 bits access is supported, |
| 3662 | * so this function should not be called. |
| 3663 | */ |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 3664 | if (hw->mac.type >= e1000_pch_spt) |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3665 | return -E1000_ERR_NVM; |
| 3666 | else |
| 3667 | ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); |
| 3668 | |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3669 | if (ret_val) |
| 3670 | return ret_val; |
| 3671 | |
| 3672 | *data = (u8)word; |
| 3673 | |
| 3674 | return 0; |
| 3675 | } |
| 3676 | |
| 3677 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3678 | * e1000_read_flash_data_ich8lan - Read byte or word from NVM |
| 3679 | * @hw: pointer to the HW structure |
| 3680 | * @offset: The offset (in bytes) of the byte or word to read. |
| 3681 | * @size: Size of data to read, 1=byte 2=word |
| 3682 | * @data: Pointer to the word to store the value read. |
| 3683 | * |
| 3684 | * Reads a byte or word from the NVM using the flash access registers. |
| 3685 | **/ |
| 3686 | static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, |
| 3687 | u8 size, u16 *data) |
| 3688 | { |
| 3689 | union ich8_hws_flash_status hsfsts; |
| 3690 | union ich8_hws_flash_ctrl hsflctl; |
| 3691 | u32 flash_linear_addr; |
| 3692 | u32 flash_data = 0; |
| 3693 | s32 ret_val = -E1000_ERR_NVM; |
| 3694 | u8 count = 0; |
| 3695 | |
Bruce Allan | e80bd1d | 2013-05-01 01:19:46 +0000 | [diff] [blame] | 3696 | if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3697 | return -E1000_ERR_NVM; |
| 3698 | |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 3699 | flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + |
| 3700 | hw->nvm.flash_base_addr); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3701 | |
| 3702 | do { |
| 3703 | udelay(1); |
| 3704 | /* Steps */ |
| 3705 | ret_val = e1000_flash_cycle_init_ich8lan(hw); |
Bruce Allan | 9e2d765 | 2012-01-31 06:37:27 +0000 | [diff] [blame] | 3706 | if (ret_val) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3707 | break; |
| 3708 | |
| 3709 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); |
| 3710 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ |
| 3711 | hsflctl.hsf_ctrl.fldbcount = size - 1; |
| 3712 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; |
| 3713 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); |
| 3714 | |
| 3715 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); |
| 3716 | |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 3717 | ret_val = |
| 3718 | e1000_flash_cycle_ich8lan(hw, |
| 3719 | ICH_FLASH_READ_COMMAND_TIMEOUT); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3720 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 3721 | /* Check if FCERR is set to 1, if set to 1, clear it |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3722 | * and try the whole sequence a few more times, else |
| 3723 | * read in (shift in) the Flash Data0, the order is |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3724 | * least significant byte first msb to lsb |
| 3725 | */ |
Bruce Allan | 9e2d765 | 2012-01-31 06:37:27 +0000 | [diff] [blame] | 3726 | if (!ret_val) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3727 | flash_data = er32flash(ICH_FLASH_FDATA0); |
Bruce Allan | b1cdfea | 2010-12-11 05:53:47 +0000 | [diff] [blame] | 3728 | if (size == 1) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3729 | *data = (u8)(flash_data & 0x000000FF); |
Bruce Allan | b1cdfea | 2010-12-11 05:53:47 +0000 | [diff] [blame] | 3730 | else if (size == 2) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3731 | *data = (u16)(flash_data & 0x0000FFFF); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3732 | break; |
| 3733 | } else { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 3734 | /* If we've gotten here, then things are probably |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3735 | * completely hosed, but if the error condition is |
| 3736 | * detected, it won't hurt to give it another try... |
| 3737 | * ICH_FLASH_CYCLE_REPEAT_COUNT times. |
| 3738 | */ |
| 3739 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 3740 | if (hsfsts.hsf_status.flcerr) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3741 | /* Repeat for some time before giving up. */ |
| 3742 | continue; |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 3743 | } else if (!hsfsts.hsf_status.flcdone) { |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 3744 | e_dbg("Timeout error - flash cycle did not complete.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3745 | break; |
| 3746 | } |
| 3747 | } |
| 3748 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); |
| 3749 | |
| 3750 | return ret_val; |
| 3751 | } |
| 3752 | |
| 3753 | /** |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3754 | * e1000_read_flash_data32_ich8lan - Read dword from NVM |
| 3755 | * @hw: pointer to the HW structure |
| 3756 | * @offset: The offset (in bytes) of the dword to read. |
| 3757 | * @data: Pointer to the dword to store the value read. |
| 3758 | * |
| 3759 | * Reads a byte or word from the NVM using the flash access registers. |
| 3760 | **/ |
| 3761 | |
| 3762 | static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, |
| 3763 | u32 *data) |
| 3764 | { |
| 3765 | union ich8_hws_flash_status hsfsts; |
| 3766 | union ich8_hws_flash_ctrl hsflctl; |
| 3767 | u32 flash_linear_addr; |
| 3768 | s32 ret_val = -E1000_ERR_NVM; |
| 3769 | u8 count = 0; |
| 3770 | |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 3771 | if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt) |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3772 | return -E1000_ERR_NVM; |
| 3773 | flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + |
| 3774 | hw->nvm.flash_base_addr); |
| 3775 | |
| 3776 | do { |
| 3777 | udelay(1); |
| 3778 | /* Steps */ |
| 3779 | ret_val = e1000_flash_cycle_init_ich8lan(hw); |
| 3780 | if (ret_val) |
| 3781 | break; |
| 3782 | /* In SPT, This register is in Lan memory space, not flash. |
| 3783 | * Therefore, only 32 bit access is supported |
| 3784 | */ |
| 3785 | hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; |
| 3786 | |
| 3787 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ |
| 3788 | hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; |
| 3789 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; |
| 3790 | /* In SPT, This register is in Lan memory space, not flash. |
| 3791 | * Therefore, only 32 bit access is supported |
| 3792 | */ |
| 3793 | ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16); |
| 3794 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); |
| 3795 | |
| 3796 | ret_val = |
| 3797 | e1000_flash_cycle_ich8lan(hw, |
| 3798 | ICH_FLASH_READ_COMMAND_TIMEOUT); |
| 3799 | |
| 3800 | /* Check if FCERR is set to 1, if set to 1, clear it |
| 3801 | * and try the whole sequence a few more times, else |
| 3802 | * read in (shift in) the Flash Data0, the order is |
| 3803 | * least significant byte first msb to lsb |
| 3804 | */ |
| 3805 | if (!ret_val) { |
| 3806 | *data = er32flash(ICH_FLASH_FDATA0); |
| 3807 | break; |
| 3808 | } else { |
| 3809 | /* If we've gotten here, then things are probably |
| 3810 | * completely hosed, but if the error condition is |
| 3811 | * detected, it won't hurt to give it another try... |
| 3812 | * ICH_FLASH_CYCLE_REPEAT_COUNT times. |
| 3813 | */ |
| 3814 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
| 3815 | if (hsfsts.hsf_status.flcerr) { |
| 3816 | /* Repeat for some time before giving up. */ |
| 3817 | continue; |
| 3818 | } else if (!hsfsts.hsf_status.flcdone) { |
| 3819 | e_dbg("Timeout error - flash cycle did not complete.\n"); |
| 3820 | break; |
| 3821 | } |
| 3822 | } |
| 3823 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); |
| 3824 | |
| 3825 | return ret_val; |
| 3826 | } |
| 3827 | |
| 3828 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3829 | * e1000_write_nvm_ich8lan - Write word(s) to the NVM |
| 3830 | * @hw: pointer to the HW structure |
| 3831 | * @offset: The offset (in bytes) of the word(s) to write. |
| 3832 | * @words: Size of data to write in words |
| 3833 | * @data: Pointer to the word(s) to write at offset. |
| 3834 | * |
| 3835 | * Writes a byte or word to the NVM using the flash access registers. |
| 3836 | **/ |
| 3837 | static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, |
| 3838 | u16 *data) |
| 3839 | { |
| 3840 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 3841 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3842 | u16 i; |
| 3843 | |
| 3844 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || |
| 3845 | (words == 0)) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3846 | e_dbg("nvm parameter(s) out of bounds\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3847 | return -E1000_ERR_NVM; |
| 3848 | } |
| 3849 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 3850 | nvm->ops.acquire(hw); |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 3851 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3852 | for (i = 0; i < words; i++) { |
Bruce Allan | 362e20c | 2013-02-20 04:05:45 +0000 | [diff] [blame] | 3853 | dev_spec->shadow_ram[offset + i].modified = true; |
| 3854 | dev_spec->shadow_ram[offset + i].value = data[i]; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3855 | } |
| 3856 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 3857 | nvm->ops.release(hw); |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 3858 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3859 | return 0; |
| 3860 | } |
| 3861 | |
| 3862 | /** |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3863 | * e1000_update_nvm_checksum_spt - Update the checksum for NVM |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3864 | * @hw: pointer to the HW structure |
| 3865 | * |
| 3866 | * The NVM checksum is updated by calling the generic update_nvm_checksum, |
| 3867 | * which writes the checksum to the shadow ram. The changes in the shadow |
| 3868 | * ram are then committed to the EEPROM by processing each bank at a time |
| 3869 | * checking for the modified bit and writing only the pending changes. |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 3870 | * After a successful commit, the shadow ram is cleared and is ready for |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3871 | * future writes. |
| 3872 | **/ |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3873 | static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3874 | { |
| 3875 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 3876 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3877 | u32 i, act_offset, new_bank_offset, old_bank_offset, bank; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3878 | s32 ret_val; |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3879 | u32 dword = 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3880 | |
| 3881 | ret_val = e1000e_update_nvm_checksum_generic(hw); |
| 3882 | if (ret_val) |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 3883 | goto out; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3884 | |
| 3885 | if (nvm->type != e1000_nvm_flash_sw) |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 3886 | goto out; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3887 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 3888 | nvm->ops.acquire(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3889 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 3890 | /* We're writing to the opposite bank so if we're on bank 1, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3891 | * write to bank 0 etc. We also need to erase the segment that |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3892 | * is going to be written |
| 3893 | */ |
Bruce Allan | e80bd1d | 2013-05-01 01:19:46 +0000 | [diff] [blame] | 3894 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 3895 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3896 | e_dbg("Could not detect valid bank, assuming bank 0\n"); |
Bruce Allan | 148675a | 2009-08-07 07:41:56 +0000 | [diff] [blame] | 3897 | bank = 0; |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 3898 | } |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3899 | |
| 3900 | if (bank == 0) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3901 | new_bank_offset = nvm->flash_bank_size; |
| 3902 | old_bank_offset = 0; |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 3903 | ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); |
Bruce Allan | 9c5e209 | 2010-05-10 15:00:31 +0000 | [diff] [blame] | 3904 | if (ret_val) |
| 3905 | goto release; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3906 | } else { |
| 3907 | old_bank_offset = nvm->flash_bank_size; |
| 3908 | new_bank_offset = 0; |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 3909 | ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); |
Bruce Allan | 9c5e209 | 2010-05-10 15:00:31 +0000 | [diff] [blame] | 3910 | if (ret_val) |
| 3911 | goto release; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3912 | } |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3913 | for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 3914 | /* Determine whether to write the value stored |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3915 | * in the other NVM bank or a modified value stored |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3916 | * in the shadow RAM |
| 3917 | */ |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3918 | ret_val = e1000_read_flash_dword_ich8lan(hw, |
| 3919 | i + old_bank_offset, |
| 3920 | &dword); |
| 3921 | |
| 3922 | if (dev_spec->shadow_ram[i].modified) { |
| 3923 | dword &= 0xffff0000; |
| 3924 | dword |= (dev_spec->shadow_ram[i].value & 0xffff); |
| 3925 | } |
| 3926 | if (dev_spec->shadow_ram[i + 1].modified) { |
| 3927 | dword &= 0x0000ffff; |
| 3928 | dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) |
| 3929 | << 16); |
| 3930 | } |
| 3931 | if (ret_val) |
| 3932 | break; |
| 3933 | |
| 3934 | /* If the word is 0x13, then make sure the signature bits |
| 3935 | * (15:14) are 11b until the commit has completed. |
| 3936 | * This will allow us to write 10b which indicates the |
| 3937 | * signature is valid. We want to do this after the write |
| 3938 | * has completed so that we don't mark the segment valid |
| 3939 | * while the write is still in progress |
| 3940 | */ |
| 3941 | if (i == E1000_ICH_NVM_SIG_WORD - 1) |
| 3942 | dword |= E1000_ICH_NVM_SIG_MASK << 16; |
| 3943 | |
| 3944 | /* Convert offset to bytes. */ |
| 3945 | act_offset = (i + new_bank_offset) << 1; |
| 3946 | |
| 3947 | usleep_range(100, 200); |
| 3948 | |
| 3949 | /* Write the data to the new bank. Offset in words */ |
| 3950 | act_offset = i + new_bank_offset; |
| 3951 | ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, |
| 3952 | dword); |
| 3953 | if (ret_val) |
| 3954 | break; |
| 3955 | } |
| 3956 | |
| 3957 | /* Don't bother writing the segment valid bits if sector |
| 3958 | * programming failed. |
| 3959 | */ |
| 3960 | if (ret_val) { |
| 3961 | /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ |
| 3962 | e_dbg("Flash commit failed.\n"); |
| 3963 | goto release; |
| 3964 | } |
| 3965 | |
| 3966 | /* Finally validate the new segment by setting bit 15:14 |
| 3967 | * to 10b in word 0x13 , this can be done without an |
| 3968 | * erase as well since these bits are 11 to start with |
| 3969 | * and we need to change bit 14 to 0b |
| 3970 | */ |
| 3971 | act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; |
| 3972 | |
| 3973 | /*offset in words but we read dword */ |
| 3974 | --act_offset; |
| 3975 | ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); |
| 3976 | |
| 3977 | if (ret_val) |
| 3978 | goto release; |
| 3979 | |
| 3980 | dword &= 0xBFFFFFFF; |
| 3981 | ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); |
| 3982 | |
| 3983 | if (ret_val) |
| 3984 | goto release; |
| 3985 | |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 3986 | /* offset in words but we read dword */ |
| 3987 | act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; |
| 3988 | ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); |
| 3989 | |
| 3990 | if (ret_val) |
| 3991 | goto release; |
| 3992 | |
| 3993 | dword &= 0x00FFFFFF; |
| 3994 | ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); |
| 3995 | |
| 3996 | if (ret_val) |
| 3997 | goto release; |
| 3998 | |
| 3999 | /* Great! Everything worked, we can now clear the cached entries. */ |
| 4000 | for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { |
| 4001 | dev_spec->shadow_ram[i].modified = false; |
| 4002 | dev_spec->shadow_ram[i].value = 0xFFFF; |
| 4003 | } |
| 4004 | |
| 4005 | release: |
| 4006 | nvm->ops.release(hw); |
| 4007 | |
| 4008 | /* Reload the EEPROM, or else modifications will not appear |
| 4009 | * until after the next adapter reset. |
| 4010 | */ |
| 4011 | if (!ret_val) { |
| 4012 | nvm->ops.reload(hw); |
Arjan van de Ven | ab6973a | 2019-06-14 17:29:35 -0700 | [diff] [blame] | 4013 | usleep_range(10000, 11000); |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 4014 | } |
| 4015 | |
| 4016 | out: |
| 4017 | if (ret_val) |
| 4018 | e_dbg("NVM update error: %d\n", ret_val); |
| 4019 | |
| 4020 | return ret_val; |
| 4021 | } |
| 4022 | |
| 4023 | /** |
| 4024 | * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM |
| 4025 | * @hw: pointer to the HW structure |
| 4026 | * |
| 4027 | * The NVM checksum is updated by calling the generic update_nvm_checksum, |
| 4028 | * which writes the checksum to the shadow ram. The changes in the shadow |
| 4029 | * ram are then committed to the EEPROM by processing each bank at a time |
| 4030 | * checking for the modified bit and writing only the pending changes. |
| 4031 | * After a successful commit, the shadow ram is cleared and is ready for |
| 4032 | * future writes. |
| 4033 | **/ |
| 4034 | static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) |
| 4035 | { |
| 4036 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 4037 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
| 4038 | u32 i, act_offset, new_bank_offset, old_bank_offset, bank; |
| 4039 | s32 ret_val; |
| 4040 | u16 data = 0; |
| 4041 | |
| 4042 | ret_val = e1000e_update_nvm_checksum_generic(hw); |
| 4043 | if (ret_val) |
| 4044 | goto out; |
| 4045 | |
| 4046 | if (nvm->type != e1000_nvm_flash_sw) |
| 4047 | goto out; |
| 4048 | |
| 4049 | nvm->ops.acquire(hw); |
| 4050 | |
| 4051 | /* We're writing to the opposite bank so if we're on bank 1, |
| 4052 | * write to bank 0 etc. We also need to erase the segment that |
| 4053 | * is going to be written |
| 4054 | */ |
| 4055 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
| 4056 | if (ret_val) { |
| 4057 | e_dbg("Could not detect valid bank, assuming bank 0\n"); |
| 4058 | bank = 0; |
| 4059 | } |
| 4060 | |
| 4061 | if (bank == 0) { |
| 4062 | new_bank_offset = nvm->flash_bank_size; |
| 4063 | old_bank_offset = 0; |
| 4064 | ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); |
| 4065 | if (ret_val) |
| 4066 | goto release; |
| 4067 | } else { |
| 4068 | old_bank_offset = nvm->flash_bank_size; |
| 4069 | new_bank_offset = 0; |
| 4070 | ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); |
| 4071 | if (ret_val) |
| 4072 | goto release; |
| 4073 | } |
| 4074 | for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4075 | if (dev_spec->shadow_ram[i].modified) { |
| 4076 | data = dev_spec->shadow_ram[i].value; |
| 4077 | } else { |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 4078 | ret_val = e1000_read_flash_word_ich8lan(hw, i + |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 4079 | old_bank_offset, |
| 4080 | &data); |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 4081 | if (ret_val) |
| 4082 | break; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4083 | } |
| 4084 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4085 | /* If the word is 0x13, then make sure the signature bits |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4086 | * (15:14) are 11b until the commit has completed. |
| 4087 | * This will allow us to write 10b which indicates the |
| 4088 | * signature is valid. We want to do this after the write |
| 4089 | * has completed so that we don't mark the segment valid |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 4090 | * while the write is still in progress |
| 4091 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4092 | if (i == E1000_ICH_NVM_SIG_WORD) |
| 4093 | data |= E1000_ICH_NVM_SIG_MASK; |
| 4094 | |
| 4095 | /* Convert offset to bytes. */ |
| 4096 | act_offset = (i + new_bank_offset) << 1; |
| 4097 | |
Bruce Allan | ce43a21 | 2013-02-20 04:06:32 +0000 | [diff] [blame] | 4098 | usleep_range(100, 200); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4099 | /* Write the bytes to the new bank. */ |
| 4100 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, |
| 4101 | act_offset, |
| 4102 | (u8)data); |
| 4103 | if (ret_val) |
| 4104 | break; |
| 4105 | |
Bruce Allan | ce43a21 | 2013-02-20 04:06:32 +0000 | [diff] [blame] | 4106 | usleep_range(100, 200); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4107 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 4108 | act_offset + 1, |
| 4109 | (u8)(data >> 8)); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4110 | if (ret_val) |
| 4111 | break; |
| 4112 | } |
| 4113 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4114 | /* Don't bother writing the segment valid bits if sector |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 4115 | * programming failed. |
| 4116 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4117 | if (ret_val) { |
Bruce Allan | 4a77035 | 2008-10-01 17:18:35 -0700 | [diff] [blame] | 4118 | /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 4119 | e_dbg("Flash commit failed.\n"); |
Bruce Allan | 9c5e209 | 2010-05-10 15:00:31 +0000 | [diff] [blame] | 4120 | goto release; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4121 | } |
| 4122 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4123 | /* Finally validate the new segment by setting bit 15:14 |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4124 | * to 10b in word 0x13 , this can be done without an |
| 4125 | * erase as well since these bits are 11 to start with |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 4126 | * and we need to change bit 14 to 0b |
| 4127 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4128 | act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 4129 | ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); |
Bruce Allan | 9c5e209 | 2010-05-10 15:00:31 +0000 | [diff] [blame] | 4130 | if (ret_val) |
| 4131 | goto release; |
| 4132 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4133 | data &= 0xBFFF; |
| 4134 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, |
| 4135 | act_offset * 2 + 1, |
| 4136 | (u8)(data >> 8)); |
Bruce Allan | 9c5e209 | 2010-05-10 15:00:31 +0000 | [diff] [blame] | 4137 | if (ret_val) |
| 4138 | goto release; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4139 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4140 | /* And invalidate the previously valid segment by setting |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4141 | * its signature word (0x13) high_byte to 0b. This can be |
| 4142 | * done without an erase because flash erase sets all bits |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 4143 | * to 1's. We can write 1's to 0's without an erase |
| 4144 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4145 | act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; |
| 4146 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); |
Bruce Allan | 9c5e209 | 2010-05-10 15:00:31 +0000 | [diff] [blame] | 4147 | if (ret_val) |
| 4148 | goto release; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4149 | |
| 4150 | /* Great! Everything worked, we can now clear the cached entries. */ |
| 4151 | for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 4152 | dev_spec->shadow_ram[i].modified = false; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4153 | dev_spec->shadow_ram[i].value = 0xFFFF; |
| 4154 | } |
| 4155 | |
Bruce Allan | 9c5e209 | 2010-05-10 15:00:31 +0000 | [diff] [blame] | 4156 | release: |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 4157 | nvm->ops.release(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4158 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4159 | /* Reload the EEPROM, or else modifications will not appear |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4160 | * until after the next adapter reset. |
| 4161 | */ |
Bruce Allan | 9c5e209 | 2010-05-10 15:00:31 +0000 | [diff] [blame] | 4162 | if (!ret_val) { |
Bruce Allan | e85e363 | 2012-02-22 09:03:14 +0000 | [diff] [blame] | 4163 | nvm->ops.reload(hw); |
Arjan van de Ven | ab6973a | 2019-06-14 17:29:35 -0700 | [diff] [blame] | 4164 | usleep_range(10000, 11000); |
Bruce Allan | 9c5e209 | 2010-05-10 15:00:31 +0000 | [diff] [blame] | 4165 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4166 | |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 4167 | out: |
| 4168 | if (ret_val) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 4169 | e_dbg("NVM update error: %d\n", ret_val); |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 4170 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4171 | return ret_val; |
| 4172 | } |
| 4173 | |
| 4174 | /** |
| 4175 | * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum |
| 4176 | * @hw: pointer to the HW structure |
| 4177 | * |
| 4178 | * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. |
| 4179 | * If the bit is 0, that the EEPROM had been modified, but the checksum was not |
| 4180 | * calculated, in which case we need to calculate the checksum and set bit 6. |
| 4181 | **/ |
| 4182 | static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) |
| 4183 | { |
| 4184 | s32 ret_val; |
| 4185 | u16 data; |
Bruce Allan | 1cc7a3a | 2013-01-09 08:15:42 +0000 | [diff] [blame] | 4186 | u16 word; |
| 4187 | u16 valid_csum_mask; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4188 | |
Bruce Allan | 1cc7a3a | 2013-01-09 08:15:42 +0000 | [diff] [blame] | 4189 | /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, |
| 4190 | * the checksum needs to be fixed. This bit is an indication that |
| 4191 | * the NVM was prepared by OEM software and did not calculate |
| 4192 | * the checksum...a likely scenario. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4193 | */ |
Bruce Allan | 1cc7a3a | 2013-01-09 08:15:42 +0000 | [diff] [blame] | 4194 | switch (hw->mac.type) { |
| 4195 | case e1000_pch_lpt: |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 4196 | case e1000_pch_spt: |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 4197 | case e1000_pch_cnp: |
Sasha Neftin | fb776f5 | 2019-10-16 11:08:38 +0300 | [diff] [blame] | 4198 | case e1000_pch_tgp: |
Sasha Neftin | 59e4668 | 2020-01-19 13:57:13 +0200 | [diff] [blame] | 4199 | case e1000_pch_adp: |
Sasha Neftin | cc23f4f | 2020-08-13 11:34:06 +0300 | [diff] [blame] | 4200 | case e1000_pch_mtp: |
Sasha Neftin | 820b8ff | 2021-03-04 09:38:13 +0200 | [diff] [blame] | 4201 | case e1000_pch_lnp: |
Sasha Neftin | 0c9183c | 2022-09-29 11:08:59 +0300 | [diff] [blame] | 4202 | case e1000_pch_ptp: |
Sasha Neftin | 1fe4f45 | 2023-07-18 19:28:57 +0300 | [diff] [blame] | 4203 | case e1000_pch_nvp: |
Bruce Allan | 1cc7a3a | 2013-01-09 08:15:42 +0000 | [diff] [blame] | 4204 | word = NVM_COMPAT; |
| 4205 | valid_csum_mask = NVM_COMPAT_VALID_CSUM; |
| 4206 | break; |
| 4207 | default: |
| 4208 | word = NVM_FUTURE_INIT_WORD1; |
| 4209 | valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; |
| 4210 | break; |
| 4211 | } |
| 4212 | |
| 4213 | ret_val = e1000_read_nvm(hw, word, 1, &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4214 | if (ret_val) |
| 4215 | return ret_val; |
| 4216 | |
Bruce Allan | 1cc7a3a | 2013-01-09 08:15:42 +0000 | [diff] [blame] | 4217 | if (!(data & valid_csum_mask)) { |
Sasha Neftin | ffd24fa | 2022-02-03 14:21:49 +0200 | [diff] [blame] | 4218 | e_dbg("NVM Checksum valid bit not set\n"); |
Sasha Neftin | 4051f68 | 2021-07-18 07:10:31 +0300 | [diff] [blame] | 4219 | |
Sasha Neftin | ffd24fa | 2022-02-03 14:21:49 +0200 | [diff] [blame] | 4220 | if (hw->mac.type < e1000_pch_tgp) { |
Sasha Neftin | 4051f68 | 2021-07-18 07:10:31 +0300 | [diff] [blame] | 4221 | data |= valid_csum_mask; |
| 4222 | ret_val = e1000_write_nvm(hw, word, 1, &data); |
| 4223 | if (ret_val) |
| 4224 | return ret_val; |
| 4225 | ret_val = e1000e_update_nvm_checksum(hw); |
| 4226 | if (ret_val) |
| 4227 | return ret_val; |
| 4228 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4229 | } |
| 4230 | |
| 4231 | return e1000e_validate_nvm_checksum_generic(hw); |
| 4232 | } |
| 4233 | |
| 4234 | /** |
Bruce Allan | 4a77035 | 2008-10-01 17:18:35 -0700 | [diff] [blame] | 4235 | * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only |
| 4236 | * @hw: pointer to the HW structure |
| 4237 | * |
| 4238 | * To prevent malicious write/erase of the NVM, set it to be read-only |
| 4239 | * so that the hardware ignores all write/erase cycles of the NVM via |
| 4240 | * the flash control registers. The shadow-ram copy of the NVM will |
| 4241 | * still be updated, however any updates to this copy will not stick |
| 4242 | * across driver reloads. |
| 4243 | **/ |
| 4244 | void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) |
| 4245 | { |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 4246 | struct e1000_nvm_info *nvm = &hw->nvm; |
Bruce Allan | 4a77035 | 2008-10-01 17:18:35 -0700 | [diff] [blame] | 4247 | union ich8_flash_protected_range pr0; |
| 4248 | union ich8_hws_flash_status hsfsts; |
| 4249 | u32 gfpreg; |
Bruce Allan | 4a77035 | 2008-10-01 17:18:35 -0700 | [diff] [blame] | 4250 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 4251 | nvm->ops.acquire(hw); |
Bruce Allan | 4a77035 | 2008-10-01 17:18:35 -0700 | [diff] [blame] | 4252 | |
| 4253 | gfpreg = er32flash(ICH_FLASH_GFPREG); |
| 4254 | |
| 4255 | /* Write-protect GbE Sector of NVM */ |
| 4256 | pr0.regval = er32flash(ICH_FLASH_PR0); |
| 4257 | pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; |
| 4258 | pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); |
| 4259 | pr0.range.wpe = true; |
| 4260 | ew32flash(ICH_FLASH_PR0, pr0.regval); |
| 4261 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4262 | /* Lock down a subset of GbE Flash Control Registers, e.g. |
Bruce Allan | 4a77035 | 2008-10-01 17:18:35 -0700 | [diff] [blame] | 4263 | * PR0 to prevent the write-protection from being lifted. |
| 4264 | * Once FLOCKDN is set, the registers protected by it cannot |
| 4265 | * be written until FLOCKDN is cleared by a hardware reset. |
| 4266 | */ |
| 4267 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
| 4268 | hsfsts.hsf_status.flockdn = true; |
| 4269 | ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); |
| 4270 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 4271 | nvm->ops.release(hw); |
Bruce Allan | 4a77035 | 2008-10-01 17:18:35 -0700 | [diff] [blame] | 4272 | } |
| 4273 | |
| 4274 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4275 | * e1000_write_flash_data_ich8lan - Writes bytes to the NVM |
| 4276 | * @hw: pointer to the HW structure |
| 4277 | * @offset: The offset (in bytes) of the byte/word to read. |
| 4278 | * @size: Size of data to read, 1=byte 2=word |
| 4279 | * @data: The byte(s) to write to the NVM. |
| 4280 | * |
| 4281 | * Writes one/two bytes to the NVM using the flash access registers. |
| 4282 | **/ |
| 4283 | static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, |
| 4284 | u8 size, u16 data) |
| 4285 | { |
| 4286 | union ich8_hws_flash_status hsfsts; |
| 4287 | union ich8_hws_flash_ctrl hsflctl; |
| 4288 | u32 flash_linear_addr; |
| 4289 | u32 flash_data = 0; |
| 4290 | s32 ret_val; |
| 4291 | u8 count = 0; |
| 4292 | |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 4293 | if (hw->mac.type >= e1000_pch_spt) { |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 4294 | if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK) |
| 4295 | return -E1000_ERR_NVM; |
| 4296 | } else { |
| 4297 | if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) |
| 4298 | return -E1000_ERR_NVM; |
| 4299 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4300 | |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 4301 | flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + |
| 4302 | hw->nvm.flash_base_addr); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4303 | |
| 4304 | do { |
| 4305 | udelay(1); |
| 4306 | /* Steps */ |
| 4307 | ret_val = e1000_flash_cycle_init_ich8lan(hw); |
| 4308 | if (ret_val) |
| 4309 | break; |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 4310 | /* In SPT, This register is in Lan memory space, not |
| 4311 | * flash. Therefore, only 32 bit access is supported |
| 4312 | */ |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 4313 | if (hw->mac.type >= e1000_pch_spt) |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 4314 | hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; |
| 4315 | else |
| 4316 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4317 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4318 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ |
Bruce Allan | 362e20c | 2013-02-20 04:05:45 +0000 | [diff] [blame] | 4319 | hsflctl.hsf_ctrl.fldbcount = size - 1; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4320 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 4321 | /* In SPT, This register is in Lan memory space, |
| 4322 | * not flash. Therefore, only 32 bit access is |
| 4323 | * supported |
| 4324 | */ |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 4325 | if (hw->mac.type >= e1000_pch_spt) |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 4326 | ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); |
| 4327 | else |
| 4328 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4329 | |
| 4330 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); |
| 4331 | |
| 4332 | if (size == 1) |
| 4333 | flash_data = (u32)data & 0x00FF; |
| 4334 | else |
| 4335 | flash_data = (u32)data; |
| 4336 | |
| 4337 | ew32flash(ICH_FLASH_FDATA0, flash_data); |
| 4338 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4339 | /* check if FCERR is set to 1 , if set to 1, clear it |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 4340 | * and try the whole sequence a few more times else done |
| 4341 | */ |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 4342 | ret_val = |
| 4343 | e1000_flash_cycle_ich8lan(hw, |
| 4344 | ICH_FLASH_WRITE_COMMAND_TIMEOUT); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4345 | if (!ret_val) |
| 4346 | break; |
| 4347 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4348 | /* If we're here, then things are most likely |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4349 | * completely hosed, but if the error condition |
| 4350 | * is detected, it won't hurt to give it another |
| 4351 | * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. |
| 4352 | */ |
| 4353 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 4354 | if (hsfsts.hsf_status.flcerr) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4355 | /* Repeat for some time before giving up. */ |
| 4356 | continue; |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 4357 | if (!hsfsts.hsf_status.flcdone) { |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 4358 | e_dbg("Timeout error - flash cycle did not complete.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4359 | break; |
| 4360 | } |
| 4361 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); |
| 4362 | |
| 4363 | return ret_val; |
| 4364 | } |
| 4365 | |
| 4366 | /** |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 4367 | * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM |
| 4368 | * @hw: pointer to the HW structure |
| 4369 | * @offset: The offset (in bytes) of the dwords to read. |
| 4370 | * @data: The 4 bytes to write to the NVM. |
| 4371 | * |
| 4372 | * Writes one/two/four bytes to the NVM using the flash access registers. |
| 4373 | **/ |
| 4374 | static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, |
| 4375 | u32 data) |
| 4376 | { |
| 4377 | union ich8_hws_flash_status hsfsts; |
| 4378 | union ich8_hws_flash_ctrl hsflctl; |
| 4379 | u32 flash_linear_addr; |
| 4380 | s32 ret_val; |
| 4381 | u8 count = 0; |
| 4382 | |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 4383 | if (hw->mac.type >= e1000_pch_spt) { |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 4384 | if (offset > ICH_FLASH_LINEAR_ADDR_MASK) |
| 4385 | return -E1000_ERR_NVM; |
| 4386 | } |
| 4387 | flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + |
| 4388 | hw->nvm.flash_base_addr); |
| 4389 | do { |
| 4390 | udelay(1); |
| 4391 | /* Steps */ |
| 4392 | ret_val = e1000_flash_cycle_init_ich8lan(hw); |
| 4393 | if (ret_val) |
| 4394 | break; |
| 4395 | |
| 4396 | /* In SPT, This register is in Lan memory space, not |
| 4397 | * flash. Therefore, only 32 bit access is supported |
| 4398 | */ |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 4399 | if (hw->mac.type >= e1000_pch_spt) |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 4400 | hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) |
| 4401 | >> 16; |
| 4402 | else |
| 4403 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); |
| 4404 | |
| 4405 | hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; |
| 4406 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; |
| 4407 | |
| 4408 | /* In SPT, This register is in Lan memory space, |
| 4409 | * not flash. Therefore, only 32 bit access is |
| 4410 | * supported |
| 4411 | */ |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 4412 | if (hw->mac.type >= e1000_pch_spt) |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 4413 | ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); |
| 4414 | else |
| 4415 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); |
| 4416 | |
| 4417 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); |
| 4418 | |
| 4419 | ew32flash(ICH_FLASH_FDATA0, data); |
| 4420 | |
| 4421 | /* check if FCERR is set to 1 , if set to 1, clear it |
| 4422 | * and try the whole sequence a few more times else done |
| 4423 | */ |
| 4424 | ret_val = |
| 4425 | e1000_flash_cycle_ich8lan(hw, |
| 4426 | ICH_FLASH_WRITE_COMMAND_TIMEOUT); |
| 4427 | |
| 4428 | if (!ret_val) |
| 4429 | break; |
| 4430 | |
| 4431 | /* If we're here, then things are most likely |
| 4432 | * completely hosed, but if the error condition |
| 4433 | * is detected, it won't hurt to give it another |
| 4434 | * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. |
| 4435 | */ |
| 4436 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
| 4437 | |
| 4438 | if (hsfsts.hsf_status.flcerr) |
| 4439 | /* Repeat for some time before giving up. */ |
| 4440 | continue; |
| 4441 | if (!hsfsts.hsf_status.flcdone) { |
| 4442 | e_dbg("Timeout error - flash cycle did not complete.\n"); |
| 4443 | break; |
| 4444 | } |
| 4445 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); |
| 4446 | |
| 4447 | return ret_val; |
| 4448 | } |
| 4449 | |
| 4450 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4451 | * e1000_write_flash_byte_ich8lan - Write a single byte to NVM |
| 4452 | * @hw: pointer to the HW structure |
| 4453 | * @offset: The index of the byte to read. |
| 4454 | * @data: The byte to write to the NVM. |
| 4455 | * |
| 4456 | * Writes a single byte to the NVM using the flash access registers. |
| 4457 | **/ |
| 4458 | static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, |
| 4459 | u8 data) |
| 4460 | { |
| 4461 | u16 word = (u16)data; |
| 4462 | |
| 4463 | return e1000_write_flash_data_ich8lan(hw, offset, 1, word); |
| 4464 | } |
| 4465 | |
| 4466 | /** |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 4467 | * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM |
| 4468 | * @hw: pointer to the HW structure |
| 4469 | * @offset: The offset of the word to write. |
| 4470 | * @dword: The dword to write to the NVM. |
| 4471 | * |
| 4472 | * Writes a single dword to the NVM using the flash access registers. |
| 4473 | * Goes through a retry algorithm before giving up. |
| 4474 | **/ |
| 4475 | static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, |
| 4476 | u32 offset, u32 dword) |
| 4477 | { |
| 4478 | s32 ret_val; |
| 4479 | u16 program_retries; |
| 4480 | |
| 4481 | /* Must convert word offset into bytes. */ |
| 4482 | offset <<= 1; |
| 4483 | ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); |
| 4484 | |
| 4485 | if (!ret_val) |
| 4486 | return ret_val; |
| 4487 | for (program_retries = 0; program_retries < 100; program_retries++) { |
| 4488 | e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset); |
| 4489 | usleep_range(100, 200); |
| 4490 | ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); |
| 4491 | if (!ret_val) |
| 4492 | break; |
| 4493 | } |
| 4494 | if (program_retries == 100) |
| 4495 | return -E1000_ERR_NVM; |
| 4496 | |
| 4497 | return 0; |
| 4498 | } |
| 4499 | |
| 4500 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4501 | * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM |
| 4502 | * @hw: pointer to the HW structure |
| 4503 | * @offset: The offset of the byte to write. |
| 4504 | * @byte: The byte to write to the NVM. |
| 4505 | * |
| 4506 | * Writes a single byte to the NVM using the flash access registers. |
| 4507 | * Goes through a retry algorithm before giving up. |
| 4508 | **/ |
| 4509 | static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, |
| 4510 | u32 offset, u8 byte) |
| 4511 | { |
| 4512 | s32 ret_val; |
| 4513 | u16 program_retries; |
| 4514 | |
| 4515 | ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); |
| 4516 | if (!ret_val) |
| 4517 | return ret_val; |
| 4518 | |
| 4519 | for (program_retries = 0; program_retries < 100; program_retries++) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 4520 | e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); |
Bruce Allan | ce43a21 | 2013-02-20 04:06:32 +0000 | [diff] [blame] | 4521 | usleep_range(100, 200); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4522 | ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); |
| 4523 | if (!ret_val) |
| 4524 | break; |
| 4525 | } |
| 4526 | if (program_retries == 100) |
| 4527 | return -E1000_ERR_NVM; |
| 4528 | |
| 4529 | return 0; |
| 4530 | } |
| 4531 | |
| 4532 | /** |
| 4533 | * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM |
| 4534 | * @hw: pointer to the HW structure |
| 4535 | * @bank: 0 for first bank, 1 for second bank, etc. |
| 4536 | * |
| 4537 | * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. |
| 4538 | * bank N is 4096 * N + flash_reg_addr. |
| 4539 | **/ |
| 4540 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) |
| 4541 | { |
| 4542 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 4543 | union ich8_hws_flash_status hsfsts; |
| 4544 | union ich8_hws_flash_ctrl hsflctl; |
| 4545 | u32 flash_linear_addr; |
| 4546 | /* bank size is in 16bit words - adjust to bytes */ |
| 4547 | u32 flash_bank_size = nvm->flash_bank_size * 2; |
| 4548 | s32 ret_val; |
| 4549 | s32 count = 0; |
Bruce Allan | a708dd8 | 2009-11-20 23:28:37 +0000 | [diff] [blame] | 4550 | s32 j, iteration, sector_size; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4551 | |
| 4552 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
| 4553 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4554 | /* Determine HW Sector size: Read BERASE bits of hw flash status |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 4555 | * register |
| 4556 | * 00: The Hw sector is 256 bytes, hence we need to erase 16 |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4557 | * consecutive sectors. The start index for the nth Hw sector |
| 4558 | * can be calculated as = bank * 4096 + n * 256 |
| 4559 | * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. |
| 4560 | * The start index for the nth Hw sector can be calculated |
| 4561 | * as = bank * 4096 |
| 4562 | * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 |
| 4563 | * (ich9 only, otherwise error condition) |
| 4564 | * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 |
| 4565 | */ |
| 4566 | switch (hsfsts.hsf_status.berasesz) { |
| 4567 | case 0: |
| 4568 | /* Hw sector size 256 */ |
| 4569 | sector_size = ICH_FLASH_SEG_SIZE_256; |
| 4570 | iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; |
| 4571 | break; |
| 4572 | case 1: |
| 4573 | sector_size = ICH_FLASH_SEG_SIZE_4K; |
Bruce Allan | 28c9195 | 2009-07-01 13:28:32 +0000 | [diff] [blame] | 4574 | iteration = 1; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4575 | break; |
| 4576 | case 2: |
Bruce Allan | 148675a | 2009-08-07 07:41:56 +0000 | [diff] [blame] | 4577 | sector_size = ICH_FLASH_SEG_SIZE_8K; |
| 4578 | iteration = 1; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4579 | break; |
| 4580 | case 3: |
| 4581 | sector_size = ICH_FLASH_SEG_SIZE_64K; |
Bruce Allan | 28c9195 | 2009-07-01 13:28:32 +0000 | [diff] [blame] | 4582 | iteration = 1; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4583 | break; |
| 4584 | default: |
| 4585 | return -E1000_ERR_NVM; |
| 4586 | } |
| 4587 | |
| 4588 | /* Start with the base address, then add the sector offset. */ |
| 4589 | flash_linear_addr = hw->nvm.flash_base_addr; |
Bruce Allan | 148675a | 2009-08-07 07:41:56 +0000 | [diff] [blame] | 4590 | flash_linear_addr += (bank) ? flash_bank_size : 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4591 | |
Bruce Allan | 53aa82d | 2013-02-20 04:06:06 +0000 | [diff] [blame] | 4592 | for (j = 0; j < iteration; j++) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4593 | do { |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 4594 | u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; |
| 4595 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4596 | /* Steps */ |
| 4597 | ret_val = e1000_flash_cycle_init_ich8lan(hw); |
| 4598 | if (ret_val) |
| 4599 | return ret_val; |
| 4600 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4601 | /* Write a value 11 (block Erase) in Flash |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 4602 | * Cycle field in hw flash control |
| 4603 | */ |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 4604 | if (hw->mac.type >= e1000_pch_spt) |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 4605 | hsflctl.regval = |
| 4606 | er32flash(ICH_FLASH_HSFSTS) >> 16; |
| 4607 | else |
| 4608 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); |
| 4609 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4610 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 4611 | if (hw->mac.type >= e1000_pch_spt) |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 4612 | ew32flash(ICH_FLASH_HSFSTS, |
| 4613 | hsflctl.regval << 16); |
| 4614 | else |
| 4615 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4616 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4617 | /* Write the last 24 bits of an index within the |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4618 | * block into Flash Linear address field in Flash |
| 4619 | * Address. |
| 4620 | */ |
| 4621 | flash_linear_addr += (j * sector_size); |
| 4622 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); |
| 4623 | |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 4624 | ret_val = e1000_flash_cycle_ich8lan(hw, timeout); |
Bruce Allan | 9e2d765 | 2012-01-31 06:37:27 +0000 | [diff] [blame] | 4625 | if (!ret_val) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4626 | break; |
| 4627 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4628 | /* Check if FCERR is set to 1. If 1, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4629 | * clear it and try the whole sequence |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 4630 | * a few more times else Done |
| 4631 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4632 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 4633 | if (hsfsts.hsf_status.flcerr) |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 4634 | /* repeat for some time before giving up */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4635 | continue; |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 4636 | else if (!hsfsts.hsf_status.flcdone) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4637 | return ret_val; |
| 4638 | } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); |
| 4639 | } |
| 4640 | |
| 4641 | return 0; |
| 4642 | } |
| 4643 | |
| 4644 | /** |
| 4645 | * e1000_valid_led_default_ich8lan - Set the default LED settings |
| 4646 | * @hw: pointer to the HW structure |
| 4647 | * @data: Pointer to the LED settings |
| 4648 | * |
| 4649 | * Reads the LED default settings from the NVM to data. If the NVM LED |
| 4650 | * settings is all 0's or F's, set the LED default to a valid LED default |
| 4651 | * setting. |
| 4652 | **/ |
| 4653 | static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) |
| 4654 | { |
| 4655 | s32 ret_val; |
| 4656 | |
| 4657 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); |
| 4658 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 4659 | e_dbg("NVM Read Error\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4660 | return ret_val; |
| 4661 | } |
| 4662 | |
Bruce Allan | e5fe254 | 2013-02-20 04:06:27 +0000 | [diff] [blame] | 4663 | if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4664 | *data = ID_LED_DEFAULT_ICH8LAN; |
| 4665 | |
| 4666 | return 0; |
| 4667 | } |
| 4668 | |
| 4669 | /** |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 4670 | * e1000_id_led_init_pchlan - store LED configurations |
| 4671 | * @hw: pointer to the HW structure |
| 4672 | * |
| 4673 | * PCH does not control LEDs via the LEDCTL register, rather it uses |
| 4674 | * the PHY LED configuration register. |
| 4675 | * |
| 4676 | * PCH also does not have an "always on" or "always off" mode which |
| 4677 | * complicates the ID feature. Instead of using the "on" mode to indicate |
Bruce Allan | d1964eb | 2012-02-22 09:02:21 +0000 | [diff] [blame] | 4678 | * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 4679 | * use "link_up" mode. The LEDs will still ID on request if there is no |
| 4680 | * link based on logic in e1000_led_[on|off]_pchlan(). |
| 4681 | **/ |
| 4682 | static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) |
| 4683 | { |
| 4684 | struct e1000_mac_info *mac = &hw->mac; |
| 4685 | s32 ret_val; |
| 4686 | const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; |
| 4687 | const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; |
| 4688 | u16 data, i, temp, shift; |
| 4689 | |
| 4690 | /* Get default ID LED modes */ |
| 4691 | ret_val = hw->nvm.ops.valid_led_default(hw, &data); |
| 4692 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 4693 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 4694 | |
| 4695 | mac->ledctl_default = er32(LEDCTL); |
| 4696 | mac->ledctl_mode1 = mac->ledctl_default; |
| 4697 | mac->ledctl_mode2 = mac->ledctl_default; |
| 4698 | |
| 4699 | for (i = 0; i < 4; i++) { |
| 4700 | temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; |
| 4701 | shift = (i * 5); |
| 4702 | switch (temp) { |
| 4703 | case ID_LED_ON1_DEF2: |
| 4704 | case ID_LED_ON1_ON2: |
| 4705 | case ID_LED_ON1_OFF2: |
| 4706 | mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); |
| 4707 | mac->ledctl_mode1 |= (ledctl_on << shift); |
| 4708 | break; |
| 4709 | case ID_LED_OFF1_DEF2: |
| 4710 | case ID_LED_OFF1_ON2: |
| 4711 | case ID_LED_OFF1_OFF2: |
| 4712 | mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); |
| 4713 | mac->ledctl_mode1 |= (ledctl_off << shift); |
| 4714 | break; |
| 4715 | default: |
| 4716 | /* Do nothing */ |
| 4717 | break; |
| 4718 | } |
| 4719 | switch (temp) { |
| 4720 | case ID_LED_DEF1_ON2: |
| 4721 | case ID_LED_ON1_ON2: |
| 4722 | case ID_LED_OFF1_ON2: |
| 4723 | mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); |
| 4724 | mac->ledctl_mode2 |= (ledctl_on << shift); |
| 4725 | break; |
| 4726 | case ID_LED_DEF1_OFF2: |
| 4727 | case ID_LED_ON1_OFF2: |
| 4728 | case ID_LED_OFF1_OFF2: |
| 4729 | mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); |
| 4730 | mac->ledctl_mode2 |= (ledctl_off << shift); |
| 4731 | break; |
| 4732 | default: |
| 4733 | /* Do nothing */ |
| 4734 | break; |
| 4735 | } |
| 4736 | } |
| 4737 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 4738 | return 0; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 4739 | } |
| 4740 | |
| 4741 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4742 | * e1000_get_bus_info_ich8lan - Get/Set the bus type and width |
| 4743 | * @hw: pointer to the HW structure |
| 4744 | * |
| 4745 | * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability |
Hao Chen | 59398af | 2021-05-19 14:14:43 +0800 | [diff] [blame] | 4746 | * register, so the bus width is hard coded. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4747 | **/ |
| 4748 | static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) |
| 4749 | { |
| 4750 | struct e1000_bus_info *bus = &hw->bus; |
| 4751 | s32 ret_val; |
| 4752 | |
| 4753 | ret_val = e1000e_get_bus_info_pcie(hw); |
| 4754 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4755 | /* ICH devices are "PCI Express"-ish. They have |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4756 | * a configuration space, but do not contain |
| 4757 | * PCI Express Capability registers, so bus width |
| 4758 | * must be hardcoded. |
| 4759 | */ |
| 4760 | if (bus->width == e1000_bus_width_unknown) |
| 4761 | bus->width = e1000_bus_width_pcie_x1; |
| 4762 | |
| 4763 | return ret_val; |
| 4764 | } |
| 4765 | |
| 4766 | /** |
| 4767 | * e1000_reset_hw_ich8lan - Reset the hardware |
| 4768 | * @hw: pointer to the HW structure |
| 4769 | * |
| 4770 | * Does a full reset of the hardware which includes a reset of the PHY and |
| 4771 | * MAC. |
| 4772 | **/ |
| 4773 | static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) |
| 4774 | { |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 4775 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
Bruce Allan | 62bc813 | 2012-03-20 03:47:57 +0000 | [diff] [blame] | 4776 | u16 kum_cfg; |
| 4777 | u32 ctrl, reg; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4778 | s32 ret_val; |
| 4779 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4780 | /* Prevent the PCI-E bus from sticking if there is no TLP connection |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4781 | * on the last TLP read/write transaction when MAC is reset. |
| 4782 | */ |
| 4783 | ret_val = e1000e_disable_pcie_master(hw); |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 4784 | if (ret_val) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 4785 | e_dbg("PCI-E Master disable polling has failed.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4786 | |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 4787 | e_dbg("Masking off all interrupts\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4788 | ew32(IMC, 0xffffffff); |
| 4789 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4790 | /* Disable the Transmit and Receive units. Then delay to allow |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4791 | * any pending transactions to complete before we hit the MAC |
| 4792 | * with the global reset. |
| 4793 | */ |
| 4794 | ew32(RCTL, 0); |
| 4795 | ew32(TCTL, E1000_TCTL_PSP); |
| 4796 | e1e_flush(); |
| 4797 | |
Arjan van de Ven | ab6973a | 2019-06-14 17:29:35 -0700 | [diff] [blame] | 4798 | usleep_range(10000, 11000); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4799 | |
| 4800 | /* Workaround for ICH8 bit corruption issue in FIFO memory */ |
| 4801 | if (hw->mac.type == e1000_ich8lan) { |
| 4802 | /* Set Tx and Rx buffer allocation to 8k apiece. */ |
| 4803 | ew32(PBA, E1000_PBA_8K); |
| 4804 | /* Set Packet Buffer Size to 16k. */ |
| 4805 | ew32(PBS, E1000_PBS_16K); |
| 4806 | } |
| 4807 | |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 4808 | if (hw->mac.type == e1000_pchlan) { |
Bruce Allan | 62bc813 | 2012-03-20 03:47:57 +0000 | [diff] [blame] | 4809 | /* Save the NVM K1 bit setting */ |
| 4810 | ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 4811 | if (ret_val) |
| 4812 | return ret_val; |
| 4813 | |
Bruce Allan | 62bc813 | 2012-03-20 03:47:57 +0000 | [diff] [blame] | 4814 | if (kum_cfg & E1000_NVM_K1_ENABLE) |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 4815 | dev_spec->nvm_k1_enabled = true; |
| 4816 | else |
| 4817 | dev_spec->nvm_k1_enabled = false; |
| 4818 | } |
| 4819 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4820 | ctrl = er32(CTRL); |
| 4821 | |
Bruce Allan | 44abd5c | 2012-02-22 09:02:37 +0000 | [diff] [blame] | 4822 | if (!hw->phy.ops.check_reset_block(hw)) { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4823 | /* Full-chip reset requires MAC and PHY reset at the same |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4824 | * time to make sure the interface between MAC and the |
| 4825 | * external PHY is reset. |
| 4826 | */ |
| 4827 | ctrl |= E1000_CTRL_PHY_RST; |
Bruce Allan | 605c82b | 2010-09-22 17:17:01 +0000 | [diff] [blame] | 4828 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4829 | /* Gate automatic PHY configuration by hardware on |
Bruce Allan | 605c82b | 2010-09-22 17:17:01 +0000 | [diff] [blame] | 4830 | * non-managed 82579 |
| 4831 | */ |
| 4832 | if ((hw->mac.type == e1000_pch2lan) && |
| 4833 | !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) |
| 4834 | e1000_gate_hw_phy_config_ich8lan(hw, true); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4835 | } |
| 4836 | ret_val = e1000_acquire_swflag_ich8lan(hw); |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 4837 | e_dbg("Issuing a global reset to ich8lan\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4838 | ew32(CTRL, (ctrl | E1000_CTRL_RST)); |
Jesse Brandeburg | 945a515 | 2011-07-20 00:56:21 +0000 | [diff] [blame] | 4839 | /* cannot issue a flush here because it hangs the hardware */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4840 | msleep(20); |
| 4841 | |
Bruce Allan | 62bc813 | 2012-03-20 03:47:57 +0000 | [diff] [blame] | 4842 | /* Set Phy Config Counter to 50msec */ |
| 4843 | if (hw->mac.type == e1000_pch2lan) { |
| 4844 | reg = er32(FEXTNVM3); |
| 4845 | reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; |
| 4846 | reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; |
| 4847 | ew32(FEXTNVM3, reg); |
| 4848 | } |
| 4849 | |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 4850 | if (!ret_val) |
Bruce Allan | a90b412 | 2011-10-07 03:50:38 +0000 | [diff] [blame] | 4851 | clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); |
Jesse Brandeburg | 37f4023 | 2008-10-02 16:33:20 -0700 | [diff] [blame] | 4852 | |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 4853 | if (ctrl & E1000_CTRL_PHY_RST) { |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 4854 | ret_val = hw->phy.ops.get_cfg_done(hw); |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 4855 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 4856 | return ret_val; |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 4857 | |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 4858 | ret_val = e1000_post_phy_reset_ich8lan(hw); |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 4859 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 4860 | return ret_val; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 4861 | } |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 4862 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4863 | /* For PCH, this write will make sure that any noise |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 4864 | * will be detected as a CRC error and be dropped rather than show up |
| 4865 | * as a bad packet to the DMA engine. |
| 4866 | */ |
| 4867 | if (hw->mac.type == e1000_pchlan) |
| 4868 | ew32(CRC_OFFSET, 0x65656565); |
| 4869 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4870 | ew32(IMC, 0xffffffff); |
Bruce Allan | dd93f95 | 2011-01-06 14:29:48 +0000 | [diff] [blame] | 4871 | er32(ICR); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4872 | |
Bruce Allan | 62bc813 | 2012-03-20 03:47:57 +0000 | [diff] [blame] | 4873 | reg = er32(KABGTXD); |
| 4874 | reg |= E1000_KABGTXD_BGSQLBIAS; |
| 4875 | ew32(KABGTXD, reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4876 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 4877 | return 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4878 | } |
| 4879 | |
| 4880 | /** |
| 4881 | * e1000_init_hw_ich8lan - Initialize the hardware |
| 4882 | * @hw: pointer to the HW structure |
| 4883 | * |
| 4884 | * Prepares the hardware for transmit and receive by doing the following: |
| 4885 | * - initialize hardware bits |
| 4886 | * - initialize LED identification |
| 4887 | * - setup receive address registers |
| 4888 | * - setup flow control |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 4889 | * - setup transmit descriptors |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4890 | * - clear statistics |
| 4891 | **/ |
| 4892 | static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) |
| 4893 | { |
| 4894 | struct e1000_mac_info *mac = &hw->mac; |
Sasha Neftin | 639e298 | 2021-09-22 09:55:42 +0300 | [diff] [blame] | 4895 | u32 ctrl_ext, txdctl, snoop, fflt_dbg; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4896 | s32 ret_val; |
| 4897 | u16 i; |
| 4898 | |
| 4899 | e1000_initialize_hw_bits_ich8lan(hw); |
| 4900 | |
| 4901 | /* Initialize identification LED */ |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 4902 | ret_val = mac->ops.id_led_init(hw); |
Bruce Allan | 33550ce | 2013-02-20 04:06:16 +0000 | [diff] [blame] | 4903 | /* An error is not fatal and we should not stop init due to this */ |
Bruce Allan | de39b75 | 2009-11-20 23:27:59 +0000 | [diff] [blame] | 4904 | if (ret_val) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 4905 | e_dbg("Error initializing identification LED\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4906 | |
| 4907 | /* Setup the receive address. */ |
| 4908 | e1000e_init_rx_addrs(hw, mac->rar_entry_count); |
| 4909 | |
| 4910 | /* Zero out the Multicast HASH table */ |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 4911 | e_dbg("Zeroing the MTA\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4912 | for (i = 0; i < mac->mta_reg_count; i++) |
| 4913 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); |
| 4914 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4915 | /* The 82578 Rx buffer will stall if wakeup is enabled in host and |
Bruce Allan | 3ebfc7c | 2011-05-13 07:20:14 +0000 | [diff] [blame] | 4916 | * the ME. Disable wakeup by clearing the host wakeup bit. |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 4917 | * Reset the phy after disabling host wakeup to reset the Rx buffer. |
| 4918 | */ |
| 4919 | if (hw->phy.type == e1000_phy_82578) { |
Bruce Allan | 3ebfc7c | 2011-05-13 07:20:14 +0000 | [diff] [blame] | 4920 | e1e_rphy(hw, BM_PORT_GEN_CFG, &i); |
| 4921 | i &= ~BM_WUC_HOST_WU_BIT; |
| 4922 | e1e_wphy(hw, BM_PORT_GEN_CFG, i); |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 4923 | ret_val = e1000_phy_hw_reset_ich8lan(hw); |
| 4924 | if (ret_val) |
| 4925 | return ret_val; |
| 4926 | } |
| 4927 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4928 | /* Setup link and flow control */ |
Bruce Allan | 1a46b40 | 2012-02-22 09:02:26 +0000 | [diff] [blame] | 4929 | ret_val = mac->ops.setup_link(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4930 | |
| 4931 | /* Set the transmit descriptor write-back policy for both queues */ |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 4932 | txdctl = er32(TXDCTL(0)); |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 4933 | txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | |
| 4934 | E1000_TXDCTL_FULL_TX_DESC_WB); |
| 4935 | txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | |
| 4936 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH); |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 4937 | ew32(TXDCTL(0), txdctl); |
| 4938 | txdctl = er32(TXDCTL(1)); |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 4939 | txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | |
| 4940 | E1000_TXDCTL_FULL_TX_DESC_WB); |
| 4941 | txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | |
| 4942 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH); |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 4943 | ew32(TXDCTL(1), txdctl); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4944 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4945 | /* ICH8 has opposite polarity of no_snoop bits. |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 4946 | * By default, we should use snoop behavior. |
| 4947 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4948 | if (mac->type == e1000_ich8lan) |
| 4949 | snoop = PCIE_ICH8_SNOOP_ALL; |
| 4950 | else |
Bruce Allan | 53aa82d | 2013-02-20 04:06:06 +0000 | [diff] [blame] | 4951 | snoop = (u32)~(PCIE_NO_SNOOP_ALL); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4952 | e1000e_set_pcie_no_snoop(hw, snoop); |
| 4953 | |
Sasha Neftin | 639e298 | 2021-09-22 09:55:42 +0300 | [diff] [blame] | 4954 | /* Enable workaround for packet loss issue on TGP PCH |
| 4955 | * Do not gate DMA clock from the modPHY block |
| 4956 | */ |
| 4957 | if (mac->type >= e1000_pch_tgp) { |
| 4958 | fflt_dbg = er32(FFLT_DBG); |
| 4959 | fflt_dbg |= E1000_FFLT_DBG_DONT_GATE_WAKE_DMA_CLK; |
| 4960 | ew32(FFLT_DBG, fflt_dbg); |
| 4961 | } |
| 4962 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4963 | ctrl_ext = er32(CTRL_EXT); |
| 4964 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; |
| 4965 | ew32(CTRL_EXT, ctrl_ext); |
| 4966 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 4967 | /* Clear all of the statistics registers (clear on read). It is |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4968 | * important that we do this after we have tried to establish link |
| 4969 | * because the symbol error count will increment wildly if there |
| 4970 | * is no link. |
| 4971 | */ |
| 4972 | e1000_clear_hw_cntrs_ich8lan(hw); |
| 4973 | |
Bruce Allan | e561a70 | 2012-02-08 02:55:46 +0000 | [diff] [blame] | 4974 | return ret_val; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4975 | } |
Bruce Allan | fc830b7 | 2013-02-20 04:06:11 +0000 | [diff] [blame] | 4976 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4977 | /** |
| 4978 | * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits |
| 4979 | * @hw: pointer to the HW structure |
| 4980 | * |
| 4981 | * Sets/Clears required hardware bits necessary for correctly setting up the |
| 4982 | * hardware for transmit and receive. |
| 4983 | **/ |
| 4984 | static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) |
| 4985 | { |
| 4986 | u32 reg; |
| 4987 | |
| 4988 | /* Extended Device Control */ |
| 4989 | reg = er32(CTRL_EXT); |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 4990 | reg |= BIT(22); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 4991 | /* Enable PHY low-power state when MAC is at D3 w/o WoL */ |
| 4992 | if (hw->mac.type >= e1000_pchlan) |
| 4993 | reg |= E1000_CTRL_EXT_PHYPDEN; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4994 | ew32(CTRL_EXT, reg); |
| 4995 | |
| 4996 | /* Transmit Descriptor Control 0 */ |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 4997 | reg = er32(TXDCTL(0)); |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 4998 | reg |= BIT(22); |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 4999 | ew32(TXDCTL(0), reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5000 | |
| 5001 | /* Transmit Descriptor Control 1 */ |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 5002 | reg = er32(TXDCTL(1)); |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 5003 | reg |= BIT(22); |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 5004 | ew32(TXDCTL(1), reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5005 | |
| 5006 | /* Transmit Arbitration Control 0 */ |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 5007 | reg = er32(TARC(0)); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5008 | if (hw->mac.type == e1000_ich8lan) |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 5009 | reg |= BIT(28) | BIT(29); |
| 5010 | reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27); |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 5011 | ew32(TARC(0), reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5012 | |
| 5013 | /* Transmit Arbitration Control 1 */ |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 5014 | reg = er32(TARC(1)); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5015 | if (er32(TCTL) & E1000_TCTL_MULR) |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 5016 | reg &= ~BIT(28); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5017 | else |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 5018 | reg |= BIT(28); |
| 5019 | reg |= BIT(24) | BIT(26) | BIT(30); |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 5020 | ew32(TARC(1), reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5021 | |
| 5022 | /* Device Status */ |
| 5023 | if (hw->mac.type == e1000_ich8lan) { |
| 5024 | reg = er32(STATUS); |
Jacob Keller | 18dd239 | 2016-04-13 16:08:32 -0700 | [diff] [blame] | 5025 | reg &= ~BIT(31); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5026 | ew32(STATUS, reg); |
| 5027 | } |
Jesse Brandeburg | a80483d | 2010-03-05 02:21:44 +0000 | [diff] [blame] | 5028 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 5029 | /* work-around descriptor data corruption issue during nfs v2 udp |
Jesse Brandeburg | a80483d | 2010-03-05 02:21:44 +0000 | [diff] [blame] | 5030 | * traffic, just disable the nfs filtering capability |
| 5031 | */ |
| 5032 | reg = er32(RFCTL); |
| 5033 | reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); |
Matthew Vick | f6bd557 | 2012-04-25 08:01:05 +0000 | [diff] [blame] | 5034 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 5035 | /* Disable IPv6 extension header parsing because some malformed |
Matthew Vick | f6bd557 | 2012-04-25 08:01:05 +0000 | [diff] [blame] | 5036 | * IPv6 headers can hang the Rx. |
| 5037 | */ |
| 5038 | if (hw->mac.type == e1000_ich8lan) |
| 5039 | reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); |
Jesse Brandeburg | a80483d | 2010-03-05 02:21:44 +0000 | [diff] [blame] | 5040 | ew32(RFCTL, reg); |
Bruce Allan | 94fb848 | 2013-01-23 09:00:03 +0000 | [diff] [blame] | 5041 | |
| 5042 | /* Enable ECC on Lynxpoint */ |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 5043 | if (hw->mac.type >= e1000_pch_lpt) { |
Bruce Allan | 94fb848 | 2013-01-23 09:00:03 +0000 | [diff] [blame] | 5044 | reg = er32(PBECCSTS); |
| 5045 | reg |= E1000_PBECCSTS_ECC_ENABLE; |
| 5046 | ew32(PBECCSTS, reg); |
| 5047 | |
| 5048 | reg = er32(CTRL); |
| 5049 | reg |= E1000_CTRL_MEHE; |
| 5050 | ew32(CTRL, reg); |
| 5051 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5052 | } |
| 5053 | |
| 5054 | /** |
| 5055 | * e1000_setup_link_ich8lan - Setup flow control and link settings |
| 5056 | * @hw: pointer to the HW structure |
| 5057 | * |
| 5058 | * Determines which flow control settings to use, then configures flow |
| 5059 | * control. Calls the appropriate media-specific link configuration |
| 5060 | * function. Assuming the adapter has a valid link partner, a valid link |
| 5061 | * should be established. Assumes the hardware has previously been reset |
| 5062 | * and the transmitter and receiver are not enabled. |
| 5063 | **/ |
| 5064 | static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) |
| 5065 | { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5066 | s32 ret_val; |
| 5067 | |
Bruce Allan | 44abd5c | 2012-02-22 09:02:37 +0000 | [diff] [blame] | 5068 | if (hw->phy.ops.check_reset_block(hw)) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5069 | return 0; |
| 5070 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 5071 | /* ICH parts do not have a word in the NVM to determine |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5072 | * the default flow control setting, so we explicitly |
| 5073 | * set it to full. |
| 5074 | */ |
Bruce Allan | 37289d9 | 2009-06-02 11:29:37 +0000 | [diff] [blame] | 5075 | if (hw->fc.requested_mode == e1000_fc_default) { |
| 5076 | /* Workaround h/w hang when Tx flow control enabled */ |
| 5077 | if (hw->mac.type == e1000_pchlan) |
| 5078 | hw->fc.requested_mode = e1000_fc_rx_pause; |
| 5079 | else |
| 5080 | hw->fc.requested_mode = e1000_fc_full; |
| 5081 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5082 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 5083 | /* Save off the requested flow control mode for use later. Depending |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 5084 | * on the link partner's capabilities, we may or may not use this mode. |
| 5085 | */ |
| 5086 | hw->fc.current_mode = hw->fc.requested_mode; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5087 | |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 5088 | e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5089 | |
| 5090 | /* Continue to configure the copper link. */ |
Bruce Allan | 944ce01 | 2012-02-22 09:02:42 +0000 | [diff] [blame] | 5091 | ret_val = hw->mac.ops.setup_physical_interface(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5092 | if (ret_val) |
| 5093 | return ret_val; |
| 5094 | |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 5095 | ew32(FCTTV, hw->fc.pause_time); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5096 | if ((hw->phy.type == e1000_phy_82578) || |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 5097 | (hw->phy.type == e1000_phy_82579) || |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5098 | (hw->phy.type == e1000_phy_i217) || |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5099 | (hw->phy.type == e1000_phy_82577)) { |
Bruce Allan | a305595 | 2010-05-10 15:02:12 +0000 | [diff] [blame] | 5100 | ew32(FCRTV_PCH, hw->fc.refresh_time); |
| 5101 | |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 5102 | ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), |
| 5103 | hw->fc.pause_time); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5104 | if (ret_val) |
| 5105 | return ret_val; |
| 5106 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5107 | |
| 5108 | return e1000e_set_fc_watermarks(hw); |
| 5109 | } |
| 5110 | |
| 5111 | /** |
| 5112 | * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface |
| 5113 | * @hw: pointer to the HW structure |
| 5114 | * |
| 5115 | * Configures the kumeran interface to the PHY to wait the appropriate time |
| 5116 | * when polling the PHY, then call the generic setup_copper_link to finish |
| 5117 | * configuring the copper link. |
| 5118 | **/ |
| 5119 | static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) |
| 5120 | { |
| 5121 | u32 ctrl; |
| 5122 | s32 ret_val; |
| 5123 | u16 reg_data; |
| 5124 | |
| 5125 | ctrl = er32(CTRL); |
| 5126 | ctrl |= E1000_CTRL_SLU; |
| 5127 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
| 5128 | ew32(CTRL, ctrl); |
| 5129 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 5130 | /* Set the mac to wait the maximum time between each iteration |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5131 | * and increase the max iterations when polling the phy; |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 5132 | * this fixes erroneous timeouts at 10Mbps. |
| 5133 | */ |
Bruce Allan | 0781895 | 2009-12-08 07:28:01 +0000 | [diff] [blame] | 5134 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5135 | if (ret_val) |
| 5136 | return ret_val; |
Bruce Allan | 0781895 | 2009-12-08 07:28:01 +0000 | [diff] [blame] | 5137 | ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 5138 | ®_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5139 | if (ret_val) |
| 5140 | return ret_val; |
| 5141 | reg_data |= 0x3F; |
Bruce Allan | 0781895 | 2009-12-08 07:28:01 +0000 | [diff] [blame] | 5142 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 5143 | reg_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5144 | if (ret_val) |
| 5145 | return ret_val; |
| 5146 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5147 | switch (hw->phy.type) { |
| 5148 | case e1000_phy_igp_3: |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5149 | ret_val = e1000e_copper_link_setup_igp(hw); |
| 5150 | if (ret_val) |
| 5151 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5152 | break; |
| 5153 | case e1000_phy_bm: |
| 5154 | case e1000_phy_82578: |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 5155 | ret_val = e1000e_copper_link_setup_m88(hw); |
| 5156 | if (ret_val) |
| 5157 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5158 | break; |
| 5159 | case e1000_phy_82577: |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 5160 | case e1000_phy_82579: |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5161 | ret_val = e1000_copper_link_setup_82577(hw); |
| 5162 | if (ret_val) |
| 5163 | return ret_val; |
| 5164 | break; |
| 5165 | case e1000_phy_ife: |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 5166 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 5167 | if (ret_val) |
| 5168 | return ret_val; |
| 5169 | |
| 5170 | reg_data &= ~IFE_PMC_AUTO_MDIX; |
| 5171 | |
| 5172 | switch (hw->phy.mdix) { |
| 5173 | case 1: |
| 5174 | reg_data &= ~IFE_PMC_FORCE_MDIX; |
| 5175 | break; |
| 5176 | case 2: |
| 5177 | reg_data |= IFE_PMC_FORCE_MDIX; |
| 5178 | break; |
| 5179 | case 0: |
| 5180 | default: |
| 5181 | reg_data |= IFE_PMC_AUTO_MDIX; |
| 5182 | break; |
| 5183 | } |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 5184 | ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 5185 | if (ret_val) |
| 5186 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5187 | break; |
| 5188 | default: |
| 5189 | break; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 5190 | } |
Bruce Allan | 3fa829363 | 2012-02-08 02:55:40 +0000 | [diff] [blame] | 5191 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5192 | return e1000e_setup_copper_link(hw); |
| 5193 | } |
| 5194 | |
| 5195 | /** |
Bruce Allan | ea8179a | 2013-03-06 09:02:47 +0000 | [diff] [blame] | 5196 | * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface |
| 5197 | * @hw: pointer to the HW structure |
| 5198 | * |
| 5199 | * Calls the PHY specific link setup function and then calls the |
| 5200 | * generic setup_copper_link to finish configuring the link for |
| 5201 | * Lynxpoint PCH devices |
| 5202 | **/ |
| 5203 | static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) |
| 5204 | { |
| 5205 | u32 ctrl; |
| 5206 | s32 ret_val; |
| 5207 | |
| 5208 | ctrl = er32(CTRL); |
| 5209 | ctrl |= E1000_CTRL_SLU; |
| 5210 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
| 5211 | ew32(CTRL, ctrl); |
| 5212 | |
| 5213 | ret_val = e1000_copper_link_setup_82577(hw); |
| 5214 | if (ret_val) |
| 5215 | return ret_val; |
| 5216 | |
| 5217 | return e1000e_setup_copper_link(hw); |
| 5218 | } |
| 5219 | |
| 5220 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5221 | * e1000_get_link_up_info_ich8lan - Get current link speed and duplex |
| 5222 | * @hw: pointer to the HW structure |
| 5223 | * @speed: pointer to store current link speed |
| 5224 | * @duplex: pointer to store the current link duplex |
| 5225 | * |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 5226 | * Calls the generic get_speed_and_duplex to retrieve the current link |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5227 | * information and then calls the Kumeran lock loss workaround for links at |
| 5228 | * gigabit speeds. |
| 5229 | **/ |
| 5230 | static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, |
| 5231 | u16 *duplex) |
| 5232 | { |
| 5233 | s32 ret_val; |
| 5234 | |
| 5235 | ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); |
| 5236 | if (ret_val) |
| 5237 | return ret_val; |
| 5238 | |
| 5239 | if ((hw->mac.type == e1000_ich8lan) && |
Bruce Allan | e5fe254 | 2013-02-20 04:06:27 +0000 | [diff] [blame] | 5240 | (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5241 | ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); |
| 5242 | } |
| 5243 | |
| 5244 | return ret_val; |
| 5245 | } |
| 5246 | |
| 5247 | /** |
| 5248 | * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround |
| 5249 | * @hw: pointer to the HW structure |
| 5250 | * |
| 5251 | * Work-around for 82566 Kumeran PCS lock loss: |
| 5252 | * On link status change (i.e. PCI reset, speed change) and link is up and |
| 5253 | * speed is gigabit- |
| 5254 | * 0) if workaround is optionally disabled do nothing |
| 5255 | * 1) wait 1ms for Kumeran link to come up |
| 5256 | * 2) check Kumeran Diagnostic register PCS lock loss bit |
| 5257 | * 3) if not set the link is locked (all is good), otherwise... |
| 5258 | * 4) reset the PHY |
| 5259 | * 5) repeat up to 10 times |
| 5260 | * Note: this is only called for IGP3 copper when speed is 1gb. |
| 5261 | **/ |
| 5262 | static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) |
| 5263 | { |
| 5264 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
| 5265 | u32 phy_ctrl; |
| 5266 | s32 ret_val; |
| 5267 | u16 i, data; |
| 5268 | bool link; |
| 5269 | |
| 5270 | if (!dev_spec->kmrn_lock_loss_workaround_enabled) |
| 5271 | return 0; |
| 5272 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 5273 | /* Make sure link is up before proceeding. If not just return. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5274 | * Attempting this while link is negotiating fouled up link |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 5275 | * stability |
| 5276 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5277 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
| 5278 | if (!link) |
| 5279 | return 0; |
| 5280 | |
| 5281 | for (i = 0; i < 10; i++) { |
| 5282 | /* read once to clear */ |
| 5283 | ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); |
| 5284 | if (ret_val) |
| 5285 | return ret_val; |
| 5286 | /* and again to get new status */ |
| 5287 | ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); |
| 5288 | if (ret_val) |
| 5289 | return ret_val; |
| 5290 | |
| 5291 | /* check for PCS lock */ |
| 5292 | if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) |
| 5293 | return 0; |
| 5294 | |
| 5295 | /* Issue PHY reset */ |
| 5296 | e1000_phy_hw_reset(hw); |
| 5297 | mdelay(5); |
| 5298 | } |
| 5299 | /* Disable GigE link negotiation */ |
| 5300 | phy_ctrl = er32(PHY_CTRL); |
| 5301 | phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | |
| 5302 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); |
| 5303 | ew32(PHY_CTRL, phy_ctrl); |
| 5304 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 5305 | /* Call gig speed drop workaround on Gig disable before accessing |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 5306 | * any PHY registers |
| 5307 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5308 | e1000e_gig_downshift_workaround_ich8lan(hw); |
| 5309 | |
| 5310 | /* unable to acquire PCS lock */ |
| 5311 | return -E1000_ERR_PHY; |
| 5312 | } |
| 5313 | |
| 5314 | /** |
Bruce Allan | 6e3c807 | 2012-02-22 09:02:47 +0000 | [diff] [blame] | 5315 | * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5316 | * @hw: pointer to the HW structure |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 5317 | * @state: boolean value used to set the current Kumeran workaround state |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5318 | * |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 5319 | * If ICH8, set the current Kumeran workaround state (enabled - true |
| 5320 | * /disabled - false). |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5321 | **/ |
| 5322 | void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 5323 | bool state) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5324 | { |
| 5325 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
| 5326 | |
| 5327 | if (hw->mac.type != e1000_ich8lan) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 5328 | e_dbg("Workaround applies to ICH8 only.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5329 | return; |
| 5330 | } |
| 5331 | |
| 5332 | dev_spec->kmrn_lock_loss_workaround_enabled = state; |
| 5333 | } |
| 5334 | |
| 5335 | /** |
Sasha Neftin | 39da2ca | 2021-03-14 15:59:20 +0200 | [diff] [blame] | 5336 | * e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5337 | * @hw: pointer to the HW structure |
| 5338 | * |
| 5339 | * Workaround for 82566 power-down on D3 entry: |
| 5340 | * 1) disable gigabit link |
| 5341 | * 2) write VR power-down enable |
| 5342 | * 3) read it back |
| 5343 | * Continue if successful, else issue LCD reset and repeat |
| 5344 | **/ |
| 5345 | void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) |
| 5346 | { |
| 5347 | u32 reg; |
| 5348 | u16 data; |
Bruce Allan | e80bd1d | 2013-05-01 01:19:46 +0000 | [diff] [blame] | 5349 | u8 retry = 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5350 | |
| 5351 | if (hw->phy.type != e1000_phy_igp_3) |
| 5352 | return; |
| 5353 | |
| 5354 | /* Try the workaround twice (if needed) */ |
| 5355 | do { |
| 5356 | /* Disable link */ |
| 5357 | reg = er32(PHY_CTRL); |
| 5358 | reg |= (E1000_PHY_CTRL_GBE_DISABLE | |
| 5359 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); |
| 5360 | ew32(PHY_CTRL, reg); |
| 5361 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 5362 | /* Call gig speed drop workaround on Gig disable before |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 5363 | * accessing any PHY registers |
| 5364 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5365 | if (hw->mac.type == e1000_ich8lan) |
| 5366 | e1000e_gig_downshift_workaround_ich8lan(hw); |
| 5367 | |
| 5368 | /* Write VR power-down enable */ |
| 5369 | e1e_rphy(hw, IGP3_VR_CTRL, &data); |
| 5370 | data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; |
| 5371 | e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); |
| 5372 | |
| 5373 | /* Read it back and test */ |
| 5374 | e1e_rphy(hw, IGP3_VR_CTRL, &data); |
| 5375 | data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; |
| 5376 | if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) |
| 5377 | break; |
| 5378 | |
| 5379 | /* Issue PHY reset and repeat at most one more time */ |
| 5380 | reg = er32(CTRL); |
| 5381 | ew32(CTRL, reg | E1000_CTRL_PHY_RST); |
| 5382 | retry++; |
| 5383 | } while (retry); |
| 5384 | } |
| 5385 | |
| 5386 | /** |
| 5387 | * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working |
| 5388 | * @hw: pointer to the HW structure |
| 5389 | * |
| 5390 | * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 5391 | * LPLU, Gig disable, MDIC PHY reset): |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5392 | * 1) Set Kumeran Near-end loopback |
| 5393 | * 2) Clear Kumeran Near-end loopback |
Bruce Allan | 462d599 | 2011-09-30 08:07:11 +0000 | [diff] [blame] | 5394 | * Should only be called for ICH8[m] devices with any 1G Phy. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5395 | **/ |
| 5396 | void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) |
| 5397 | { |
| 5398 | s32 ret_val; |
| 5399 | u16 reg_data; |
| 5400 | |
Bruce Allan | 462d599 | 2011-09-30 08:07:11 +0000 | [diff] [blame] | 5401 | if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5402 | return; |
| 5403 | |
| 5404 | ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 5405 | ®_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5406 | if (ret_val) |
| 5407 | return; |
| 5408 | reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; |
| 5409 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 5410 | reg_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5411 | if (ret_val) |
| 5412 | return; |
| 5413 | reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; |
Bruce Allan | 7dbbe5d | 2013-01-05 05:08:31 +0000 | [diff] [blame] | 5414 | e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5415 | } |
| 5416 | |
| 5417 | /** |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 5418 | * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 5419 | * @hw: pointer to the HW structure |
| 5420 | * |
| 5421 | * During S0 to Sx transition, it is possible the link remains at gig |
| 5422 | * instead of negotiating to a lower speed. Before going to Sx, set |
Bruce Allan | c077a90 | 2011-12-16 00:46:38 +0000 | [diff] [blame] | 5423 | * 'Gig Disable' to force link speed negotiation to a lower speed based on |
| 5424 | * the LPLU setting in the NVM or custom setting. For PCH and newer parts, |
| 5425 | * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also |
| 5426 | * needs to be written. |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5427 | * Parts that support (and are linked to a partner which support) EEE in |
| 5428 | * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power |
| 5429 | * than 10Mbps w/o EEE. |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 5430 | **/ |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 5431 | void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 5432 | { |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5433 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 5434 | u32 phy_ctrl; |
Bruce Allan | 8395ae8 | 2010-09-22 17:15:08 +0000 | [diff] [blame] | 5435 | s32 ret_val; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 5436 | |
Bruce Allan | 17f085d | 2010-06-17 18:59:48 +0000 | [diff] [blame] | 5437 | phy_ctrl = er32(PHY_CTRL); |
Bruce Allan | c077a90 | 2011-12-16 00:46:38 +0000 | [diff] [blame] | 5438 | phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; |
Bruce Allan | e08f626 | 2013-02-20 03:06:34 +0000 | [diff] [blame] | 5439 | |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5440 | if (hw->phy.type == e1000_phy_i217) { |
Bruce Allan | e08f626 | 2013-02-20 03:06:34 +0000 | [diff] [blame] | 5441 | u16 phy_reg, device_id = hw->adapter->pdev->device; |
| 5442 | |
| 5443 | if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || |
Bruce Allan | 91a3d82 | 2013-06-29 01:15:16 +0000 | [diff] [blame] | 5444 | (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || |
| 5445 | (device_id == E1000_DEV_ID_PCH_I218_LM3) || |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 5446 | (device_id == E1000_DEV_ID_PCH_I218_V3) || |
Sasha Neftin | c8744f4 | 2017-04-06 10:26:47 +0300 | [diff] [blame] | 5447 | (hw->mac.type >= e1000_pch_spt)) { |
Bruce Allan | e08f626 | 2013-02-20 03:06:34 +0000 | [diff] [blame] | 5448 | u32 fextnvm6 = er32(FEXTNVM6); |
| 5449 | |
| 5450 | ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); |
| 5451 | } |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5452 | |
| 5453 | ret_val = hw->phy.ops.acquire(hw); |
| 5454 | if (ret_val) |
| 5455 | goto out; |
| 5456 | |
| 5457 | if (!dev_spec->eee_disable) { |
| 5458 | u16 eee_advert; |
| 5459 | |
Bruce Allan | 4ddc48a | 2012-12-05 06:25:58 +0000 | [diff] [blame] | 5460 | ret_val = |
| 5461 | e1000_read_emi_reg_locked(hw, |
| 5462 | I217_EEE_ADVERTISEMENT, |
| 5463 | &eee_advert); |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5464 | if (ret_val) |
| 5465 | goto release; |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5466 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 5467 | /* Disable LPLU if both link partners support 100BaseT |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5468 | * EEE and 100Full is advertised on both ends of the |
David Ertman | b4c1e6b | 2014-07-11 06:20:51 +0000 | [diff] [blame] | 5469 | * link, and enable Auto Enable LPI since there will |
| 5470 | * be no driver to enable LPI while in Sx. |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5471 | */ |
Bruce Allan | 3d4d575 | 2012-12-05 06:26:08 +0000 | [diff] [blame] | 5472 | if ((eee_advert & I82579_EEE_100_SUPPORTED) && |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5473 | (dev_spec->eee_lp_ability & |
Bruce Allan | 3d4d575 | 2012-12-05 06:26:08 +0000 | [diff] [blame] | 5474 | I82579_EEE_100_SUPPORTED) && |
David Ertman | b4c1e6b | 2014-07-11 06:20:51 +0000 | [diff] [blame] | 5475 | (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5476 | phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | |
| 5477 | E1000_PHY_CTRL_NOND0A_LPLU); |
David Ertman | b4c1e6b | 2014-07-11 06:20:51 +0000 | [diff] [blame] | 5478 | |
| 5479 | /* Set Auto Enable LPI after link up */ |
| 5480 | e1e_rphy_locked(hw, |
| 5481 | I217_LPI_GPIO_CTRL, &phy_reg); |
| 5482 | phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI; |
| 5483 | e1e_wphy_locked(hw, |
| 5484 | I217_LPI_GPIO_CTRL, phy_reg); |
| 5485 | } |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5486 | } |
| 5487 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 5488 | /* For i217 Intel Rapid Start Technology support, |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5489 | * when the system is going into Sx and no manageability engine |
| 5490 | * is present, the driver must configure proxy to reset only on |
| 5491 | * power good. LPI (Low Power Idle) state must also reset only |
| 5492 | * on power good, as well as the MTA (Multicast table array). |
| 5493 | * The SMBus release must also be disabled on LCD reset. |
| 5494 | */ |
| 5495 | if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5496 | /* Enable proxy to reset only on power good. */ |
| 5497 | e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); |
| 5498 | phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; |
| 5499 | e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); |
| 5500 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 5501 | /* Set bit enable LPI (EEE) to reset only on |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5502 | * power good. |
| 5503 | */ |
| 5504 | e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); |
Bruce Allan | 6d7407b | 2012-05-10 02:51:17 +0000 | [diff] [blame] | 5505 | phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5506 | e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); |
| 5507 | |
| 5508 | /* Disable the SMB release on LCD reset. */ |
| 5509 | e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); |
Bruce Allan | 6d7407b | 2012-05-10 02:51:17 +0000 | [diff] [blame] | 5510 | phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5511 | e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); |
| 5512 | } |
| 5513 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 5514 | /* Enable MTA to reset for Intel Rapid Start Technology |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5515 | * Support |
| 5516 | */ |
| 5517 | e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); |
Bruce Allan | 6d7407b | 2012-05-10 02:51:17 +0000 | [diff] [blame] | 5518 | phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5519 | e1e_wphy_locked(hw, I217_CGFREG, phy_reg); |
| 5520 | |
| 5521 | release: |
| 5522 | hw->phy.ops.release(hw); |
| 5523 | } |
| 5524 | out: |
Bruce Allan | 17f085d | 2010-06-17 18:59:48 +0000 | [diff] [blame] | 5525 | ew32(PHY_CTRL, phy_ctrl); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5526 | |
Bruce Allan | 462d599 | 2011-09-30 08:07:11 +0000 | [diff] [blame] | 5527 | if (hw->mac.type == e1000_ich8lan) |
| 5528 | e1000e_gig_downshift_workaround_ich8lan(hw); |
| 5529 | |
Bruce Allan | 8395ae8 | 2010-09-22 17:15:08 +0000 | [diff] [blame] | 5530 | if (hw->mac.type >= e1000_pchlan) { |
Bruce Allan | ce54afd | 2010-11-24 06:01:41 +0000 | [diff] [blame] | 5531 | e1000_oem_bits_config_ich8lan(hw, false); |
Bruce Allan | 92fe173 | 2012-04-12 06:27:03 +0000 | [diff] [blame] | 5532 | |
| 5533 | /* Reset PHY to activate OEM bits on 82577/8 */ |
| 5534 | if (hw->mac.type == e1000_pchlan) |
| 5535 | e1000e_phy_hw_reset_generic(hw); |
| 5536 | |
Bruce Allan | 8395ae8 | 2010-09-22 17:15:08 +0000 | [diff] [blame] | 5537 | ret_val = hw->phy.ops.acquire(hw); |
| 5538 | if (ret_val) |
| 5539 | return; |
| 5540 | e1000_write_smbus_addr(hw); |
| 5541 | hw->phy.ops.release(hw); |
| 5542 | } |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 5543 | } |
| 5544 | |
| 5545 | /** |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 5546 | * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 |
| 5547 | * @hw: pointer to the HW structure |
| 5548 | * |
| 5549 | * During Sx to S0 transitions on non-managed devices or managed devices |
| 5550 | * on which PHY resets are not blocked, if the PHY registers cannot be |
| 5551 | * accessed properly by the s/w toggle the LANPHYPC value to power cycle |
| 5552 | * the PHY. |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5553 | * On i217, setup Intel Rapid Start Technology. |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 5554 | **/ |
| 5555 | void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) |
| 5556 | { |
Bruce Allan | 90b8298 | 2011-12-16 00:46:33 +0000 | [diff] [blame] | 5557 | s32 ret_val; |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 5558 | |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 5559 | if (hw->mac.type < e1000_pch2lan) |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 5560 | return; |
| 5561 | |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 5562 | ret_val = e1000_init_phy_workarounds_pchlan(hw); |
Bruce Allan | 90b8298 | 2011-12-16 00:46:33 +0000 | [diff] [blame] | 5563 | if (ret_val) { |
Bruce Allan | cb17aab | 2012-04-13 03:16:22 +0000 | [diff] [blame] | 5564 | e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 5565 | return; |
| 5566 | } |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5567 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 5568 | /* For i217 Intel Rapid Start Technology support when the system |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5569 | * is transitioning from Sx and no manageability engine is present |
| 5570 | * configure SMBus to restore on reset, disable proxy, and enable |
| 5571 | * the reset on MTA (Multicast table array). |
| 5572 | */ |
| 5573 | if (hw->phy.type == e1000_phy_i217) { |
| 5574 | u16 phy_reg; |
| 5575 | |
| 5576 | ret_val = hw->phy.ops.acquire(hw); |
| 5577 | if (ret_val) { |
| 5578 | e_dbg("Failed to setup iRST\n"); |
| 5579 | return; |
| 5580 | } |
| 5581 | |
David Ertman | b4c1e6b | 2014-07-11 06:20:51 +0000 | [diff] [blame] | 5582 | /* Clear Auto Enable LPI after link up */ |
| 5583 | e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); |
| 5584 | phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI; |
| 5585 | e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); |
| 5586 | |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5587 | if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 5588 | /* Restore clear on SMB if no manageability engine |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5589 | * is present |
| 5590 | */ |
| 5591 | ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); |
| 5592 | if (ret_val) |
| 5593 | goto release; |
Bruce Allan | 6d7407b | 2012-05-10 02:51:17 +0000 | [diff] [blame] | 5594 | phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5595 | e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); |
| 5596 | |
| 5597 | /* Disable Proxy */ |
| 5598 | e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); |
| 5599 | } |
| 5600 | /* Enable reset on MTA */ |
| 5601 | ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); |
| 5602 | if (ret_val) |
| 5603 | goto release; |
Bruce Allan | 6d7407b | 2012-05-10 02:51:17 +0000 | [diff] [blame] | 5604 | phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5605 | e1e_wphy_locked(hw, I217_CGFREG, phy_reg); |
| 5606 | release: |
| 5607 | if (ret_val) |
| 5608 | e_dbg("Error %d in resume workarounds\n", ret_val); |
| 5609 | hw->phy.ops.release(hw); |
| 5610 | } |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 5611 | } |
| 5612 | |
| 5613 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5614 | * e1000_cleanup_led_ich8lan - Restore the default LED operation |
| 5615 | * @hw: pointer to the HW structure |
| 5616 | * |
| 5617 | * Return the LED back to the default configuration. |
| 5618 | **/ |
| 5619 | static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) |
| 5620 | { |
| 5621 | if (hw->phy.type == e1000_phy_ife) |
| 5622 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); |
| 5623 | |
| 5624 | ew32(LEDCTL, hw->mac.ledctl_default); |
| 5625 | return 0; |
| 5626 | } |
| 5627 | |
| 5628 | /** |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 5629 | * e1000_led_on_ich8lan - Turn LEDs on |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5630 | * @hw: pointer to the HW structure |
| 5631 | * |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 5632 | * Turn on the LEDs. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5633 | **/ |
| 5634 | static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) |
| 5635 | { |
| 5636 | if (hw->phy.type == e1000_phy_ife) |
| 5637 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, |
| 5638 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); |
| 5639 | |
| 5640 | ew32(LEDCTL, hw->mac.ledctl_mode2); |
| 5641 | return 0; |
| 5642 | } |
| 5643 | |
| 5644 | /** |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 5645 | * e1000_led_off_ich8lan - Turn LEDs off |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5646 | * @hw: pointer to the HW structure |
| 5647 | * |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 5648 | * Turn off the LEDs. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5649 | **/ |
| 5650 | static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) |
| 5651 | { |
| 5652 | if (hw->phy.type == e1000_phy_ife) |
| 5653 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 5654 | (IFE_PSCL_PROBE_MODE | |
| 5655 | IFE_PSCL_PROBE_LEDS_OFF)); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5656 | |
| 5657 | ew32(LEDCTL, hw->mac.ledctl_mode1); |
| 5658 | return 0; |
| 5659 | } |
| 5660 | |
| 5661 | /** |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5662 | * e1000_setup_led_pchlan - Configures SW controllable LED |
| 5663 | * @hw: pointer to the HW structure |
| 5664 | * |
| 5665 | * This prepares the SW controllable LED for use. |
| 5666 | **/ |
| 5667 | static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) |
| 5668 | { |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 5669 | return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5670 | } |
| 5671 | |
| 5672 | /** |
| 5673 | * e1000_cleanup_led_pchlan - Restore the default LED operation |
| 5674 | * @hw: pointer to the HW structure |
| 5675 | * |
| 5676 | * Return the LED back to the default configuration. |
| 5677 | **/ |
| 5678 | static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) |
| 5679 | { |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 5680 | return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5681 | } |
| 5682 | |
| 5683 | /** |
| 5684 | * e1000_led_on_pchlan - Turn LEDs on |
| 5685 | * @hw: pointer to the HW structure |
| 5686 | * |
| 5687 | * Turn on the LEDs. |
| 5688 | **/ |
| 5689 | static s32 e1000_led_on_pchlan(struct e1000_hw *hw) |
| 5690 | { |
| 5691 | u16 data = (u16)hw->mac.ledctl_mode2; |
| 5692 | u32 i, led; |
| 5693 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 5694 | /* If no link, then turn LED on by setting the invert bit |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5695 | * for each LED that's mode is "link_up" in ledctl_mode2. |
| 5696 | */ |
| 5697 | if (!(er32(STATUS) & E1000_STATUS_LU)) { |
| 5698 | for (i = 0; i < 3; i++) { |
| 5699 | led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; |
| 5700 | if ((led & E1000_PHY_LED0_MODE_MASK) != |
| 5701 | E1000_LEDCTL_MODE_LINK_UP) |
| 5702 | continue; |
| 5703 | if (led & E1000_PHY_LED0_IVRT) |
| 5704 | data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); |
| 5705 | else |
| 5706 | data |= (E1000_PHY_LED0_IVRT << (i * 5)); |
| 5707 | } |
| 5708 | } |
| 5709 | |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 5710 | return e1e_wphy(hw, HV_LED_CONFIG, data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5711 | } |
| 5712 | |
| 5713 | /** |
| 5714 | * e1000_led_off_pchlan - Turn LEDs off |
| 5715 | * @hw: pointer to the HW structure |
| 5716 | * |
| 5717 | * Turn off the LEDs. |
| 5718 | **/ |
| 5719 | static s32 e1000_led_off_pchlan(struct e1000_hw *hw) |
| 5720 | { |
| 5721 | u16 data = (u16)hw->mac.ledctl_mode1; |
| 5722 | u32 i, led; |
| 5723 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 5724 | /* If no link, then turn LED off by clearing the invert bit |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5725 | * for each LED that's mode is "link_up" in ledctl_mode1. |
| 5726 | */ |
| 5727 | if (!(er32(STATUS) & E1000_STATUS_LU)) { |
| 5728 | for (i = 0; i < 3; i++) { |
| 5729 | led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; |
| 5730 | if ((led & E1000_PHY_LED0_MODE_MASK) != |
| 5731 | E1000_LEDCTL_MODE_LINK_UP) |
| 5732 | continue; |
| 5733 | if (led & E1000_PHY_LED0_IVRT) |
| 5734 | data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); |
| 5735 | else |
| 5736 | data |= (E1000_PHY_LED0_IVRT << (i * 5)); |
| 5737 | } |
| 5738 | } |
| 5739 | |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 5740 | return e1e_wphy(hw, HV_LED_CONFIG, data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5741 | } |
| 5742 | |
| 5743 | /** |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 5744 | * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 5745 | * @hw: pointer to the HW structure |
| 5746 | * |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 5747 | * Read appropriate register for the config done bit for completion status |
| 5748 | * and configure the PHY through s/w for EEPROM-less parts. |
| 5749 | * |
| 5750 | * NOTE: some silicon which is EEPROM-less will fail trying to read the |
| 5751 | * config done bit, so only an error is logged and continues. If we were |
| 5752 | * to return with error, EEPROM-less silicon would not be able to be reset |
| 5753 | * or change link. |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 5754 | **/ |
| 5755 | static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) |
| 5756 | { |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 5757 | s32 ret_val = 0; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 5758 | u32 bank = 0; |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 5759 | u32 status; |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 5760 | |
Bruce Allan | fe90849 | 2013-01-05 08:06:14 +0000 | [diff] [blame] | 5761 | e1000e_get_cfg_done_generic(hw); |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 5762 | |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 5763 | /* Wait for indication from h/w that it has completed basic config */ |
| 5764 | if (hw->mac.type >= e1000_ich10lan) { |
| 5765 | e1000_lan_init_done_ich8lan(hw); |
| 5766 | } else { |
| 5767 | ret_val = e1000e_get_auto_rd_done(hw); |
| 5768 | if (ret_val) { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 5769 | /* When auto config read does not complete, do not |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 5770 | * return with an error. This can happen in situations |
| 5771 | * where there is no eeprom and prevents getting link. |
| 5772 | */ |
| 5773 | e_dbg("Auto Read Done did not complete\n"); |
| 5774 | ret_val = 0; |
| 5775 | } |
| 5776 | } |
| 5777 | |
| 5778 | /* Clear PHY Reset Asserted bit */ |
| 5779 | status = er32(STATUS); |
| 5780 | if (status & E1000_STATUS_PHYRA) |
| 5781 | ew32(STATUS, status & ~E1000_STATUS_PHYRA); |
| 5782 | else |
| 5783 | e_dbg("PHY Reset Asserted not set - needs delay\n"); |
| 5784 | |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 5785 | /* If EEPROM is not marked present, init the IGP 3 PHY manually */ |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 5786 | if (hw->mac.type <= e1000_ich9lan) { |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 5787 | if (!(er32(EECD) & E1000_EECD_PRES) && |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 5788 | (hw->phy.type == e1000_phy_igp_3)) { |
| 5789 | e1000e_phy_init_script_igp3(hw); |
| 5790 | } |
| 5791 | } else { |
| 5792 | if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { |
| 5793 | /* Maybe we should do a basic PHY config */ |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 5794 | e_dbg("EEPROM not present\n"); |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 5795 | ret_val = -E1000_ERR_CONFIG; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 5796 | } |
| 5797 | } |
| 5798 | |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 5799 | return ret_val; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 5800 | } |
| 5801 | |
| 5802 | /** |
Bruce Allan | 17f208d | 2009-12-01 15:47:22 +0000 | [diff] [blame] | 5803 | * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down |
| 5804 | * @hw: pointer to the HW structure |
| 5805 | * |
| 5806 | * In the case of a PHY power down to save power, or to turn off link during a |
| 5807 | * driver unload, or wake on lan is not enabled, remove the link. |
| 5808 | **/ |
| 5809 | static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) |
| 5810 | { |
| 5811 | /* If the management interface is not enabled, then power down */ |
| 5812 | if (!(hw->mac.ops.check_mng_mode(hw) || |
| 5813 | hw->phy.ops.check_reset_block(hw))) |
| 5814 | e1000_power_down_phy_copper(hw); |
Bruce Allan | 17f208d | 2009-12-01 15:47:22 +0000 | [diff] [blame] | 5815 | } |
| 5816 | |
| 5817 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5818 | * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters |
| 5819 | * @hw: pointer to the HW structure |
| 5820 | * |
| 5821 | * Clears hardware counters specific to the silicon family and calls |
| 5822 | * clear_hw_cntrs_generic to clear all general purpose counters. |
| 5823 | **/ |
| 5824 | static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) |
| 5825 | { |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5826 | u16 phy_data; |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 5827 | s32 ret_val; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5828 | |
| 5829 | e1000e_clear_hw_cntrs_base(hw); |
| 5830 | |
Bruce Allan | 99673d9 | 2009-11-20 23:27:21 +0000 | [diff] [blame] | 5831 | er32(ALGNERRC); |
| 5832 | er32(RXERRC); |
| 5833 | er32(TNCRS); |
| 5834 | er32(CEXTERR); |
| 5835 | er32(TSCTC); |
| 5836 | er32(TSCTFC); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5837 | |
Bruce Allan | 99673d9 | 2009-11-20 23:27:21 +0000 | [diff] [blame] | 5838 | er32(MGTPRC); |
| 5839 | er32(MGTPDC); |
| 5840 | er32(MGTPTC); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5841 | |
Bruce Allan | 99673d9 | 2009-11-20 23:27:21 +0000 | [diff] [blame] | 5842 | er32(IAC); |
| 5843 | er32(ICRXOC); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5844 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5845 | /* Clear PHY statistics registers */ |
| 5846 | if ((hw->phy.type == e1000_phy_82578) || |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 5847 | (hw->phy.type == e1000_phy_82579) || |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 5848 | (hw->phy.type == e1000_phy_i217) || |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5849 | (hw->phy.type == e1000_phy_82577)) { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 5850 | ret_val = hw->phy.ops.acquire(hw); |
| 5851 | if (ret_val) |
| 5852 | return; |
| 5853 | ret_val = hw->phy.ops.set_page(hw, |
| 5854 | HV_STATS_PAGE << IGP_PAGE_SHIFT); |
| 5855 | if (ret_val) |
| 5856 | goto release; |
| 5857 | hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); |
| 5858 | hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); |
| 5859 | hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); |
| 5860 | hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); |
| 5861 | hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); |
| 5862 | hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); |
| 5863 | hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); |
| 5864 | hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); |
| 5865 | hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); |
| 5866 | hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); |
| 5867 | hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); |
| 5868 | hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); |
| 5869 | hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); |
| 5870 | hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); |
| 5871 | release: |
| 5872 | hw->phy.ops.release(hw); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5873 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5874 | } |
| 5875 | |
Jeff Kirsher | 8ce9d6c | 2011-09-24 13:23:52 +0000 | [diff] [blame] | 5876 | static const struct e1000_mac_operations ich8_mac_ops = { |
Bruce Allan | eb7700d | 2010-06-16 13:27:05 +0000 | [diff] [blame] | 5877 | /* check_mng_mode dependent on mac type */ |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 5878 | .check_for_link = e1000_check_for_copper_link_ich8lan, |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5879 | /* cleanup_led dependent on mac type */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5880 | .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, |
| 5881 | .get_bus_info = e1000_get_bus_info_ich8lan, |
Bruce Allan | f4d2dd4 | 2010-01-13 02:05:18 +0000 | [diff] [blame] | 5882 | .set_lan_id = e1000_set_lan_id_single_port, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5883 | .get_link_up_info = e1000_get_link_up_info_ich8lan, |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5884 | /* led_on dependent on mac type */ |
| 5885 | /* led_off dependent on mac type */ |
Jeff Kirsher | e2de3eb | 2008-03-28 09:15:11 -0700 | [diff] [blame] | 5886 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5887 | .reset_hw = e1000_reset_hw_ich8lan, |
| 5888 | .init_hw = e1000_init_hw_ich8lan, |
| 5889 | .setup_link = e1000_setup_link_ich8lan, |
Bruce Allan | 55c5f55 | 2013-01-12 07:28:24 +0000 | [diff] [blame] | 5890 | .setup_physical_interface = e1000_setup_copper_link_ich8lan, |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5891 | /* id_led_init dependent on mac type */ |
Bruce Allan | 57cde76 | 2012-02-22 09:02:58 +0000 | [diff] [blame] | 5892 | .config_collision_dist = e1000e_config_collision_dist_generic, |
Bruce Allan | 69e1e01 | 2012-04-14 03:28:50 +0000 | [diff] [blame] | 5893 | .rar_set = e1000e_rar_set_generic, |
David Ertman | b3e5bf1 | 2014-05-06 03:50:17 +0000 | [diff] [blame] | 5894 | .rar_get_count = e1000e_rar_get_count_generic, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5895 | }; |
| 5896 | |
Jeff Kirsher | 8ce9d6c | 2011-09-24 13:23:52 +0000 | [diff] [blame] | 5897 | static const struct e1000_phy_operations ich8_phy_ops = { |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 5898 | .acquire = e1000_acquire_swflag_ich8lan, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5899 | .check_reset_block = e1000_check_reset_block_ich8lan, |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 5900 | .commit = NULL, |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 5901 | .get_cfg_done = e1000_get_cfg_done_ich8lan, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5902 | .get_cable_length = e1000e_get_cable_length_igp_2, |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 5903 | .read_reg = e1000e_read_phy_reg_igp, |
| 5904 | .release = e1000_release_swflag_ich8lan, |
| 5905 | .reset = e1000_phy_hw_reset_ich8lan, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5906 | .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, |
| 5907 | .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 5908 | .write_reg = e1000e_write_phy_reg_igp, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5909 | }; |
| 5910 | |
Jeff Kirsher | 8ce9d6c | 2011-09-24 13:23:52 +0000 | [diff] [blame] | 5911 | static const struct e1000_nvm_operations ich8_nvm_ops = { |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 5912 | .acquire = e1000_acquire_nvm_ich8lan, |
Bruce Allan | 55c5f55 | 2013-01-12 07:28:24 +0000 | [diff] [blame] | 5913 | .read = e1000_read_nvm_ich8lan, |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 5914 | .release = e1000_release_nvm_ich8lan, |
Bruce Allan | e85e363 | 2012-02-22 09:03:14 +0000 | [diff] [blame] | 5915 | .reload = e1000e_reload_nvm_generic, |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 5916 | .update = e1000_update_nvm_checksum_ich8lan, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5917 | .valid_led_default = e1000_valid_led_default_ich8lan, |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 5918 | .validate = e1000_validate_nvm_checksum_ich8lan, |
| 5919 | .write = e1000_write_nvm_ich8lan, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5920 | }; |
| 5921 | |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 5922 | static const struct e1000_nvm_operations spt_nvm_ops = { |
| 5923 | .acquire = e1000_acquire_nvm_ich8lan, |
| 5924 | .release = e1000_release_nvm_ich8lan, |
| 5925 | .read = e1000_read_nvm_spt, |
| 5926 | .update = e1000_update_nvm_checksum_spt, |
| 5927 | .reload = e1000e_reload_nvm_generic, |
| 5928 | .valid_led_default = e1000_valid_led_default_ich8lan, |
| 5929 | .validate = e1000_validate_nvm_checksum_ich8lan, |
| 5930 | .write = e1000_write_nvm_ich8lan, |
| 5931 | }; |
| 5932 | |
Jeff Kirsher | 8ce9d6c | 2011-09-24 13:23:52 +0000 | [diff] [blame] | 5933 | const struct e1000_info e1000_ich8_info = { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5934 | .mac = e1000_ich8lan, |
| 5935 | .flags = FLAG_HAS_WOL |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 5936 | | FLAG_IS_ICH |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5937 | | FLAG_HAS_CTRLEXT_ON_LOAD |
| 5938 | | FLAG_HAS_AMT |
| 5939 | | FLAG_HAS_FLASH |
| 5940 | | FLAG_APME_IN_WUC, |
| 5941 | .pba = 8, |
Alexander Duyck | 8084b86 | 2015-05-02 00:52:00 -0700 | [diff] [blame] | 5942 | .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN, |
Jeff Kirsher | 69e3fd8 | 2008-04-02 13:48:18 -0700 | [diff] [blame] | 5943 | .get_variants = e1000_get_variants_ich8lan, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5944 | .mac_ops = &ich8_mac_ops, |
| 5945 | .phy_ops = &ich8_phy_ops, |
| 5946 | .nvm_ops = &ich8_nvm_ops, |
| 5947 | }; |
| 5948 | |
Jeff Kirsher | 8ce9d6c | 2011-09-24 13:23:52 +0000 | [diff] [blame] | 5949 | const struct e1000_info e1000_ich9_info = { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5950 | .mac = e1000_ich9lan, |
| 5951 | .flags = FLAG_HAS_JUMBO_FRAMES |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 5952 | | FLAG_IS_ICH |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5953 | | FLAG_HAS_WOL |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5954 | | FLAG_HAS_CTRLEXT_ON_LOAD |
| 5955 | | FLAG_HAS_AMT |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5956 | | FLAG_HAS_FLASH |
| 5957 | | FLAG_APME_IN_WUC, |
Bruce Allan | 7f1557e | 2011-12-16 00:46:43 +0000 | [diff] [blame] | 5958 | .pba = 18, |
Bruce Allan | 2adc55c | 2009-06-02 11:28:58 +0000 | [diff] [blame] | 5959 | .max_hw_frame_size = DEFAULT_JUMBO, |
Jeff Kirsher | 69e3fd8 | 2008-04-02 13:48:18 -0700 | [diff] [blame] | 5960 | .get_variants = e1000_get_variants_ich8lan, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5961 | .mac_ops = &ich8_mac_ops, |
| 5962 | .phy_ops = &ich8_phy_ops, |
| 5963 | .nvm_ops = &ich8_nvm_ops, |
| 5964 | }; |
| 5965 | |
Jeff Kirsher | 8ce9d6c | 2011-09-24 13:23:52 +0000 | [diff] [blame] | 5966 | const struct e1000_info e1000_ich10_info = { |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 5967 | .mac = e1000_ich10lan, |
| 5968 | .flags = FLAG_HAS_JUMBO_FRAMES |
| 5969 | | FLAG_IS_ICH |
| 5970 | | FLAG_HAS_WOL |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 5971 | | FLAG_HAS_CTRLEXT_ON_LOAD |
| 5972 | | FLAG_HAS_AMT |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 5973 | | FLAG_HAS_FLASH |
| 5974 | | FLAG_APME_IN_WUC, |
Bruce Allan | 7f1557e | 2011-12-16 00:46:43 +0000 | [diff] [blame] | 5975 | .pba = 18, |
Bruce Allan | 2adc55c | 2009-06-02 11:28:58 +0000 | [diff] [blame] | 5976 | .max_hw_frame_size = DEFAULT_JUMBO, |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 5977 | .get_variants = e1000_get_variants_ich8lan, |
| 5978 | .mac_ops = &ich8_mac_ops, |
| 5979 | .phy_ops = &ich8_phy_ops, |
| 5980 | .nvm_ops = &ich8_nvm_ops, |
| 5981 | }; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5982 | |
Jeff Kirsher | 8ce9d6c | 2011-09-24 13:23:52 +0000 | [diff] [blame] | 5983 | const struct e1000_info e1000_pch_info = { |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5984 | .mac = e1000_pchlan, |
| 5985 | .flags = FLAG_IS_ICH |
| 5986 | | FLAG_HAS_WOL |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5987 | | FLAG_HAS_CTRLEXT_ON_LOAD |
| 5988 | | FLAG_HAS_AMT |
| 5989 | | FLAG_HAS_FLASH |
| 5990 | | FLAG_HAS_JUMBO_FRAMES |
Bruce Allan | 38eb394 | 2009-11-19 12:34:20 +0000 | [diff] [blame] | 5991 | | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5992 | | FLAG_APME_IN_WUC, |
Bruce Allan | 8c7bbb9 | 2010-06-16 13:26:41 +0000 | [diff] [blame] | 5993 | .flags2 = FLAG2_HAS_PHY_STATS, |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 5994 | .pba = 26, |
| 5995 | .max_hw_frame_size = 4096, |
| 5996 | .get_variants = e1000_get_variants_ich8lan, |
| 5997 | .mac_ops = &ich8_mac_ops, |
| 5998 | .phy_ops = &ich8_phy_ops, |
| 5999 | .nvm_ops = &ich8_nvm_ops, |
| 6000 | }; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 6001 | |
Jeff Kirsher | 8ce9d6c | 2011-09-24 13:23:52 +0000 | [diff] [blame] | 6002 | const struct e1000_info e1000_pch2_info = { |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 6003 | .mac = e1000_pch2lan, |
| 6004 | .flags = FLAG_IS_ICH |
| 6005 | | FLAG_HAS_WOL |
Bruce Allan | b67e191 | 2012-12-27 08:32:33 +0000 | [diff] [blame] | 6006 | | FLAG_HAS_HW_TIMESTAMP |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 6007 | | FLAG_HAS_CTRLEXT_ON_LOAD |
| 6008 | | FLAG_HAS_AMT |
| 6009 | | FLAG_HAS_FLASH |
| 6010 | | FLAG_HAS_JUMBO_FRAMES |
| 6011 | | FLAG_APME_IN_WUC, |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 6012 | .flags2 = FLAG2_HAS_PHY_STATS |
Jarod Wilson | 10ed1e0 | 2016-07-26 14:25:35 -0400 | [diff] [blame] | 6013 | | FLAG2_HAS_EEE |
| 6014 | | FLAG2_CHECK_SYSTIM_OVERFLOW, |
Bruce Allan | 828bac8 | 2010-09-29 21:39:37 +0000 | [diff] [blame] | 6015 | .pba = 26, |
Alexander Duyck | 8084b86 | 2015-05-02 00:52:00 -0700 | [diff] [blame] | 6016 | .max_hw_frame_size = 9022, |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 6017 | .get_variants = e1000_get_variants_ich8lan, |
| 6018 | .mac_ops = &ich8_mac_ops, |
| 6019 | .phy_ops = &ich8_phy_ops, |
| 6020 | .nvm_ops = &ich8_nvm_ops, |
| 6021 | }; |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 6022 | |
| 6023 | const struct e1000_info e1000_pch_lpt_info = { |
| 6024 | .mac = e1000_pch_lpt, |
| 6025 | .flags = FLAG_IS_ICH |
| 6026 | | FLAG_HAS_WOL |
Bruce Allan | b67e191 | 2012-12-27 08:32:33 +0000 | [diff] [blame] | 6027 | | FLAG_HAS_HW_TIMESTAMP |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 6028 | | FLAG_HAS_CTRLEXT_ON_LOAD |
| 6029 | | FLAG_HAS_AMT |
| 6030 | | FLAG_HAS_FLASH |
| 6031 | | FLAG_HAS_JUMBO_FRAMES |
| 6032 | | FLAG_APME_IN_WUC, |
| 6033 | .flags2 = FLAG2_HAS_PHY_STATS |
Jarod Wilson | 8037dd6 | 2016-07-26 14:25:35 -0400 | [diff] [blame] | 6034 | | FLAG2_HAS_EEE |
| 6035 | | FLAG2_CHECK_SYSTIM_OVERFLOW, |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 6036 | .pba = 26, |
Alexander Duyck | 8084b86 | 2015-05-02 00:52:00 -0700 | [diff] [blame] | 6037 | .max_hw_frame_size = 9022, |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 6038 | .get_variants = e1000_get_variants_ich8lan, |
| 6039 | .mac_ops = &ich8_mac_ops, |
| 6040 | .phy_ops = &ich8_phy_ops, |
| 6041 | .nvm_ops = &ich8_nvm_ops, |
| 6042 | }; |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 6043 | |
| 6044 | const struct e1000_info e1000_pch_spt_info = { |
| 6045 | .mac = e1000_pch_spt, |
| 6046 | .flags = FLAG_IS_ICH |
| 6047 | | FLAG_HAS_WOL |
| 6048 | | FLAG_HAS_HW_TIMESTAMP |
| 6049 | | FLAG_HAS_CTRLEXT_ON_LOAD |
| 6050 | | FLAG_HAS_AMT |
| 6051 | | FLAG_HAS_FLASH |
| 6052 | | FLAG_HAS_JUMBO_FRAMES |
| 6053 | | FLAG_APME_IN_WUC, |
| 6054 | .flags2 = FLAG2_HAS_PHY_STATS |
| 6055 | | FLAG2_HAS_EEE, |
| 6056 | .pba = 26, |
Alexander Duyck | 8084b86 | 2015-05-02 00:52:00 -0700 | [diff] [blame] | 6057 | .max_hw_frame_size = 9022, |
David Ertman | 79849eb | 2015-02-10 09:10:43 +0000 | [diff] [blame] | 6058 | .get_variants = e1000_get_variants_ich8lan, |
| 6059 | .mac_ops = &ich8_mac_ops, |
| 6060 | .phy_ops = &ich8_phy_ops, |
| 6061 | .nvm_ops = &spt_nvm_ops, |
| 6062 | }; |
Sasha Neftin | 3a3173b | 2017-04-06 10:26:32 +0300 | [diff] [blame] | 6063 | |
| 6064 | const struct e1000_info e1000_pch_cnp_info = { |
| 6065 | .mac = e1000_pch_cnp, |
| 6066 | .flags = FLAG_IS_ICH |
| 6067 | | FLAG_HAS_WOL |
| 6068 | | FLAG_HAS_HW_TIMESTAMP |
| 6069 | | FLAG_HAS_CTRLEXT_ON_LOAD |
| 6070 | | FLAG_HAS_AMT |
| 6071 | | FLAG_HAS_FLASH |
| 6072 | | FLAG_HAS_JUMBO_FRAMES |
| 6073 | | FLAG_APME_IN_WUC, |
| 6074 | .flags2 = FLAG2_HAS_PHY_STATS |
| 6075 | | FLAG2_HAS_EEE, |
| 6076 | .pba = 26, |
| 6077 | .max_hw_frame_size = 9022, |
| 6078 | .get_variants = e1000_get_variants_ich8lan, |
| 6079 | .mac_ops = &ich8_mac_ops, |
| 6080 | .phy_ops = &ich8_phy_ops, |
| 6081 | .nvm_ops = &spt_nvm_ops, |
| 6082 | }; |
Sasha Neftin | 280db5d | 2021-09-22 09:54:49 +0300 | [diff] [blame] | 6083 | |
| 6084 | const struct e1000_info e1000_pch_tgp_info = { |
| 6085 | .mac = e1000_pch_tgp, |
| 6086 | .flags = FLAG_IS_ICH |
| 6087 | | FLAG_HAS_WOL |
| 6088 | | FLAG_HAS_HW_TIMESTAMP |
| 6089 | | FLAG_HAS_CTRLEXT_ON_LOAD |
| 6090 | | FLAG_HAS_AMT |
| 6091 | | FLAG_HAS_FLASH |
| 6092 | | FLAG_HAS_JUMBO_FRAMES |
| 6093 | | FLAG_APME_IN_WUC, |
| 6094 | .flags2 = FLAG2_HAS_PHY_STATS |
| 6095 | | FLAG2_HAS_EEE, |
| 6096 | .pba = 26, |
| 6097 | .max_hw_frame_size = 9022, |
| 6098 | .get_variants = e1000_get_variants_ich8lan, |
| 6099 | .mac_ops = &ich8_mac_ops, |
| 6100 | .phy_ops = &ich8_phy_ops, |
| 6101 | .nvm_ops = &spt_nvm_ops, |
| 6102 | }; |
Sasha Neftin | 68defd5 | 2021-12-07 13:23:06 +0200 | [diff] [blame] | 6103 | |
| 6104 | const struct e1000_info e1000_pch_adp_info = { |
| 6105 | .mac = e1000_pch_adp, |
| 6106 | .flags = FLAG_IS_ICH |
| 6107 | | FLAG_HAS_WOL |
| 6108 | | FLAG_HAS_HW_TIMESTAMP |
| 6109 | | FLAG_HAS_CTRLEXT_ON_LOAD |
| 6110 | | FLAG_HAS_AMT |
| 6111 | | FLAG_HAS_FLASH |
| 6112 | | FLAG_HAS_JUMBO_FRAMES |
| 6113 | | FLAG_APME_IN_WUC, |
| 6114 | .flags2 = FLAG2_HAS_PHY_STATS |
| 6115 | | FLAG2_HAS_EEE, |
| 6116 | .pba = 26, |
| 6117 | .max_hw_frame_size = 9022, |
| 6118 | .get_variants = e1000_get_variants_ich8lan, |
| 6119 | .mac_ops = &ich8_mac_ops, |
| 6120 | .phy_ops = &ich8_phy_ops, |
| 6121 | .nvm_ops = &spt_nvm_ops, |
| 6122 | }; |
Sasha Neftin | db2d737 | 2022-07-26 17:36:25 +0300 | [diff] [blame] | 6123 | |
| 6124 | const struct e1000_info e1000_pch_mtp_info = { |
| 6125 | .mac = e1000_pch_mtp, |
| 6126 | .flags = FLAG_IS_ICH |
| 6127 | | FLAG_HAS_WOL |
| 6128 | | FLAG_HAS_HW_TIMESTAMP |
| 6129 | | FLAG_HAS_CTRLEXT_ON_LOAD |
| 6130 | | FLAG_HAS_AMT |
| 6131 | | FLAG_HAS_FLASH |
| 6132 | | FLAG_HAS_JUMBO_FRAMES |
| 6133 | | FLAG_APME_IN_WUC, |
| 6134 | .flags2 = FLAG2_HAS_PHY_STATS |
| 6135 | | FLAG2_HAS_EEE, |
| 6136 | .pba = 26, |
| 6137 | .max_hw_frame_size = 9022, |
| 6138 | .get_variants = e1000_get_variants_ich8lan, |
| 6139 | .mac_ops = &ich8_mac_ops, |
| 6140 | .phy_ops = &ich8_phy_ops, |
| 6141 | .nvm_ops = &spt_nvm_ops, |
| 6142 | }; |