Greg Kroah-Hartman | e3b3d0f | 2017-11-06 18:11:51 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 2 | /* |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 3 | * Application UART driver for: |
| 4 | * Freescale STMP37XX/STMP378X |
| 5 | * Alphascale ASM9260 |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 6 | * |
| 7 | * Author: dmitry pervushin <dimka@embeddedalley.com> |
| 8 | * |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 9 | * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de> |
| 10 | * Provide Alphascale ASM9260 support. |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 11 | * Copyright 2008-2010 Freescale Semiconductor, Inc. |
| 12 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <linux/kernel.h> |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 16 | #include <linux/errno.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/console.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/slab.h> |
| 22 | #include <linux/wait.h> |
| 23 | #include <linux/tty.h> |
| 24 | #include <linux/tty_driver.h> |
| 25 | #include <linux/tty_flip.h> |
| 26 | #include <linux/serial.h> |
| 27 | #include <linux/serial_core.h> |
| 28 | #include <linux/platform_device.h> |
| 29 | #include <linux/device.h> |
| 30 | #include <linux/clk.h> |
| 31 | #include <linux/delay.h> |
| 32 | #include <linux/io.h> |
Fabio Estevam | 1ea6607 | 2012-06-18 10:06:09 -0300 | [diff] [blame] | 33 | #include <linux/of_device.h> |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 34 | #include <linux/dma-mapping.h> |
Shawn Guo | bcc20f9 | 2013-02-26 13:47:41 +0800 | [diff] [blame] | 35 | #include <linux/dmaengine.h> |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 36 | |
| 37 | #include <asm/cacheflush.h> |
| 38 | |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 39 | #include <linux/gpio/consumer.h> |
Janusz Uzycki | 7c573d7 | 2014-10-10 18:53:25 +0200 | [diff] [blame] | 40 | #include <linux/err.h> |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 41 | #include <linux/irq.h> |
Janusz Uzycki | 7c573d7 | 2014-10-10 18:53:25 +0200 | [diff] [blame] | 42 | #include "serial_mctrl_gpio.h" |
| 43 | |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 44 | #define MXS_AUART_PORTS 5 |
Hector Palacios | 9987f76 | 2013-10-03 09:32:03 +0200 | [diff] [blame] | 45 | #define MXS_AUART_FIFO_SIZE 16 |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 46 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 47 | #define SET_REG 0x4 |
| 48 | #define CLR_REG 0x8 |
| 49 | #define TOG_REG 0xc |
| 50 | |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 51 | #define AUART_CTRL0 0x00000000 |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 52 | #define AUART_CTRL1 0x00000010 |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 53 | #define AUART_CTRL2 0x00000020 |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 54 | #define AUART_LINECTRL 0x00000030 |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 55 | #define AUART_LINECTRL2 0x00000040 |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 56 | #define AUART_INTR 0x00000050 |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 57 | #define AUART_DATA 0x00000060 |
| 58 | #define AUART_STAT 0x00000070 |
| 59 | #define AUART_DEBUG 0x00000080 |
| 60 | #define AUART_VERSION 0x00000090 |
| 61 | #define AUART_AUTOBAUD 0x000000a0 |
| 62 | |
| 63 | #define AUART_CTRL0_SFTRST (1 << 31) |
| 64 | #define AUART_CTRL0_CLKGATE (1 << 30) |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 65 | #define AUART_CTRL0_RXTO_ENABLE (1 << 27) |
| 66 | #define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16) |
| 67 | #define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff) |
| 68 | |
| 69 | #define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff) |
| 70 | |
| 71 | #define AUART_CTRL2_DMAONERR (1 << 26) |
| 72 | #define AUART_CTRL2_TXDMAE (1 << 25) |
| 73 | #define AUART_CTRL2_RXDMAE (1 << 24) |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 74 | |
| 75 | #define AUART_CTRL2_CTSEN (1 << 15) |
Huang Shijie | 0059202 | 2012-08-08 10:37:59 +0800 | [diff] [blame] | 76 | #define AUART_CTRL2_RTSEN (1 << 14) |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 77 | #define AUART_CTRL2_RTS (1 << 11) |
| 78 | #define AUART_CTRL2_RXE (1 << 9) |
| 79 | #define AUART_CTRL2_TXE (1 << 8) |
| 80 | #define AUART_CTRL2_UARTEN (1 << 0) |
| 81 | |
Stefan Wahren | df57cf6 | 2015-08-11 11:46:01 +0000 | [diff] [blame] | 82 | #define AUART_LINECTRL_BAUD_DIV_MAX 0x003fffc0 |
| 83 | #define AUART_LINECTRL_BAUD_DIV_MIN 0x000000ec |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 84 | #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16 |
| 85 | #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000 |
| 86 | #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16) |
| 87 | #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8 |
| 88 | #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00 |
| 89 | #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8) |
Wolfgang Ocker | f87fa71 | 2016-12-12 08:21:01 +0100 | [diff] [blame] | 90 | #define AUART_LINECTRL_SPS (1 << 7) |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 91 | #define AUART_LINECTRL_WLEN_MASK 0x00000060 |
| 92 | #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5) |
| 93 | #define AUART_LINECTRL_FEN (1 << 4) |
| 94 | #define AUART_LINECTRL_STP2 (1 << 3) |
| 95 | #define AUART_LINECTRL_EPS (1 << 2) |
| 96 | #define AUART_LINECTRL_PEN (1 << 1) |
| 97 | #define AUART_LINECTRL_BRK (1 << 0) |
| 98 | |
| 99 | #define AUART_INTR_RTIEN (1 << 22) |
| 100 | #define AUART_INTR_TXIEN (1 << 21) |
| 101 | #define AUART_INTR_RXIEN (1 << 20) |
| 102 | #define AUART_INTR_CTSMIEN (1 << 17) |
| 103 | #define AUART_INTR_RTIS (1 << 6) |
| 104 | #define AUART_INTR_TXIS (1 << 5) |
| 105 | #define AUART_INTR_RXIS (1 << 4) |
| 106 | #define AUART_INTR_CTSMIS (1 << 1) |
| 107 | |
| 108 | #define AUART_STAT_BUSY (1 << 29) |
| 109 | #define AUART_STAT_CTS (1 << 28) |
| 110 | #define AUART_STAT_TXFE (1 << 27) |
| 111 | #define AUART_STAT_TXFF (1 << 25) |
| 112 | #define AUART_STAT_RXFE (1 << 24) |
| 113 | #define AUART_STAT_OERR (1 << 19) |
| 114 | #define AUART_STAT_BERR (1 << 18) |
| 115 | #define AUART_STAT_PERR (1 << 17) |
| 116 | #define AUART_STAT_FERR (1 << 16) |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 117 | #define AUART_STAT_RXCOUNT_MASK 0xffff |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 118 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 119 | /* |
| 120 | * Start of Alphascale asm9260 defines |
| 121 | * This list contains only differences of existing bits |
| 122 | * between imx2x and asm9260 |
| 123 | */ |
| 124 | #define ASM9260_HW_CTRL0 0x0000 |
| 125 | /* |
| 126 | * RW. Tell the UART to execute the RX DMA Command. The |
| 127 | * UART will clear this bit at the end of receive execution. |
| 128 | */ |
| 129 | #define ASM9260_BM_CTRL0_RXDMA_RUN BIT(28) |
| 130 | /* RW. 0 use FIFO for status register; 1 use DMA */ |
| 131 | #define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS BIT(25) |
| 132 | /* |
| 133 | * RW. RX TIMEOUT Enable. Valid for FIFO and DMA. |
| 134 | * Warning: If this bit is set to 0, the RX timeout will not affect receive DMA |
| 135 | * operation. If this bit is set to 1, a receive timeout will cause the receive |
| 136 | * DMA logic to terminate by filling the remaining DMA bytes with garbage data. |
| 137 | */ |
| 138 | #define ASM9260_BM_CTRL0_RXTO_ENABLE BIT(24) |
| 139 | /* |
| 140 | * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before |
| 141 | * asserting timeout on the RX input. If the RXFIFO is not empty and the RX |
| 142 | * input is idle, then the watchdog counter will decrement each bit-time. Note |
| 143 | * 7-bit-time is added to the programmed value, so a value of zero will set |
| 144 | * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also |
| 145 | * note that the counter is reloaded at the end of each frame, so if the frame |
| 146 | * is 10 bits long and the timeout counter value is zero, then timeout will |
| 147 | * occur (when FIFO is not empty) even if the RX input is not idle. The default |
| 148 | * value is 0x3 (31 bit-time). |
| 149 | */ |
| 150 | #define ASM9260_BM_CTRL0_RXTO_MASK (0xff << 16) |
| 151 | /* TIMEOUT = (100*7+1)*(1/BAUD) */ |
| 152 | #define ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT (20 << 16) |
| 153 | |
| 154 | /* TX ctrl register */ |
| 155 | #define ASM9260_HW_CTRL1 0x0010 |
| 156 | /* |
| 157 | * RW. Tell the UART to execute the TX DMA Command. The |
| 158 | * UART will clear this bit at the end of transmit execution. |
| 159 | */ |
| 160 | #define ASM9260_BM_CTRL1_TXDMA_RUN BIT(28) |
| 161 | |
| 162 | #define ASM9260_HW_CTRL2 0x0020 |
| 163 | /* |
| 164 | * RW. Receive Interrupt FIFO Level Select. |
| 165 | * The trigger points for the receive interrupt are as follows: |
| 166 | * ONE_EIGHTHS = 0x0 Trigger on FIFO full to at least 2 of 16 entries. |
| 167 | * ONE_QUARTER = 0x1 Trigger on FIFO full to at least 4 of 16 entries. |
| 168 | * ONE_HALF = 0x2 Trigger on FIFO full to at least 8 of 16 entries. |
| 169 | * THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 12 of 16 entries. |
| 170 | * SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 14 of 16 entries. |
| 171 | */ |
| 172 | #define ASM9260_BM_CTRL2_RXIFLSEL (7 << 20) |
| 173 | #define ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL (3 << 20) |
| 174 | /* RW. Same as RXIFLSEL */ |
| 175 | #define ASM9260_BM_CTRL2_TXIFLSEL (7 << 16) |
| 176 | #define ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL (2 << 16) |
| 177 | /* RW. Set DTR. When this bit is 1, the output is 0. */ |
| 178 | #define ASM9260_BM_CTRL2_DTR BIT(10) |
| 179 | /* RW. Loop Back Enable */ |
| 180 | #define ASM9260_BM_CTRL2_LBE BIT(7) |
| 181 | #define ASM9260_BM_CTRL2_PORT_ENABLE BIT(0) |
| 182 | |
| 183 | #define ASM9260_HW_LINECTRL 0x0030 |
| 184 | /* |
| 185 | * RW. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the |
| 186 | * parity bit is transmitted and checked as a 0. When bits 1 and 7 are set, |
| 187 | * and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this |
| 188 | * bit is cleared stick parity is disabled. |
| 189 | */ |
| 190 | #define ASM9260_BM_LCTRL_SPS BIT(7) |
| 191 | /* RW. Word length */ |
| 192 | #define ASM9260_BM_LCTRL_WLEN (3 << 5) |
| 193 | #define ASM9260_BM_LCTRL_CHRL_5 (0 << 5) |
| 194 | #define ASM9260_BM_LCTRL_CHRL_6 (1 << 5) |
| 195 | #define ASM9260_BM_LCTRL_CHRL_7 (2 << 5) |
| 196 | #define ASM9260_BM_LCTRL_CHRL_8 (3 << 5) |
| 197 | |
| 198 | /* |
| 199 | * Interrupt register. |
| 200 | * contains the interrupt enables and the interrupt status bits |
| 201 | */ |
| 202 | #define ASM9260_HW_INTR 0x0040 |
| 203 | /* Tx FIFO EMPTY Raw Interrupt enable */ |
| 204 | #define ASM9260_BM_INTR_TFEIEN BIT(27) |
| 205 | /* Overrun Error Interrupt Enable. */ |
| 206 | #define ASM9260_BM_INTR_OEIEN BIT(26) |
| 207 | /* Break Error Interrupt Enable. */ |
| 208 | #define ASM9260_BM_INTR_BEIEN BIT(25) |
| 209 | /* Parity Error Interrupt Enable. */ |
| 210 | #define ASM9260_BM_INTR_PEIEN BIT(24) |
| 211 | /* Framing Error Interrupt Enable. */ |
| 212 | #define ASM9260_BM_INTR_FEIEN BIT(23) |
| 213 | |
| 214 | /* nUARTDSR Modem Interrupt Enable. */ |
| 215 | #define ASM9260_BM_INTR_DSRMIEN BIT(19) |
| 216 | /* nUARTDCD Modem Interrupt Enable. */ |
| 217 | #define ASM9260_BM_INTR_DCDMIEN BIT(18) |
| 218 | /* nUARTRI Modem Interrupt Enable. */ |
| 219 | #define ASM9260_BM_INTR_RIMIEN BIT(16) |
| 220 | /* Auto-Boud Timeout */ |
| 221 | #define ASM9260_BM_INTR_ABTO BIT(13) |
| 222 | #define ASM9260_BM_INTR_ABEO BIT(12) |
| 223 | /* Tx FIFO EMPTY Raw Interrupt state */ |
| 224 | #define ASM9260_BM_INTR_TFEIS BIT(11) |
| 225 | /* Overrun Error */ |
| 226 | #define ASM9260_BM_INTR_OEIS BIT(10) |
| 227 | /* Break Error */ |
| 228 | #define ASM9260_BM_INTR_BEIS BIT(9) |
| 229 | /* Parity Error */ |
| 230 | #define ASM9260_BM_INTR_PEIS BIT(8) |
| 231 | /* Framing Error */ |
| 232 | #define ASM9260_BM_INTR_FEIS BIT(7) |
| 233 | #define ASM9260_BM_INTR_DSRMIS BIT(3) |
| 234 | #define ASM9260_BM_INTR_DCDMIS BIT(2) |
| 235 | #define ASM9260_BM_INTR_RIMIS BIT(0) |
| 236 | |
| 237 | /* |
| 238 | * RW. In DMA mode, up to 4 Received/Transmit characters can be accessed at a |
| 239 | * time. In PIO mode, only one character can be accessed at a time. The status |
| 240 | * register contains the receive data flags and valid bits. |
| 241 | */ |
| 242 | #define ASM9260_HW_DATA 0x0050 |
| 243 | |
| 244 | #define ASM9260_HW_STAT 0x0060 |
| 245 | /* RO. If 1, UARTAPP is present in this product. */ |
| 246 | #define ASM9260_BM_STAT_PRESENT BIT(31) |
| 247 | /* RO. If 1, HISPEED is present in this product. */ |
| 248 | #define ASM9260_BM_STAT_HISPEED BIT(30) |
| 249 | /* RO. Receive FIFO Full. */ |
| 250 | #define ASM9260_BM_STAT_RXFULL BIT(26) |
| 251 | |
| 252 | /* RO. The UART Debug Register contains the state of the DMA signals. */ |
| 253 | #define ASM9260_HW_DEBUG 0x0070 |
| 254 | /* DMA Command Run Status */ |
| 255 | #define ASM9260_BM_DEBUG_TXDMARUN BIT(5) |
| 256 | #define ASM9260_BM_DEBUG_RXDMARUN BIT(4) |
| 257 | /* DMA Command End Status */ |
| 258 | #define ASM9260_BM_DEBUG_TXCMDEND BIT(3) |
| 259 | #define ASM9260_BM_DEBUG_RXCMDEND BIT(2) |
| 260 | /* DMA Request Status */ |
| 261 | #define ASM9260_BM_DEBUG_TXDMARQ BIT(1) |
| 262 | #define ASM9260_BM_DEBUG_RXDMARQ BIT(0) |
| 263 | |
| 264 | #define ASM9260_HW_ILPR 0x0080 |
| 265 | |
| 266 | #define ASM9260_HW_RS485CTRL 0x0090 |
| 267 | /* |
| 268 | * RW. This bit reverses the polarity of the direction control signal on the RTS |
| 269 | * (or DTR) pin. |
| 270 | * If 0, The direction control pin will be driven to logic ‘0’ when the |
| 271 | * transmitter has data to be sent. It will be driven to logic ‘1’ after the |
| 272 | * last bit of data has been transmitted. |
| 273 | */ |
| 274 | #define ASM9260_BM_RS485CTRL_ONIV BIT(5) |
| 275 | /* RW. Enable Auto Direction Control. */ |
| 276 | #define ASM9260_BM_RS485CTRL_DIR_CTRL BIT(4) |
| 277 | /* |
| 278 | * RW. If 0 and DIR_CTRL = 1, pin RTS is used for direction control. |
| 279 | * If 1 and DIR_CTRL = 1, pin DTR is used for direction control. |
| 280 | */ |
| 281 | #define ASM9260_BM_RS485CTRL_PINSEL BIT(3) |
| 282 | /* RW. Enable Auto Address Detect (AAD). */ |
| 283 | #define ASM9260_BM_RS485CTRL_AADEN BIT(2) |
| 284 | /* RW. Disable receiver. */ |
| 285 | #define ASM9260_BM_RS485CTRL_RXDIS BIT(1) |
| 286 | /* RW. Enable RS-485/EIA-485 Normal Multidrop Mode (NMM) */ |
| 287 | #define ASM9260_BM_RS485CTRL_RS485EN BIT(0) |
| 288 | |
| 289 | #define ASM9260_HW_RS485ADRMATCH 0x00a0 |
| 290 | /* Contains the address match value. */ |
| 291 | #define ASM9260_BM_RS485ADRMATCH_MASK (0xff << 0) |
| 292 | |
| 293 | #define ASM9260_HW_RS485DLY 0x00b0 |
| 294 | /* |
| 295 | * RW. Contains the direction control (RTS or DTR) delay value. This delay time |
| 296 | * is in periods of the baud clock. |
| 297 | */ |
| 298 | #define ASM9260_BM_RS485DLY_MASK (0xff << 0) |
| 299 | |
| 300 | #define ASM9260_HW_AUTOBAUD 0x00c0 |
| 301 | /* WO. Auto-baud time-out interrupt clear bit. */ |
| 302 | #define ASM9260_BM_AUTOBAUD_TO_INT_CLR BIT(9) |
| 303 | /* WO. End of auto-baud interrupt clear bit. */ |
| 304 | #define ASM9260_BM_AUTOBAUD_EO_INT_CLR BIT(8) |
| 305 | /* Restart in case of timeout (counter restarts at next UART Rx falling edge) */ |
| 306 | #define ASM9260_BM_AUTOBAUD_AUTORESTART BIT(2) |
| 307 | /* Auto-baud mode select bit. 0 - Mode 0, 1 - Mode 1. */ |
| 308 | #define ASM9260_BM_AUTOBAUD_MODE BIT(1) |
| 309 | /* |
| 310 | * Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is |
| 311 | * automatically cleared after auto-baud completion. |
| 312 | */ |
| 313 | #define ASM9260_BM_AUTOBAUD_START BIT(0) |
| 314 | |
| 315 | #define ASM9260_HW_CTRL3 0x00d0 |
| 316 | #define ASM9260_BM_CTRL3_OUTCLK_DIV_MASK (0xffff << 16) |
| 317 | /* |
| 318 | * RW. Provide clk over OUTCLK pin. In case of asm9260 it can be configured on |
| 319 | * pins 137 and 144. |
| 320 | */ |
| 321 | #define ASM9260_BM_CTRL3_MASTERMODE BIT(6) |
| 322 | /* RW. Baud Rate Mode: 1 - Enable sync mode. 0 - async mode. */ |
| 323 | #define ASM9260_BM_CTRL3_SYNCMODE BIT(4) |
| 324 | /* RW. 1 - MSB bit send frist; 0 - LSB bit frist. */ |
| 325 | #define ASM9260_BM_CTRL3_MSBF BIT(2) |
| 326 | /* RW. 1 - sample rate = 8 x Baudrate; 0 - sample rate = 16 x Baudrate. */ |
| 327 | #define ASM9260_BM_CTRL3_BAUD8 BIT(1) |
| 328 | /* RW. 1 - Set word length to 9bit. 0 - use ASM9260_BM_LCTRL_WLEN */ |
| 329 | #define ASM9260_BM_CTRL3_9BIT BIT(0) |
| 330 | |
| 331 | #define ASM9260_HW_ISO7816_CTRL 0x00e0 |
| 332 | /* RW. Enable High Speed mode. */ |
| 333 | #define ASM9260_BM_ISO7816CTRL_HS BIT(12) |
| 334 | /* Disable Successive Receive NACK */ |
| 335 | #define ASM9260_BM_ISO7816CTRL_DS_NACK BIT(8) |
| 336 | #define ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK (0xff << 4) |
| 337 | /* Receive NACK Inhibit */ |
| 338 | #define ASM9260_BM_ISO7816CTRL_INACK BIT(3) |
| 339 | #define ASM9260_BM_ISO7816CTRL_NEG_DATA BIT(2) |
| 340 | /* RW. 1 - ISO7816 mode; 0 - USART mode */ |
| 341 | #define ASM9260_BM_ISO7816CTRL_ENABLE BIT(0) |
| 342 | |
| 343 | #define ASM9260_HW_ISO7816_ERRCNT 0x00f0 |
| 344 | /* Parity error counter. Will be cleared after reading */ |
| 345 | #define ASM9260_BM_ISO7816_NB_ERRORS_MASK (0xff << 0) |
| 346 | |
| 347 | #define ASM9260_HW_ISO7816_STATUS 0x0100 |
| 348 | /* Max number of Repetitions Reached */ |
| 349 | #define ASM9260_BM_ISO7816_STAT_ITERATION BIT(0) |
| 350 | |
| 351 | /* End of Alphascale asm9260 defines */ |
| 352 | |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 353 | static struct uart_driver auart_driver; |
| 354 | |
Huang Shijie | f4b1f03b | 2012-11-16 16:03:52 +0800 | [diff] [blame] | 355 | enum mxs_auart_type { |
| 356 | IMX23_AUART, |
| 357 | IMX28_AUART, |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 358 | ASM9260_AUART, |
| 359 | }; |
| 360 | |
| 361 | struct vendor_data { |
| 362 | const u16 *reg_offset; |
| 363 | }; |
| 364 | |
| 365 | enum { |
| 366 | REG_CTRL0, |
| 367 | REG_CTRL1, |
| 368 | REG_CTRL2, |
| 369 | REG_LINECTRL, |
| 370 | REG_LINECTRL2, |
| 371 | REG_INTR, |
| 372 | REG_DATA, |
| 373 | REG_STAT, |
| 374 | REG_DEBUG, |
| 375 | REG_VERSION, |
| 376 | REG_AUTOBAUD, |
| 377 | |
| 378 | /* The size of the array - must be last */ |
| 379 | REG_ARRAY_SIZE, |
| 380 | }; |
| 381 | |
| 382 | static const u16 mxs_asm9260_offsets[REG_ARRAY_SIZE] = { |
| 383 | [REG_CTRL0] = ASM9260_HW_CTRL0, |
| 384 | [REG_CTRL1] = ASM9260_HW_CTRL1, |
| 385 | [REG_CTRL2] = ASM9260_HW_CTRL2, |
| 386 | [REG_LINECTRL] = ASM9260_HW_LINECTRL, |
| 387 | [REG_INTR] = ASM9260_HW_INTR, |
| 388 | [REG_DATA] = ASM9260_HW_DATA, |
| 389 | [REG_STAT] = ASM9260_HW_STAT, |
| 390 | [REG_DEBUG] = ASM9260_HW_DEBUG, |
| 391 | [REG_AUTOBAUD] = ASM9260_HW_AUTOBAUD, |
| 392 | }; |
| 393 | |
| 394 | static const u16 mxs_stmp37xx_offsets[REG_ARRAY_SIZE] = { |
| 395 | [REG_CTRL0] = AUART_CTRL0, |
| 396 | [REG_CTRL1] = AUART_CTRL1, |
| 397 | [REG_CTRL2] = AUART_CTRL2, |
| 398 | [REG_LINECTRL] = AUART_LINECTRL, |
| 399 | [REG_LINECTRL2] = AUART_LINECTRL2, |
| 400 | [REG_INTR] = AUART_INTR, |
| 401 | [REG_DATA] = AUART_DATA, |
| 402 | [REG_STAT] = AUART_STAT, |
| 403 | [REG_DEBUG] = AUART_DEBUG, |
| 404 | [REG_VERSION] = AUART_VERSION, |
| 405 | [REG_AUTOBAUD] = AUART_AUTOBAUD, |
| 406 | }; |
| 407 | |
| 408 | static const struct vendor_data vendor_alphascale_asm9260 = { |
| 409 | .reg_offset = mxs_asm9260_offsets, |
| 410 | }; |
| 411 | |
| 412 | static const struct vendor_data vendor_freescale_stmp37xx = { |
| 413 | .reg_offset = mxs_stmp37xx_offsets, |
Huang Shijie | f4b1f03b | 2012-11-16 16:03:52 +0800 | [diff] [blame] | 414 | }; |
| 415 | |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 416 | struct mxs_auart_port { |
| 417 | struct uart_port port; |
| 418 | |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 419 | #define MXS_AUART_DMA_ENABLED 0x2 |
| 420 | #define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */ |
| 421 | #define MXS_AUART_DMA_RX_READY 3 /* bit 3 */ |
Huang Shijie | 8418e67 | 2013-08-03 10:09:14 -0400 | [diff] [blame] | 422 | #define MXS_AUART_RTSCTS 4 /* bit 4 */ |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 423 | unsigned long flags; |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 424 | unsigned int mctrl_prev; |
Huang Shijie | f4b1f03b | 2012-11-16 16:03:52 +0800 | [diff] [blame] | 425 | enum mxs_auart_type devtype; |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 426 | const struct vendor_data *vendor; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 427 | |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 428 | struct clk *clk; |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 429 | struct clk *clk_ahb; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 430 | struct device *dev; |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 431 | |
| 432 | /* for DMA */ |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 433 | struct scatterlist tx_sgl; |
| 434 | struct dma_chan *tx_dma_chan; |
| 435 | void *tx_dma_buf; |
| 436 | |
| 437 | struct scatterlist rx_sgl; |
| 438 | struct dma_chan *rx_dma_chan; |
| 439 | void *rx_dma_buf; |
Janusz Uzycki | 7c573d7 | 2014-10-10 18:53:25 +0200 | [diff] [blame] | 440 | |
| 441 | struct mctrl_gpios *gpios; |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 442 | int gpio_irq[UART_GPIO_MAX]; |
| 443 | bool ms_irq_enabled; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 444 | }; |
| 445 | |
Krzysztof Kozlowski | 0cd4521 | 2015-05-02 00:40:03 +0900 | [diff] [blame] | 446 | static const struct platform_device_id mxs_auart_devtype[] = { |
Huang Shijie | f4b1f03b | 2012-11-16 16:03:52 +0800 | [diff] [blame] | 447 | { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART }, |
| 448 | { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART }, |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 449 | { .name = "as-auart-asm9260", .driver_data = ASM9260_AUART }, |
Huang Shijie | f4b1f03b | 2012-11-16 16:03:52 +0800 | [diff] [blame] | 450 | { /* sentinel */ } |
| 451 | }; |
| 452 | MODULE_DEVICE_TABLE(platform, mxs_auart_devtype); |
| 453 | |
Fabian Frederick | ed0bb23 | 2015-03-16 20:17:11 +0100 | [diff] [blame] | 454 | static const struct of_device_id mxs_auart_dt_ids[] = { |
Huang Shijie | f4b1f03b | 2012-11-16 16:03:52 +0800 | [diff] [blame] | 455 | { |
| 456 | .compatible = "fsl,imx28-auart", |
| 457 | .data = &mxs_auart_devtype[IMX28_AUART] |
| 458 | }, { |
| 459 | .compatible = "fsl,imx23-auart", |
| 460 | .data = &mxs_auart_devtype[IMX23_AUART] |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 461 | }, { |
| 462 | .compatible = "alphascale,asm9260-auart", |
| 463 | .data = &mxs_auart_devtype[ASM9260_AUART] |
Huang Shijie | f4b1f03b | 2012-11-16 16:03:52 +0800 | [diff] [blame] | 464 | }, { /* sentinel */ } |
| 465 | }; |
| 466 | MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids); |
| 467 | |
| 468 | static inline int is_imx28_auart(struct mxs_auart_port *s) |
| 469 | { |
| 470 | return s->devtype == IMX28_AUART; |
| 471 | } |
| 472 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 473 | static inline int is_asm9260_auart(struct mxs_auart_port *s) |
| 474 | { |
| 475 | return s->devtype == ASM9260_AUART; |
| 476 | } |
| 477 | |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 478 | static inline bool auart_dma_enabled(struct mxs_auart_port *s) |
| 479 | { |
| 480 | return s->flags & MXS_AUART_DMA_ENABLED; |
| 481 | } |
| 482 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 483 | static unsigned int mxs_reg_to_offset(const struct mxs_auart_port *uap, |
| 484 | unsigned int reg) |
| 485 | { |
| 486 | return uap->vendor->reg_offset[reg]; |
| 487 | } |
| 488 | |
| 489 | static unsigned int mxs_read(const struct mxs_auart_port *uap, |
| 490 | unsigned int reg) |
| 491 | { |
| 492 | void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); |
| 493 | |
| 494 | return readl_relaxed(addr); |
| 495 | } |
| 496 | |
| 497 | static void mxs_write(unsigned int val, struct mxs_auart_port *uap, |
| 498 | unsigned int reg) |
| 499 | { |
| 500 | void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); |
| 501 | |
| 502 | writel_relaxed(val, addr); |
| 503 | } |
| 504 | |
| 505 | static void mxs_set(unsigned int val, struct mxs_auart_port *uap, |
| 506 | unsigned int reg) |
| 507 | { |
| 508 | void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); |
| 509 | |
| 510 | writel_relaxed(val, addr + SET_REG); |
| 511 | } |
| 512 | |
| 513 | static void mxs_clr(unsigned int val, struct mxs_auart_port *uap, |
| 514 | unsigned int reg) |
| 515 | { |
| 516 | void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); |
| 517 | |
| 518 | writel_relaxed(val, addr + CLR_REG); |
| 519 | } |
| 520 | |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 521 | static void mxs_auart_stop_tx(struct uart_port *u); |
| 522 | |
| 523 | #define to_auart_port(u) container_of(u, struct mxs_auart_port, port) |
| 524 | |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 525 | static void mxs_auart_tx_chars(struct mxs_auart_port *s); |
| 526 | |
| 527 | static void dma_tx_callback(void *param) |
| 528 | { |
| 529 | struct mxs_auart_port *s = param; |
| 530 | struct circ_buf *xmit = &s->port.state->xmit; |
| 531 | |
| 532 | dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE); |
| 533 | |
| 534 | /* clear the bit used to serialize the DMA tx. */ |
| 535 | clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); |
Peter Zijlstra | 4e857c5 | 2014-03-17 18:06:10 +0100 | [diff] [blame] | 536 | smp_mb__after_atomic(); |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 537 | |
| 538 | /* wake up the possible processes. */ |
| 539 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
| 540 | uart_write_wakeup(&s->port); |
| 541 | |
| 542 | mxs_auart_tx_chars(s); |
| 543 | } |
| 544 | |
| 545 | static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size) |
| 546 | { |
| 547 | struct dma_async_tx_descriptor *desc; |
| 548 | struct scatterlist *sgl = &s->tx_sgl; |
| 549 | struct dma_chan *channel = s->tx_dma_chan; |
| 550 | u32 pio; |
| 551 | |
| 552 | /* [1] : send PIO. Note, the first pio word is CTRL1. */ |
| 553 | pio = AUART_CTRL1_XFER_COUNT(size); |
| 554 | desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio, |
| 555 | 1, DMA_TRANS_NONE, 0); |
| 556 | if (!desc) { |
| 557 | dev_err(s->dev, "step 1 error\n"); |
| 558 | return -EINVAL; |
| 559 | } |
| 560 | |
| 561 | /* [2] : set DMA buffer. */ |
| 562 | sg_init_one(sgl, s->tx_dma_buf, size); |
| 563 | dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE); |
| 564 | desc = dmaengine_prep_slave_sg(channel, sgl, |
| 565 | 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 566 | if (!desc) { |
| 567 | dev_err(s->dev, "step 2 error\n"); |
| 568 | return -EINVAL; |
| 569 | } |
| 570 | |
| 571 | /* [3] : submit the DMA */ |
| 572 | desc->callback = dma_tx_callback; |
| 573 | desc->callback_param = s; |
| 574 | dmaengine_submit(desc); |
| 575 | dma_async_issue_pending(channel); |
| 576 | return 0; |
| 577 | } |
| 578 | |
| 579 | static void mxs_auart_tx_chars(struct mxs_auart_port *s) |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 580 | { |
| 581 | struct circ_buf *xmit = &s->port.state->xmit; |
| 582 | |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 583 | if (auart_dma_enabled(s)) { |
fabio.estevam@freescale.com | 87b8bed | 2013-01-07 23:11:06 -0200 | [diff] [blame] | 584 | u32 i = 0; |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 585 | int size; |
| 586 | void *buffer = s->tx_dma_buf; |
| 587 | |
| 588 | if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags)) |
| 589 | return; |
| 590 | |
| 591 | while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { |
| 592 | size = min_t(u32, UART_XMIT_SIZE - i, |
| 593 | CIRC_CNT_TO_END(xmit->head, |
| 594 | xmit->tail, |
| 595 | UART_XMIT_SIZE)); |
| 596 | memcpy(buffer + i, xmit->buf + xmit->tail, size); |
| 597 | xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1); |
| 598 | |
| 599 | i += size; |
| 600 | if (i >= UART_XMIT_SIZE) |
| 601 | break; |
| 602 | } |
| 603 | |
| 604 | if (uart_tx_stopped(&s->port)) |
| 605 | mxs_auart_stop_tx(&s->port); |
| 606 | |
| 607 | if (i) { |
| 608 | mxs_auart_dma_tx(s, i); |
| 609 | } else { |
| 610 | clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); |
Peter Zijlstra | 4e857c5 | 2014-03-17 18:06:10 +0100 | [diff] [blame] | 611 | smp_mb__after_atomic(); |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 612 | } |
| 613 | return; |
| 614 | } |
| 615 | |
| 616 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 617 | while (!(mxs_read(s, REG_STAT) & AUART_STAT_TXFF)) { |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 618 | if (s->port.x_char) { |
| 619 | s->port.icount.tx++; |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 620 | mxs_write(s->port.x_char, s, REG_DATA); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 621 | s->port.x_char = 0; |
| 622 | continue; |
| 623 | } |
| 624 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { |
| 625 | s->port.icount.tx++; |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 626 | mxs_write(xmit->buf[xmit->tail], s, REG_DATA); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 627 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 628 | } else |
| 629 | break; |
| 630 | } |
Uwe Kleine-König | d0758a2 | 2011-11-22 14:22:56 +0100 | [diff] [blame] | 631 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
| 632 | uart_write_wakeup(&s->port); |
| 633 | |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 634 | if (uart_circ_empty(&(s->port.state->xmit))) |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 635 | mxs_clr(AUART_INTR_TXIEN, s, REG_INTR); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 636 | else |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 637 | mxs_set(AUART_INTR_TXIEN, s, REG_INTR); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 638 | |
| 639 | if (uart_tx_stopped(&s->port)) |
| 640 | mxs_auart_stop_tx(&s->port); |
| 641 | } |
| 642 | |
| 643 | static void mxs_auart_rx_char(struct mxs_auart_port *s) |
| 644 | { |
| 645 | int flag; |
| 646 | u32 stat; |
| 647 | u8 c; |
| 648 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 649 | c = mxs_read(s, REG_DATA); |
| 650 | stat = mxs_read(s, REG_STAT); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 651 | |
| 652 | flag = TTY_NORMAL; |
| 653 | s->port.icount.rx++; |
| 654 | |
| 655 | if (stat & AUART_STAT_BERR) { |
| 656 | s->port.icount.brk++; |
| 657 | if (uart_handle_break(&s->port)) |
| 658 | goto out; |
| 659 | } else if (stat & AUART_STAT_PERR) { |
| 660 | s->port.icount.parity++; |
| 661 | } else if (stat & AUART_STAT_FERR) { |
| 662 | s->port.icount.frame++; |
| 663 | } |
| 664 | |
| 665 | /* |
| 666 | * Mask off conditions which should be ingored. |
| 667 | */ |
| 668 | stat &= s->port.read_status_mask; |
| 669 | |
| 670 | if (stat & AUART_STAT_BERR) { |
| 671 | flag = TTY_BREAK; |
| 672 | } else if (stat & AUART_STAT_PERR) |
| 673 | flag = TTY_PARITY; |
| 674 | else if (stat & AUART_STAT_FERR) |
| 675 | flag = TTY_FRAME; |
| 676 | |
| 677 | if (stat & AUART_STAT_OERR) |
| 678 | s->port.icount.overrun++; |
| 679 | |
| 680 | if (uart_handle_sysrq_char(&s->port, c)) |
| 681 | goto out; |
| 682 | |
| 683 | uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag); |
| 684 | out: |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 685 | mxs_write(stat, s, REG_STAT); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 686 | } |
| 687 | |
| 688 | static void mxs_auart_rx_chars(struct mxs_auart_port *s) |
| 689 | { |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 690 | u32 stat = 0; |
| 691 | |
| 692 | for (;;) { |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 693 | stat = mxs_read(s, REG_STAT); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 694 | if (stat & AUART_STAT_RXFE) |
| 695 | break; |
| 696 | mxs_auart_rx_char(s); |
| 697 | } |
| 698 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 699 | mxs_write(stat, s, REG_STAT); |
Jiri Slaby | 2e124b4 | 2013-01-03 15:53:06 +0100 | [diff] [blame] | 700 | tty_flip_buffer_push(&s->port.state->port); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 701 | } |
| 702 | |
| 703 | static int mxs_auart_request_port(struct uart_port *u) |
| 704 | { |
| 705 | return 0; |
| 706 | } |
| 707 | |
| 708 | static int mxs_auart_verify_port(struct uart_port *u, |
| 709 | struct serial_struct *ser) |
| 710 | { |
| 711 | if (u->type != PORT_UNKNOWN && u->type != PORT_IMX) |
| 712 | return -EINVAL; |
| 713 | return 0; |
| 714 | } |
| 715 | |
| 716 | static void mxs_auart_config_port(struct uart_port *u, int flags) |
| 717 | { |
| 718 | } |
| 719 | |
| 720 | static const char *mxs_auart_type(struct uart_port *u) |
| 721 | { |
| 722 | struct mxs_auart_port *s = to_auart_port(u); |
| 723 | |
| 724 | return dev_name(s->dev); |
| 725 | } |
| 726 | |
| 727 | static void mxs_auart_release_port(struct uart_port *u) |
| 728 | { |
| 729 | } |
| 730 | |
| 731 | static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl) |
| 732 | { |
Janusz Uzycki | 7c573d7 | 2014-10-10 18:53:25 +0200 | [diff] [blame] | 733 | struct mxs_auart_port *s = to_auart_port(u); |
| 734 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 735 | u32 ctrl = mxs_read(s, REG_CTRL2); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 736 | |
Steffen Trumtrar | a683321 | 2012-12-13 14:27:43 +0100 | [diff] [blame] | 737 | ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS); |
Huang Shijie | 0059202 | 2012-08-08 10:37:59 +0800 | [diff] [blame] | 738 | if (mctrl & TIOCM_RTS) { |
Peter Hurley | 299245a | 2014-09-10 15:06:24 -0400 | [diff] [blame] | 739 | if (uart_cts_enabled(u)) |
Huang Shijie | 0059202 | 2012-08-08 10:37:59 +0800 | [diff] [blame] | 740 | ctrl |= AUART_CTRL2_RTSEN; |
Steffen Trumtrar | a683321 | 2012-12-13 14:27:43 +0100 | [diff] [blame] | 741 | else |
| 742 | ctrl |= AUART_CTRL2_RTS; |
Huang Shijie | 0059202 | 2012-08-08 10:37:59 +0800 | [diff] [blame] | 743 | } |
| 744 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 745 | mxs_write(ctrl, s, REG_CTRL2); |
Janusz Uzycki | 7c573d7 | 2014-10-10 18:53:25 +0200 | [diff] [blame] | 746 | |
| 747 | mctrl_gpio_set(s->gpios, mctrl); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 748 | } |
| 749 | |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 750 | #define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS) |
| 751 | static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl) |
| 752 | { |
| 753 | u32 mctrl_diff; |
| 754 | |
| 755 | mctrl_diff = mctrl ^ s->mctrl_prev; |
| 756 | s->mctrl_prev = mctrl; |
| 757 | if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled && |
| 758 | s->port.state != NULL) { |
| 759 | if (mctrl_diff & TIOCM_RI) |
| 760 | s->port.icount.rng++; |
| 761 | if (mctrl_diff & TIOCM_DSR) |
| 762 | s->port.icount.dsr++; |
| 763 | if (mctrl_diff & TIOCM_CD) |
| 764 | uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD); |
| 765 | if (mctrl_diff & TIOCM_CTS) |
| 766 | uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS); |
| 767 | |
| 768 | wake_up_interruptible(&s->port.state->port.delta_msr_wait); |
| 769 | } |
| 770 | return mctrl; |
| 771 | } |
| 772 | |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 773 | static u32 mxs_auart_get_mctrl(struct uart_port *u) |
| 774 | { |
Janusz Uzycki | 7c573d7 | 2014-10-10 18:53:25 +0200 | [diff] [blame] | 775 | struct mxs_auart_port *s = to_auart_port(u); |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 776 | u32 stat = mxs_read(s, REG_STAT); |
Janusz Uzycki | 42b4eba | 2014-10-10 18:53:24 +0200 | [diff] [blame] | 777 | u32 mctrl = 0; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 778 | |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 779 | if (stat & AUART_STAT_CTS) |
| 780 | mctrl |= TIOCM_CTS; |
| 781 | |
Janusz Uzycki | 7c573d7 | 2014-10-10 18:53:25 +0200 | [diff] [blame] | 782 | return mctrl_gpio_get(s->gpios, &mctrl); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 783 | } |
| 784 | |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 785 | /* |
| 786 | * Enable modem status interrupts |
| 787 | */ |
| 788 | static void mxs_auart_enable_ms(struct uart_port *port) |
| 789 | { |
| 790 | struct mxs_auart_port *s = to_auart_port(port); |
| 791 | |
| 792 | /* |
| 793 | * Interrupt should not be enabled twice |
| 794 | */ |
| 795 | if (s->ms_irq_enabled) |
| 796 | return; |
| 797 | |
| 798 | s->ms_irq_enabled = true; |
| 799 | |
| 800 | if (s->gpio_irq[UART_GPIO_CTS] >= 0) |
| 801 | enable_irq(s->gpio_irq[UART_GPIO_CTS]); |
| 802 | /* TODO: enable AUART_INTR_CTSMIEN otherwise */ |
| 803 | |
| 804 | if (s->gpio_irq[UART_GPIO_DSR] >= 0) |
| 805 | enable_irq(s->gpio_irq[UART_GPIO_DSR]); |
| 806 | |
| 807 | if (s->gpio_irq[UART_GPIO_RI] >= 0) |
| 808 | enable_irq(s->gpio_irq[UART_GPIO_RI]); |
| 809 | |
| 810 | if (s->gpio_irq[UART_GPIO_DCD] >= 0) |
| 811 | enable_irq(s->gpio_irq[UART_GPIO_DCD]); |
| 812 | } |
| 813 | |
| 814 | /* |
| 815 | * Disable modem status interrupts |
| 816 | */ |
| 817 | static void mxs_auart_disable_ms(struct uart_port *port) |
| 818 | { |
| 819 | struct mxs_auart_port *s = to_auart_port(port); |
| 820 | |
| 821 | /* |
| 822 | * Interrupt should not be disabled twice |
| 823 | */ |
| 824 | if (!s->ms_irq_enabled) |
| 825 | return; |
| 826 | |
| 827 | s->ms_irq_enabled = false; |
| 828 | |
| 829 | if (s->gpio_irq[UART_GPIO_CTS] >= 0) |
| 830 | disable_irq(s->gpio_irq[UART_GPIO_CTS]); |
| 831 | /* TODO: disable AUART_INTR_CTSMIEN otherwise */ |
| 832 | |
| 833 | if (s->gpio_irq[UART_GPIO_DSR] >= 0) |
| 834 | disable_irq(s->gpio_irq[UART_GPIO_DSR]); |
| 835 | |
| 836 | if (s->gpio_irq[UART_GPIO_RI] >= 0) |
| 837 | disable_irq(s->gpio_irq[UART_GPIO_RI]); |
| 838 | |
| 839 | if (s->gpio_irq[UART_GPIO_DCD] >= 0) |
| 840 | disable_irq(s->gpio_irq[UART_GPIO_DCD]); |
| 841 | } |
| 842 | |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 843 | static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s); |
| 844 | static void dma_rx_callback(void *arg) |
| 845 | { |
| 846 | struct mxs_auart_port *s = (struct mxs_auart_port *) arg; |
Jiri Slaby | 05c7cd3 | 2013-01-03 15:53:04 +0100 | [diff] [blame] | 847 | struct tty_port *port = &s->port.state->port; |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 848 | int count; |
| 849 | u32 stat; |
| 850 | |
Huang Shijie | d7ffb93 | 2012-11-22 15:06:30 +0800 | [diff] [blame] | 851 | dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE); |
| 852 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 853 | stat = mxs_read(s, REG_STAT); |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 854 | stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR | |
| 855 | AUART_STAT_PERR | AUART_STAT_FERR); |
| 856 | |
| 857 | count = stat & AUART_STAT_RXCOUNT_MASK; |
Jiri Slaby | 05c7cd3 | 2013-01-03 15:53:04 +0100 | [diff] [blame] | 858 | tty_insert_flip_string(port, s->rx_dma_buf, count); |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 859 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 860 | mxs_write(stat, s, REG_STAT); |
Jiri Slaby | 2e124b4 | 2013-01-03 15:53:06 +0100 | [diff] [blame] | 861 | tty_flip_buffer_push(port); |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 862 | |
| 863 | /* start the next DMA for RX. */ |
| 864 | mxs_auart_dma_prep_rx(s); |
| 865 | } |
| 866 | |
| 867 | static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s) |
| 868 | { |
| 869 | struct dma_async_tx_descriptor *desc; |
| 870 | struct scatterlist *sgl = &s->rx_sgl; |
| 871 | struct dma_chan *channel = s->rx_dma_chan; |
| 872 | u32 pio[1]; |
| 873 | |
| 874 | /* [1] : send PIO */ |
| 875 | pio[0] = AUART_CTRL0_RXTO_ENABLE |
| 876 | | AUART_CTRL0_RXTIMEOUT(0x80) |
| 877 | | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE); |
| 878 | desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio, |
| 879 | 1, DMA_TRANS_NONE, 0); |
| 880 | if (!desc) { |
| 881 | dev_err(s->dev, "step 1 error\n"); |
| 882 | return -EINVAL; |
| 883 | } |
| 884 | |
| 885 | /* [2] : send DMA request */ |
| 886 | sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE); |
| 887 | dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE); |
| 888 | desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM, |
| 889 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 890 | if (!desc) { |
| 891 | dev_err(s->dev, "step 2 error\n"); |
| 892 | return -1; |
| 893 | } |
| 894 | |
| 895 | /* [3] : submit the DMA, but do not issue it. */ |
| 896 | desc->callback = dma_rx_callback; |
| 897 | desc->callback_param = s; |
| 898 | dmaengine_submit(desc); |
| 899 | dma_async_issue_pending(channel); |
| 900 | return 0; |
| 901 | } |
| 902 | |
| 903 | static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s) |
| 904 | { |
| 905 | if (s->tx_dma_chan) { |
| 906 | dma_release_channel(s->tx_dma_chan); |
| 907 | s->tx_dma_chan = NULL; |
| 908 | } |
| 909 | if (s->rx_dma_chan) { |
| 910 | dma_release_channel(s->rx_dma_chan); |
| 911 | s->rx_dma_chan = NULL; |
| 912 | } |
| 913 | |
| 914 | kfree(s->tx_dma_buf); |
| 915 | kfree(s->rx_dma_buf); |
| 916 | s->tx_dma_buf = NULL; |
| 917 | s->rx_dma_buf = NULL; |
| 918 | } |
| 919 | |
| 920 | static void mxs_auart_dma_exit(struct mxs_auart_port *s) |
| 921 | { |
| 922 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 923 | mxs_clr(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR, |
| 924 | s, REG_CTRL2); |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 925 | |
| 926 | mxs_auart_dma_exit_channel(s); |
| 927 | s->flags &= ~MXS_AUART_DMA_ENABLED; |
| 928 | clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); |
| 929 | clear_bit(MXS_AUART_DMA_RX_READY, &s->flags); |
| 930 | } |
| 931 | |
| 932 | static int mxs_auart_dma_init(struct mxs_auart_port *s) |
| 933 | { |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 934 | if (auart_dma_enabled(s)) |
| 935 | return 0; |
| 936 | |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 937 | /* init for RX */ |
Shawn Guo | bcc20f9 | 2013-02-26 13:47:41 +0800 | [diff] [blame] | 938 | s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx"); |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 939 | if (!s->rx_dma_chan) |
| 940 | goto err_out; |
| 941 | s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA); |
| 942 | if (!s->rx_dma_buf) |
| 943 | goto err_out; |
| 944 | |
| 945 | /* init for TX */ |
Shawn Guo | bcc20f9 | 2013-02-26 13:47:41 +0800 | [diff] [blame] | 946 | s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx"); |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 947 | if (!s->tx_dma_chan) |
| 948 | goto err_out; |
| 949 | s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA); |
| 950 | if (!s->tx_dma_buf) |
| 951 | goto err_out; |
| 952 | |
| 953 | /* set the flags */ |
| 954 | s->flags |= MXS_AUART_DMA_ENABLED; |
| 955 | dev_dbg(s->dev, "enabled the DMA support."); |
| 956 | |
Hector Palacios | 9987f76 | 2013-10-03 09:32:03 +0200 | [diff] [blame] | 957 | /* The DMA buffer is now the FIFO the TTY subsystem can use */ |
| 958 | s->port.fifosize = UART_XMIT_SIZE; |
| 959 | |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 960 | return 0; |
| 961 | |
| 962 | err_out: |
| 963 | mxs_auart_dma_exit_channel(s); |
| 964 | return -EINVAL; |
| 965 | |
| 966 | } |
| 967 | |
Geert Uytterhoeven | 6cbdf5c | 2019-08-14 11:29:23 +0200 | [diff] [blame] | 968 | #define RTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_RTS) |
| 969 | #define CTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_CTS) |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 970 | static void mxs_auart_settermios(struct uart_port *u, |
| 971 | struct ktermios *termios, |
| 972 | struct ktermios *old) |
| 973 | { |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 974 | struct mxs_auart_port *s = to_auart_port(u); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 975 | u32 bm, ctrl, ctrl2, div; |
Stefan Wahren | df57cf6 | 2015-08-11 11:46:01 +0000 | [diff] [blame] | 976 | unsigned int cflag, baud, baud_min, baud_max; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 977 | |
| 978 | cflag = termios->c_cflag; |
| 979 | |
| 980 | ctrl = AUART_LINECTRL_FEN; |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 981 | ctrl2 = mxs_read(s, REG_CTRL2); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 982 | |
| 983 | /* byte size */ |
| 984 | switch (cflag & CSIZE) { |
| 985 | case CS5: |
| 986 | bm = 0; |
| 987 | break; |
| 988 | case CS6: |
| 989 | bm = 1; |
| 990 | break; |
| 991 | case CS7: |
| 992 | bm = 2; |
| 993 | break; |
| 994 | case CS8: |
| 995 | bm = 3; |
| 996 | break; |
| 997 | default: |
| 998 | return; |
| 999 | } |
| 1000 | |
| 1001 | ctrl |= AUART_LINECTRL_WLEN(bm); |
| 1002 | |
| 1003 | /* parity */ |
| 1004 | if (cflag & PARENB) { |
| 1005 | ctrl |= AUART_LINECTRL_PEN; |
| 1006 | if ((cflag & PARODD) == 0) |
| 1007 | ctrl |= AUART_LINECTRL_EPS; |
Wolfgang Ocker | f87fa71 | 2016-12-12 08:21:01 +0100 | [diff] [blame] | 1008 | if (cflag & CMSPAR) |
| 1009 | ctrl |= AUART_LINECTRL_SPS; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1010 | } |
| 1011 | |
Wolfgang Ocker | b810645 | 2016-11-16 12:37:45 +0100 | [diff] [blame] | 1012 | u->read_status_mask = AUART_STAT_OERR; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1013 | |
| 1014 | if (termios->c_iflag & INPCK) |
| 1015 | u->read_status_mask |= AUART_STAT_PERR; |
Peter Hurley | ef8b9dd | 2014-06-16 08:10:41 -0400 | [diff] [blame] | 1016 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1017 | u->read_status_mask |= AUART_STAT_BERR; |
| 1018 | |
| 1019 | /* |
| 1020 | * Characters to ignore |
| 1021 | */ |
| 1022 | u->ignore_status_mask = 0; |
| 1023 | if (termios->c_iflag & IGNPAR) |
| 1024 | u->ignore_status_mask |= AUART_STAT_PERR; |
| 1025 | if (termios->c_iflag & IGNBRK) { |
| 1026 | u->ignore_status_mask |= AUART_STAT_BERR; |
| 1027 | /* |
| 1028 | * If we're ignoring parity and break indicators, |
| 1029 | * ignore overruns too (for real raw support). |
| 1030 | */ |
| 1031 | if (termios->c_iflag & IGNPAR) |
| 1032 | u->ignore_status_mask |= AUART_STAT_OERR; |
| 1033 | } |
| 1034 | |
| 1035 | /* |
| 1036 | * ignore all characters if CREAD is not set |
| 1037 | */ |
| 1038 | if (cflag & CREAD) |
| 1039 | ctrl2 |= AUART_CTRL2_RXE; |
| 1040 | else |
| 1041 | ctrl2 &= ~AUART_CTRL2_RXE; |
| 1042 | |
| 1043 | /* figure out the stop bits requested */ |
| 1044 | if (cflag & CSTOPB) |
| 1045 | ctrl |= AUART_LINECTRL_STP2; |
| 1046 | |
| 1047 | /* figure out the hardware flow control settings */ |
Janusz Uzycki | 7c573d7 | 2014-10-10 18:53:25 +0200 | [diff] [blame] | 1048 | ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN); |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 1049 | if (cflag & CRTSCTS) { |
| 1050 | /* |
| 1051 | * The DMA has a bug(see errata:2836) in mx23. |
| 1052 | * So we can not implement the DMA for auart in mx23, |
| 1053 | * we can only implement the DMA support for auart |
| 1054 | * in mx28. |
| 1055 | */ |
Huang Shijie | afab220 | 2013-08-03 10:09:15 -0400 | [diff] [blame] | 1056 | if (is_imx28_auart(s) |
Huang Shijie | 8418e67 | 2013-08-03 10:09:14 -0400 | [diff] [blame] | 1057 | && test_bit(MXS_AUART_RTSCTS, &s->flags)) { |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 1058 | if (!mxs_auart_dma_init(s)) |
| 1059 | /* enable DMA tranfer */ |
| 1060 | ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE |
| 1061 | | AUART_CTRL2_DMAONERR; |
| 1062 | } |
Janusz Uzycki | 7c573d7 | 2014-10-10 18:53:25 +0200 | [diff] [blame] | 1063 | /* Even if RTS is GPIO line RTSEN can be enabled because |
| 1064 | * the pinctrl configuration decides about RTS pin function */ |
| 1065 | ctrl2 |= AUART_CTRL2_RTSEN; |
| 1066 | if (CTS_AT_AUART()) |
| 1067 | ctrl2 |= AUART_CTRL2_CTSEN; |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 1068 | } |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1069 | |
| 1070 | /* set baud rate */ |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1071 | if (is_asm9260_auart(s)) { |
| 1072 | baud = uart_get_baud_rate(u, termios, old, |
| 1073 | u->uartclk * 4 / 0x3FFFFF, |
| 1074 | u->uartclk / 16); |
| 1075 | div = u->uartclk * 4 / baud; |
| 1076 | } else { |
| 1077 | baud_min = DIV_ROUND_UP(u->uartclk * 32, |
| 1078 | AUART_LINECTRL_BAUD_DIV_MAX); |
| 1079 | baud_max = u->uartclk * 32 / AUART_LINECTRL_BAUD_DIV_MIN; |
| 1080 | baud = uart_get_baud_rate(u, termios, old, baud_min, baud_max); |
Uwe Kleine-König | a6040bc | 2017-03-20 10:05:38 +0100 | [diff] [blame] | 1081 | div = DIV_ROUND_CLOSEST(u->uartclk * 32, baud); |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1082 | } |
| 1083 | |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1084 | ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F); |
| 1085 | ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6); |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1086 | mxs_write(ctrl, s, REG_LINECTRL); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1087 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1088 | mxs_write(ctrl2, s, REG_CTRL2); |
Lothar Waßmann | 8b979f7 | 2012-05-03 11:37:12 +0200 | [diff] [blame] | 1089 | |
| 1090 | uart_update_timeout(u, termios->c_cflag, baud); |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 1091 | |
| 1092 | /* prepare for the DMA RX. */ |
| 1093 | if (auart_dma_enabled(s) && |
| 1094 | !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) { |
| 1095 | if (!mxs_auart_dma_prep_rx(s)) { |
| 1096 | /* Disable the normal RX interrupt. */ |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1097 | mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN, |
| 1098 | s, REG_INTR); |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 1099 | } else { |
| 1100 | mxs_auart_dma_exit(s); |
| 1101 | dev_err(s->dev, "We can not start up the DMA.\n"); |
| 1102 | } |
| 1103 | } |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 1104 | |
| 1105 | /* CTS flow-control and modem-status interrupts */ |
| 1106 | if (UART_ENABLE_MS(u, termios->c_cflag)) |
| 1107 | mxs_auart_enable_ms(u); |
| 1108 | else |
| 1109 | mxs_auart_disable_ms(u); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1110 | } |
| 1111 | |
Fabio Estevam | f3006e4 | 2014-11-12 20:32:49 -0200 | [diff] [blame] | 1112 | static void mxs_auart_set_ldisc(struct uart_port *port, |
| 1113 | struct ktermios *termios) |
Janusz Uzycki | 36a2627 | 2014-10-10 18:53:27 +0200 | [diff] [blame] | 1114 | { |
Fabio Estevam | f3006e4 | 2014-11-12 20:32:49 -0200 | [diff] [blame] | 1115 | if (termios->c_line == N_PPS) { |
Janusz Uzycki | 36a2627 | 2014-10-10 18:53:27 +0200 | [diff] [blame] | 1116 | port->flags |= UPF_HARDPPS_CD; |
| 1117 | mxs_auart_enable_ms(port); |
| 1118 | } else { |
| 1119 | port->flags &= ~UPF_HARDPPS_CD; |
| 1120 | } |
| 1121 | } |
| 1122 | |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1123 | static irqreturn_t mxs_auart_irq_handle(int irq, void *context) |
| 1124 | { |
Uwe Kleine-König | d970d7f | 2013-07-04 11:28:51 +0200 | [diff] [blame] | 1125 | u32 istat; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1126 | struct mxs_auart_port *s = context; |
Janusz Uzycki | 08f937f | 2014-11-14 23:24:33 +0100 | [diff] [blame] | 1127 | u32 mctrl_temp = s->mctrl_prev; |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1128 | u32 stat = mxs_read(s, REG_STAT); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1129 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1130 | istat = mxs_read(s, REG_INTR); |
Uwe Kleine-König | d970d7f | 2013-07-04 11:28:51 +0200 | [diff] [blame] | 1131 | |
| 1132 | /* ack irq */ |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1133 | mxs_clr(istat & (AUART_INTR_RTIS | AUART_INTR_TXIS | AUART_INTR_RXIS |
| 1134 | | AUART_INTR_CTSMIS), s, REG_INTR); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1135 | |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 1136 | /* |
| 1137 | * Dealing with GPIO interrupt |
| 1138 | */ |
| 1139 | if (irq == s->gpio_irq[UART_GPIO_CTS] || |
| 1140 | irq == s->gpio_irq[UART_GPIO_DCD] || |
| 1141 | irq == s->gpio_irq[UART_GPIO_DSR] || |
| 1142 | irq == s->gpio_irq[UART_GPIO_RI]) |
| 1143 | mxs_auart_modem_status(s, |
Janusz Uzycki | 08f937f | 2014-11-14 23:24:33 +0100 | [diff] [blame] | 1144 | mctrl_gpio_get(s->gpios, &mctrl_temp)); |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 1145 | |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1146 | if (istat & AUART_INTR_CTSMIS) { |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 1147 | if (CTS_AT_AUART() && s->ms_irq_enabled) |
Janusz Uzycki | 7c573d7 | 2014-10-10 18:53:25 +0200 | [diff] [blame] | 1148 | uart_handle_cts_change(&s->port, |
| 1149 | stat & AUART_STAT_CTS); |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1150 | mxs_clr(AUART_INTR_CTSMIS, s, REG_INTR); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1151 | istat &= ~AUART_INTR_CTSMIS; |
| 1152 | } |
| 1153 | |
| 1154 | if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) { |
Huang Shijie | a591944 | 2012-11-22 15:06:29 +0800 | [diff] [blame] | 1155 | if (!auart_dma_enabled(s)) |
| 1156 | mxs_auart_rx_chars(s); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1157 | istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS); |
| 1158 | } |
| 1159 | |
| 1160 | if (istat & AUART_INTR_TXIS) { |
| 1161 | mxs_auart_tx_chars(s); |
| 1162 | istat &= ~AUART_INTR_TXIS; |
| 1163 | } |
| 1164 | |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1165 | return IRQ_HANDLED; |
| 1166 | } |
| 1167 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1168 | static void mxs_auart_reset_deassert(struct mxs_auart_port *s) |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1169 | { |
| 1170 | int i; |
| 1171 | unsigned int reg; |
| 1172 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1173 | mxs_clr(AUART_CTRL0_SFTRST, s, REG_CTRL0); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1174 | |
| 1175 | for (i = 0; i < 10000; i++) { |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1176 | reg = mxs_read(s, REG_CTRL0); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1177 | if (!(reg & AUART_CTRL0_SFTRST)) |
| 1178 | break; |
| 1179 | udelay(3); |
| 1180 | } |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1181 | mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1182 | } |
| 1183 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1184 | static void mxs_auart_reset_assert(struct mxs_auart_port *s) |
Juergen Borleis | 17dc72c | 2015-08-07 12:47:04 +0200 | [diff] [blame] | 1185 | { |
| 1186 | int i; |
| 1187 | u32 reg; |
| 1188 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1189 | reg = mxs_read(s, REG_CTRL0); |
Juergen Borleis | 17dc72c | 2015-08-07 12:47:04 +0200 | [diff] [blame] | 1190 | /* if already in reset state, keep it untouched */ |
| 1191 | if (reg & AUART_CTRL0_SFTRST) |
| 1192 | return; |
| 1193 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1194 | mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0); |
| 1195 | mxs_set(AUART_CTRL0_SFTRST, s, REG_CTRL0); |
Juergen Borleis | 17dc72c | 2015-08-07 12:47:04 +0200 | [diff] [blame] | 1196 | |
| 1197 | for (i = 0; i < 1000; i++) { |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1198 | reg = mxs_read(s, REG_CTRL0); |
Juergen Borleis | 17dc72c | 2015-08-07 12:47:04 +0200 | [diff] [blame] | 1199 | /* reset is finished when the clock is gated */ |
| 1200 | if (reg & AUART_CTRL0_CLKGATE) |
| 1201 | return; |
| 1202 | udelay(10); |
| 1203 | } |
| 1204 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1205 | dev_err(s->dev, "Failed to reset the unit."); |
Juergen Borleis | 17dc72c | 2015-08-07 12:47:04 +0200 | [diff] [blame] | 1206 | } |
| 1207 | |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1208 | static int mxs_auart_startup(struct uart_port *u) |
| 1209 | { |
Fabio Estevam | 9bbc3dc | 2013-12-02 01:17:58 -0200 | [diff] [blame] | 1210 | int ret; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1211 | struct mxs_auart_port *s = to_auart_port(u); |
| 1212 | |
Fabio Estevam | 9bbc3dc | 2013-12-02 01:17:58 -0200 | [diff] [blame] | 1213 | ret = clk_prepare_enable(s->clk); |
| 1214 | if (ret) |
| 1215 | return ret; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1216 | |
Juergen Borleis | 17dc72c | 2015-08-07 12:47:04 +0200 | [diff] [blame] | 1217 | if (uart_console(u)) { |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1218 | mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0); |
Juergen Borleis | 17dc72c | 2015-08-07 12:47:04 +0200 | [diff] [blame] | 1219 | } else { |
| 1220 | /* reset the unit to a well known state */ |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1221 | mxs_auart_reset_assert(s); |
| 1222 | mxs_auart_reset_deassert(s); |
Juergen Borleis | 17dc72c | 2015-08-07 12:47:04 +0200 | [diff] [blame] | 1223 | } |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1224 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1225 | mxs_set(AUART_CTRL2_UARTEN, s, REG_CTRL2); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1226 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1227 | mxs_write(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN, |
| 1228 | s, REG_INTR); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1229 | |
Hector Palacios | 9987f76 | 2013-10-03 09:32:03 +0200 | [diff] [blame] | 1230 | /* Reset FIFO size (it could have changed if DMA was enabled) */ |
| 1231 | u->fifosize = MXS_AUART_FIFO_SIZE; |
| 1232 | |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1233 | /* |
| 1234 | * Enable fifo so all four bytes of a DMA word are written to |
| 1235 | * output (otherwise, only the LSB is written, ie. 1 in 4 bytes) |
| 1236 | */ |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1237 | mxs_set(AUART_LINECTRL_FEN, s, REG_LINECTRL); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1238 | |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 1239 | /* get initial status of modem lines */ |
| 1240 | mctrl_gpio_get(s->gpios, &s->mctrl_prev); |
| 1241 | |
| 1242 | s->ms_irq_enabled = false; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1243 | return 0; |
| 1244 | } |
| 1245 | |
| 1246 | static void mxs_auart_shutdown(struct uart_port *u) |
| 1247 | { |
| 1248 | struct mxs_auart_port *s = to_auart_port(u); |
| 1249 | |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 1250 | mxs_auart_disable_ms(u); |
| 1251 | |
Huang Shijie | e800163 | 2012-11-16 16:03:53 +0800 | [diff] [blame] | 1252 | if (auart_dma_enabled(s)) |
| 1253 | mxs_auart_dma_exit(s); |
| 1254 | |
Juergen Borleis | 17dc72c | 2015-08-07 12:47:04 +0200 | [diff] [blame] | 1255 | if (uart_console(u)) { |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1256 | mxs_clr(AUART_CTRL2_UARTEN, s, REG_CTRL2); |
| 1257 | |
| 1258 | mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN | |
| 1259 | AUART_INTR_CTSMIEN, s, REG_INTR); |
| 1260 | mxs_set(AUART_CTRL0_CLKGATE, s, REG_CTRL0); |
Juergen Borleis | 17dc72c | 2015-08-07 12:47:04 +0200 | [diff] [blame] | 1261 | } else { |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1262 | mxs_auart_reset_assert(s); |
Juergen Borleis | 17dc72c | 2015-08-07 12:47:04 +0200 | [diff] [blame] | 1263 | } |
Huang Shijie | 851b714 | 2012-09-06 22:38:40 -0400 | [diff] [blame] | 1264 | |
Shawn Guo | a481377 | 2011-12-20 14:10:29 +0800 | [diff] [blame] | 1265 | clk_disable_unprepare(s->clk); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1266 | } |
| 1267 | |
| 1268 | static unsigned int mxs_auart_tx_empty(struct uart_port *u) |
| 1269 | { |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1270 | struct mxs_auart_port *s = to_auart_port(u); |
| 1271 | |
| 1272 | if ((mxs_read(s, REG_STAT) & |
Janusz Uzycki | 2b310ec | 2014-11-18 18:37:13 +0100 | [diff] [blame] | 1273 | (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE) |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1274 | return TIOCSER_TEMT; |
Janusz Uzycki | 2b310ec | 2014-11-18 18:37:13 +0100 | [diff] [blame] | 1275 | |
| 1276 | return 0; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1277 | } |
| 1278 | |
| 1279 | static void mxs_auart_start_tx(struct uart_port *u) |
| 1280 | { |
| 1281 | struct mxs_auart_port *s = to_auart_port(u); |
| 1282 | |
| 1283 | /* enable transmitter */ |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1284 | mxs_set(AUART_CTRL2_TXE, s, REG_CTRL2); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1285 | |
| 1286 | mxs_auart_tx_chars(s); |
| 1287 | } |
| 1288 | |
| 1289 | static void mxs_auart_stop_tx(struct uart_port *u) |
| 1290 | { |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1291 | struct mxs_auart_port *s = to_auart_port(u); |
| 1292 | |
| 1293 | mxs_clr(AUART_CTRL2_TXE, s, REG_CTRL2); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1294 | } |
| 1295 | |
| 1296 | static void mxs_auart_stop_rx(struct uart_port *u) |
| 1297 | { |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1298 | struct mxs_auart_port *s = to_auart_port(u); |
| 1299 | |
| 1300 | mxs_clr(AUART_CTRL2_RXE, s, REG_CTRL2); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1301 | } |
| 1302 | |
| 1303 | static void mxs_auart_break_ctl(struct uart_port *u, int ctl) |
| 1304 | { |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1305 | struct mxs_auart_port *s = to_auart_port(u); |
| 1306 | |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1307 | if (ctl) |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1308 | mxs_set(AUART_LINECTRL_BRK, s, REG_LINECTRL); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1309 | else |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1310 | mxs_clr(AUART_LINECTRL_BRK, s, REG_LINECTRL); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1311 | } |
| 1312 | |
Julia Lawall | 069a47e | 2016-09-01 19:51:35 +0200 | [diff] [blame] | 1313 | static const struct uart_ops mxs_auart_ops = { |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1314 | .tx_empty = mxs_auart_tx_empty, |
| 1315 | .start_tx = mxs_auart_start_tx, |
| 1316 | .stop_tx = mxs_auart_stop_tx, |
| 1317 | .stop_rx = mxs_auart_stop_rx, |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 1318 | .enable_ms = mxs_auart_enable_ms, |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1319 | .break_ctl = mxs_auart_break_ctl, |
| 1320 | .set_mctrl = mxs_auart_set_mctrl, |
| 1321 | .get_mctrl = mxs_auart_get_mctrl, |
| 1322 | .startup = mxs_auart_startup, |
| 1323 | .shutdown = mxs_auart_shutdown, |
| 1324 | .set_termios = mxs_auart_settermios, |
Janusz Uzycki | 36a2627 | 2014-10-10 18:53:27 +0200 | [diff] [blame] | 1325 | .set_ldisc = mxs_auart_set_ldisc, |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1326 | .type = mxs_auart_type, |
| 1327 | .release_port = mxs_auart_release_port, |
| 1328 | .request_port = mxs_auart_request_port, |
| 1329 | .config_port = mxs_auart_config_port, |
| 1330 | .verify_port = mxs_auart_verify_port, |
| 1331 | }; |
| 1332 | |
| 1333 | static struct mxs_auart_port *auart_port[MXS_AUART_PORTS]; |
| 1334 | |
| 1335 | #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE |
| 1336 | static void mxs_auart_console_putchar(struct uart_port *port, int ch) |
| 1337 | { |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1338 | struct mxs_auart_port *s = to_auart_port(port); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1339 | unsigned int to = 1000; |
| 1340 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1341 | while (mxs_read(s, REG_STAT) & AUART_STAT_TXFF) { |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1342 | if (!to--) |
| 1343 | break; |
| 1344 | udelay(1); |
| 1345 | } |
| 1346 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1347 | mxs_write(ch, s, REG_DATA); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1348 | } |
| 1349 | |
| 1350 | static void |
| 1351 | auart_console_write(struct console *co, const char *str, unsigned int count) |
| 1352 | { |
| 1353 | struct mxs_auart_port *s; |
| 1354 | struct uart_port *port; |
| 1355 | unsigned int old_ctrl0, old_ctrl2; |
Uwe Kleine-König | 079a036 | 2013-06-28 11:49:41 +0200 | [diff] [blame] | 1356 | unsigned int to = 20000; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1357 | |
Wolfram Sang | 4829e76 | 2013-04-19 21:12:17 +0200 | [diff] [blame] | 1358 | if (co->index >= MXS_AUART_PORTS || co->index < 0) |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1359 | return; |
| 1360 | |
| 1361 | s = auart_port[co->index]; |
| 1362 | port = &s->port; |
| 1363 | |
| 1364 | clk_enable(s->clk); |
| 1365 | |
| 1366 | /* First save the CR then disable the interrupts */ |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1367 | old_ctrl2 = mxs_read(s, REG_CTRL2); |
| 1368 | old_ctrl0 = mxs_read(s, REG_CTRL0); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1369 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1370 | mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0); |
| 1371 | mxs_set(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, s, REG_CTRL2); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1372 | |
| 1373 | uart_console_write(port, str, count, mxs_auart_console_putchar); |
| 1374 | |
Uwe Kleine-König | 079a036 | 2013-06-28 11:49:41 +0200 | [diff] [blame] | 1375 | /* Finally, wait for transmitter to become empty ... */ |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1376 | while (mxs_read(s, REG_STAT) & AUART_STAT_BUSY) { |
Uwe Kleine-König | 079a036 | 2013-06-28 11:49:41 +0200 | [diff] [blame] | 1377 | udelay(1); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1378 | if (!to--) |
| 1379 | break; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1380 | } |
| 1381 | |
Uwe Kleine-König | 079a036 | 2013-06-28 11:49:41 +0200 | [diff] [blame] | 1382 | /* |
| 1383 | * ... and restore the TCR if we waited long enough for the transmitter |
| 1384 | * to be idle. This might keep the transmitter enabled although it is |
| 1385 | * unused, but that is better than to disable it while it is still |
| 1386 | * transmitting. |
| 1387 | */ |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1388 | if (!(mxs_read(s, REG_STAT) & AUART_STAT_BUSY)) { |
| 1389 | mxs_write(old_ctrl0, s, REG_CTRL0); |
| 1390 | mxs_write(old_ctrl2, s, REG_CTRL2); |
Uwe Kleine-König | 079a036 | 2013-06-28 11:49:41 +0200 | [diff] [blame] | 1391 | } |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1392 | |
| 1393 | clk_disable(s->clk); |
| 1394 | } |
| 1395 | |
| 1396 | static void __init |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1397 | auart_console_get_options(struct mxs_auart_port *s, int *baud, |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1398 | int *parity, int *bits) |
| 1399 | { |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1400 | struct uart_port *port = &s->port; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1401 | unsigned int lcr_h, quot; |
| 1402 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1403 | if (!(mxs_read(s, REG_CTRL2) & AUART_CTRL2_UARTEN)) |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1404 | return; |
| 1405 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1406 | lcr_h = mxs_read(s, REG_LINECTRL); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1407 | |
| 1408 | *parity = 'n'; |
| 1409 | if (lcr_h & AUART_LINECTRL_PEN) { |
| 1410 | if (lcr_h & AUART_LINECTRL_EPS) |
| 1411 | *parity = 'e'; |
| 1412 | else |
| 1413 | *parity = 'o'; |
| 1414 | } |
| 1415 | |
| 1416 | if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2)) |
| 1417 | *bits = 7; |
| 1418 | else |
| 1419 | *bits = 8; |
| 1420 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1421 | quot = ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVINT_MASK)) |
| 1422 | >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6); |
| 1423 | quot |= ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVFRAC_MASK)) |
| 1424 | >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1425 | if (quot == 0) |
| 1426 | quot = 1; |
| 1427 | |
| 1428 | *baud = (port->uartclk << 2) / quot; |
| 1429 | } |
| 1430 | |
| 1431 | static int __init |
| 1432 | auart_console_setup(struct console *co, char *options) |
| 1433 | { |
| 1434 | struct mxs_auart_port *s; |
| 1435 | int baud = 9600; |
| 1436 | int bits = 8; |
| 1437 | int parity = 'n'; |
| 1438 | int flow = 'n'; |
| 1439 | int ret; |
| 1440 | |
| 1441 | /* |
| 1442 | * Check whether an invalid uart number has been specified, and |
| 1443 | * if so, search for the first available port that does have |
| 1444 | * console support. |
| 1445 | */ |
| 1446 | if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port)) |
| 1447 | co->index = 0; |
| 1448 | s = auart_port[co->index]; |
| 1449 | if (!s) |
| 1450 | return -ENODEV; |
| 1451 | |
Fabio Estevam | 9bbc3dc | 2013-12-02 01:17:58 -0200 | [diff] [blame] | 1452 | ret = clk_prepare_enable(s->clk); |
| 1453 | if (ret) |
| 1454 | return ret; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1455 | |
| 1456 | if (options) |
| 1457 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
| 1458 | else |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1459 | auart_console_get_options(s, &baud, &parity, &bits); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1460 | |
| 1461 | ret = uart_set_options(&s->port, co, baud, parity, bits, flow); |
| 1462 | |
Shawn Guo | a481377 | 2011-12-20 14:10:29 +0800 | [diff] [blame] | 1463 | clk_disable_unprepare(s->clk); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1464 | |
| 1465 | return ret; |
| 1466 | } |
| 1467 | |
| 1468 | static struct console auart_console = { |
| 1469 | .name = "ttyAPP", |
| 1470 | .write = auart_console_write, |
| 1471 | .device = uart_console_device, |
| 1472 | .setup = auart_console_setup, |
| 1473 | .flags = CON_PRINTBUFFER, |
| 1474 | .index = -1, |
| 1475 | .data = &auart_driver, |
| 1476 | }; |
| 1477 | #endif |
| 1478 | |
| 1479 | static struct uart_driver auart_driver = { |
| 1480 | .owner = THIS_MODULE, |
| 1481 | .driver_name = "ttyAPP", |
| 1482 | .dev_name = "ttyAPP", |
| 1483 | .major = 0, |
| 1484 | .minor = 0, |
| 1485 | .nr = MXS_AUART_PORTS, |
| 1486 | #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE |
| 1487 | .cons = &auart_console, |
| 1488 | #endif |
| 1489 | }; |
| 1490 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1491 | static void mxs_init_regs(struct mxs_auart_port *s) |
| 1492 | { |
| 1493 | if (is_asm9260_auart(s)) |
| 1494 | s->vendor = &vendor_alphascale_asm9260; |
| 1495 | else |
| 1496 | s->vendor = &vendor_freescale_stmp37xx; |
| 1497 | } |
| 1498 | |
| 1499 | static int mxs_get_clks(struct mxs_auart_port *s, |
| 1500 | struct platform_device *pdev) |
| 1501 | { |
| 1502 | int err; |
| 1503 | |
| 1504 | if (!is_asm9260_auart(s)) { |
| 1505 | s->clk = devm_clk_get(&pdev->dev, NULL); |
Wei Yongjun | 0d2665b | 2016-09-10 12:22:17 +0000 | [diff] [blame] | 1506 | return PTR_ERR_OR_ZERO(s->clk); |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1507 | } |
| 1508 | |
| 1509 | s->clk = devm_clk_get(s->dev, "mod"); |
| 1510 | if (IS_ERR(s->clk)) { |
| 1511 | dev_err(s->dev, "Failed to get \"mod\" clk\n"); |
| 1512 | return PTR_ERR(s->clk); |
| 1513 | } |
| 1514 | |
| 1515 | s->clk_ahb = devm_clk_get(s->dev, "ahb"); |
| 1516 | if (IS_ERR(s->clk_ahb)) { |
| 1517 | dev_err(s->dev, "Failed to get \"ahb\" clk\n"); |
| 1518 | return PTR_ERR(s->clk_ahb); |
| 1519 | } |
| 1520 | |
| 1521 | err = clk_prepare_enable(s->clk_ahb); |
| 1522 | if (err) { |
| 1523 | dev_err(s->dev, "Failed to enable ahb_clk!\n"); |
| 1524 | return err; |
| 1525 | } |
| 1526 | |
| 1527 | err = clk_set_rate(s->clk, clk_get_rate(s->clk_ahb)); |
| 1528 | if (err) { |
| 1529 | dev_err(s->dev, "Failed to set rate!\n"); |
Wei Yongjun | 1664bc4 | 2016-09-17 01:13:46 +0000 | [diff] [blame] | 1530 | goto disable_clk_ahb; |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1531 | } |
| 1532 | |
| 1533 | err = clk_prepare_enable(s->clk); |
| 1534 | if (err) { |
| 1535 | dev_err(s->dev, "Failed to enable clk!\n"); |
Fabio Estevam | 5d7519d | 2016-09-09 08:31:33 -0300 | [diff] [blame] | 1536 | goto disable_clk_ahb; |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1537 | } |
| 1538 | |
| 1539 | return 0; |
Fabio Estevam | 5d7519d | 2016-09-09 08:31:33 -0300 | [diff] [blame] | 1540 | |
| 1541 | disable_clk_ahb: |
| 1542 | clk_disable_unprepare(s->clk_ahb); |
| 1543 | return err; |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1544 | } |
| 1545 | |
Fabio Estevam | 1ea6607 | 2012-06-18 10:06:09 -0300 | [diff] [blame] | 1546 | /* |
| 1547 | * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it |
| 1548 | * could successfully get all information from dt or a negative errno. |
| 1549 | */ |
| 1550 | static int serial_mxs_probe_dt(struct mxs_auart_port *s, |
| 1551 | struct platform_device *pdev) |
| 1552 | { |
| 1553 | struct device_node *np = pdev->dev.of_node; |
| 1554 | int ret; |
| 1555 | |
| 1556 | if (!np) |
| 1557 | /* no device tree device */ |
| 1558 | return 1; |
| 1559 | |
| 1560 | ret = of_alias_get_id(np, "serial"); |
| 1561 | if (ret < 0) { |
| 1562 | dev_err(&pdev->dev, "failed to get alias id: %d\n", ret); |
| 1563 | return ret; |
| 1564 | } |
| 1565 | s->port.line = ret; |
| 1566 | |
Geert Uytterhoeven | 182cdcb | 2016-04-22 17:22:22 +0200 | [diff] [blame] | 1567 | if (of_get_property(np, "uart-has-rtscts", NULL) || |
| 1568 | of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) |
Huang Shijie | 8418e67 | 2013-08-03 10:09:14 -0400 | [diff] [blame] | 1569 | set_bit(MXS_AUART_RTSCTS, &s->flags); |
| 1570 | |
Fabio Estevam | 1ea6607 | 2012-06-18 10:06:09 -0300 | [diff] [blame] | 1571 | return 0; |
| 1572 | } |
| 1573 | |
Uwe Kleine-König | 343fda9 | 2015-02-12 15:24:40 +0100 | [diff] [blame] | 1574 | static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev) |
Janusz Uzycki | 7c573d7 | 2014-10-10 18:53:25 +0200 | [diff] [blame] | 1575 | { |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 1576 | enum mctrl_gpio_idx i; |
| 1577 | struct gpio_desc *gpiod; |
| 1578 | |
Uwe Kleine-König | 7d8c70d | 2015-09-30 10:19:40 +0200 | [diff] [blame] | 1579 | s->gpios = mctrl_gpio_init_noauto(dev, 0); |
Uwe Kleine-König | 343fda9 | 2015-02-12 15:24:40 +0100 | [diff] [blame] | 1580 | if (IS_ERR(s->gpios)) |
| 1581 | return PTR_ERR(s->gpios); |
Janusz Uzycki | 7c573d7 | 2014-10-10 18:53:25 +0200 | [diff] [blame] | 1582 | |
| 1583 | /* Block (enabled before) DMA option if RTS or CTS is GPIO line */ |
| 1584 | if (!RTS_AT_AUART() || !CTS_AT_AUART()) { |
| 1585 | if (test_bit(MXS_AUART_RTSCTS, &s->flags)) |
| 1586 | dev_warn(dev, |
| 1587 | "DMA and flow control via gpio may cause some problems. DMA disabled!\n"); |
| 1588 | clear_bit(MXS_AUART_RTSCTS, &s->flags); |
| 1589 | } |
| 1590 | |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 1591 | for (i = 0; i < UART_GPIO_MAX; i++) { |
| 1592 | gpiod = mctrl_gpio_to_gpiod(s->gpios, i); |
Wolfram Sang | f8bdfe9 | 2018-01-14 22:07:09 +0100 | [diff] [blame] | 1593 | if (gpiod && (gpiod_get_direction(gpiod) == 1)) |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 1594 | s->gpio_irq[i] = gpiod_to_irq(gpiod); |
| 1595 | else |
| 1596 | s->gpio_irq[i] = -EINVAL; |
| 1597 | } |
| 1598 | |
Uwe Kleine-König | 343fda9 | 2015-02-12 15:24:40 +0100 | [diff] [blame] | 1599 | return 0; |
Janusz Uzycki | 7c573d7 | 2014-10-10 18:53:25 +0200 | [diff] [blame] | 1600 | } |
| 1601 | |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 1602 | static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s) |
| 1603 | { |
| 1604 | enum mctrl_gpio_idx i; |
| 1605 | |
| 1606 | for (i = 0; i < UART_GPIO_MAX; i++) |
| 1607 | if (s->gpio_irq[i] >= 0) |
| 1608 | free_irq(s->gpio_irq[i], s); |
| 1609 | } |
| 1610 | |
| 1611 | static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s) |
| 1612 | { |
| 1613 | int *irq = s->gpio_irq; |
| 1614 | enum mctrl_gpio_idx i; |
| 1615 | int err = 0; |
| 1616 | |
| 1617 | for (i = 0; (i < UART_GPIO_MAX) && !err; i++) { |
| 1618 | if (irq[i] < 0) |
| 1619 | continue; |
| 1620 | |
| 1621 | irq_set_status_flags(irq[i], IRQ_NOAUTOEN); |
| 1622 | err = request_irq(irq[i], mxs_auart_irq_handle, |
| 1623 | IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s); |
| 1624 | if (err) |
| 1625 | dev_err(s->dev, "%s - Can't get %d irq\n", |
| 1626 | __func__, irq[i]); |
| 1627 | } |
| 1628 | |
| 1629 | /* |
| 1630 | * If something went wrong, rollback. |
Anton Vasilyev | 5963e8a | 2018-08-07 13:59:05 +0300 | [diff] [blame] | 1631 | * Be careful: i may be unsigned. |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 1632 | */ |
Anton Vasilyev | 5963e8a | 2018-08-07 13:59:05 +0300 | [diff] [blame] | 1633 | while (err && (i-- > 0)) |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 1634 | if (irq[i] >= 0) |
| 1635 | free_irq(irq[i], s); |
| 1636 | |
| 1637 | return err; |
| 1638 | } |
| 1639 | |
Bill Pemberton | 9671f09 | 2012-11-19 13:21:50 -0500 | [diff] [blame] | 1640 | static int mxs_auart_probe(struct platform_device *pdev) |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1641 | { |
Huang Shijie | f4b1f03b | 2012-11-16 16:03:52 +0800 | [diff] [blame] | 1642 | const struct of_device_id *of_id = |
| 1643 | of_match_device(mxs_auart_dt_ids, &pdev->dev); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1644 | struct mxs_auart_port *s; |
| 1645 | u32 version; |
Fabio Estevam | 5f9ba5b | 2015-01-14 14:39:09 -0200 | [diff] [blame] | 1646 | int ret, irq; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1647 | struct resource *r; |
| 1648 | |
Fabio Estevam | 46778bc | 2014-11-27 17:08:31 -0200 | [diff] [blame] | 1649 | s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL); |
Fabio Estevam | 11387b0 | 2014-11-27 17:08:30 -0200 | [diff] [blame] | 1650 | if (!s) |
| 1651 | return -ENOMEM; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1652 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1653 | s->port.dev = &pdev->dev; |
| 1654 | s->dev = &pdev->dev; |
| 1655 | |
Fabio Estevam | 1ea6607 | 2012-06-18 10:06:09 -0300 | [diff] [blame] | 1656 | ret = serial_mxs_probe_dt(s, pdev); |
| 1657 | if (ret > 0) |
| 1658 | s->port.line = pdev->id < 0 ? 0 : pdev->id; |
| 1659 | else if (ret < 0) |
Fabio Estevam | 46778bc | 2014-11-27 17:08:31 -0200 | [diff] [blame] | 1660 | return ret; |
Geert Uytterhoeven | dd345a3 | 2018-02-23 14:38:32 +0100 | [diff] [blame] | 1661 | if (s->port.line >= ARRAY_SIZE(auart_port)) { |
| 1662 | dev_err(&pdev->dev, "serial%d out of range\n", s->port.line); |
| 1663 | return -EINVAL; |
| 1664 | } |
Fabio Estevam | 1ea6607 | 2012-06-18 10:06:09 -0300 | [diff] [blame] | 1665 | |
Huang Shijie | f4b1f03b | 2012-11-16 16:03:52 +0800 | [diff] [blame] | 1666 | if (of_id) { |
| 1667 | pdev->id_entry = of_id->data; |
| 1668 | s->devtype = pdev->id_entry->driver_data; |
| 1669 | } |
| 1670 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1671 | ret = mxs_get_clks(s, pdev); |
| 1672 | if (ret) |
| 1673 | return ret; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1674 | |
| 1675 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Alexey Khoroshilov | ca7c22f | 2018-03-03 01:42:01 +0300 | [diff] [blame] | 1676 | if (!r) { |
| 1677 | ret = -ENXIO; |
| 1678 | goto out_disable_clks; |
| 1679 | } |
Fabio Estevam | 75beb26 | 2014-11-27 17:08:32 -0200 | [diff] [blame] | 1680 | |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1681 | s->port.mapbase = r->start; |
| 1682 | s->port.membase = ioremap(r->start, resource_size(r)); |
Kangjie Lu | 6734330 | 2019-03-14 02:21:51 -0500 | [diff] [blame] | 1683 | if (!s->port.membase) { |
| 1684 | ret = -ENOMEM; |
| 1685 | goto out_disable_clks; |
| 1686 | } |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1687 | s->port.ops = &mxs_auart_ops; |
| 1688 | s->port.iotype = UPIO_MEM; |
Hector Palacios | 9987f76 | 2013-10-03 09:32:03 +0200 | [diff] [blame] | 1689 | s->port.fifosize = MXS_AUART_FIFO_SIZE; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1690 | s->port.uartclk = clk_get_rate(s->clk); |
| 1691 | s->port.type = PORT_IMX; |
Dmitry Safonov | 2deed95 | 2019-12-13 00:06:26 +0000 | [diff] [blame] | 1692 | s->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_MXS_AUART_CONSOLE); |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1693 | |
| 1694 | mxs_init_regs(s); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1695 | |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 1696 | s->mctrl_prev = 0; |
| 1697 | |
Fabio Estevam | 6960cd4 | 2015-01-14 14:39:07 -0200 | [diff] [blame] | 1698 | irq = platform_get_irq(pdev, 0); |
Alexey Khoroshilov | ca7c22f | 2018-03-03 01:42:01 +0300 | [diff] [blame] | 1699 | if (irq < 0) { |
| 1700 | ret = irq; |
| 1701 | goto out_disable_clks; |
| 1702 | } |
Fabio Estevam | 99c932c | 2015-01-14 14:39:08 -0200 | [diff] [blame] | 1703 | |
Fabio Estevam | 6960cd4 | 2015-01-14 14:39:07 -0200 | [diff] [blame] | 1704 | s->port.irq = irq; |
| 1705 | ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0, |
Fabio Estevam | 9e5df9f | 2014-11-27 17:08:33 -0200 | [diff] [blame] | 1706 | dev_name(&pdev->dev), s); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1707 | if (ret) |
Alexey Khoroshilov | ca7c22f | 2018-03-03 01:42:01 +0300 | [diff] [blame] | 1708 | goto out_disable_clks; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1709 | |
| 1710 | platform_set_drvdata(pdev, s); |
| 1711 | |
Uwe Kleine-König | 343fda9 | 2015-02-12 15:24:40 +0100 | [diff] [blame] | 1712 | ret = mxs_auart_init_gpios(s, &pdev->dev); |
| 1713 | if (ret) { |
| 1714 | dev_err(&pdev->dev, "Failed to initialize GPIOs.\n"); |
Alexey Khoroshilov | ca7c22f | 2018-03-03 01:42:01 +0300 | [diff] [blame] | 1715 | goto out_disable_clks; |
Uwe Kleine-König | 343fda9 | 2015-02-12 15:24:40 +0100 | [diff] [blame] | 1716 | } |
Janusz Uzycki | 7c573d7 | 2014-10-10 18:53:25 +0200 | [diff] [blame] | 1717 | |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 1718 | /* |
| 1719 | * Get the GPIO lines IRQ |
| 1720 | */ |
| 1721 | ret = mxs_auart_request_gpio_irq(s); |
| 1722 | if (ret) |
Alexey Khoroshilov | ca7c22f | 2018-03-03 01:42:01 +0300 | [diff] [blame] | 1723 | goto out_disable_clks; |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 1724 | |
Fabio Estevam | 1ea6607 | 2012-06-18 10:06:09 -0300 | [diff] [blame] | 1725 | auart_port[s->port.line] = s; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1726 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1727 | mxs_auart_reset_deassert(s); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1728 | |
| 1729 | ret = uart_add_one_port(&auart_driver, &s->port); |
| 1730 | if (ret) |
Alexey Khoroshilov | ca7c22f | 2018-03-03 01:42:01 +0300 | [diff] [blame] | 1731 | goto out_free_qpio_irq; |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1732 | |
Oleksij Rempel | 254da0d | 2016-03-16 14:05:52 +0100 | [diff] [blame] | 1733 | /* ASM9260 don't have version reg */ |
| 1734 | if (is_asm9260_auart(s)) { |
| 1735 | dev_info(&pdev->dev, "Found APPUART ASM9260\n"); |
| 1736 | } else { |
| 1737 | version = mxs_read(s, REG_VERSION); |
| 1738 | dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n", |
| 1739 | (version >> 24) & 0xff, |
| 1740 | (version >> 16) & 0xff, version & 0xffff); |
| 1741 | } |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1742 | |
| 1743 | return 0; |
| 1744 | |
Alexey Khoroshilov | ca7c22f | 2018-03-03 01:42:01 +0300 | [diff] [blame] | 1745 | out_free_qpio_irq: |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 1746 | mxs_auart_free_gpio_irq(s); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1747 | auart_port[pdev->id] = NULL; |
Alexey Khoroshilov | ca7c22f | 2018-03-03 01:42:01 +0300 | [diff] [blame] | 1748 | |
| 1749 | out_disable_clks: |
| 1750 | if (is_asm9260_auart(s)) { |
| 1751 | clk_disable_unprepare(s->clk); |
| 1752 | clk_disable_unprepare(s->clk_ahb); |
| 1753 | } |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1754 | return ret; |
| 1755 | } |
| 1756 | |
Bill Pemberton | ae8d8a1 | 2012-11-19 13:26:18 -0500 | [diff] [blame] | 1757 | static int mxs_auart_remove(struct platform_device *pdev) |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1758 | { |
| 1759 | struct mxs_auart_port *s = platform_get_drvdata(pdev); |
| 1760 | |
| 1761 | uart_remove_one_port(&auart_driver, &s->port); |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1762 | auart_port[pdev->id] = NULL; |
Janusz Uzycki | f9e4239 | 2014-10-10 18:53:26 +0200 | [diff] [blame] | 1763 | mxs_auart_free_gpio_irq(s); |
Alexey Khoroshilov | ca7c22f | 2018-03-03 01:42:01 +0300 | [diff] [blame] | 1764 | if (is_asm9260_auart(s)) { |
| 1765 | clk_disable_unprepare(s->clk); |
| 1766 | clk_disable_unprepare(s->clk_ahb); |
| 1767 | } |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1768 | |
| 1769 | return 0; |
| 1770 | } |
| 1771 | |
| 1772 | static struct platform_driver mxs_auart_driver = { |
| 1773 | .probe = mxs_auart_probe, |
Bill Pemberton | 2d47b71 | 2012-11-19 13:21:34 -0500 | [diff] [blame] | 1774 | .remove = mxs_auart_remove, |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1775 | .driver = { |
| 1776 | .name = "mxs-auart", |
Fabio Estevam | 1ea6607 | 2012-06-18 10:06:09 -0300 | [diff] [blame] | 1777 | .of_match_table = mxs_auart_dt_ids, |
Sascha Hauer | 47d37d6 | 2011-01-11 15:54:54 +0100 | [diff] [blame] | 1778 | }, |
| 1779 | }; |
| 1780 | |
| 1781 | static int __init mxs_auart_init(void) |
| 1782 | { |
| 1783 | int r; |
| 1784 | |
| 1785 | r = uart_register_driver(&auart_driver); |
| 1786 | if (r) |
| 1787 | goto out; |
| 1788 | |
| 1789 | r = platform_driver_register(&mxs_auart_driver); |
| 1790 | if (r) |
| 1791 | goto out_err; |
| 1792 | |
| 1793 | return 0; |
| 1794 | out_err: |
| 1795 | uart_unregister_driver(&auart_driver); |
| 1796 | out: |
| 1797 | return r; |
| 1798 | } |
| 1799 | |
| 1800 | static void __exit mxs_auart_exit(void) |
| 1801 | { |
| 1802 | platform_driver_unregister(&mxs_auart_driver); |
| 1803 | uart_unregister_driver(&auart_driver); |
| 1804 | } |
| 1805 | |
| 1806 | module_init(mxs_auart_init); |
| 1807 | module_exit(mxs_auart_exit); |
| 1808 | MODULE_LICENSE("GPL"); |
| 1809 | MODULE_DESCRIPTION("Freescale MXS application uart driver"); |
Fabio Estevam | 1ea6607 | 2012-06-18 10:06:09 -0300 | [diff] [blame] | 1810 | MODULE_ALIAS("platform:mxs-auart"); |