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Sam Shih4bea6dd2019-09-20 06:49:06 +08001// SPDX-License-Identifier: GPL-2.0
John Crispincaf065f2017-01-23 19:34:37 +01002/*
Sam Shih4bea6dd2019-09-20 06:49:06 +08003 * MediaTek Pulse Width Modulator driver
John Crispincaf065f2017-01-23 19:34:37 +01004 *
5 * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
Zhi Maoe7c197e2017-06-30 14:05:18 +08006 * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
John Crispincaf065f2017-01-23 19:34:37 +01007 *
John Crispincaf065f2017-01-23 19:34:37 +01008 */
9
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/ioport.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/clk.h>
16#include <linux/of.h>
Zhi Mao424268c2017-10-25 18:11:01 +080017#include <linux/of_device.h>
John Crispincaf065f2017-01-23 19:34:37 +010018#include <linux/platform_device.h>
19#include <linux/pwm.h>
20#include <linux/slab.h>
21#include <linux/types.h>
22
23/* PWM registers and bits definitions */
24#define PWMCON 0x00
25#define PWMHDUR 0x04
26#define PWMLDUR 0x08
27#define PWMGDUR 0x0c
28#define PWMWAVENUM 0x28
29#define PWMDWIDTH 0x2c
Sean Wang360cc032018-03-01 16:19:12 +080030#define PWM45DWIDTH_FIXUP 0x30
John Crispincaf065f2017-01-23 19:34:37 +010031#define PWMTHRES 0x30
Sean Wang360cc032018-03-01 16:19:12 +080032#define PWM45THRES_FIXUP 0x34
Fabien Parent0c0ead72020-10-19 16:07:02 +020033#define PWM_CK_26M_SEL 0x210
John Crispincaf065f2017-01-23 19:34:37 +010034
Zhi Mao8bdb65d2017-06-30 14:05:20 +080035#define PWM_CLK_DIV_MAX 7
36
Sam Shih25037812019-09-20 06:49:05 +080037struct pwm_mediatek_of_data {
Zhi Mao424268c2017-10-25 18:11:01 +080038 unsigned int num_pwms;
Sean Wang360cc032018-03-01 16:19:12 +080039 bool pwm45_fixup;
Fabien Parent0c0ead72020-10-19 16:07:02 +020040 bool has_ck_26m_sel;
John Crispincaf065f2017-01-23 19:34:37 +010041};
42
43/**
Sam Shih25037812019-09-20 06:49:05 +080044 * struct pwm_mediatek_chip - struct representing PWM chip
John Crispincaf065f2017-01-23 19:34:37 +010045 * @chip: linux PWM chip representation
46 * @regs: base address of PWM chip
Sam Shihefecdeb2019-09-20 06:49:04 +080047 * @clk_top: the top clock generator
48 * @clk_main: the clock used by PWM core
49 * @clk_pwms: the clock used by each PWM channel
50 * @clk_freq: the fix clock frequency of legacy MIPS SoC
Lee Jonesfc810e72020-06-29 13:47:51 +010051 * @soc: pointer to chip's platform data
John Crispincaf065f2017-01-23 19:34:37 +010052 */
Sam Shih25037812019-09-20 06:49:05 +080053struct pwm_mediatek_chip {
John Crispincaf065f2017-01-23 19:34:37 +010054 struct pwm_chip chip;
55 void __iomem *regs;
Sam Shihefecdeb2019-09-20 06:49:04 +080056 struct clk *clk_top;
57 struct clk *clk_main;
58 struct clk **clk_pwms;
Sam Shih25037812019-09-20 06:49:05 +080059 const struct pwm_mediatek_of_data *soc;
John Crispincaf065f2017-01-23 19:34:37 +010060};
61
Sam Shih25037812019-09-20 06:49:05 +080062static const unsigned int pwm_mediatek_reg_offset[] = {
Zhi Mao424268c2017-10-25 18:11:01 +080063 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
64};
65
Sam Shih25037812019-09-20 06:49:05 +080066static inline struct pwm_mediatek_chip *
67to_pwm_mediatek_chip(struct pwm_chip *chip)
John Crispincaf065f2017-01-23 19:34:37 +010068{
Sam Shih25037812019-09-20 06:49:05 +080069 return container_of(chip, struct pwm_mediatek_chip, chip);
John Crispincaf065f2017-01-23 19:34:37 +010070}
71
Sam Shih25037812019-09-20 06:49:05 +080072static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
73 struct pwm_device *pwm)
Zhi Maoe7c197e2017-06-30 14:05:18 +080074{
Sam Shih25037812019-09-20 06:49:05 +080075 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
Zhi Maoe7c197e2017-06-30 14:05:18 +080076 int ret;
77
Sam Shihefecdeb2019-09-20 06:49:04 +080078 ret = clk_prepare_enable(pc->clk_top);
Zhi Maoe7c197e2017-06-30 14:05:18 +080079 if (ret < 0)
80 return ret;
81
Sam Shihefecdeb2019-09-20 06:49:04 +080082 ret = clk_prepare_enable(pc->clk_main);
Zhi Maoe7c197e2017-06-30 14:05:18 +080083 if (ret < 0)
84 goto disable_clk_top;
85
Sam Shihefecdeb2019-09-20 06:49:04 +080086 ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
Zhi Maoe7c197e2017-06-30 14:05:18 +080087 if (ret < 0)
88 goto disable_clk_main;
89
90 return 0;
91
92disable_clk_main:
Sam Shihefecdeb2019-09-20 06:49:04 +080093 clk_disable_unprepare(pc->clk_main);
Zhi Maoe7c197e2017-06-30 14:05:18 +080094disable_clk_top:
Sam Shihefecdeb2019-09-20 06:49:04 +080095 clk_disable_unprepare(pc->clk_top);
Zhi Maoe7c197e2017-06-30 14:05:18 +080096
97 return ret;
98}
99
Sam Shih25037812019-09-20 06:49:05 +0800100static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
101 struct pwm_device *pwm)
Zhi Maoe7c197e2017-06-30 14:05:18 +0800102{
Sam Shih25037812019-09-20 06:49:05 +0800103 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
Zhi Maoe7c197e2017-06-30 14:05:18 +0800104
Sam Shihefecdeb2019-09-20 06:49:04 +0800105 clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
106 clk_disable_unprepare(pc->clk_main);
107 clk_disable_unprepare(pc->clk_top);
Zhi Maoe7c197e2017-06-30 14:05:18 +0800108}
109
Sam Shih25037812019-09-20 06:49:05 +0800110static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
111 unsigned int num, unsigned int offset,
112 u32 value)
John Crispincaf065f2017-01-23 19:34:37 +0100113{
Sam Shih25037812019-09-20 06:49:05 +0800114 writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
John Crispincaf065f2017-01-23 19:34:37 +0100115}
116
Sam Shih25037812019-09-20 06:49:05 +0800117static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
118 int duty_ns, int period_ns)
John Crispincaf065f2017-01-23 19:34:37 +0100119{
Sam Shih25037812019-09-20 06:49:05 +0800120 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
Sean Wang04c0a4e2018-03-02 16:49:14 +0800121 u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
Sean Wang360cc032018-03-01 16:19:12 +0800122 reg_thres = PWMTHRES;
Sean Wang04c0a4e2018-03-02 16:49:14 +0800123 u64 resolution;
Zhi Maoe7c197e2017-06-30 14:05:18 +0800124 int ret;
125
Sam Shih25037812019-09-20 06:49:05 +0800126 ret = pwm_mediatek_clk_enable(chip, pwm);
127
Zhi Maoe7c197e2017-06-30 14:05:18 +0800128 if (ret < 0)
129 return ret;
John Crispincaf065f2017-01-23 19:34:37 +0100130
Fabien Parent0c0ead72020-10-19 16:07:02 +0200131 /* Make sure we use the bus clock and not the 26MHz clock */
132 if (pc->soc->has_ck_26m_sel)
133 writel(0, pc->regs + PWM_CK_26M_SEL);
134
Sean Wang04c0a4e2018-03-02 16:49:14 +0800135 /* Using resolution in picosecond gets accuracy higher */
136 resolution = (u64)NSEC_PER_SEC * 1000;
Sam Shih25037812019-09-20 06:49:05 +0800137 do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));
John Crispincaf065f2017-01-23 19:34:37 +0100138
Sean Wang04c0a4e2018-03-02 16:49:14 +0800139 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
140 while (cnt_period > 8191) {
John Crispincaf065f2017-01-23 19:34:37 +0100141 resolution *= 2;
142 clkdiv++;
Sean Wang04c0a4e2018-03-02 16:49:14 +0800143 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
144 resolution);
John Crispincaf065f2017-01-23 19:34:37 +0100145 }
146
Zhi Mao8bdb65d2017-06-30 14:05:20 +0800147 if (clkdiv > PWM_CLK_DIV_MAX) {
Sam Shih25037812019-09-20 06:49:05 +0800148 pwm_mediatek_clk_disable(chip, pwm);
Zhi Mao8bdb65d2017-06-30 14:05:20 +0800149 dev_err(chip->dev, "period %d not supported\n", period_ns);
John Crispincaf065f2017-01-23 19:34:37 +0100150 return -EINVAL;
Zhi Mao8bdb65d2017-06-30 14:05:20 +0800151 }
John Crispincaf065f2017-01-23 19:34:37 +0100152
Sean Wang360cc032018-03-01 16:19:12 +0800153 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
154 /*
155 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
156 * from the other PWMs on MT7623.
157 */
158 reg_width = PWM45DWIDTH_FIXUP;
159 reg_thres = PWM45THRES_FIXUP;
160 }
161
Sean Wang04c0a4e2018-03-02 16:49:14 +0800162 cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
Sam Shih25037812019-09-20 06:49:05 +0800163 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
164 pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
165 pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
John Crispincaf065f2017-01-23 19:34:37 +0100166
Sam Shih25037812019-09-20 06:49:05 +0800167 pwm_mediatek_clk_disable(chip, pwm);
Zhi Maoe7c197e2017-06-30 14:05:18 +0800168
John Crispincaf065f2017-01-23 19:34:37 +0100169 return 0;
170}
171
Sam Shih25037812019-09-20 06:49:05 +0800172static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)
John Crispincaf065f2017-01-23 19:34:37 +0100173{
Sam Shih25037812019-09-20 06:49:05 +0800174 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
John Crispincaf065f2017-01-23 19:34:37 +0100175 u32 value;
176 int ret;
177
Sam Shih25037812019-09-20 06:49:05 +0800178 ret = pwm_mediatek_clk_enable(chip, pwm);
John Crispincaf065f2017-01-23 19:34:37 +0100179 if (ret < 0)
180 return ret;
181
182 value = readl(pc->regs);
183 value |= BIT(pwm->hwpwm);
184 writel(value, pc->regs);
185
186 return 0;
187}
188
Sam Shih25037812019-09-20 06:49:05 +0800189static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm)
John Crispincaf065f2017-01-23 19:34:37 +0100190{
Sam Shih25037812019-09-20 06:49:05 +0800191 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
John Crispincaf065f2017-01-23 19:34:37 +0100192 u32 value;
193
194 value = readl(pc->regs);
195 value &= ~BIT(pwm->hwpwm);
196 writel(value, pc->regs);
197
Sam Shih25037812019-09-20 06:49:05 +0800198 pwm_mediatek_clk_disable(chip, pwm);
John Crispincaf065f2017-01-23 19:34:37 +0100199}
200
Sam Shih25037812019-09-20 06:49:05 +0800201static const struct pwm_ops pwm_mediatek_ops = {
202 .config = pwm_mediatek_config,
203 .enable = pwm_mediatek_enable,
204 .disable = pwm_mediatek_disable,
John Crispincaf065f2017-01-23 19:34:37 +0100205 .owner = THIS_MODULE,
206};
207
Sam Shih25037812019-09-20 06:49:05 +0800208static int pwm_mediatek_probe(struct platform_device *pdev)
John Crispincaf065f2017-01-23 19:34:37 +0100209{
Sam Shih25037812019-09-20 06:49:05 +0800210 struct pwm_mediatek_chip *pc;
John Crispincaf065f2017-01-23 19:34:37 +0100211 unsigned int i;
212 int ret;
213
214 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
215 if (!pc)
216 return -ENOMEM;
217
Sam Shihe6c7c252019-09-20 06:49:02 +0800218 pc->soc = of_device_get_match_data(&pdev->dev);
Zhi Mao424268c2017-10-25 18:11:01 +0800219
Yangtao Li7681c2b2019-12-29 08:05:45 +0000220 pc->regs = devm_platform_ioremap_resource(pdev, 0);
John Crispincaf065f2017-01-23 19:34:37 +0100221 if (IS_ERR(pc->regs))
222 return PTR_ERR(pc->regs);
223
Sam Shihefecdeb2019-09-20 06:49:04 +0800224 pc->clk_pwms = devm_kcalloc(&pdev->dev, pc->soc->num_pwms,
225 sizeof(*pc->clk_pwms), GFP_KERNEL);
226 if (!pc->clk_pwms)
227 return -ENOMEM;
228
229 pc->clk_top = devm_clk_get(&pdev->dev, "top");
230 if (IS_ERR(pc->clk_top)) {
231 dev_err(&pdev->dev, "clock: top fail: %ld\n",
232 PTR_ERR(pc->clk_top));
233 return PTR_ERR(pc->clk_top);
234 }
235
236 pc->clk_main = devm_clk_get(&pdev->dev, "main");
237 if (IS_ERR(pc->clk_main)) {
238 dev_err(&pdev->dev, "clock: main fail: %ld\n",
239 PTR_ERR(pc->clk_main));
240 return PTR_ERR(pc->clk_main);
241 }
242
243 for (i = 0; i < pc->soc->num_pwms; i++) {
244 char name[8];
245
246 snprintf(name, sizeof(name), "pwm%d", i + 1);
247
248 pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
249 if (IS_ERR(pc->clk_pwms[i])) {
Zhi Mao424268c2017-10-25 18:11:01 +0800250 dev_err(&pdev->dev, "clock: %s fail: %ld\n",
Sam Shihefecdeb2019-09-20 06:49:04 +0800251 name, PTR_ERR(pc->clk_pwms[i]));
252 return PTR_ERR(pc->clk_pwms[i]);
Zhi Mao424268c2017-10-25 18:11:01 +0800253 }
John Crispincaf065f2017-01-23 19:34:37 +0100254 }
255
John Crispincaf065f2017-01-23 19:34:37 +0100256 platform_set_drvdata(pdev, pc);
257
258 pc->chip.dev = &pdev->dev;
Sam Shih25037812019-09-20 06:49:05 +0800259 pc->chip.ops = &pwm_mediatek_ops;
Sam Shihe6c7c252019-09-20 06:49:02 +0800260 pc->chip.npwm = pc->soc->num_pwms;
John Crispincaf065f2017-01-23 19:34:37 +0100261
262 ret = pwmchip_add(&pc->chip);
263 if (ret < 0) {
264 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
Zhi Maoe7c197e2017-06-30 14:05:18 +0800265 return ret;
John Crispincaf065f2017-01-23 19:34:37 +0100266 }
267
268 return 0;
John Crispincaf065f2017-01-23 19:34:37 +0100269}
270
Sam Shih25037812019-09-20 06:49:05 +0800271static int pwm_mediatek_remove(struct platform_device *pdev)
John Crispincaf065f2017-01-23 19:34:37 +0100272{
Sam Shih25037812019-09-20 06:49:05 +0800273 struct pwm_mediatek_chip *pc = platform_get_drvdata(pdev);
John Crispincaf065f2017-01-23 19:34:37 +0100274
275 return pwmchip_remove(&pc->chip);
276}
277
Sam Shih25037812019-09-20 06:49:05 +0800278static const struct pwm_mediatek_of_data mt2712_pwm_data = {
Zhi Mao424268c2017-10-25 18:11:01 +0800279 .num_pwms = 8,
Sean Wang360cc032018-03-01 16:19:12 +0800280 .pwm45_fixup = false,
Fabien Parent0c0ead72020-10-19 16:07:02 +0200281 .has_ck_26m_sel = false,
Zhi Mao424268c2017-10-25 18:11:01 +0800282};
283
Sam Shih25037812019-09-20 06:49:05 +0800284static const struct pwm_mediatek_of_data mt7622_pwm_data = {
Zhi Mao424268c2017-10-25 18:11:01 +0800285 .num_pwms = 6,
Sean Wang360cc032018-03-01 16:19:12 +0800286 .pwm45_fixup = false,
Fabien Parent0c0ead72020-10-19 16:07:02 +0200287 .has_ck_26m_sel = false,
Zhi Mao424268c2017-10-25 18:11:01 +0800288};
289
Sam Shih25037812019-09-20 06:49:05 +0800290static const struct pwm_mediatek_of_data mt7623_pwm_data = {
Zhi Mao424268c2017-10-25 18:11:01 +0800291 .num_pwms = 5,
Sean Wang360cc032018-03-01 16:19:12 +0800292 .pwm45_fixup = true,
Fabien Parent0c0ead72020-10-19 16:07:02 +0200293 .has_ck_26m_sel = false,
John Crispin8cdc43a2018-07-25 11:52:09 +0200294};
295
Sam Shih25037812019-09-20 06:49:05 +0800296static const struct pwm_mediatek_of_data mt7628_pwm_data = {
John Crispin8cdc43a2018-07-25 11:52:09 +0200297 .num_pwms = 4,
298 .pwm45_fixup = true,
Fabien Parent0c0ead72020-10-19 16:07:02 +0200299 .has_ck_26m_sel = false,
Zhi Mao424268c2017-10-25 18:11:01 +0800300};
301
Sam Shih715d14d2019-09-25 22:32:33 +0800302static const struct pwm_mediatek_of_data mt7629_pwm_data = {
303 .num_pwms = 1,
304 .pwm45_fixup = false,
Fabien Parent0c0ead72020-10-19 16:07:02 +0200305 .has_ck_26m_sel = false,
Sam Shih715d14d2019-09-25 22:32:33 +0800306};
307
Fabien Parent8b2fbae2020-10-19 16:07:03 +0200308static const struct pwm_mediatek_of_data mt8183_pwm_data = {
309 .num_pwms = 4,
310 .pwm45_fixup = false,
311 .has_ck_26m_sel = true,
312};
313
Sam Shih25037812019-09-20 06:49:05 +0800314static const struct pwm_mediatek_of_data mt8516_pwm_data = {
Fabien Parent8d190722019-08-05 14:58:48 +0200315 .num_pwms = 5,
316 .pwm45_fixup = false,
Fabien Parent0c0ead72020-10-19 16:07:02 +0200317 .has_ck_26m_sel = true,
Fabien Parent8d190722019-08-05 14:58:48 +0200318};
319
Sam Shih25037812019-09-20 06:49:05 +0800320static const struct of_device_id pwm_mediatek_of_match[] = {
Zhi Mao424268c2017-10-25 18:11:01 +0800321 { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
322 { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
323 { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
John Crispin8cdc43a2018-07-25 11:52:09 +0200324 { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
Sam Shih715d14d2019-09-25 22:32:33 +0800325 { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
Fabien Parent8b2fbae2020-10-19 16:07:03 +0200326 { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
Fabien Parent8d190722019-08-05 14:58:48 +0200327 { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
Zhi Mao424268c2017-10-25 18:11:01 +0800328 { },
John Crispincaf065f2017-01-23 19:34:37 +0100329};
Sam Shih25037812019-09-20 06:49:05 +0800330MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);
John Crispincaf065f2017-01-23 19:34:37 +0100331
Sam Shih25037812019-09-20 06:49:05 +0800332static struct platform_driver pwm_mediatek_driver = {
John Crispincaf065f2017-01-23 19:34:37 +0100333 .driver = {
Sam Shih25037812019-09-20 06:49:05 +0800334 .name = "pwm-mediatek",
335 .of_match_table = pwm_mediatek_of_match,
John Crispincaf065f2017-01-23 19:34:37 +0100336 },
Sam Shih25037812019-09-20 06:49:05 +0800337 .probe = pwm_mediatek_probe,
338 .remove = pwm_mediatek_remove,
John Crispincaf065f2017-01-23 19:34:37 +0100339};
Sam Shih25037812019-09-20 06:49:05 +0800340module_platform_driver(pwm_mediatek_driver);
John Crispincaf065f2017-01-23 19:34:37 +0100341
342MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
Sam Shih4bea6dd2019-09-20 06:49:06 +0800343MODULE_LICENSE("GPL v2");