blob: 82b415be18d1ff4ac04516f13e561446a33d3d9b [file] [log] [blame]
Thomas Gleixner714c29cf2019-06-04 10:11:04 +02001// SPDX-License-Identifier: GPL-2.0-only
Markus Mayer2f330ca2017-08-24 16:36:26 -07002/*
3 * DDR PHY Front End (DPFE) driver for Broadcom set top box SoCs
4 *
5 * Copyright (c) 2017 Broadcom
Markus Mayer2f330ca2017-08-24 16:36:26 -07006 */
7
8/*
9 * This driver provides access to the DPFE interface of Broadcom STB SoCs.
10 * The firmware running on the DCPU inside the DDR PHY can provide current
11 * information about the system's RAM, for instance the DRAM refresh rate.
12 * This can be used as an indirect indicator for the DRAM's temperature.
13 * Slower refresh rate means cooler RAM, higher refresh rate means hotter
14 * RAM.
15 *
16 * Throughout the driver, we use readl_relaxed() and writel_relaxed(), which
17 * already contain the appropriate le32_to_cpu()/cpu_to_le32() calls.
18 *
19 * Note regarding the loading of the firmware image: we use be32_to_cpu()
20 * and le_32_to_cpu(), so we can support the following four cases:
21 * - LE kernel + LE firmware image (the most common case)
22 * - LE kernel + BE firmware image
23 * - BE kernel + LE firmware image
24 * - BE kernel + BE firmware image
25 *
26 * The DPCU always runs in big endian mode. The firwmare image, however, can
27 * be in either format. Also, communication between host CPU and DCPU is
28 * always in little endian.
29 */
30
31#include <linux/delay.h>
32#include <linux/firmware.h>
33#include <linux/io.h>
34#include <linux/module.h>
35#include <linux/of_address.h>
Markus Mayer58a84992019-04-02 16:01:01 -070036#include <linux/of_device.h>
Markus Mayer2f330ca2017-08-24 16:36:26 -070037#include <linux/platform_device.h>
38
39#define DRVNAME "brcmstb-dpfe"
Markus Mayer2f330ca2017-08-24 16:36:26 -070040
41/* DCPU register offsets */
42#define REG_DCPU_RESET 0x0
43#define REG_TO_DCPU_MBOX 0x10
44#define REG_TO_HOST_MBOX 0x14
45
Markus Mayerfee5f1e2018-02-13 12:40:40 -080046/* Macros to process offsets returned by the DCPU */
47#define DRAM_MSG_ADDR_OFFSET 0x0
48#define DRAM_MSG_TYPE_OFFSET 0x1c
49#define DRAM_MSG_ADDR_MASK ((1UL << DRAM_MSG_TYPE_OFFSET) - 1)
50#define DRAM_MSG_TYPE_MASK ((1UL << \
51 (BITS_PER_LONG - DRAM_MSG_TYPE_OFFSET)) - 1)
52
Markus Mayer2f330ca2017-08-24 16:36:26 -070053/* Message RAM */
Markus Mayerfee5f1e2018-02-13 12:40:40 -080054#define DCPU_MSG_RAM_START 0x100
55#define DCPU_MSG_RAM(x) (DCPU_MSG_RAM_START + (x) * sizeof(u32))
Markus Mayer2f330ca2017-08-24 16:36:26 -070056
57/* DRAM Info Offsets & Masks */
58#define DRAM_INFO_INTERVAL 0x0
59#define DRAM_INFO_MR4 0x4
60#define DRAM_INFO_ERROR 0x8
61#define DRAM_INFO_MR4_MASK 0xff
Markus Mayer78a6f5b2019-02-11 17:24:43 -080062#define DRAM_INFO_MR4_SHIFT 24 /* We need to look at byte 3 */
Markus Mayer2f330ca2017-08-24 16:36:26 -070063
64/* DRAM MR4 Offsets & Masks */
65#define DRAM_MR4_REFRESH 0x0 /* Refresh rate */
66#define DRAM_MR4_SR_ABORT 0x3 /* Self Refresh Abort */
67#define DRAM_MR4_PPRE 0x4 /* Post-package repair entry/exit */
68#define DRAM_MR4_TH_OFFS 0x5 /* Thermal Offset; vendor specific */
69#define DRAM_MR4_TUF 0x7 /* Temperature Update Flag */
70
71#define DRAM_MR4_REFRESH_MASK 0x7
72#define DRAM_MR4_SR_ABORT_MASK 0x1
73#define DRAM_MR4_PPRE_MASK 0x1
74#define DRAM_MR4_TH_OFFS_MASK 0x3
75#define DRAM_MR4_TUF_MASK 0x1
76
Markus Mayere3b74722019-04-02 16:01:03 -070077/* DRAM Vendor Offsets & Masks (API v2) */
Markus Mayer2f330ca2017-08-24 16:36:26 -070078#define DRAM_VENDOR_MR5 0x0
79#define DRAM_VENDOR_MR6 0x4
80#define DRAM_VENDOR_MR7 0x8
81#define DRAM_VENDOR_MR8 0xc
82#define DRAM_VENDOR_ERROR 0x10
83#define DRAM_VENDOR_MASK 0xff
Markus Mayer78a6f5b2019-02-11 17:24:43 -080084#define DRAM_VENDOR_SHIFT 24 /* We need to look at byte 3 */
Markus Mayer2f330ca2017-08-24 16:36:26 -070085
Markus Mayere3b74722019-04-02 16:01:03 -070086/* DRAM Information Offsets & Masks (API v3) */
87#define DRAM_DDR_INFO_MR4 0x0
88#define DRAM_DDR_INFO_MR5 0x4
89#define DRAM_DDR_INFO_MR6 0x8
90#define DRAM_DDR_INFO_MR7 0xc
91#define DRAM_DDR_INFO_MR8 0x10
92#define DRAM_DDR_INFO_ERROR 0x14
93#define DRAM_DDR_INFO_MASK 0xff
Markus Mayer2f330ca2017-08-24 16:36:26 -070094
95/* Reset register bits & masks */
96#define DCPU_RESET_SHIFT 0x0
97#define DCPU_RESET_MASK 0x1
98#define DCPU_CLK_DISABLE_SHIFT 0x2
99
100/* DCPU return codes */
101#define DCPU_RET_ERROR_BIT BIT(31)
102#define DCPU_RET_SUCCESS 0x1
103#define DCPU_RET_ERR_HEADER (DCPU_RET_ERROR_BIT | BIT(0))
104#define DCPU_RET_ERR_INVAL (DCPU_RET_ERROR_BIT | BIT(1))
105#define DCPU_RET_ERR_CHKSUM (DCPU_RET_ERROR_BIT | BIT(2))
106#define DCPU_RET_ERR_COMMAND (DCPU_RET_ERROR_BIT | BIT(3))
107/* This error code is not firmware defined and only used in the driver. */
108#define DCPU_RET_ERR_TIMEDOUT (DCPU_RET_ERROR_BIT | BIT(4))
109
110/* Firmware magic */
111#define DPFE_BE_MAGIC 0xfe1010fe
112#define DPFE_LE_MAGIC 0xfe0101fe
113
114/* Error codes */
115#define ERR_INVALID_MAGIC -1
116#define ERR_INVALID_SIZE -2
117#define ERR_INVALID_CHKSUM -3
118
119/* Message types */
120#define DPFE_MSG_TYPE_COMMAND 1
121#define DPFE_MSG_TYPE_RESPONSE 2
122
Markus Mayer7ccd2ff2019-02-11 17:24:41 -0800123#define DELAY_LOOP_MAX 1000
Markus Mayer2f330ca2017-08-24 16:36:26 -0700124
125enum dpfe_msg_fields {
126 MSG_HEADER,
127 MSG_COMMAND,
128 MSG_ARG_COUNT,
129 MSG_ARG0,
Markus Mayere3b74722019-04-02 16:01:03 -0700130 MSG_FIELD_MAX = 16 /* Max number of arguments */
Markus Mayer2f330ca2017-08-24 16:36:26 -0700131};
132
133enum dpfe_commands {
134 DPFE_CMD_GET_INFO,
135 DPFE_CMD_GET_REFRESH,
136 DPFE_CMD_GET_VENDOR,
137 DPFE_CMD_MAX /* Last entry */
138};
139
Markus Mayer2f330ca2017-08-24 16:36:26 -0700140/*
141 * Format of the binary firmware file:
142 *
143 * entry
144 * 0 header
145 * value: 0xfe0101fe <== little endian
146 * 0xfe1010fe <== big endian
147 * 1 sequence:
148 * [31:16] total segments on this build
149 * [15:0] this segment sequence.
150 * 2 FW version
151 * 3 IMEM byte size
152 * 4 DMEM byte size
153 * IMEM
154 * DMEM
155 * last checksum ==> sum of everything
156 */
157struct dpfe_firmware_header {
158 u32 magic;
159 u32 sequence;
160 u32 version;
161 u32 imem_size;
162 u32 dmem_size;
163};
164
165/* Things we only need during initialization. */
166struct init_data {
167 unsigned int dmem_len;
168 unsigned int imem_len;
169 unsigned int chksum;
170 bool is_big_endian;
171};
172
Markus Mayer58a84992019-04-02 16:01:01 -0700173/* API version and corresponding commands */
174struct dpfe_api {
175 int version;
176 const char *fw_name;
Markus Mayer5ef108b2019-04-02 16:01:02 -0700177 const struct attribute_group **sysfs_attrs;
Markus Mayer58a84992019-04-02 16:01:01 -0700178 u32 command[DPFE_CMD_MAX][MSG_FIELD_MAX];
179};
180
Markus Mayer2f330ca2017-08-24 16:36:26 -0700181/* Things we need for as long as we are active. */
Markus Mayerabf94562019-10-15 15:45:06 -0700182struct brcmstb_dpfe_priv {
Markus Mayer2f330ca2017-08-24 16:36:26 -0700183 void __iomem *regs;
184 void __iomem *dmem;
185 void __iomem *imem;
186 struct device *dev;
Markus Mayer58a84992019-04-02 16:01:01 -0700187 const struct dpfe_api *dpfe_api;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700188 struct mutex lock;
189};
190
191static const char *error_text[] = {
192 "Success", "Header code incorrect", "Unknown command or argument",
193 "Incorrect checksum", "Malformed command", "Timed out",
194};
195
Markus Mayer5ef108b2019-04-02 16:01:02 -0700196/*
197 * Forward declaration of our sysfs attribute functions, so we can declare the
198 * attribute data structures early.
199 */
200static ssize_t show_info(struct device *, struct device_attribute *, char *);
201static ssize_t show_refresh(struct device *, struct device_attribute *, char *);
202static ssize_t store_refresh(struct device *, struct device_attribute *,
203 const char *, size_t);
204static ssize_t show_vendor(struct device *, struct device_attribute *, char *);
Markus Mayere3b74722019-04-02 16:01:03 -0700205static ssize_t show_dram(struct device *, struct device_attribute *, char *);
Markus Mayer5ef108b2019-04-02 16:01:02 -0700206
207/*
208 * Declare our attributes early, so they can be referenced in the API data
209 * structure. We need to do this, because the attributes depend on the API
210 * version.
211 */
212static DEVICE_ATTR(dpfe_info, 0444, show_info, NULL);
213static DEVICE_ATTR(dpfe_refresh, 0644, show_refresh, store_refresh);
214static DEVICE_ATTR(dpfe_vendor, 0444, show_vendor, NULL);
Markus Mayere3b74722019-04-02 16:01:03 -0700215static DEVICE_ATTR(dpfe_dram, 0444, show_dram, NULL);
Markus Mayer5ef108b2019-04-02 16:01:02 -0700216
217/* API v2 sysfs attributes */
218static struct attribute *dpfe_v2_attrs[] = {
219 &dev_attr_dpfe_info.attr,
220 &dev_attr_dpfe_refresh.attr,
221 &dev_attr_dpfe_vendor.attr,
222 NULL
223};
224ATTRIBUTE_GROUPS(dpfe_v2);
225
Markus Mayere3b74722019-04-02 16:01:03 -0700226/* API v3 sysfs attributes */
227static struct attribute *dpfe_v3_attrs[] = {
228 &dev_attr_dpfe_info.attr,
229 &dev_attr_dpfe_dram.attr,
230 NULL
231};
232ATTRIBUTE_GROUPS(dpfe_v3);
233
Florian Fainellib61d3e82019-10-15 15:45:13 -0700234/*
235 * Old API v2 firmware commands, as defined in the rev 0.61 specification, we
236 * use a version set to 1 to denote that it is not compatible with the new API
237 * v2 and onwards.
238 */
239static const struct dpfe_api dpfe_api_old_v2 = {
240 .version = 1,
Markus Mayer58a84992019-04-02 16:01:01 -0700241 .fw_name = "dpfe.bin",
Markus Mayer5ef108b2019-04-02 16:01:02 -0700242 .sysfs_attrs = dpfe_v2_groups,
Markus Mayer58a84992019-04-02 16:01:01 -0700243 .command = {
244 [DPFE_CMD_GET_INFO] = {
245 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
246 [MSG_COMMAND] = 1,
247 [MSG_ARG_COUNT] = 1,
248 [MSG_ARG0] = 1,
Markus Mayer58a84992019-04-02 16:01:01 -0700249 },
250 [DPFE_CMD_GET_REFRESH] = {
251 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
252 [MSG_COMMAND] = 2,
253 [MSG_ARG_COUNT] = 1,
254 [MSG_ARG0] = 1,
Markus Mayer58a84992019-04-02 16:01:01 -0700255 },
256 [DPFE_CMD_GET_VENDOR] = {
257 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
258 [MSG_COMMAND] = 2,
259 [MSG_ARG_COUNT] = 1,
260 [MSG_ARG0] = 2,
Markus Mayer58a84992019-04-02 16:01:01 -0700261 },
262 }
Markus Mayer2f330ca2017-08-24 16:36:26 -0700263};
264
Florian Fainellib61d3e82019-10-15 15:45:13 -0700265/*
266 * API v2 firmware commands, as defined in the rev 0.8 specification, named new
267 * v2 here
268 */
269static const struct dpfe_api dpfe_api_new_v2 = {
270 .version = 2,
271 .fw_name = NULL, /* We expect the firmware to have been downloaded! */
272 .sysfs_attrs = dpfe_v2_groups,
273 .command = {
274 [DPFE_CMD_GET_INFO] = {
275 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
276 [MSG_COMMAND] = 0x101,
277 },
278 [DPFE_CMD_GET_REFRESH] = {
279 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
280 [MSG_COMMAND] = 0x201,
281 },
282 [DPFE_CMD_GET_VENDOR] = {
283 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
284 [MSG_COMMAND] = 0x202,
285 },
286 }
287};
288
Markus Mayere3b74722019-04-02 16:01:03 -0700289/* API v3 firmware commands */
290static const struct dpfe_api dpfe_api_v3 = {
291 .version = 3,
292 .fw_name = NULL, /* We expect the firmware to have been downloaded! */
293 .sysfs_attrs = dpfe_v3_groups,
294 .command = {
295 [DPFE_CMD_GET_INFO] = {
296 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
297 [MSG_COMMAND] = 0x0101,
298 [MSG_ARG_COUNT] = 1,
299 [MSG_ARG0] = 1,
Markus Mayere3b74722019-04-02 16:01:03 -0700300 },
301 [DPFE_CMD_GET_REFRESH] = {
302 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
303 [MSG_COMMAND] = 0x0202,
304 [MSG_ARG_COUNT] = 0,
Markus Mayere3b74722019-04-02 16:01:03 -0700305 },
306 /* There's no GET_VENDOR command in API v3. */
Markus Mayer2f330ca2017-08-24 16:36:26 -0700307 },
308};
309
Markus Mayer75d316e2019-10-15 15:45:08 -0700310static bool is_dcpu_enabled(struct brcmstb_dpfe_priv *priv)
Markus Mayerd56e7462017-10-02 16:13:46 -0700311{
312 u32 val;
313
Markus Mayer75d316e2019-10-15 15:45:08 -0700314 mutex_lock(&priv->lock);
315 val = readl_relaxed(priv->regs + REG_DCPU_RESET);
316 mutex_unlock(&priv->lock);
Markus Mayerd56e7462017-10-02 16:13:46 -0700317
318 return !(val & DCPU_RESET_MASK);
319}
320
Markus Mayer75d316e2019-10-15 15:45:08 -0700321static void __disable_dcpu(struct brcmstb_dpfe_priv *priv)
Markus Mayer2f330ca2017-08-24 16:36:26 -0700322{
323 u32 val;
324
Markus Mayer75d316e2019-10-15 15:45:08 -0700325 if (!is_dcpu_enabled(priv))
Markus Mayerd56e7462017-10-02 16:13:46 -0700326 return;
327
Markus Mayer75d316e2019-10-15 15:45:08 -0700328 mutex_lock(&priv->lock);
329
Markus Mayerd56e7462017-10-02 16:13:46 -0700330 /* Put DCPU in reset if it's running. */
Markus Mayer75d316e2019-10-15 15:45:08 -0700331 val = readl_relaxed(priv->regs + REG_DCPU_RESET);
Markus Mayerd56e7462017-10-02 16:13:46 -0700332 val |= (1 << DCPU_RESET_SHIFT);
Markus Mayer75d316e2019-10-15 15:45:08 -0700333 writel_relaxed(val, priv->regs + REG_DCPU_RESET);
334
335 mutex_unlock(&priv->lock);
Markus Mayer2f330ca2017-08-24 16:36:26 -0700336}
337
Markus Mayer75d316e2019-10-15 15:45:08 -0700338static void __enable_dcpu(struct brcmstb_dpfe_priv *priv)
Markus Mayer2f330ca2017-08-24 16:36:26 -0700339{
Markus Mayer75d316e2019-10-15 15:45:08 -0700340 void __iomem *regs = priv->regs;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700341 u32 val;
342
Markus Mayer75d316e2019-10-15 15:45:08 -0700343 mutex_lock(&priv->lock);
344
Markus Mayer2f330ca2017-08-24 16:36:26 -0700345 /* Clear mailbox registers. */
346 writel_relaxed(0, regs + REG_TO_DCPU_MBOX);
347 writel_relaxed(0, regs + REG_TO_HOST_MBOX);
348
349 /* Disable DCPU clock gating */
350 val = readl_relaxed(regs + REG_DCPU_RESET);
351 val &= ~(1 << DCPU_CLK_DISABLE_SHIFT);
352 writel_relaxed(val, regs + REG_DCPU_RESET);
353
354 /* Take DCPU out of reset */
355 val = readl_relaxed(regs + REG_DCPU_RESET);
356 val &= ~(1 << DCPU_RESET_SHIFT);
357 writel_relaxed(val, regs + REG_DCPU_RESET);
Markus Mayer75d316e2019-10-15 15:45:08 -0700358
359 mutex_unlock(&priv->lock);
Markus Mayer2f330ca2017-08-24 16:36:26 -0700360}
361
Markus Mayere3b74722019-04-02 16:01:03 -0700362static unsigned int get_msg_chksum(const u32 msg[], unsigned int max)
Markus Mayer2f330ca2017-08-24 16:36:26 -0700363{
364 unsigned int sum = 0;
365 unsigned int i;
366
367 /* Don't include the last field in the checksum. */
Markus Mayere3b74722019-04-02 16:01:03 -0700368 for (i = 0; i < max; i++)
Markus Mayer2f330ca2017-08-24 16:36:26 -0700369 sum += msg[i];
370
371 return sum;
372}
373
Markus Mayerabf94562019-10-15 15:45:06 -0700374static void __iomem *get_msg_ptr(struct brcmstb_dpfe_priv *priv, u32 response,
Markus Mayerfee5f1e2018-02-13 12:40:40 -0800375 char *buf, ssize_t *size)
376{
377 unsigned int msg_type;
378 unsigned int offset;
379 void __iomem *ptr = NULL;
380
Markus Mayere3b74722019-04-02 16:01:03 -0700381 /* There is no need to use this function for API v3 or later. */
382 if (unlikely(priv->dpfe_api->version >= 3)) {
383 return NULL;
384 }
385
Markus Mayerfee5f1e2018-02-13 12:40:40 -0800386 msg_type = (response >> DRAM_MSG_TYPE_OFFSET) & DRAM_MSG_TYPE_MASK;
387 offset = (response >> DRAM_MSG_ADDR_OFFSET) & DRAM_MSG_ADDR_MASK;
388
389 /*
390 * msg_type == 1: the offset is relative to the message RAM
391 * msg_type == 0: the offset is relative to the data RAM (this is the
392 * previous way of passing data)
393 * msg_type is anything else: there's critical hardware problem
394 */
395 switch (msg_type) {
396 case 1:
397 ptr = priv->regs + DCPU_MSG_RAM_START + offset;
398 break;
399 case 0:
400 ptr = priv->dmem + offset;
401 break;
402 default:
403 dev_emerg(priv->dev, "invalid message reply from DCPU: %#x\n",
404 response);
405 if (buf && size)
406 *size = sprintf(buf,
407 "FATAL: communication error with DCPU\n");
408 }
409
410 return ptr;
411}
412
Markus Mayerabf94562019-10-15 15:45:06 -0700413static void __finalize_command(struct brcmstb_dpfe_priv *priv)
Markus Mayere3b74722019-04-02 16:01:03 -0700414{
415 unsigned int release_mbox;
416
417 /*
418 * It depends on the API version which MBOX register we have to write to
419 * to signal we are done.
420 */
Florian Fainellib61d3e82019-10-15 15:45:13 -0700421 release_mbox = (priv->dpfe_api->version < 2)
Markus Mayere3b74722019-04-02 16:01:03 -0700422 ? REG_TO_HOST_MBOX : REG_TO_DCPU_MBOX;
423 writel_relaxed(0, priv->regs + release_mbox);
424}
425
Markus Mayerabf94562019-10-15 15:45:06 -0700426static int __send_command(struct brcmstb_dpfe_priv *priv, unsigned int cmd,
Markus Mayer2f330ca2017-08-24 16:36:26 -0700427 u32 result[])
428{
Markus Mayer58a84992019-04-02 16:01:01 -0700429 const u32 *msg = priv->dpfe_api->command[cmd];
Markus Mayer2f330ca2017-08-24 16:36:26 -0700430 void __iomem *regs = priv->regs;
Markus Mayere3b74722019-04-02 16:01:03 -0700431 unsigned int i, chksum, chksum_idx;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700432 int ret = 0;
433 u32 resp;
434
435 if (cmd >= DPFE_CMD_MAX)
436 return -1;
437
438 mutex_lock(&priv->lock);
439
Markus Mayera7c25752019-04-02 16:01:00 -0700440 /* Wait for DCPU to become ready */
441 for (i = 0; i < DELAY_LOOP_MAX; i++) {
442 resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
443 if (resp == 0)
444 break;
445 msleep(1);
446 }
447 if (resp != 0) {
448 mutex_unlock(&priv->lock);
449 return -ETIMEDOUT;
450 }
451
Florian Fainelli5d06f532019-10-15 15:45:12 -0700452 /* Compute checksum over the message */
453 chksum_idx = msg[MSG_ARG_COUNT] + MSG_ARG_COUNT + 1;
454 chksum = get_msg_chksum(msg, chksum_idx);
455
Markus Mayer2f330ca2017-08-24 16:36:26 -0700456 /* Write command and arguments to message area */
Florian Fainelli5d06f532019-10-15 15:45:12 -0700457 for (i = 0; i < MSG_FIELD_MAX; i++) {
458 if (i == chksum_idx)
459 writel_relaxed(chksum, regs + DCPU_MSG_RAM(i));
460 else
461 writel_relaxed(msg[i], regs + DCPU_MSG_RAM(i));
462 }
Markus Mayer2f330ca2017-08-24 16:36:26 -0700463
464 /* Tell DCPU there is a command waiting */
465 writel_relaxed(1, regs + REG_TO_DCPU_MBOX);
466
467 /* Wait for DCPU to process the command */
468 for (i = 0; i < DELAY_LOOP_MAX; i++) {
469 /* Read response code */
470 resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
471 if (resp > 0)
472 break;
Markus Mayer7ccd2ff2019-02-11 17:24:41 -0800473 msleep(1);
Markus Mayer2f330ca2017-08-24 16:36:26 -0700474 }
475
476 if (i == DELAY_LOOP_MAX) {
477 resp = (DCPU_RET_ERR_TIMEDOUT & ~DCPU_RET_ERROR_BIT);
478 ret = -ffs(resp);
479 } else {
480 /* Read response data */
481 for (i = 0; i < MSG_FIELD_MAX; i++)
482 result[i] = readl_relaxed(regs + DCPU_MSG_RAM(i));
Markus Mayere3b74722019-04-02 16:01:03 -0700483 chksum_idx = result[MSG_ARG_COUNT] + MSG_ARG_COUNT + 1;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700484 }
485
486 /* Tell DCPU we are done */
Markus Mayere3b74722019-04-02 16:01:03 -0700487 __finalize_command(priv);
Markus Mayer2f330ca2017-08-24 16:36:26 -0700488
489 mutex_unlock(&priv->lock);
490
491 if (ret)
492 return ret;
493
494 /* Verify response */
Markus Mayere3b74722019-04-02 16:01:03 -0700495 chksum = get_msg_chksum(result, chksum_idx);
496 if (chksum != result[chksum_idx])
Markus Mayer2f330ca2017-08-24 16:36:26 -0700497 resp = DCPU_RET_ERR_CHKSUM;
498
499 if (resp != DCPU_RET_SUCCESS) {
500 resp &= ~DCPU_RET_ERROR_BIT;
501 ret = -ffs(resp);
502 }
503
504 return ret;
505}
506
507/* Ensure that the firmware file loaded meets all the requirements. */
508static int __verify_firmware(struct init_data *init,
509 const struct firmware *fw)
510{
511 const struct dpfe_firmware_header *header = (void *)fw->data;
512 unsigned int dmem_size, imem_size, total_size;
513 bool is_big_endian = false;
514 const u32 *chksum_ptr;
515
516 if (header->magic == DPFE_BE_MAGIC)
517 is_big_endian = true;
518 else if (header->magic != DPFE_LE_MAGIC)
519 return ERR_INVALID_MAGIC;
520
521 if (is_big_endian) {
522 dmem_size = be32_to_cpu(header->dmem_size);
523 imem_size = be32_to_cpu(header->imem_size);
524 } else {
525 dmem_size = le32_to_cpu(header->dmem_size);
526 imem_size = le32_to_cpu(header->imem_size);
527 }
528
529 /* Data and instruction sections are 32 bit words. */
530 if ((dmem_size % sizeof(u32)) != 0 || (imem_size % sizeof(u32)) != 0)
531 return ERR_INVALID_SIZE;
532
533 /*
534 * The header + the data section + the instruction section + the
535 * checksum must be equal to the total firmware size.
536 */
537 total_size = dmem_size + imem_size + sizeof(*header) +
538 sizeof(*chksum_ptr);
539 if (total_size != fw->size)
540 return ERR_INVALID_SIZE;
541
542 /* The checksum comes at the very end. */
543 chksum_ptr = (void *)fw->data + sizeof(*header) + dmem_size + imem_size;
544
545 init->is_big_endian = is_big_endian;
546 init->dmem_len = dmem_size;
547 init->imem_len = imem_size;
548 init->chksum = (is_big_endian)
549 ? be32_to_cpu(*chksum_ptr) : le32_to_cpu(*chksum_ptr);
550
551 return 0;
552}
553
554/* Verify checksum by reading back the firmware from co-processor RAM. */
555static int __verify_fw_checksum(struct init_data *init,
Markus Mayerabf94562019-10-15 15:45:06 -0700556 struct brcmstb_dpfe_priv *priv,
Markus Mayer2f330ca2017-08-24 16:36:26 -0700557 const struct dpfe_firmware_header *header,
558 u32 checksum)
559{
560 u32 magic, sequence, version, sum;
561 u32 __iomem *dmem = priv->dmem;
562 u32 __iomem *imem = priv->imem;
563 unsigned int i;
564
565 if (init->is_big_endian) {
566 magic = be32_to_cpu(header->magic);
567 sequence = be32_to_cpu(header->sequence);
568 version = be32_to_cpu(header->version);
569 } else {
570 magic = le32_to_cpu(header->magic);
571 sequence = le32_to_cpu(header->sequence);
572 version = le32_to_cpu(header->version);
573 }
574
575 sum = magic + sequence + version + init->dmem_len + init->imem_len;
576
577 for (i = 0; i < init->dmem_len / sizeof(u32); i++)
578 sum += readl_relaxed(dmem + i);
579
580 for (i = 0; i < init->imem_len / sizeof(u32); i++)
581 sum += readl_relaxed(imem + i);
582
583 return (sum == checksum) ? 0 : -1;
584}
585
586static int __write_firmware(u32 __iomem *mem, const u32 *fw,
587 unsigned int size, bool is_big_endian)
588{
589 unsigned int i;
590
591 /* Convert size to 32-bit words. */
592 size /= sizeof(u32);
593
594 /* It is recommended to clear the firmware area first. */
595 for (i = 0; i < size; i++)
596 writel_relaxed(0, mem + i);
597
598 /* Now copy it. */
599 if (is_big_endian) {
600 for (i = 0; i < size; i++)
601 writel_relaxed(be32_to_cpu(fw[i]), mem + i);
602 } else {
603 for (i = 0; i < size; i++)
604 writel_relaxed(le32_to_cpu(fw[i]), mem + i);
605 }
606
607 return 0;
608}
609
Markus Mayerac2ea9c2019-10-15 15:45:10 -0700610static int brcmstb_dpfe_download_firmware(struct brcmstb_dpfe_priv *priv)
Markus Mayer2f330ca2017-08-24 16:36:26 -0700611{
612 const struct dpfe_firmware_header *header;
613 unsigned int dmem_size, imem_size;
Markus Mayerac2ea9c2019-10-15 15:45:10 -0700614 struct device *dev = priv->dev;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700615 bool is_big_endian = false;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700616 const struct firmware *fw;
617 const u32 *dmem, *imem;
Markus Mayer6ef972b2019-10-15 15:45:09 -0700618 struct init_data init;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700619 const void *fw_blob;
620 int ret;
621
Markus Mayera56d3392017-10-02 16:13:47 -0700622 /*
623 * Skip downloading the firmware if the DCPU is already running and
624 * responding to commands.
625 */
Markus Mayer75d316e2019-10-15 15:45:08 -0700626 if (is_dcpu_enabled(priv)) {
Markus Mayera56d3392017-10-02 16:13:47 -0700627 u32 response[MSG_FIELD_MAX];
628
629 ret = __send_command(priv, DPFE_CMD_GET_INFO, response);
630 if (!ret)
631 return 0;
632 }
633
Markus Mayer58a84992019-04-02 16:01:01 -0700634 /*
635 * If the firmware filename is NULL it means the boot firmware has to
636 * download the DCPU firmware for us. If that didn't work, we have to
637 * bail, since downloading it ourselves wouldn't work either.
638 */
639 if (!priv->dpfe_api->fw_name)
640 return -ENODEV;
641
Markus Mayer242fb2f2019-10-15 15:45:11 -0700642 ret = firmware_request_nowarn(&fw, priv->dpfe_api->fw_name, dev);
643 /*
644 * Defer the firmware download if the firmware file couldn't be found.
645 * The root file system may not be available yet.
646 */
Markus Mayer2f330ca2017-08-24 16:36:26 -0700647 if (ret)
Markus Mayer242fb2f2019-10-15 15:45:11 -0700648 return (ret == -ENOENT) ? -EPROBE_DEFER : ret;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700649
Markus Mayer6ef972b2019-10-15 15:45:09 -0700650 ret = __verify_firmware(&init, fw);
Markus Mayer2f330ca2017-08-24 16:36:26 -0700651 if (ret)
652 return -EFAULT;
653
Markus Mayer75d316e2019-10-15 15:45:08 -0700654 __disable_dcpu(priv);
Markus Mayer2f330ca2017-08-24 16:36:26 -0700655
Markus Mayer6ef972b2019-10-15 15:45:09 -0700656 is_big_endian = init.is_big_endian;
657 dmem_size = init.dmem_len;
658 imem_size = init.imem_len;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700659
660 /* At the beginning of the firmware blob is a header. */
661 header = (struct dpfe_firmware_header *)fw->data;
662 /* Void pointer to the beginning of the actual firmware. */
663 fw_blob = fw->data + sizeof(*header);
664 /* IMEM comes right after the header. */
665 imem = fw_blob;
666 /* DMEM follows after IMEM. */
667 dmem = fw_blob + imem_size;
668
669 ret = __write_firmware(priv->dmem, dmem, dmem_size, is_big_endian);
670 if (ret)
671 return ret;
672 ret = __write_firmware(priv->imem, imem, imem_size, is_big_endian);
673 if (ret)
674 return ret;
675
Markus Mayer6ef972b2019-10-15 15:45:09 -0700676 ret = __verify_fw_checksum(&init, priv, header, init.chksum);
Markus Mayer2f330ca2017-08-24 16:36:26 -0700677 if (ret)
678 return ret;
679
Markus Mayer75d316e2019-10-15 15:45:08 -0700680 __enable_dcpu(priv);
Markus Mayer2f330ca2017-08-24 16:36:26 -0700681
682 return 0;
683}
684
685static ssize_t generic_show(unsigned int command, u32 response[],
Markus Mayerabf94562019-10-15 15:45:06 -0700686 struct brcmstb_dpfe_priv *priv, char *buf)
Markus Mayer2f330ca2017-08-24 16:36:26 -0700687{
Markus Mayer2f330ca2017-08-24 16:36:26 -0700688 int ret;
689
Markus Mayer2f330ca2017-08-24 16:36:26 -0700690 if (!priv)
691 return sprintf(buf, "ERROR: driver private data not set\n");
692
693 ret = __send_command(priv, command, response);
694 if (ret < 0)
695 return sprintf(buf, "ERROR: %s\n", error_text[-ret]);
696
697 return 0;
698}
699
700static ssize_t show_info(struct device *dev, struct device_attribute *devattr,
701 char *buf)
702{
703 u32 response[MSG_FIELD_MAX];
Markus Mayerabf94562019-10-15 15:45:06 -0700704 struct brcmstb_dpfe_priv *priv;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700705 unsigned int info;
Markus Mayer9f2c4d92018-02-13 12:40:39 -0800706 ssize_t ret;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700707
Markus Mayer900c8f52019-02-11 17:24:42 -0800708 priv = dev_get_drvdata(dev);
709 ret = generic_show(DPFE_CMD_GET_INFO, response, priv, buf);
Markus Mayer2f330ca2017-08-24 16:36:26 -0700710 if (ret)
711 return ret;
712
713 info = response[MSG_ARG0];
714
715 return sprintf(buf, "%u.%u.%u.%u\n",
716 (info >> 24) & 0xff,
717 (info >> 16) & 0xff,
718 (info >> 8) & 0xff,
719 info & 0xff);
720}
721
722static ssize_t show_refresh(struct device *dev,
723 struct device_attribute *devattr, char *buf)
724{
725 u32 response[MSG_FIELD_MAX];
726 void __iomem *info;
Markus Mayerabf94562019-10-15 15:45:06 -0700727 struct brcmstb_dpfe_priv *priv;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700728 u8 refresh, sr_abort, ppre, thermal_offs, tuf;
729 u32 mr4;
Markus Mayer9f2c4d92018-02-13 12:40:39 -0800730 ssize_t ret;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700731
Markus Mayer900c8f52019-02-11 17:24:42 -0800732 priv = dev_get_drvdata(dev);
733 ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf);
Markus Mayer2f330ca2017-08-24 16:36:26 -0700734 if (ret)
735 return ret;
736
Markus Mayerfee5f1e2018-02-13 12:40:40 -0800737 info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
738 if (!info)
739 return ret;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700740
Markus Mayer78a6f5b2019-02-11 17:24:43 -0800741 mr4 = (readl_relaxed(info + DRAM_INFO_MR4) >> DRAM_INFO_MR4_SHIFT) &
Markus Mayer1ffc0b52019-04-02 16:00:58 -0700742 DRAM_INFO_MR4_MASK;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700743
744 refresh = (mr4 >> DRAM_MR4_REFRESH) & DRAM_MR4_REFRESH_MASK;
745 sr_abort = (mr4 >> DRAM_MR4_SR_ABORT) & DRAM_MR4_SR_ABORT_MASK;
746 ppre = (mr4 >> DRAM_MR4_PPRE) & DRAM_MR4_PPRE_MASK;
747 thermal_offs = (mr4 >> DRAM_MR4_TH_OFFS) & DRAM_MR4_TH_OFFS_MASK;
748 tuf = (mr4 >> DRAM_MR4_TUF) & DRAM_MR4_TUF_MASK;
749
750 return sprintf(buf, "%#x %#x %#x %#x %#x %#x %#x\n",
751 readl_relaxed(info + DRAM_INFO_INTERVAL),
752 refresh, sr_abort, ppre, thermal_offs, tuf,
753 readl_relaxed(info + DRAM_INFO_ERROR));
754}
755
756static ssize_t store_refresh(struct device *dev, struct device_attribute *attr,
757 const char *buf, size_t count)
758{
759 u32 response[MSG_FIELD_MAX];
Markus Mayerabf94562019-10-15 15:45:06 -0700760 struct brcmstb_dpfe_priv *priv;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700761 void __iomem *info;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700762 unsigned long val;
763 int ret;
764
765 if (kstrtoul(buf, 0, &val) < 0)
766 return -EINVAL;
767
768 priv = dev_get_drvdata(dev);
Markus Mayer2f330ca2017-08-24 16:36:26 -0700769 ret = __send_command(priv, DPFE_CMD_GET_REFRESH, response);
770 if (ret)
771 return ret;
772
Markus Mayerfee5f1e2018-02-13 12:40:40 -0800773 info = get_msg_ptr(priv, response[MSG_ARG0], NULL, NULL);
774 if (!info)
775 return -EIO;
776
Markus Mayer2f330ca2017-08-24 16:36:26 -0700777 writel_relaxed(val, info + DRAM_INFO_INTERVAL);
778
779 return count;
780}
781
782static ssize_t show_vendor(struct device *dev, struct device_attribute *devattr,
Markus Mayer1ffc0b52019-04-02 16:00:58 -0700783 char *buf)
Markus Mayer2f330ca2017-08-24 16:36:26 -0700784{
785 u32 response[MSG_FIELD_MAX];
Markus Mayerabf94562019-10-15 15:45:06 -0700786 struct brcmstb_dpfe_priv *priv;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700787 void __iomem *info;
Markus Mayer9f2c4d92018-02-13 12:40:39 -0800788 ssize_t ret;
Markus Mayer78a6f5b2019-02-11 17:24:43 -0800789 u32 mr5, mr6, mr7, mr8, err;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700790
Markus Mayer2f330ca2017-08-24 16:36:26 -0700791 priv = dev_get_drvdata(dev);
Markus Mayer900c8f52019-02-11 17:24:42 -0800792 ret = generic_show(DPFE_CMD_GET_VENDOR, response, priv, buf);
Markus Mayer2f330ca2017-08-24 16:36:26 -0700793 if (ret)
794 return ret;
Markus Mayerfee5f1e2018-02-13 12:40:40 -0800795
796 info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
797 if (!info)
798 return ret;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700799
Markus Mayer78a6f5b2019-02-11 17:24:43 -0800800 mr5 = (readl_relaxed(info + DRAM_VENDOR_MR5) >> DRAM_VENDOR_SHIFT) &
801 DRAM_VENDOR_MASK;
802 mr6 = (readl_relaxed(info + DRAM_VENDOR_MR6) >> DRAM_VENDOR_SHIFT) &
803 DRAM_VENDOR_MASK;
804 mr7 = (readl_relaxed(info + DRAM_VENDOR_MR7) >> DRAM_VENDOR_SHIFT) &
805 DRAM_VENDOR_MASK;
806 mr8 = (readl_relaxed(info + DRAM_VENDOR_MR8) >> DRAM_VENDOR_SHIFT) &
807 DRAM_VENDOR_MASK;
808 err = readl_relaxed(info + DRAM_VENDOR_ERROR) & DRAM_VENDOR_MASK;
809
810 return sprintf(buf, "%#x %#x %#x %#x %#x\n", mr5, mr6, mr7, mr8, err);
Markus Mayer2f330ca2017-08-24 16:36:26 -0700811}
812
Markus Mayere3b74722019-04-02 16:01:03 -0700813static ssize_t show_dram(struct device *dev, struct device_attribute *devattr,
814 char *buf)
815{
816 u32 response[MSG_FIELD_MAX];
Markus Mayerabf94562019-10-15 15:45:06 -0700817 struct brcmstb_dpfe_priv *priv;
Markus Mayere3b74722019-04-02 16:01:03 -0700818 ssize_t ret;
819 u32 mr4, mr5, mr6, mr7, mr8, err;
820
821 priv = dev_get_drvdata(dev);
822 ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf);
823 if (ret)
824 return ret;
825
826 mr4 = response[MSG_ARG0 + 0] & DRAM_INFO_MR4_MASK;
827 mr5 = response[MSG_ARG0 + 1] & DRAM_DDR_INFO_MASK;
828 mr6 = response[MSG_ARG0 + 2] & DRAM_DDR_INFO_MASK;
829 mr7 = response[MSG_ARG0 + 3] & DRAM_DDR_INFO_MASK;
830 mr8 = response[MSG_ARG0 + 4] & DRAM_DDR_INFO_MASK;
831 err = response[MSG_ARG0 + 5] & DRAM_DDR_INFO_MASK;
832
833 return sprintf(buf, "%#x %#x %#x %#x %#x %#x\n", mr4, mr5, mr6, mr7,
834 mr8, err);
Markus Mayer2f330ca2017-08-24 16:36:26 -0700835}
836
837static int brcmstb_dpfe_resume(struct platform_device *pdev)
838{
Markus Mayerac2ea9c2019-10-15 15:45:10 -0700839 struct brcmstb_dpfe_priv *priv = platform_get_drvdata(pdev);
840
841 return brcmstb_dpfe_download_firmware(priv);
Markus Mayer2f330ca2017-08-24 16:36:26 -0700842}
843
Markus Mayer2f330ca2017-08-24 16:36:26 -0700844static int brcmstb_dpfe_probe(struct platform_device *pdev)
845{
846 struct device *dev = &pdev->dev;
Markus Mayerabf94562019-10-15 15:45:06 -0700847 struct brcmstb_dpfe_priv *priv;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700848 struct resource *res;
Markus Mayer2f330ca2017-08-24 16:36:26 -0700849 int ret;
850
851 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
852 if (!priv)
853 return -ENOMEM;
854
Markus Mayer56ece3f2019-10-15 15:45:07 -0700855 priv->dev = dev;
856
Markus Mayer2f330ca2017-08-24 16:36:26 -0700857 mutex_init(&priv->lock);
858 platform_set_drvdata(pdev, priv);
859
Markus Mayer2f330ca2017-08-24 16:36:26 -0700860 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-cpu");
861 priv->regs = devm_ioremap_resource(dev, res);
862 if (IS_ERR(priv->regs)) {
863 dev_err(dev, "couldn't map DCPU registers\n");
864 return -ENODEV;
865 }
866
867 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-dmem");
868 priv->dmem = devm_ioremap_resource(dev, res);
869 if (IS_ERR(priv->dmem)) {
870 dev_err(dev, "Couldn't map DCPU data memory\n");
871 return -ENOENT;
872 }
873
874 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-imem");
875 priv->imem = devm_ioremap_resource(dev, res);
876 if (IS_ERR(priv->imem)) {
877 dev_err(dev, "Couldn't map DCPU instruction memory\n");
878 return -ENOENT;
879 }
880
Markus Mayer58a84992019-04-02 16:01:01 -0700881 priv->dpfe_api = of_device_get_match_data(dev);
882 if (unlikely(!priv->dpfe_api)) {
883 /*
884 * It should be impossible to end up here, but to be safe we
885 * check anyway.
886 */
887 dev_err(dev, "Couldn't determine API\n");
888 return -ENOENT;
889 }
Markus Mayer2f330ca2017-08-24 16:36:26 -0700890
Markus Mayerac2ea9c2019-10-15 15:45:10 -0700891 ret = brcmstb_dpfe_download_firmware(priv);
Markus Mayer6ca5d2ba2019-04-02 16:00:59 -0700892 if (ret) {
Markus Mayer242fb2f2019-10-15 15:45:11 -0700893 if (ret != -EPROBE_DEFER)
894 dev_err(dev, "Couldn't download firmware -- %d\n", ret);
Markus Mayer2f330ca2017-08-24 16:36:26 -0700895 return ret;
Markus Mayer6ca5d2ba2019-04-02 16:00:59 -0700896 }
Markus Mayer2f330ca2017-08-24 16:36:26 -0700897
Markus Mayer5ef108b2019-04-02 16:01:02 -0700898 ret = sysfs_create_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs);
Florian Fainellib1d09732018-03-27 16:40:38 -0700899 if (!ret)
Markus Mayer58a84992019-04-02 16:01:01 -0700900 dev_info(dev, "registered with API v%d.\n",
901 priv->dpfe_api->version);
Markus Mayer2f330ca2017-08-24 16:36:26 -0700902
903 return ret;
904}
905
Florian Fainellib1d09732018-03-27 16:40:38 -0700906static int brcmstb_dpfe_remove(struct platform_device *pdev)
907{
Markus Mayerabf94562019-10-15 15:45:06 -0700908 struct brcmstb_dpfe_priv *priv = dev_get_drvdata(&pdev->dev);
Markus Mayer5ef108b2019-04-02 16:01:02 -0700909
910 sysfs_remove_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs);
Florian Fainellib1d09732018-03-27 16:40:38 -0700911
912 return 0;
913}
914
Markus Mayer2f330ca2017-08-24 16:36:26 -0700915static const struct of_device_id brcmstb_dpfe_of_match[] = {
Markus Mayere3b74722019-04-02 16:01:03 -0700916 /* Use legacy API v2 for a select number of chips */
Florian Fainellib61d3e82019-10-15 15:45:13 -0700917 { .compatible = "brcm,bcm7268-dpfe-cpu", .data = &dpfe_api_old_v2 },
918 { .compatible = "brcm,bcm7271-dpfe-cpu", .data = &dpfe_api_old_v2 },
919 { .compatible = "brcm,bcm7278-dpfe-cpu", .data = &dpfe_api_old_v2 },
920 { .compatible = "brcm,bcm7211-dpfe-cpu", .data = &dpfe_api_new_v2 },
Markus Mayere3b74722019-04-02 16:01:03 -0700921 /* API v3 is the default going forward */
922 { .compatible = "brcm,dpfe-cpu", .data = &dpfe_api_v3 },
Markus Mayer2f330ca2017-08-24 16:36:26 -0700923 {}
924};
925MODULE_DEVICE_TABLE(of, brcmstb_dpfe_of_match);
926
927static struct platform_driver brcmstb_dpfe_driver = {
928 .driver = {
929 .name = DRVNAME,
930 .of_match_table = brcmstb_dpfe_of_match,
931 },
932 .probe = brcmstb_dpfe_probe,
Florian Fainellib1d09732018-03-27 16:40:38 -0700933 .remove = brcmstb_dpfe_remove,
Markus Mayer2f330ca2017-08-24 16:36:26 -0700934 .resume = brcmstb_dpfe_resume,
935};
936
937module_platform_driver(brcmstb_dpfe_driver);
938
939MODULE_AUTHOR("Markus Mayer <mmayer@broadcom.com>");
940MODULE_DESCRIPTION("BRCMSTB DDR PHY Front End Driver");
941MODULE_LICENSE("GPL");