Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 1 | /* |
Sujith Manoharan | 5b68138 | 2011-05-17 13:36:18 +0530 | [diff] [blame] | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
| 17 | #include "hw.h" |
Luis R. Rodriguez | b622a72 | 2010-04-15 17:39:28 -0400 | [diff] [blame] | 18 | #include "ar9003_mac.h" |
Luis R. Rodriguez | 7284635 | 2010-05-12 21:15:05 -0400 | [diff] [blame] | 19 | #include "ar9003_2p2_initvals.h" |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 20 | #include "ar9485_initvals.h" |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 21 | #include "ar9340_initvals.h" |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 22 | #include "ar9330_1p1_initvals.h" |
| 23 | #include "ar9330_1p2_initvals.h" |
Gabor Juhos | a0fbb9b | 2012-07-03 19:13:22 +0200 | [diff] [blame] | 24 | #include "ar955x_1p0_initvals.h" |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 25 | #include "ar9580_1p0_initvals.h" |
Rajkumar Manoharan | 76db2f8 | 2011-10-13 11:00:43 +0530 | [diff] [blame] | 26 | #include "ar9462_2p0_initvals.h" |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 27 | #include "ar9565_1p0_initvals.h" |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 28 | |
| 29 | /* General hardware code for the AR9003 hadware family */ |
| 30 | |
Luis R. Rodriguez | 886b42b | 2010-10-14 11:44:27 -0700 | [diff] [blame] | 31 | /* |
| 32 | * The AR9003 family uses a new INI format (pre, core, post |
| 33 | * arrays per subsystem). This provides support for the |
| 34 | * AR9003 2.2 chipsets. |
| 35 | */ |
| 36 | static void ar9003_hw_init_mode_regs(struct ath_hw *ah) |
Luis R. Rodriguez | 7284635 | 2010-05-12 21:15:05 -0400 | [diff] [blame] | 37 | { |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 38 | if (AR_SREV_9330_11(ah)) { |
| 39 | /* mac */ |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 40 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 41 | ar9331_1p1_mac_core); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 42 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 43 | ar9331_1p1_mac_postamble); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 44 | |
| 45 | /* bb */ |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 46 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 47 | ar9331_1p1_baseband_core); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 48 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 49 | ar9331_1p1_baseband_postamble); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 50 | |
| 51 | /* radio */ |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 52 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 53 | ar9331_1p1_radio_core); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 54 | |
| 55 | /* soc */ |
| 56 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 57 | ar9331_1p1_soc_preamble); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 58 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 59 | ar9331_1p1_soc_postamble); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 60 | |
| 61 | /* rx/tx gain */ |
| 62 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 63 | ar9331_common_rx_gain_1p1); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 64 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 65 | ar9331_modes_lowest_ob_db_tx_gain_1p1); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 66 | |
Sujith Manoharan | 57527f8 | 2012-11-13 11:33:53 +0530 | [diff] [blame] | 67 | /* Japan 2484 Mhz CCK */ |
| 68 | INIT_INI_ARRAY(&ah->iniCckfirJapan2484, |
| 69 | ar9331_1p1_baseband_core_txfir_coeff_japan_2484); |
| 70 | |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 71 | /* additional clock settings */ |
| 72 | if (ah->is_clk_25mhz) |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 73 | INIT_INI_ARRAY(&ah->iniAdditional, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 74 | ar9331_1p1_xtal_25M); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 75 | else |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 76 | INIT_INI_ARRAY(&ah->iniAdditional, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 77 | ar9331_1p1_xtal_40M); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 78 | } else if (AR_SREV_9330_12(ah)) { |
| 79 | /* mac */ |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 80 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 81 | ar9331_1p2_mac_core); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 82 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 83 | ar9331_1p2_mac_postamble); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 84 | |
| 85 | /* bb */ |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 86 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 87 | ar9331_1p2_baseband_core); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 88 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 89 | ar9331_1p2_baseband_postamble); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 90 | |
| 91 | /* radio */ |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 92 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 93 | ar9331_1p2_radio_core); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 94 | |
| 95 | /* soc */ |
| 96 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 97 | ar9331_1p2_soc_preamble); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 98 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 99 | ar9331_1p2_soc_postamble); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 100 | |
| 101 | /* rx/tx gain */ |
| 102 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 103 | ar9331_common_rx_gain_1p2); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 104 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 105 | ar9331_modes_lowest_ob_db_tx_gain_1p2); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 106 | |
Sujith Manoharan | 57527f8 | 2012-11-13 11:33:53 +0530 | [diff] [blame] | 107 | /* Japan 2484 Mhz CCK */ |
| 108 | INIT_INI_ARRAY(&ah->iniCckfirJapan2484, |
| 109 | ar9331_1p2_baseband_core_txfir_coeff_japan_2484); |
| 110 | |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 111 | /* additional clock settings */ |
| 112 | if (ah->is_clk_25mhz) |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 113 | INIT_INI_ARRAY(&ah->iniAdditional, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 114 | ar9331_1p2_xtal_25M); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 115 | else |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 116 | INIT_INI_ARRAY(&ah->iniAdditional, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 117 | ar9331_1p2_xtal_40M); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 118 | } else if (AR_SREV_9340(ah)) { |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 119 | /* mac */ |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 120 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 121 | ar9340_1p0_mac_core); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 122 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 123 | ar9340_1p0_mac_postamble); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 124 | |
| 125 | /* bb */ |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 126 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 127 | ar9340_1p0_baseband_core); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 128 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 129 | ar9340_1p0_baseband_postamble); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 130 | |
| 131 | /* radio */ |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 132 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 133 | ar9340_1p0_radio_core); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 134 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 135 | ar9340_1p0_radio_postamble); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 136 | |
| 137 | /* soc */ |
| 138 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 139 | ar9340_1p0_soc_preamble); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 140 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 141 | ar9340_1p0_soc_postamble); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 142 | |
| 143 | /* rx/tx gain */ |
| 144 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 145 | ar9340Common_wo_xlna_rx_gain_table_1p0); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 146 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 147 | ar9340Modes_high_ob_db_tx_gain_table_1p0); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 148 | |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 149 | INIT_INI_ARRAY(&ah->iniModesFastClock, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 150 | ar9340Modes_fast_clock_1p0); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 151 | |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 152 | if (!ah->is_clk_25mhz) |
| 153 | INIT_INI_ARRAY(&ah->iniAdditional, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 154 | ar9340_1p0_radio_core_40M); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 155 | } else if (AR_SREV_9485_11(ah)) { |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 156 | /* mac */ |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 157 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 158 | ar9485_1_1_mac_core); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 159 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 160 | ar9485_1_1_mac_postamble); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 161 | |
| 162 | /* bb */ |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 163 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 164 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 165 | ar9485_1_1_baseband_core); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 166 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 167 | ar9485_1_1_baseband_postamble); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 168 | |
| 169 | /* radio */ |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 170 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 171 | ar9485_1_1_radio_core); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 172 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 173 | ar9485_1_1_radio_postamble); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 174 | |
| 175 | /* soc */ |
| 176 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 177 | ar9485_1_1_soc_preamble); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 178 | |
| 179 | /* rx/tx gain */ |
| 180 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 181 | ar9485Common_wo_xlna_rx_gain_1_1); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 182 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 183 | ar9485_modes_lowest_ob_db_tx_gain_1_1); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 184 | |
Sujith Manoharan | 57527f8 | 2012-11-13 11:33:53 +0530 | [diff] [blame] | 185 | /* Japan 2484 Mhz CCK */ |
| 186 | INIT_INI_ARRAY(&ah->iniCckfirJapan2484, |
| 187 | ar9485_1_1_baseband_core_txfir_coeff_japan_2484); |
| 188 | |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 189 | /* Load PCIE SERDES settings from INI */ |
| 190 | |
| 191 | /* Awake Setting */ |
| 192 | |
| 193 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 194 | ar9485_1_1_pcie_phy_clkreq_disable_L1); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 195 | |
| 196 | /* Sleep Setting */ |
| 197 | |
| 198 | INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 199 | ar9485_1_1_pcie_phy_clkreq_disable_L1); |
Rajkumar Manoharan | 423e38e | 2011-10-13 11:00:44 +0530 | [diff] [blame] | 200 | } else if (AR_SREV_9462_20(ah)) { |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 201 | |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 202 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 203 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 204 | ar9462_2p0_mac_postamble); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 205 | |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 206 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 207 | ar9462_2p0_baseband_core); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 208 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 209 | ar9462_2p0_baseband_postamble); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 210 | |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 211 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 212 | ar9462_2p0_radio_core); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 213 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 214 | ar9462_2p0_radio_postamble); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 215 | INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 216 | ar9462_2p0_radio_postamble_sys2ant); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 217 | |
| 218 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 219 | ar9462_2p0_soc_preamble); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 220 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 221 | ar9462_2p0_soc_postamble); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 222 | |
| 223 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 224 | ar9462_common_rx_gain_table_2p0); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 225 | |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 226 | /* Awake -> Sleep Setting */ |
| 227 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Rajkumar Manoharan | 1680260 | 2012-10-25 17:11:31 +0530 | [diff] [blame] | 228 | ar9462_pciephy_clkreq_disable_L1_2p0); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 229 | /* Sleep -> Awake Setting */ |
| 230 | INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, |
Rajkumar Manoharan | 1680260 | 2012-10-25 17:11:31 +0530 | [diff] [blame] | 231 | ar9462_pciephy_clkreq_disable_L1_2p0); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 232 | |
| 233 | /* Fast clock modal settings */ |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 234 | INIT_INI_ARRAY(&ah->iniModesFastClock, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 235 | ar9462_modes_fast_clock_2p0); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 236 | |
| 237 | INIT_INI_ARRAY(&ah->iniCckfirJapan2484, |
Sujith Manoharan | 57527f8 | 2012-11-13 11:33:53 +0530 | [diff] [blame] | 238 | ar9462_2p0_baseband_core_txfir_coeff_japan_2484); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 239 | } else if (AR_SREV_9550(ah)) { |
| 240 | /* mac */ |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 241 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 242 | ar955x_1p0_mac_core); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 243 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 244 | ar955x_1p0_mac_postamble); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 245 | |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 246 | /* bb */ |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 247 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 248 | ar955x_1p0_baseband_core); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 249 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 250 | ar955x_1p0_baseband_postamble); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 251 | |
| 252 | /* radio */ |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 253 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 254 | ar955x_1p0_radio_core); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 255 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 256 | ar955x_1p0_radio_postamble); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 257 | |
| 258 | /* soc */ |
| 259 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 260 | ar955x_1p0_soc_preamble); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 261 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 262 | ar955x_1p0_soc_postamble); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 263 | |
| 264 | /* rx/tx gain */ |
| 265 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 266 | ar955x_1p0_common_wo_xlna_rx_gain_table); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 267 | INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 268 | ar955x_1p0_common_wo_xlna_rx_gain_bounds); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 269 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 270 | ar955x_1p0_modes_xpa_tx_gain_table); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 271 | |
| 272 | /* Fast clock modal settings */ |
| 273 | INIT_INI_ARRAY(&ah->iniModesFastClock, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 274 | ar955x_1p0_modes_fast_clock); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 275 | } else if (AR_SREV_9580(ah)) { |
| 276 | /* mac */ |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 277 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 278 | ar9580_1p0_mac_core); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 279 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 280 | ar9580_1p0_mac_postamble); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 281 | |
| 282 | /* bb */ |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 283 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 284 | ar9580_1p0_baseband_core); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 285 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 286 | ar9580_1p0_baseband_postamble); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 287 | |
| 288 | /* radio */ |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 289 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 290 | ar9580_1p0_radio_core); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 291 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 292 | ar9580_1p0_radio_postamble); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 293 | |
| 294 | /* soc */ |
| 295 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 296 | ar9580_1p0_soc_preamble); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 297 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 298 | ar9580_1p0_soc_postamble); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 299 | |
| 300 | /* rx/tx gain */ |
| 301 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 302 | ar9580_1p0_rx_gain_table); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 303 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 304 | ar9580_1p0_low_ob_db_tx_gain_table); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 305 | |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 306 | INIT_INI_ARRAY(&ah->iniModesFastClock, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 307 | ar9580_1p0_modes_fast_clock); |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 308 | } else if (AR_SREV_9565(ah)) { |
| 309 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
| 310 | ar9565_1p0_mac_core); |
| 311 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
| 312 | ar9565_1p0_mac_postamble); |
| 313 | |
| 314 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
| 315 | ar9565_1p0_baseband_core); |
| 316 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
| 317 | ar9565_1p0_baseband_postamble); |
| 318 | |
| 319 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
| 320 | ar9565_1p0_radio_core); |
| 321 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
| 322 | ar9565_1p0_radio_postamble); |
| 323 | |
| 324 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
| 325 | ar9565_1p0_soc_preamble); |
| 326 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
| 327 | ar9565_1p0_soc_postamble); |
| 328 | |
| 329 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 330 | ar9565_1p0_Common_rx_gain_table); |
| 331 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 332 | ar9565_1p0_Modes_lowest_ob_db_tx_gain_table); |
| 333 | |
| 334 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Rajkumar Manoharan | 8446484 | 2012-10-25 17:16:51 +0530 | [diff] [blame] | 335 | ar9565_1p0_pciephy_clkreq_disable_L1); |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 336 | INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, |
Rajkumar Manoharan | 8446484 | 2012-10-25 17:16:51 +0530 | [diff] [blame] | 337 | ar9565_1p0_pciephy_clkreq_disable_L1); |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 338 | |
| 339 | INIT_INI_ARRAY(&ah->iniModesFastClock, |
| 340 | ar9565_1p0_modes_fast_clock); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 341 | } else { |
| 342 | /* mac */ |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 343 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 344 | ar9300_2p2_mac_core); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 345 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 346 | ar9300_2p2_mac_postamble); |
Luis R. Rodriguez | 7284635 | 2010-05-12 21:15:05 -0400 | [diff] [blame] | 347 | |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 348 | /* bb */ |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 349 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 350 | ar9300_2p2_baseband_core); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 351 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 352 | ar9300_2p2_baseband_postamble); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 353 | |
| 354 | /* radio */ |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 355 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 356 | ar9300_2p2_radio_core); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 357 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 358 | ar9300_2p2_radio_postamble); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 359 | |
| 360 | /* soc */ |
| 361 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 362 | ar9300_2p2_soc_preamble); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 363 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 364 | ar9300_2p2_soc_postamble); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 365 | |
| 366 | /* rx/tx gain */ |
| 367 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 368 | ar9300Common_rx_gain_table_2p2); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 369 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 370 | ar9300Modes_lowest_ob_db_tx_gain_table_2p2); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 371 | |
| 372 | /* Load PCIE SERDES settings from INI */ |
| 373 | |
| 374 | /* Awake Setting */ |
| 375 | |
| 376 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 377 | ar9300PciePhy_pll_on_clkreq_disable_L1_2p2); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 378 | |
| 379 | /* Sleep Setting */ |
| 380 | |
| 381 | INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 382 | ar9300PciePhy_pll_on_clkreq_disable_L1_2p2); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 383 | |
| 384 | /* Fast clock modal settings */ |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 385 | INIT_INI_ARRAY(&ah->iniModesFastClock, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 386 | ar9300Modes_fast_clock_2p2); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 387 | } |
Luis R. Rodriguez | 7284635 | 2010-05-12 21:15:05 -0400 | [diff] [blame] | 388 | } |
| 389 | |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 390 | static void ar9003_tx_gain_table_mode0(struct ath_hw *ah) |
| 391 | { |
| 392 | if (AR_SREV_9330_12(ah)) |
| 393 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 394 | ar9331_modes_lowest_ob_db_tx_gain_1p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 395 | else if (AR_SREV_9330_11(ah)) |
| 396 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 397 | ar9331_modes_lowest_ob_db_tx_gain_1p1); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 398 | else if (AR_SREV_9340(ah)) |
| 399 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 400 | ar9340Modes_lowest_ob_db_tx_gain_table_1p0); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 401 | else if (AR_SREV_9485_11(ah)) |
| 402 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 403 | ar9485_modes_lowest_ob_db_tx_gain_1_1); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 404 | else if (AR_SREV_9550(ah)) |
| 405 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 406 | ar955x_1p0_modes_xpa_tx_gain_table); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 407 | else if (AR_SREV_9580(ah)) |
| 408 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 409 | ar9580_1p0_lowest_ob_db_tx_gain_table); |
Rajkumar Manoharan | 423e38e | 2011-10-13 11:00:44 +0530 | [diff] [blame] | 410 | else if (AR_SREV_9462_20(ah)) |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 411 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 412 | ar9462_modes_low_ob_db_tx_gain_table_2p0); |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 413 | else if (AR_SREV_9565(ah)) |
| 414 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 415 | ar9565_1p0_modes_low_ob_db_tx_gain_table); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 416 | else |
| 417 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 418 | ar9300Modes_lowest_ob_db_tx_gain_table_2p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 419 | } |
| 420 | |
| 421 | static void ar9003_tx_gain_table_mode1(struct ath_hw *ah) |
| 422 | { |
| 423 | if (AR_SREV_9330_12(ah)) |
| 424 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 425 | ar9331_modes_high_ob_db_tx_gain_1p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 426 | else if (AR_SREV_9330_11(ah)) |
| 427 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 428 | ar9331_modes_high_ob_db_tx_gain_1p1); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 429 | else if (AR_SREV_9340(ah)) |
| 430 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 431 | ar9340Modes_high_ob_db_tx_gain_table_1p0); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 432 | else if (AR_SREV_9485_11(ah)) |
| 433 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 434 | ar9485Modes_high_ob_db_tx_gain_1_1); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 435 | else if (AR_SREV_9580(ah)) |
| 436 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 437 | ar9580_1p0_high_ob_db_tx_gain_table); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 438 | else if (AR_SREV_9550(ah)) |
| 439 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 440 | ar955x_1p0_modes_no_xpa_tx_gain_table); |
Rajkumar Manoharan | 423e38e | 2011-10-13 11:00:44 +0530 | [diff] [blame] | 441 | else if (AR_SREV_9462_20(ah)) |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 442 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 443 | ar9462_modes_high_ob_db_tx_gain_table_2p0); |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 444 | else if (AR_SREV_9565(ah)) |
| 445 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 446 | ar9565_1p0_modes_high_ob_db_tx_gain_table); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 447 | else |
| 448 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 449 | ar9300Modes_high_ob_db_tx_gain_table_2p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 450 | } |
| 451 | |
| 452 | static void ar9003_tx_gain_table_mode2(struct ath_hw *ah) |
| 453 | { |
| 454 | if (AR_SREV_9330_12(ah)) |
| 455 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 456 | ar9331_modes_low_ob_db_tx_gain_1p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 457 | else if (AR_SREV_9330_11(ah)) |
| 458 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 459 | ar9331_modes_low_ob_db_tx_gain_1p1); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 460 | else if (AR_SREV_9340(ah)) |
| 461 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 462 | ar9340Modes_low_ob_db_tx_gain_table_1p0); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 463 | else if (AR_SREV_9485_11(ah)) |
| 464 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 465 | ar9485Modes_low_ob_db_tx_gain_1_1); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 466 | else if (AR_SREV_9580(ah)) |
| 467 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 468 | ar9580_1p0_low_ob_db_tx_gain_table); |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 469 | else if (AR_SREV_9565(ah)) |
| 470 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 471 | ar9565_1p0_modes_low_ob_db_tx_gain_table); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 472 | else |
| 473 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 474 | ar9300Modes_low_ob_db_tx_gain_table_2p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 475 | } |
| 476 | |
| 477 | static void ar9003_tx_gain_table_mode3(struct ath_hw *ah) |
| 478 | { |
| 479 | if (AR_SREV_9330_12(ah)) |
| 480 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 481 | ar9331_modes_high_power_tx_gain_1p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 482 | else if (AR_SREV_9330_11(ah)) |
| 483 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 484 | ar9331_modes_high_power_tx_gain_1p1); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 485 | else if (AR_SREV_9340(ah)) |
| 486 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 487 | ar9340Modes_high_power_tx_gain_table_1p0); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 488 | else if (AR_SREV_9485_11(ah)) |
| 489 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 490 | ar9485Modes_high_power_tx_gain_1_1); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 491 | else if (AR_SREV_9580(ah)) |
| 492 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 493 | ar9580_1p0_high_power_tx_gain_table); |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 494 | else if (AR_SREV_9565(ah)) |
| 495 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 496 | ar9565_1p0_modes_high_power_tx_gain_table); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 497 | else |
| 498 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 499 | ar9300Modes_high_power_tx_gain_table_2p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 500 | } |
| 501 | |
Felix Fietkau | b05a011 | 2012-07-15 19:53:32 +0200 | [diff] [blame] | 502 | static void ar9003_tx_gain_table_mode4(struct ath_hw *ah) |
| 503 | { |
| 504 | if (AR_SREV_9340(ah)) |
| 505 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 506 | ar9340Modes_mixed_ob_db_tx_gain_table_1p0); |
Felix Fietkau | b05a011 | 2012-07-15 19:53:32 +0200 | [diff] [blame] | 507 | else if (AR_SREV_9580(ah)) |
| 508 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 509 | ar9580_1p0_mixed_ob_db_tx_gain_table); |
Felix Fietkau | eab6d79 | 2013-01-10 19:41:52 +0100 | [diff] [blame] | 510 | else |
| 511 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 512 | ar9300Modes_mixed_ob_db_tx_gain_table_2p2); |
Felix Fietkau | b05a011 | 2012-07-15 19:53:32 +0200 | [diff] [blame] | 513 | } |
| 514 | |
Felix Fietkau | eab6d79 | 2013-01-10 19:41:52 +0100 | [diff] [blame] | 515 | static void ar9003_tx_gain_table_mode5(struct ath_hw *ah) |
| 516 | { |
| 517 | if (AR_SREV_9485_11(ah)) |
| 518 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 519 | ar9485Modes_green_ob_db_tx_gain_1_1); |
| 520 | else if (AR_SREV_9340(ah)) |
| 521 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 522 | ar9340Modes_ub124_tx_gain_table_1p0); |
| 523 | else if (AR_SREV_9580(ah)) |
| 524 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 525 | ar9580_1p0_type5_tx_gain_table); |
| 526 | else if (AR_SREV_9300_22(ah)) |
| 527 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 528 | ar9300Modes_type5_tx_gain_table_2p2); |
| 529 | } |
| 530 | |
| 531 | static void ar9003_tx_gain_table_mode6(struct ath_hw *ah) |
| 532 | { |
| 533 | if (AR_SREV_9340(ah)) |
| 534 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 535 | ar9340Modes_low_ob_db_and_spur_tx_gain_table_1p0); |
| 536 | else if (AR_SREV_9485_11(ah)) |
| 537 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 538 | ar9485Modes_green_spur_ob_db_tx_gain_1_1); |
| 539 | else if (AR_SREV_9580(ah)) |
| 540 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 541 | ar9580_1p0_type6_tx_gain_table); |
| 542 | } |
| 543 | |
| 544 | typedef void (*ath_txgain_tab)(struct ath_hw *ah); |
| 545 | |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 546 | static void ar9003_tx_gain_table_apply(struct ath_hw *ah) |
| 547 | { |
Felix Fietkau | eab6d79 | 2013-01-10 19:41:52 +0100 | [diff] [blame] | 548 | static const ath_txgain_tab modes[] = { |
| 549 | ar9003_tx_gain_table_mode0, |
| 550 | ar9003_tx_gain_table_mode1, |
| 551 | ar9003_tx_gain_table_mode2, |
| 552 | ar9003_tx_gain_table_mode3, |
| 553 | ar9003_tx_gain_table_mode4, |
| 554 | ar9003_tx_gain_table_mode5, |
| 555 | ar9003_tx_gain_table_mode6, |
| 556 | }; |
| 557 | int idx = ar9003_hw_get_tx_gain_idx(ah); |
| 558 | |
| 559 | if (idx >= ARRAY_SIZE(modes)) |
| 560 | idx = 0; |
| 561 | |
| 562 | modes[idx](ah); |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 563 | } |
| 564 | |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 565 | static void ar9003_rx_gain_table_mode0(struct ath_hw *ah) |
| 566 | { |
| 567 | if (AR_SREV_9330_12(ah)) |
| 568 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 569 | ar9331_common_rx_gain_1p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 570 | else if (AR_SREV_9330_11(ah)) |
| 571 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 572 | ar9331_common_rx_gain_1p1); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 573 | else if (AR_SREV_9340(ah)) |
| 574 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 575 | ar9340Common_rx_gain_table_1p0); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 576 | else if (AR_SREV_9485_11(ah)) |
| 577 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Sujith Manoharan | a796a1d | 2012-12-26 12:27:39 +0530 | [diff] [blame] | 578 | ar9485_common_rx_gain_1_1); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 579 | else if (AR_SREV_9550(ah)) { |
| 580 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 581 | ar955x_1p0_common_rx_gain_table); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 582 | INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 583 | ar955x_1p0_common_rx_gain_bounds); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 584 | } else if (AR_SREV_9580(ah)) |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 585 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 586 | ar9580_1p0_rx_gain_table); |
Rajkumar Manoharan | 423e38e | 2011-10-13 11:00:44 +0530 | [diff] [blame] | 587 | else if (AR_SREV_9462_20(ah)) |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 588 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 589 | ar9462_common_rx_gain_table_2p0); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 590 | else |
| 591 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 592 | ar9300Common_rx_gain_table_2p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 593 | } |
| 594 | |
| 595 | static void ar9003_rx_gain_table_mode1(struct ath_hw *ah) |
| 596 | { |
| 597 | if (AR_SREV_9330_12(ah)) |
| 598 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 599 | ar9331_common_wo_xlna_rx_gain_1p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 600 | else if (AR_SREV_9330_11(ah)) |
| 601 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 602 | ar9331_common_wo_xlna_rx_gain_1p1); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 603 | else if (AR_SREV_9340(ah)) |
| 604 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 605 | ar9340Common_wo_xlna_rx_gain_table_1p0); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 606 | else if (AR_SREV_9485_11(ah)) |
| 607 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 608 | ar9485Common_wo_xlna_rx_gain_1_1); |
Rajkumar Manoharan | 423e38e | 2011-10-13 11:00:44 +0530 | [diff] [blame] | 609 | else if (AR_SREV_9462_20(ah)) |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 610 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 611 | ar9462_common_wo_xlna_rx_gain_table_2p0); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 612 | else if (AR_SREV_9550(ah)) { |
| 613 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 614 | ar955x_1p0_common_wo_xlna_rx_gain_table); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 615 | INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 616 | ar955x_1p0_common_wo_xlna_rx_gain_bounds); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 617 | } else if (AR_SREV_9580(ah)) |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 618 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 619 | ar9580_1p0_wo_xlna_rx_gain_table); |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 620 | else if (AR_SREV_9565(ah)) |
| 621 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 622 | ar9565_1p0_common_wo_xlna_rx_gain_table); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 623 | else |
| 624 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 625 | ar9300Common_wo_xlna_rx_gain_table_2p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 626 | } |
| 627 | |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 628 | static void ar9003_rx_gain_table_mode2(struct ath_hw *ah) |
| 629 | { |
Sujith Manoharan | c91ec46 | 2012-02-22 12:40:03 +0530 | [diff] [blame] | 630 | if (AR_SREV_9462_20(ah)) |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 631 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 632 | ar9462_common_mixed_rx_gain_table_2p0); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 633 | } |
| 634 | |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 635 | static void ar9003_rx_gain_table_apply(struct ath_hw *ah) |
| 636 | { |
| 637 | switch (ar9003_hw_get_rx_gain_idx(ah)) { |
| 638 | case 0: |
| 639 | default: |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 640 | ar9003_rx_gain_table_mode0(ah); |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 641 | break; |
| 642 | case 1: |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 643 | ar9003_rx_gain_table_mode1(ah); |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 644 | break; |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 645 | case 2: |
| 646 | ar9003_rx_gain_table_mode2(ah); |
| 647 | break; |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 648 | } |
| 649 | } |
| 650 | |
| 651 | /* set gain table pointers according to values read from the eeprom */ |
| 652 | static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah) |
| 653 | { |
| 654 | ar9003_tx_gain_table_apply(ah); |
| 655 | ar9003_rx_gain_table_apply(ah); |
| 656 | } |
| 657 | |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 658 | /* |
| 659 | * Helper for ASPM support. |
| 660 | * |
| 661 | * Disable PLL when in L0s as well as receiver clock when in L1. |
| 662 | * This power saving option must be enabled through the SerDes. |
| 663 | * |
| 664 | * Programming the SerDes must go through the same 288 bit serial shift |
| 665 | * register as the other analog registers. Hence the 9 writes. |
| 666 | */ |
| 667 | static void ar9003_hw_configpcipowersave(struct ath_hw *ah, |
Stanislaw Gruszka | 84c87dc | 2011-08-05 13:10:32 +0200 | [diff] [blame] | 668 | bool power_off) |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 669 | { |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 670 | /* Nothing to do on restore for 11N */ |
Stanislaw Gruszka | 84c87dc | 2011-08-05 13:10:32 +0200 | [diff] [blame] | 671 | if (!power_off /* !restore */) { |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 672 | /* set bit 19 to allow forcing of pcie core into L1 state */ |
| 673 | REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); |
| 674 | |
| 675 | /* Several PCIe massages to ensure proper behaviour */ |
| 676 | if (ah->config.pcie_waen) |
| 677 | REG_WRITE(ah, AR_WA, ah->config.pcie_waen); |
Luis R. Rodriguez | 9a658d2 | 2010-06-21 18:38:47 -0400 | [diff] [blame] | 678 | else |
| 679 | REG_WRITE(ah, AR_WA, ah->WARegVal); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 680 | } |
Luis R. Rodriguez | 653fe37 | 2010-06-21 18:38:48 -0400 | [diff] [blame] | 681 | |
| 682 | /* |
| 683 | * Configire PCIE after Ini init. SERDES values now come from ini file |
| 684 | * This enables PCIe low power mode. |
| 685 | */ |
Luis R. Rodriguez | 6a0ec30 | 2010-06-21 18:38:49 -0400 | [diff] [blame] | 686 | if (ah->config.pcieSerDesWrite) { |
Luis R. Rodriguez | 653fe37 | 2010-06-21 18:38:48 -0400 | [diff] [blame] | 687 | unsigned int i; |
Luis R. Rodriguez | d5c4d19 | 2010-06-21 18:38:50 -0400 | [diff] [blame] | 688 | struct ar5416IniArray *array; |
Luis R. Rodriguez | 653fe37 | 2010-06-21 18:38:48 -0400 | [diff] [blame] | 689 | |
Luis R. Rodriguez | d5c4d19 | 2010-06-21 18:38:50 -0400 | [diff] [blame] | 690 | array = power_off ? &ah->iniPcieSerdes : |
| 691 | &ah->iniPcieSerdesLowPower; |
| 692 | |
| 693 | for (i = 0; i < array->ia_rows; i++) { |
Luis R. Rodriguez | 653fe37 | 2010-06-21 18:38:48 -0400 | [diff] [blame] | 694 | REG_WRITE(ah, |
Luis R. Rodriguez | d5c4d19 | 2010-06-21 18:38:50 -0400 | [diff] [blame] | 695 | INI_RA(array, i, 0), |
| 696 | INI_RA(array, i, 1)); |
Luis R. Rodriguez | 653fe37 | 2010-06-21 18:38:48 -0400 | [diff] [blame] | 697 | } |
| 698 | } |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 699 | } |
| 700 | |
| 701 | /* Sets up the AR9003 hardware familiy callbacks */ |
| 702 | void ar9003_hw_attach_ops(struct ath_hw *ah) |
| 703 | { |
| 704 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); |
| 705 | struct ath_hw_ops *ops = ath9k_hw_ops(ah); |
| 706 | |
Felix Fietkau | 6aaacd8 | 2013-01-13 19:54:58 +0100 | [diff] [blame] | 707 | ar9003_hw_init_mode_regs(ah); |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 708 | priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs; |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 709 | |
| 710 | ops->config_pci_powersave = ar9003_hw_configpcipowersave; |
| 711 | |
| 712 | ar9003_hw_attach_phy_ops(ah); |
| 713 | ar9003_hw_attach_calib_ops(ah); |
| 714 | ar9003_hw_attach_mac_ops(ah); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 715 | } |