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Jeff Kirsherae06c702018-03-22 10:08:48 -07001// SPDX-License-Identifier: GPL-2.0
Jeff Kirsher51dce242018-04-26 08:08:09 -07002/* Copyright(c) 1999 - 2018 Intel Corporation. */
Auke Kokbc7f75f2007-09-17 12:30:59 -07003
Bruce Allane921eb12012-11-28 09:28:37 +00004/* 80003ES2LAN Gigabit Ethernet Controller (Copper)
Auke Kokbc7f75f2007-09-17 12:30:59 -07005 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
6 */
7
Auke Kokbc7f75f2007-09-17 12:30:59 -07008#include "e1000.h"
9
Bruce Allane921eb12012-11-28 09:28:37 +000010/* A table for the GG82563 cable length where the range is defined
Auke Kokbc7f75f2007-09-17 12:30:59 -070011 * with a lower bound at "index" and the upper bound at
12 * "index + 5".
13 */
Bruce Allan64806412010-12-11 05:53:42 +000014static const u16 e1000_gg82563_cable_length_table[] = {
Bruce Allan04e115c2013-02-20 04:06:22 +000015 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF
16};
Bruce Allanfc830b72013-02-20 04:06:11 +000017
Bruce Allaneb656d42009-12-01 15:47:02 +000018#define GG82563_CABLE_LENGTH_TABLE_SIZE \
19 ARRAY_SIZE(e1000_gg82563_cable_length_table)
Auke Kokbc7f75f2007-09-17 12:30:59 -070020
21static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
22static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
23static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
24static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
25static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
26static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
27static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
Bruce Allan1f96012d2013-01-05 03:06:54 +000028static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
29 u16 *data);
30static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
31 u16 data);
Bruce Allan17f208d2009-12-01 15:47:22 +000032static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -070033
34/**
35 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
36 * @hw: pointer to the HW structure
Auke Kokbc7f75f2007-09-17 12:30:59 -070037 **/
38static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
39{
40 struct e1000_phy_info *phy = &hw->phy;
41 s32 ret_val;
42
Jeff Kirsher318a94d2008-03-28 09:15:16 -070043 if (hw->phy.media_type != e1000_media_type_copper) {
Bruce Allane80bd1d2013-05-01 01:19:46 +000044 phy->type = e1000_phy_none;
Auke Kokbc7f75f2007-09-17 12:30:59 -070045 return 0;
Bruce Allan17f208d2009-12-01 15:47:22 +000046 } else {
47 phy->ops.power_up = e1000_power_up_phy_copper;
48 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
Auke Kokbc7f75f2007-09-17 12:30:59 -070049 }
50
Bruce Allane80bd1d2013-05-01 01:19:46 +000051 phy->addr = 1;
52 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
53 phy->reset_delay_us = 100;
54 phy->type = e1000_phy_gg82563;
Auke Kokbc7f75f2007-09-17 12:30:59 -070055
56 /* This can only be done after all function pointers are setup. */
57 ret_val = e1000e_get_phy_id(hw);
58
59 /* Verify phy id */
60 if (phy->id != GG82563_E_PHY_ID)
61 return -E1000_ERR_PHY;
62
63 return ret_val;
64}
65
66/**
67 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
68 * @hw: pointer to the HW structure
Auke Kokbc7f75f2007-09-17 12:30:59 -070069 **/
70static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
71{
72 struct e1000_nvm_info *nvm = &hw->nvm;
73 u32 eecd = er32(EECD);
74 u16 size;
75
Bruce Allane80bd1d2013-05-01 01:19:46 +000076 nvm->opcode_bits = 8;
77 nvm->delay_usec = 1;
Auke Kokbc7f75f2007-09-17 12:30:59 -070078 switch (nvm->override) {
79 case e1000_nvm_override_spi_large:
Bruce Allane80bd1d2013-05-01 01:19:46 +000080 nvm->page_size = 32;
Auke Kokbc7f75f2007-09-17 12:30:59 -070081 nvm->address_bits = 16;
82 break;
83 case e1000_nvm_override_spi_small:
Bruce Allane80bd1d2013-05-01 01:19:46 +000084 nvm->page_size = 8;
Auke Kokbc7f75f2007-09-17 12:30:59 -070085 nvm->address_bits = 8;
86 break;
87 default:
Bruce Allane80bd1d2013-05-01 01:19:46 +000088 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
Auke Kokbc7f75f2007-09-17 12:30:59 -070089 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
90 break;
91 }
92
Bruce Allanad680762008-03-28 09:15:03 -070093 nvm->type = e1000_nvm_eeprom_spi;
Auke Kokbc7f75f2007-09-17 12:30:59 -070094
Jesse Brandeburgb9a45252023-12-05 17:01:08 -080095 size = (u16)FIELD_GET(E1000_EECD_SIZE_EX_MASK, eecd);
Auke Kokbc7f75f2007-09-17 12:30:59 -070096
Bruce Allane921eb12012-11-28 09:28:37 +000097 /* Added to a constant, "size" becomes the left-shift value
Auke Kokbc7f75f2007-09-17 12:30:59 -070098 * for setting word_size.
99 */
100 size += NVM_WORD_SIZE_BASE_SHIFT;
Jeff Kirsher8d7c2942008-04-02 13:48:07 -0700101
102 /* EEPROM access above 16k is unsupported */
103 if (size > 14)
104 size = 14;
Jacob Keller18dd2392016-04-13 16:08:32 -0700105 nvm->word_size = BIT(size);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700106
107 return 0;
108}
109
110/**
111 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
112 * @hw: pointer to the HW structure
Auke Kokbc7f75f2007-09-17 12:30:59 -0700113 **/
Bruce Allanec34c172012-02-01 10:53:05 +0000114static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700115{
Auke Kokbc7f75f2007-09-17 12:30:59 -0700116 struct e1000_mac_info *mac = &hw->mac;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700117
Bruce Allane68782e2012-01-31 06:37:43 +0000118 /* Set media type and media-dependent function pointers */
Bruce Allanec34c172012-02-01 10:53:05 +0000119 switch (hw->adapter->pdev->device) {
Auke Kokbc7f75f2007-09-17 12:30:59 -0700120 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
Jeff Kirsher318a94d2008-03-28 09:15:16 -0700121 hw->phy.media_type = e1000_media_type_internal_serdes;
Bruce Allane68782e2012-01-31 06:37:43 +0000122 mac->ops.check_for_link = e1000e_check_for_serdes_link;
123 mac->ops.setup_physical_interface =
124 e1000e_setup_fiber_serdes_link;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700125 break;
126 default:
Jeff Kirsher318a94d2008-03-28 09:15:16 -0700127 hw->phy.media_type = e1000_media_type_copper;
Bruce Allane68782e2012-01-31 06:37:43 +0000128 mac->ops.check_for_link = e1000e_check_for_copper_link;
129 mac->ops.setup_physical_interface =
130 e1000_setup_copper_link_80003es2lan;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700131 break;
132 }
133
134 /* Set mta register count */
135 mac->mta_reg_count = 128;
136 /* Set rar entry count */
137 mac->rar_entry_count = E1000_RAR_ENTRIES;
Bruce Allana65a4a02010-05-10 15:01:51 +0000138 /* FWSM register */
139 mac->has_fwsm = true;
140 /* ARC supported; valid only if manageability features are enabled. */
Bruce Allan04499ec2012-04-13 00:08:31 +0000141 mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);
Bruce Allanf464ba82010-01-07 16:31:35 +0000142 /* Adaptive IFS not supported */
143 mac->adaptive_ifs = false;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700144
Bruce Allanf4d2dd42010-01-13 02:05:18 +0000145 /* set lan id for port to determine which phy lock to use */
146 hw->mac.ops.set_lan_id(hw);
147
Auke Kokbc7f75f2007-09-17 12:30:59 -0700148 return 0;
149}
150
Jeff Kirsher69e3fd82008-04-02 13:48:18 -0700151static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700152{
153 struct e1000_hw *hw = &adapter->hw;
154 s32 rc;
155
Bruce Allanec34c172012-02-01 10:53:05 +0000156 rc = e1000_init_mac_params_80003es2lan(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700157 if (rc)
158 return rc;
159
160 rc = e1000_init_nvm_params_80003es2lan(hw);
161 if (rc)
162 return rc;
163
164 rc = e1000_init_phy_params_80003es2lan(hw);
165 if (rc)
166 return rc;
167
168 return 0;
169}
170
171/**
172 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
173 * @hw: pointer to the HW structure
174 *
Bruce Allanfe401672009-11-20 23:26:05 +0000175 * A wrapper to acquire access rights to the correct PHY.
Auke Kokbc7f75f2007-09-17 12:30:59 -0700176 **/
177static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
178{
179 u16 mask;
180
181 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700182 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
183}
184
185/**
186 * e1000_release_phy_80003es2lan - Release rights to access PHY
187 * @hw: pointer to the HW structure
188 *
Bruce Allanfe401672009-11-20 23:26:05 +0000189 * A wrapper to release access rights to the correct PHY.
Auke Kokbc7f75f2007-09-17 12:30:59 -0700190 **/
191static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
192{
193 u16 mask;
194
195 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
Bruce Allan75eb0fa2008-11-21 16:53:51 -0800196 e1000_release_swfw_sync_80003es2lan(hw, mask);
197}
198
199/**
Bruce Allandffcdde2012-02-17 09:35:33 +0000200 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
Bruce Allan75eb0fa2008-11-21 16:53:51 -0800201 * @hw: pointer to the HW structure
202 *
203 * Acquire the semaphore to access the Kumeran interface.
204 *
205 **/
206static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
207{
208 u16 mask;
209
210 mask = E1000_SWFW_CSR_SM;
211
212 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
213}
214
215/**
Bruce Allandffcdde2012-02-17 09:35:33 +0000216 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
Bruce Allan75eb0fa2008-11-21 16:53:51 -0800217 * @hw: pointer to the HW structure
218 *
219 * Release the semaphore used to access the Kumeran interface
220 **/
221static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
222{
223 u16 mask;
224
225 mask = E1000_SWFW_CSR_SM;
David Graham2d9498f2008-04-23 11:09:14 -0700226
Auke Kokbc7f75f2007-09-17 12:30:59 -0700227 e1000_release_swfw_sync_80003es2lan(hw, mask);
228}
229
230/**
231 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
232 * @hw: pointer to the HW structure
233 *
Bruce Allanfe401672009-11-20 23:26:05 +0000234 * Acquire the semaphore to access the EEPROM.
Auke Kokbc7f75f2007-09-17 12:30:59 -0700235 **/
236static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
237{
238 s32 ret_val;
239
240 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
241 if (ret_val)
242 return ret_val;
243
244 ret_val = e1000e_acquire_nvm(hw);
245
246 if (ret_val)
247 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
248
249 return ret_val;
250}
251
252/**
253 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
254 * @hw: pointer to the HW structure
255 *
Bruce Allanfe401672009-11-20 23:26:05 +0000256 * Release the semaphore used to access the EEPROM.
Auke Kokbc7f75f2007-09-17 12:30:59 -0700257 **/
258static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
259{
260 e1000e_release_nvm(hw);
261 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
262}
263
264/**
265 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
266 * @hw: pointer to the HW structure
267 * @mask: specifies which semaphore to acquire
268 *
269 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
270 * will also specify which port we're acquiring the lock for.
271 **/
272static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
273{
274 u32 swfw_sync;
275 u32 swmask = mask;
276 u32 fwmask = mask << 16;
277 s32 i = 0;
Bruce Allan75eb0fa2008-11-21 16:53:51 -0800278 s32 timeout = 50;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700279
280 while (i < timeout) {
281 if (e1000e_get_hw_semaphore(hw))
282 return -E1000_ERR_SWFW_SYNC;
283
284 swfw_sync = er32(SW_FW_SYNC);
285 if (!(swfw_sync & (fwmask | swmask)))
286 break;
287
Bruce Allane921eb12012-11-28 09:28:37 +0000288 /* Firmware currently using resource (fwmask)
Bruce Allanad680762008-03-28 09:15:03 -0700289 * or other software thread using resource (swmask)
290 */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700291 e1000e_put_hw_semaphore(hw);
292 mdelay(5);
293 i++;
294 }
295
296 if (i == timeout) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000297 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700298 return -E1000_ERR_SWFW_SYNC;
299 }
300
301 swfw_sync |= swmask;
302 ew32(SW_FW_SYNC, swfw_sync);
303
304 e1000e_put_hw_semaphore(hw);
305
306 return 0;
307}
308
309/**
310 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
311 * @hw: pointer to the HW structure
312 * @mask: specifies which semaphore to acquire
313 *
314 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
315 * will also specify which port we're releasing the lock for.
316 **/
317static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
318{
319 u32 swfw_sync;
320
Bruce Allan184125a2010-12-11 05:53:37 +0000321 while (e1000e_get_hw_semaphore(hw) != 0)
322 ; /* Empty */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700323
324 swfw_sync = er32(SW_FW_SYNC);
325 swfw_sync &= ~mask;
326 ew32(SW_FW_SYNC, swfw_sync);
327
328 e1000e_put_hw_semaphore(hw);
329}
330
331/**
332 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
333 * @hw: pointer to the HW structure
334 * @offset: offset of the register to read
335 * @data: pointer to the data returned from the operation
336 *
Bruce Allanfe401672009-11-20 23:26:05 +0000337 * Read the GG82563 PHY register.
Auke Kokbc7f75f2007-09-17 12:30:59 -0700338 **/
339static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
340 u32 offset, u16 *data)
341{
342 s32 ret_val;
343 u32 page_select;
344 u16 temp;
345
David Graham2d9498f2008-04-23 11:09:14 -0700346 ret_val = e1000_acquire_phy_80003es2lan(hw);
347 if (ret_val)
348 return ret_val;
349
Auke Kokbc7f75f2007-09-17 12:30:59 -0700350 /* Select Configuration Page */
David Graham2d9498f2008-04-23 11:09:14 -0700351 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
Auke Kokbc7f75f2007-09-17 12:30:59 -0700352 page_select = GG82563_PHY_PAGE_SELECT;
David Graham2d9498f2008-04-23 11:09:14 -0700353 } else {
Bruce Allane921eb12012-11-28 09:28:37 +0000354 /* Use Alternative Page Select register to access
Auke Kokbc7f75f2007-09-17 12:30:59 -0700355 * registers 30 and 31
356 */
357 page_select = GG82563_PHY_PAGE_SELECT_ALT;
David Graham2d9498f2008-04-23 11:09:14 -0700358 }
Auke Kokbc7f75f2007-09-17 12:30:59 -0700359
360 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
David Graham2d9498f2008-04-23 11:09:14 -0700361 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
362 if (ret_val) {
363 e1000_release_phy_80003es2lan(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700364 return ret_val;
David Graham2d9498f2008-04-23 11:09:14 -0700365 }
Auke Kokbc7f75f2007-09-17 12:30:59 -0700366
Bruce Allanb4d8e212012-02-17 03:17:55 +0000367 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
Bruce Allane921eb12012-11-28 09:28:37 +0000368 /* The "ready" bit in the MDIC register may be incorrectly set
Bruce Allan3421eec2009-12-08 07:28:20 +0000369 * before the device has completed the "Page Select" MDI
370 * transaction. So we wait 200us after each MDI command...
371 */
Bruce Allance43a212013-02-20 04:06:32 +0000372 usleep_range(200, 400);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700373
Bruce Allan3421eec2009-12-08 07:28:20 +0000374 /* ...and verify the command was successful. */
375 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700376
Bruce Allan3421eec2009-12-08 07:28:20 +0000377 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
Bruce Allan3421eec2009-12-08 07:28:20 +0000378 e1000_release_phy_80003es2lan(hw);
Bruce Allan7eb61d82012-02-08 02:55:03 +0000379 return -E1000_ERR_PHY;
Bruce Allan3421eec2009-12-08 07:28:20 +0000380 }
381
Bruce Allance43a212013-02-20 04:06:32 +0000382 usleep_range(200, 400);
Bruce Allan3421eec2009-12-08 07:28:20 +0000383
384 ret_val = e1000e_read_phy_reg_mdic(hw,
Bruce Allanf0ff4392013-02-20 04:05:39 +0000385 MAX_PHY_REG_ADDRESS & offset,
386 data);
Bruce Allan3421eec2009-12-08 07:28:20 +0000387
Bruce Allance43a212013-02-20 04:06:32 +0000388 usleep_range(200, 400);
Bruce Allan3421eec2009-12-08 07:28:20 +0000389 } else {
390 ret_val = e1000e_read_phy_reg_mdic(hw,
Bruce Allanf0ff4392013-02-20 04:05:39 +0000391 MAX_PHY_REG_ADDRESS & offset,
392 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700393 }
394
David Graham2d9498f2008-04-23 11:09:14 -0700395 e1000_release_phy_80003es2lan(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700396
397 return ret_val;
398}
399
400/**
401 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
402 * @hw: pointer to the HW structure
403 * @offset: offset of the register to read
404 * @data: value to write to the register
405 *
Bruce Allanfe401672009-11-20 23:26:05 +0000406 * Write to the GG82563 PHY register.
Auke Kokbc7f75f2007-09-17 12:30:59 -0700407 **/
408static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
409 u32 offset, u16 data)
410{
411 s32 ret_val;
412 u32 page_select;
413 u16 temp;
414
David Graham2d9498f2008-04-23 11:09:14 -0700415 ret_val = e1000_acquire_phy_80003es2lan(hw);
416 if (ret_val)
417 return ret_val;
418
Auke Kokbc7f75f2007-09-17 12:30:59 -0700419 /* Select Configuration Page */
David Graham2d9498f2008-04-23 11:09:14 -0700420 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
Auke Kokbc7f75f2007-09-17 12:30:59 -0700421 page_select = GG82563_PHY_PAGE_SELECT;
David Graham2d9498f2008-04-23 11:09:14 -0700422 } else {
Bruce Allane921eb12012-11-28 09:28:37 +0000423 /* Use Alternative Page Select register to access
Auke Kokbc7f75f2007-09-17 12:30:59 -0700424 * registers 30 and 31
425 */
426 page_select = GG82563_PHY_PAGE_SELECT_ALT;
David Graham2d9498f2008-04-23 11:09:14 -0700427 }
Auke Kokbc7f75f2007-09-17 12:30:59 -0700428
429 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
David Graham2d9498f2008-04-23 11:09:14 -0700430 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
431 if (ret_val) {
432 e1000_release_phy_80003es2lan(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700433 return ret_val;
David Graham2d9498f2008-04-23 11:09:14 -0700434 }
Auke Kokbc7f75f2007-09-17 12:30:59 -0700435
Bruce Allanb4d8e212012-02-17 03:17:55 +0000436 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
Bruce Allane921eb12012-11-28 09:28:37 +0000437 /* The "ready" bit in the MDIC register may be incorrectly set
Bruce Allan3421eec2009-12-08 07:28:20 +0000438 * before the device has completed the "Page Select" MDI
439 * transaction. So we wait 200us after each MDI command...
440 */
Bruce Allance43a212013-02-20 04:06:32 +0000441 usleep_range(200, 400);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700442
Bruce Allan3421eec2009-12-08 07:28:20 +0000443 /* ...and verify the command was successful. */
444 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700445
Bruce Allan3421eec2009-12-08 07:28:20 +0000446 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
447 e1000_release_phy_80003es2lan(hw);
448 return -E1000_ERR_PHY;
449 }
Auke Kokbc7f75f2007-09-17 12:30:59 -0700450
Bruce Allance43a212013-02-20 04:06:32 +0000451 usleep_range(200, 400);
Bruce Allan3421eec2009-12-08 07:28:20 +0000452
453 ret_val = e1000e_write_phy_reg_mdic(hw,
Bruce Allanf0ff4392013-02-20 04:05:39 +0000454 MAX_PHY_REG_ADDRESS &
455 offset, data);
Bruce Allan3421eec2009-12-08 07:28:20 +0000456
Bruce Allance43a212013-02-20 04:06:32 +0000457 usleep_range(200, 400);
Bruce Allan3421eec2009-12-08 07:28:20 +0000458 } else {
459 ret_val = e1000e_write_phy_reg_mdic(hw,
Bruce Allanf0ff4392013-02-20 04:05:39 +0000460 MAX_PHY_REG_ADDRESS &
461 offset, data);
David Graham2d9498f2008-04-23 11:09:14 -0700462 }
Auke Kokbc7f75f2007-09-17 12:30:59 -0700463
David Graham2d9498f2008-04-23 11:09:14 -0700464 e1000_release_phy_80003es2lan(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700465
466 return ret_val;
467}
468
469/**
470 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
471 * @hw: pointer to the HW structure
472 * @offset: offset of the register to read
473 * @words: number of words to write
474 * @data: buffer of data to write to the NVM
475 *
Bruce Allanfe401672009-11-20 23:26:05 +0000476 * Write "words" of data to the ESB2 NVM.
Auke Kokbc7f75f2007-09-17 12:30:59 -0700477 **/
478static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
479 u16 words, u16 *data)
480{
481 return e1000e_write_nvm_spi(hw, offset, words, data);
482}
483
484/**
485 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
486 * @hw: pointer to the HW structure
487 *
488 * Wait a specific amount of time for manageability processes to complete.
489 * This is a function pointer entry point called by the phy module.
490 **/
491static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
492{
493 s32 timeout = PHY_CFG_TIMEOUT;
494 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
495
496 if (hw->bus.func == 1)
497 mask = E1000_NVM_CFG_DONE_PORT_1;
498
499 while (timeout) {
500 if (er32(EEMNGCTL) & mask)
501 break;
Bruce Allan1bba4382011-03-19 00:27:20 +0000502 usleep_range(1000, 2000);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700503 timeout--;
504 }
505 if (!timeout) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000506 e_dbg("MNG configuration cycle has not completed.\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700507 return -E1000_ERR_RESET;
508 }
509
510 return 0;
511}
512
513/**
514 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
515 * @hw: pointer to the HW structure
516 *
517 * Force the speed and duplex settings onto the PHY. This is a
518 * function pointer entry point called by the phy module.
519 **/
520static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
521{
522 s32 ret_val;
523 u16 phy_data;
524 bool link;
525
Bruce Allane921eb12012-11-28 09:28:37 +0000526 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
Auke Kokbc7f75f2007-09-17 12:30:59 -0700527 * forced whenever speed and duplex are forced.
528 */
529 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
530 if (ret_val)
531 return ret_val;
532
533 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
534 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
535 if (ret_val)
536 return ret_val;
537
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000538 e_dbg("GG82563 PSCR: %X\n", phy_data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700539
Bruce Allanc2ade1a2013-01-16 08:54:35 +0000540 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700541 if (ret_val)
542 return ret_val;
543
544 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
545
546 /* Reset the phy to commit changes. */
Bruce Allanc2ade1a2013-01-16 08:54:35 +0000547 phy_data |= BMCR_RESET;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700548
Bruce Allanc2ade1a2013-01-16 08:54:35 +0000549 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700550 if (ret_val)
551 return ret_val;
552
553 udelay(1);
554
Jeff Kirsher318a94d2008-03-28 09:15:16 -0700555 if (hw->phy.autoneg_wait_to_complete) {
Bruce Allan434f1392011-12-16 00:46:54 +0000556 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700557
558 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
Bruce Allan17e813e2013-02-20 04:06:01 +0000559 100000, &link);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700560 if (ret_val)
561 return ret_val;
562
563 if (!link) {
Bruce Allane921eb12012-11-28 09:28:37 +0000564 /* We didn't get link.
Auke Kokbc7f75f2007-09-17 12:30:59 -0700565 * Reset the DSP and cross our fingers.
566 */
567 ret_val = e1000e_phy_reset_dsp(hw);
568 if (ret_val)
569 return ret_val;
570 }
571
572 /* Try once more */
573 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
Bruce Allan17e813e2013-02-20 04:06:01 +0000574 100000, &link);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700575 if (ret_val)
576 return ret_val;
577 }
578
579 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
580 if (ret_val)
581 return ret_val;
582
Bruce Allane921eb12012-11-28 09:28:37 +0000583 /* Resetting the phy means we need to verify the TX_CLK corresponds
Auke Kokbc7f75f2007-09-17 12:30:59 -0700584 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
585 */
586 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
587 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
588 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
589 else
590 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
591
Bruce Allane921eb12012-11-28 09:28:37 +0000592 /* In addition, we must re-enable CRS on Tx for both half and full
Auke Kokbc7f75f2007-09-17 12:30:59 -0700593 * duplex.
594 */
595 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
596 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
597
598 return ret_val;
599}
600
601/**
602 * e1000_get_cable_length_80003es2lan - Set approximate cable length
603 * @hw: pointer to the HW structure
604 *
605 * Find the approximate cable length as measured by the GG82563 PHY.
606 * This is a function pointer entry point called by the phy module.
607 **/
608static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
609{
610 struct e1000_phy_info *phy = &hw->phy;
Bruce Allan70806a72013-01-05 05:08:37 +0000611 s32 ret_val;
Bruce Allana708dd82009-11-20 23:28:37 +0000612 u16 phy_data, index;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700613
614 ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
615 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +0000616 return ret_val;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700617
618 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
Bruce Allaneb656d42009-12-01 15:47:02 +0000619
Bruce Allan5015e532012-02-08 02:55:56 +0000620 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
621 return -E1000_ERR_PHY;
Bruce Allaneb656d42009-12-01 15:47:02 +0000622
Auke Kokbc7f75f2007-09-17 12:30:59 -0700623 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
Bruce Allaneb656d42009-12-01 15:47:02 +0000624 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
Auke Kokbc7f75f2007-09-17 12:30:59 -0700625
626 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
627
Bruce Allan5015e532012-02-08 02:55:56 +0000628 return 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700629}
630
631/**
632 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
633 * @hw: pointer to the HW structure
634 * @speed: pointer to speed buffer
635 * @duplex: pointer to duplex buffer
636 *
637 * Retrieve the current speed and duplex configuration.
Auke Kokbc7f75f2007-09-17 12:30:59 -0700638 **/
639static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
640 u16 *duplex)
641{
642 s32 ret_val;
643
Jeff Kirsher318a94d2008-03-28 09:15:16 -0700644 if (hw->phy.media_type == e1000_media_type_copper) {
Bruce Allan17e813e2013-02-20 04:06:01 +0000645 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
Bruce Allan75eb0fa2008-11-21 16:53:51 -0800646 hw->phy.ops.cfg_on_link_up(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700647 } else {
648 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
Bruce Allan17e813e2013-02-20 04:06:01 +0000649 speed,
650 duplex);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700651 }
652
653 return ret_val;
654}
655
656/**
657 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
658 * @hw: pointer to the HW structure
659 *
660 * Perform a global reset to the ESB2 controller.
Auke Kokbc7f75f2007-09-17 12:30:59 -0700661 **/
662static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
663{
Bruce Allandd93f952011-01-06 14:29:48 +0000664 u32 ctrl;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700665 s32 ret_val;
Matthew Vick1c1093a2012-03-16 09:02:58 +0000666 u16 kum_reg_data;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700667
Bruce Allane921eb12012-11-28 09:28:37 +0000668 /* Prevent the PCI-E bus from sticking if there is no TLP connection
Auke Kokbc7f75f2007-09-17 12:30:59 -0700669 * on the last TLP read/write transaction when MAC is reset.
670 */
671 ret_val = e1000e_disable_pcie_master(hw);
672 if (ret_val)
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000673 e_dbg("PCI-E Master disable polling has failed.\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700674
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000675 e_dbg("Masking off all interrupts\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700676 ew32(IMC, 0xffffffff);
677
678 ew32(RCTL, 0);
679 ew32(TCTL, E1000_TCTL_PSP);
680 e1e_flush();
681
Arjan van de Venab6973a2019-06-14 17:29:35 -0700682 usleep_range(10000, 11000);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700683
684 ctrl = er32(CTRL);
685
Bruce Allan75eb0fa2008-11-21 16:53:51 -0800686 ret_val = e1000_acquire_phy_80003es2lan(hw);
Bruce Allan7dbbe5d2013-01-05 05:08:31 +0000687 if (ret_val)
688 return ret_val;
689
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000690 e_dbg("Issuing a global reset to MAC\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700691 ew32(CTRL, ctrl | E1000_CTRL_RST);
Bruce Allan75eb0fa2008-11-21 16:53:51 -0800692 e1000_release_phy_80003es2lan(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700693
Matthew Vick1c1093a2012-03-16 09:02:58 +0000694 /* Disable IBIST slave mode (far-end loopback) */
David Ertman918a4302013-12-14 07:30:39 +0000695 ret_val =
696 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
697 &kum_reg_data);
Jeff Kirsher979eff22019-01-03 17:17:03 -0800698 if (!ret_val) {
699 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
700 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
701 E1000_KMRNCTRLSTA_INBAND_PARAM,
702 kum_reg_data);
703 if (ret_val)
704 e_dbg("Error disabling far-end loopback\n");
705 } else {
706 e_dbg("Error disabling far-end loopback\n");
707 }
Matthew Vick1c1093a2012-03-16 09:02:58 +0000708
Auke Kokbc7f75f2007-09-17 12:30:59 -0700709 ret_val = e1000e_get_auto_rd_done(hw);
710 if (ret_val)
711 /* We don't want to continue accessing MAC registers. */
712 return ret_val;
713
714 /* Clear any pending interrupt events. */
715 ew32(IMC, 0xffffffff);
Bruce Allandd93f952011-01-06 14:29:48 +0000716 er32(ICR);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700717
Bruce Allan7eb61d82012-02-08 02:55:03 +0000718 return e1000_check_alt_mac_addr_generic(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700719}
720
721/**
722 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
723 * @hw: pointer to the HW structure
724 *
725 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
Auke Kokbc7f75f2007-09-17 12:30:59 -0700726 **/
727static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
728{
729 struct e1000_mac_info *mac = &hw->mac;
730 u32 reg_data;
731 s32 ret_val;
Bruce Alland9b24132011-05-13 07:19:42 +0000732 u16 kum_reg_data;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700733 u16 i;
734
735 e1000_initialize_hw_bits_80003es2lan(hw);
736
737 /* Initialize identification LED */
Bruce Alland1964eb2012-02-22 09:02:21 +0000738 ret_val = mac->ops.id_led_init(hw);
Bruce Allan33550ce2013-02-20 04:06:16 +0000739 /* An error is not fatal and we should not stop init due to this */
Bruce Allande39b752009-11-20 23:27:59 +0000740 if (ret_val)
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000741 e_dbg("Error initializing identification LED\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700742
743 /* Disabling VLAN filtering */
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000744 e_dbg("Initializing the IEEE VLAN\n");
Bruce Allancaaddaf2009-12-01 15:46:43 +0000745 mac->ops.clear_vfta(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700746
747 /* Setup the receive address. */
748 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
749
750 /* Zero out the Multicast HASH table */
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000751 e_dbg("Zeroing the MTA\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700752 for (i = 0; i < mac->mta_reg_count; i++)
753 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
754
755 /* Setup link and flow control */
Bruce Allan1a46b402012-02-22 09:02:26 +0000756 ret_val = mac->ops.setup_link(hw);
Bruce Allan7dbbe5d2013-01-05 05:08:31 +0000757 if (ret_val)
758 return ret_val;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700759
Bruce Alland9b24132011-05-13 07:19:42 +0000760 /* Disable IBIST slave mode (far-end loopback) */
Jeff Kirsher979eff22019-01-03 17:17:03 -0800761 ret_val =
762 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
763 &kum_reg_data);
764 if (!ret_val) {
765 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
766 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
767 E1000_KMRNCTRLSTA_INBAND_PARAM,
768 kum_reg_data);
769 if (ret_val)
770 e_dbg("Error disabling far-end loopback\n");
771 } else {
772 e_dbg("Error disabling far-end loopback\n");
773 }
Bruce Alland9b24132011-05-13 07:19:42 +0000774
Auke Kokbc7f75f2007-09-17 12:30:59 -0700775 /* Set the transmit descriptor write-back policy */
Jeff Kirshere9ec2c02008-04-02 13:48:13 -0700776 reg_data = er32(TXDCTL(0));
Bruce Allanf0ff4392013-02-20 04:05:39 +0000777 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
778 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
Jeff Kirshere9ec2c02008-04-02 13:48:13 -0700779 ew32(TXDCTL(0), reg_data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700780
781 /* ...for both queues. */
Jeff Kirshere9ec2c02008-04-02 13:48:13 -0700782 reg_data = er32(TXDCTL(1));
Bruce Allanf0ff4392013-02-20 04:05:39 +0000783 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
784 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
Jeff Kirshere9ec2c02008-04-02 13:48:13 -0700785 ew32(TXDCTL(1), reg_data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700786
787 /* Enable retransmit on late collisions */
788 reg_data = er32(TCTL);
789 reg_data |= E1000_TCTL_RTLC;
790 ew32(TCTL, reg_data);
791
792 /* Configure Gigabit Carry Extend Padding */
793 reg_data = er32(TCTL_EXT);
794 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
795 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
796 ew32(TCTL_EXT, reg_data);
797
798 /* Configure Transmit Inter-Packet Gap */
799 reg_data = er32(TIPG);
800 reg_data &= ~E1000_TIPG_IPGT_MASK;
801 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
802 ew32(TIPG, reg_data);
803
804 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
805 reg_data &= ~0x00100000;
806 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
807
Bruce Allan3421eec2009-12-08 07:28:20 +0000808 /* default to true to enable the MDIC W/A */
809 hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
810
Bruce Allanf0ff4392013-02-20 04:05:39 +0000811 ret_val =
812 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
813 E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
Bruce Allan3421eec2009-12-08 07:28:20 +0000814 if (!ret_val) {
815 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
Bruce Allan17e813e2013-02-20 04:06:01 +0000816 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
Bruce Allan3421eec2009-12-08 07:28:20 +0000817 hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
818 }
819
Bruce Allane921eb12012-11-28 09:28:37 +0000820 /* Clear all of the statistics registers (clear on read). It is
Auke Kokbc7f75f2007-09-17 12:30:59 -0700821 * important that we do this after we have tried to establish link
822 * because the symbol error count will increment wildly if there
823 * is no link.
824 */
825 e1000_clear_hw_cntrs_80003es2lan(hw);
826
827 return ret_val;
828}
829
830/**
831 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
832 * @hw: pointer to the HW structure
833 *
834 * Initializes required hardware-dependent bits needed for normal operation.
835 **/
836static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
837{
838 u32 reg;
839
840 /* Transmit Descriptor Control 0 */
Jeff Kirshere9ec2c02008-04-02 13:48:13 -0700841 reg = er32(TXDCTL(0));
Jacob Keller18dd2392016-04-13 16:08:32 -0700842 reg |= BIT(22);
Jeff Kirshere9ec2c02008-04-02 13:48:13 -0700843 ew32(TXDCTL(0), reg);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700844
845 /* Transmit Descriptor Control 1 */
Jeff Kirshere9ec2c02008-04-02 13:48:13 -0700846 reg = er32(TXDCTL(1));
Jacob Keller18dd2392016-04-13 16:08:32 -0700847 reg |= BIT(22);
Jeff Kirshere9ec2c02008-04-02 13:48:13 -0700848 ew32(TXDCTL(1), reg);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700849
850 /* Transmit Arbitration Control 0 */
Jeff Kirshere9ec2c02008-04-02 13:48:13 -0700851 reg = er32(TARC(0));
Bruce Allane80bd1d2013-05-01 01:19:46 +0000852 reg &= ~(0xF << 27); /* 30:27 */
Jeff Kirsher318a94d2008-03-28 09:15:16 -0700853 if (hw->phy.media_type != e1000_media_type_copper)
Jacob Keller18dd2392016-04-13 16:08:32 -0700854 reg &= ~BIT(20);
Jeff Kirshere9ec2c02008-04-02 13:48:13 -0700855 ew32(TARC(0), reg);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700856
857 /* Transmit Arbitration Control 1 */
Jeff Kirshere9ec2c02008-04-02 13:48:13 -0700858 reg = er32(TARC(1));
Auke Kokbc7f75f2007-09-17 12:30:59 -0700859 if (er32(TCTL) & E1000_TCTL_MULR)
Jacob Keller18dd2392016-04-13 16:08:32 -0700860 reg &= ~BIT(28);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700861 else
Jacob Keller18dd2392016-04-13 16:08:32 -0700862 reg |= BIT(28);
Jeff Kirshere9ec2c02008-04-02 13:48:13 -0700863 ew32(TARC(1), reg);
Matthew Vickf6bd5572012-04-25 08:01:05 +0000864
Bruce Allane921eb12012-11-28 09:28:37 +0000865 /* Disable IPv6 extension header parsing because some malformed
Matthew Vickf6bd5572012-04-25 08:01:05 +0000866 * IPv6 headers can hang the Rx.
867 */
868 reg = er32(RFCTL);
869 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
870 ew32(RFCTL, reg);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700871}
872
873/**
874 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
875 * @hw: pointer to the HW structure
876 *
877 * Setup some GG82563 PHY registers for obtaining link
878 **/
879static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
880{
881 struct e1000_phy_info *phy = &hw->phy;
882 s32 ret_val;
Bruce Allan17e813e2013-02-20 04:06:01 +0000883 u32 reg;
Bruce Allan75eb0fa2008-11-21 16:53:51 -0800884 u16 data;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700885
David Graham2d9498f2008-04-23 11:09:14 -0700886 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700887 if (ret_val)
888 return ret_val;
889
890 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
891 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
892 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
893
David Graham2d9498f2008-04-23 11:09:14 -0700894 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700895 if (ret_val)
896 return ret_val;
897
Bruce Allane921eb12012-11-28 09:28:37 +0000898 /* Options:
Auke Kokbc7f75f2007-09-17 12:30:59 -0700899 * MDI/MDI-X = 0 (default)
900 * 0 - Auto for all speeds
901 * 1 - MDI mode
902 * 2 - MDI-X mode
903 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
904 */
905 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
906 if (ret_val)
907 return ret_val;
908
909 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
910
911 switch (phy->mdix) {
912 case 1:
913 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
914 break;
915 case 2:
916 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
917 break;
918 case 0:
919 default:
920 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
921 break;
922 }
923
Bruce Allane921eb12012-11-28 09:28:37 +0000924 /* Options:
Auke Kokbc7f75f2007-09-17 12:30:59 -0700925 * disable_polarity_correction = 0 (default)
926 * Automatic Correction for Reversed Cable Polarity
927 * 0 - Disabled
928 * 1 - Enabled
929 */
930 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
931 if (phy->disable_polarity_correction)
932 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
933
934 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
935 if (ret_val)
936 return ret_val;
937
938 /* SW Reset the PHY so all changes take effect */
Bruce Allan6b598e12013-01-23 06:50:05 +0000939 ret_val = hw->phy.ops.commit(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700940 if (ret_val) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000941 e_dbg("Error Resetting the PHY\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700942 return ret_val;
943 }
944
Bruce Allanad680762008-03-28 09:15:03 -0700945 /* Bypass Rx and Tx FIFO's */
Bruce Allan17e813e2013-02-20 04:06:01 +0000946 reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
947 data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
948 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
949 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700950 if (ret_val)
951 return ret_val;
952
Bruce Allan17e813e2013-02-20 04:06:01 +0000953 reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
954 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
David Graham2d9498f2008-04-23 11:09:14 -0700955 if (ret_val)
956 return ret_val;
957 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
Bruce Allan17e813e2013-02-20 04:06:01 +0000958 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
David Graham2d9498f2008-04-23 11:09:14 -0700959 if (ret_val)
960 return ret_val;
961
Auke Kokbc7f75f2007-09-17 12:30:59 -0700962 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
963 if (ret_val)
964 return ret_val;
965
966 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
967 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
968 if (ret_val)
969 return ret_val;
970
Bruce Allan17e813e2013-02-20 04:06:01 +0000971 reg = er32(CTRL_EXT);
972 reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
973 ew32(CTRL_EXT, reg);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700974
975 ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
976 if (ret_val)
977 return ret_val;
978
Bruce Allane921eb12012-11-28 09:28:37 +0000979 /* Do not init these registers when the HW is in IAMT mode, since the
Auke Kokbc7f75f2007-09-17 12:30:59 -0700980 * firmware will have already initialized them. We only initialize
981 * them if the HW is not in IAMT mode.
982 */
Bruce Allan487683292012-02-22 09:02:32 +0000983 if (!hw->mac.ops.check_mng_mode(hw)) {
Auke Kokbc7f75f2007-09-17 12:30:59 -0700984 /* Enable Electrical Idle on the PHY */
985 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
986 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
987 if (ret_val)
988 return ret_val;
989
Bruce Allan75eb0fa2008-11-21 16:53:51 -0800990 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
991 if (ret_val)
992 return ret_val;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700993
994 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
995 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
996 if (ret_val)
997 return ret_val;
998 }
999
Bruce Allane921eb12012-11-28 09:28:37 +00001000 /* Workaround: Disable padding in Kumeran interface in the MAC
Auke Kokbc7f75f2007-09-17 12:30:59 -07001001 * and in the PHY to avoid CRC errors.
1002 */
1003 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1004 if (ret_val)
1005 return ret_val;
1006
1007 data |= GG82563_ICR_DIS_PADDING;
1008 ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1009 if (ret_val)
1010 return ret_val;
1011
1012 return 0;
1013}
1014
1015/**
1016 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1017 * @hw: pointer to the HW structure
1018 *
1019 * Essentially a wrapper for setting up all things "copper" related.
1020 * This is a function pointer entry point called by the mac module.
1021 **/
1022static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1023{
1024 u32 ctrl;
1025 s32 ret_val;
1026 u16 reg_data;
1027
1028 ctrl = er32(CTRL);
1029 ctrl |= E1000_CTRL_SLU;
1030 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1031 ew32(CTRL, ctrl);
1032
Bruce Allane921eb12012-11-28 09:28:37 +00001033 /* Set the mac to wait the maximum time between each
Auke Kokbc7f75f2007-09-17 12:30:59 -07001034 * iteration and increase the max iterations when
Bruce Allanad680762008-03-28 09:15:03 -07001035 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1036 */
Jesse Brandeburg236f31b2023-12-05 17:01:00 -08001037 /* these next three accesses were always meant to use page 0x34 using
1038 * GG82563_REG(0x34, N) but never did, so we've just corrected the call
1039 * to not drop bits
1040 */
1041 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 4, 0xFFFF);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001042 if (ret_val)
1043 return ret_val;
Jesse Brandeburg236f31b2023-12-05 17:01:00 -08001044 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, 9, &reg_data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001045 if (ret_val)
1046 return ret_val;
1047 reg_data |= 0x3F;
Jesse Brandeburg236f31b2023-12-05 17:01:00 -08001048 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 9, reg_data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001049 if (ret_val)
1050 return ret_val;
Bruce Allanf0ff4392013-02-20 04:05:39 +00001051 ret_val =
1052 e1000_read_kmrn_reg_80003es2lan(hw,
1053 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1054 &reg_data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001055 if (ret_val)
1056 return ret_val;
1057 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
Bruce Allanf0ff4392013-02-20 04:05:39 +00001058 ret_val =
1059 e1000_write_kmrn_reg_80003es2lan(hw,
1060 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1061 reg_data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001062 if (ret_val)
1063 return ret_val;
1064
1065 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1066 if (ret_val)
1067 return ret_val;
1068
Bruce Allan8649f432012-02-08 02:54:58 +00001069 return e1000e_setup_copper_link(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001070}
1071
1072/**
Bruce Allan75eb0fa2008-11-21 16:53:51 -08001073 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1074 * @hw: pointer to the HW structure
Bruce Allan75eb0fa2008-11-21 16:53:51 -08001075 *
1076 * Configure the KMRN interface by applying last minute quirks for
1077 * 10/100 operation.
1078 **/
1079static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1080{
1081 s32 ret_val = 0;
1082 u16 speed;
1083 u16 duplex;
1084
1085 if (hw->phy.media_type == e1000_media_type_copper) {
1086 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
Bruce Allanf0ff4392013-02-20 04:05:39 +00001087 &duplex);
Bruce Allan75eb0fa2008-11-21 16:53:51 -08001088 if (ret_val)
1089 return ret_val;
1090
1091 if (speed == SPEED_1000)
1092 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1093 else
1094 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1095 }
1096
1097 return ret_val;
1098}
1099
1100/**
Auke Kokbc7f75f2007-09-17 12:30:59 -07001101 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1102 * @hw: pointer to the HW structure
1103 * @duplex: current duplex setting
1104 *
1105 * Configure the KMRN interface by applying last minute quirks for
1106 * 10/100 operation.
1107 **/
1108static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1109{
1110 s32 ret_val;
1111 u32 tipg;
David Graham2d9498f2008-04-23 11:09:14 -07001112 u32 i = 0;
1113 u16 reg_data, reg_data2;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001114
1115 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
Bruce Allanf0ff4392013-02-20 04:05:39 +00001116 ret_val =
1117 e1000_write_kmrn_reg_80003es2lan(hw,
1118 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1119 reg_data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001120 if (ret_val)
1121 return ret_val;
1122
1123 /* Configure Transmit Inter-Packet Gap */
1124 tipg = er32(TIPG);
1125 tipg &= ~E1000_TIPG_IPGT_MASK;
1126 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1127 ew32(TIPG, tipg);
1128
David Graham2d9498f2008-04-23 11:09:14 -07001129 do {
1130 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1131 if (ret_val)
1132 return ret_val;
1133
1134 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1135 if (ret_val)
1136 return ret_val;
1137 i++;
1138 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
Auke Kokbc7f75f2007-09-17 12:30:59 -07001139
1140 if (duplex == HALF_DUPLEX)
1141 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1142 else
1143 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1144
Bruce Allan520d6f22012-02-08 02:54:53 +00001145 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001146}
1147
1148/**
1149 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1150 * @hw: pointer to the HW structure
1151 *
1152 * Configure the KMRN interface by applying last minute quirks for
1153 * gigabit operation.
1154 **/
1155static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1156{
1157 s32 ret_val;
David Graham2d9498f2008-04-23 11:09:14 -07001158 u16 reg_data, reg_data2;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001159 u32 tipg;
David Graham2d9498f2008-04-23 11:09:14 -07001160 u32 i = 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001161
1162 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
Bruce Allanf0ff4392013-02-20 04:05:39 +00001163 ret_val =
1164 e1000_write_kmrn_reg_80003es2lan(hw,
1165 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1166 reg_data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001167 if (ret_val)
1168 return ret_val;
1169
1170 /* Configure Transmit Inter-Packet Gap */
1171 tipg = er32(TIPG);
1172 tipg &= ~E1000_TIPG_IPGT_MASK;
1173 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1174 ew32(TIPG, tipg);
1175
David Graham2d9498f2008-04-23 11:09:14 -07001176 do {
1177 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1178 if (ret_val)
1179 return ret_val;
1180
1181 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1182 if (ret_val)
1183 return ret_val;
1184 i++;
1185 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
Auke Kokbc7f75f2007-09-17 12:30:59 -07001186
1187 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001188
Bruce Allan7eb61d82012-02-08 02:55:03 +00001189 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001190}
1191
1192/**
Bruce Allan75eb0fa2008-11-21 16:53:51 -08001193 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1194 * @hw: pointer to the HW structure
1195 * @offset: register offset to be read
1196 * @data: pointer to the read data
1197 *
1198 * Acquire semaphore, then read the PHY register at offset
1199 * using the kumeran interface. The information retrieved is stored in data.
1200 * Release the semaphore before exiting.
1201 **/
Hannes Ederfa4c16d2008-12-22 09:16:13 +00001202static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1203 u16 *data)
Bruce Allan75eb0fa2008-11-21 16:53:51 -08001204{
1205 u32 kmrnctrlsta;
Bruce Allan70806a72013-01-05 05:08:37 +00001206 s32 ret_val;
Bruce Allan75eb0fa2008-11-21 16:53:51 -08001207
1208 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1209 if (ret_val)
1210 return ret_val;
1211
Jesse Brandeburg4d893c12023-12-05 17:01:02 -08001212 kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) |
1213 E1000_KMRNCTRLSTA_REN;
Bruce Allan75eb0fa2008-11-21 16:53:51 -08001214 ew32(KMRNCTRLSTA, kmrnctrlsta);
Jesse Brandeburg945a5152011-07-20 00:56:21 +00001215 e1e_flush();
Bruce Allan75eb0fa2008-11-21 16:53:51 -08001216
1217 udelay(2);
1218
1219 kmrnctrlsta = er32(KMRNCTRLSTA);
1220 *data = (u16)kmrnctrlsta;
1221
1222 e1000_release_mac_csr_80003es2lan(hw);
1223
1224 return ret_val;
1225}
1226
1227/**
1228 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1229 * @hw: pointer to the HW structure
1230 * @offset: register offset to write to
1231 * @data: data to write at register offset
1232 *
1233 * Acquire semaphore, then write the data to PHY register
1234 * at the offset using the kumeran interface. Release semaphore
1235 * before exiting.
1236 **/
Hannes Ederfa4c16d2008-12-22 09:16:13 +00001237static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1238 u16 data)
Bruce Allan75eb0fa2008-11-21 16:53:51 -08001239{
1240 u32 kmrnctrlsta;
Bruce Allan70806a72013-01-05 05:08:37 +00001241 s32 ret_val;
Bruce Allan75eb0fa2008-11-21 16:53:51 -08001242
1243 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1244 if (ret_val)
1245 return ret_val;
1246
Jesse Brandeburg4d893c12023-12-05 17:01:02 -08001247 kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) | data;
Bruce Allan75eb0fa2008-11-21 16:53:51 -08001248 ew32(KMRNCTRLSTA, kmrnctrlsta);
Jesse Brandeburg945a5152011-07-20 00:56:21 +00001249 e1e_flush();
Bruce Allan75eb0fa2008-11-21 16:53:51 -08001250
1251 udelay(2);
1252
1253 e1000_release_mac_csr_80003es2lan(hw);
1254
1255 return ret_val;
1256}
1257
1258/**
Bruce Allan608f8a02010-01-13 02:04:58 +00001259 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1260 * @hw: pointer to the HW structure
1261 **/
1262static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1263{
Bruce Allan70806a72013-01-05 05:08:37 +00001264 s32 ret_val;
Bruce Allan608f8a02010-01-13 02:04:58 +00001265
Bruce Allane921eb12012-11-28 09:28:37 +00001266 /* If there's an alternate MAC address place it in RAR0
Bruce Allan608f8a02010-01-13 02:04:58 +00001267 * so that it will override the Si installed default perm
1268 * address.
1269 */
1270 ret_val = e1000_check_alt_mac_addr_generic(hw);
1271 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00001272 return ret_val;
Bruce Allan608f8a02010-01-13 02:04:58 +00001273
Bruce Allan5015e532012-02-08 02:55:56 +00001274 return e1000_read_mac_addr_generic(hw);
Bruce Allan608f8a02010-01-13 02:04:58 +00001275}
1276
1277/**
Bruce Allan17f208d2009-12-01 15:47:22 +00001278 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1279 * @hw: pointer to the HW structure
1280 *
1281 * In the case of a PHY power down to save power, or to turn off link during a
1282 * driver unload, or wake on lan is not enabled, remove the link.
1283 **/
1284static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1285{
1286 /* If the management interface is not enabled, then power down */
1287 if (!(hw->mac.ops.check_mng_mode(hw) ||
1288 hw->phy.ops.check_reset_block(hw)))
1289 e1000_power_down_phy_copper(hw);
Bruce Allan17f208d2009-12-01 15:47:22 +00001290}
1291
1292/**
Auke Kokbc7f75f2007-09-17 12:30:59 -07001293 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1294 * @hw: pointer to the HW structure
1295 *
1296 * Clears the hardware counters by reading the counter registers.
1297 **/
1298static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1299{
Auke Kokbc7f75f2007-09-17 12:30:59 -07001300 e1000e_clear_hw_cntrs_base(hw);
1301
Bruce Allan99673d92009-11-20 23:27:21 +00001302 er32(PRC64);
1303 er32(PRC127);
1304 er32(PRC255);
1305 er32(PRC511);
1306 er32(PRC1023);
1307 er32(PRC1522);
1308 er32(PTC64);
1309 er32(PTC127);
1310 er32(PTC255);
1311 er32(PTC511);
1312 er32(PTC1023);
1313 er32(PTC1522);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001314
Bruce Allan99673d92009-11-20 23:27:21 +00001315 er32(ALGNERRC);
1316 er32(RXERRC);
1317 er32(TNCRS);
1318 er32(CEXTERR);
1319 er32(TSCTC);
1320 er32(TSCTFC);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001321
Bruce Allan99673d92009-11-20 23:27:21 +00001322 er32(MGTPRC);
1323 er32(MGTPDC);
1324 er32(MGTPTC);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001325
Bruce Allan99673d92009-11-20 23:27:21 +00001326 er32(IAC);
1327 er32(ICRXOC);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001328
Bruce Allan99673d92009-11-20 23:27:21 +00001329 er32(ICRXPTC);
1330 er32(ICRXATC);
1331 er32(ICTXPTC);
1332 er32(ICTXATC);
1333 er32(ICTXQEC);
1334 er32(ICTXQMTC);
1335 er32(ICRXDMTC);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001336}
1337
Jeff Kirsher8ce9d6c2011-09-24 13:23:52 +00001338static const struct e1000_mac_operations es2_mac_ops = {
Bruce Allan608f8a02010-01-13 02:04:58 +00001339 .read_mac_addr = e1000_read_mac_addr_80003es2lan,
Bruce Alland1964eb2012-02-22 09:02:21 +00001340 .id_led_init = e1000e_id_led_init_generic,
Bruce Allandbf80dc2011-04-16 00:34:40 +00001341 .blink_led = e1000e_blink_led_generic,
Bruce Allan4662e822008-08-26 18:37:06 -07001342 .check_mng_mode = e1000e_check_mng_mode_generic,
Auke Kokbc7f75f2007-09-17 12:30:59 -07001343 /* check_for_link dependent on media type */
1344 .cleanup_led = e1000e_cleanup_led_generic,
1345 .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan,
1346 .get_bus_info = e1000e_get_bus_info_pcie,
Bruce Allanf4d2dd42010-01-13 02:05:18 +00001347 .set_lan_id = e1000_set_lan_id_multi_port_pcie,
Auke Kokbc7f75f2007-09-17 12:30:59 -07001348 .get_link_up_info = e1000_get_link_up_info_80003es2lan,
1349 .led_on = e1000e_led_on_generic,
1350 .led_off = e1000e_led_off_generic,
Jeff Kirshere2de3eb2008-03-28 09:15:11 -07001351 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
Bruce Allancaaddaf2009-12-01 15:46:43 +00001352 .write_vfta = e1000_write_vfta_generic,
1353 .clear_vfta = e1000_clear_vfta_generic,
Auke Kokbc7f75f2007-09-17 12:30:59 -07001354 .reset_hw = e1000_reset_hw_80003es2lan,
1355 .init_hw = e1000_init_hw_80003es2lan,
Bruce Allan1a46b402012-02-22 09:02:26 +00001356 .setup_link = e1000e_setup_link_generic,
Auke Kokbc7f75f2007-09-17 12:30:59 -07001357 /* setup_physical_interface dependent on media type */
Bruce Allana4f58f52009-06-02 11:29:18 +00001358 .setup_led = e1000e_setup_led_generic,
Bruce Allan57cde762012-02-22 09:02:58 +00001359 .config_collision_dist = e1000e_config_collision_dist_generic,
Bruce Allan69e1e012012-04-14 03:28:50 +00001360 .rar_set = e1000e_rar_set_generic,
David Ertmanb3e5bf12014-05-06 03:50:17 +00001361 .rar_get_count = e1000e_rar_get_count_generic,
Auke Kokbc7f75f2007-09-17 12:30:59 -07001362};
1363
Jeff Kirsher8ce9d6c2011-09-24 13:23:52 +00001364static const struct e1000_phy_operations es2_phy_ops = {
Bruce Allan94d81862009-11-20 23:25:26 +00001365 .acquire = e1000_acquire_phy_80003es2lan,
Bruce Allan94e5b652009-12-02 17:02:14 +00001366 .check_polarity = e1000_check_polarity_m88,
Auke Kokbc7f75f2007-09-17 12:30:59 -07001367 .check_reset_block = e1000e_check_reset_block_generic,
Bruce Allan55c5f552013-01-12 07:28:24 +00001368 .commit = e1000e_phy_sw_reset,
1369 .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan,
1370 .get_cfg_done = e1000_get_cfg_done_80003es2lan,
1371 .get_cable_length = e1000_get_cable_length_80003es2lan,
1372 .get_info = e1000e_get_phy_info_m88,
1373 .read_reg = e1000_read_phy_reg_gg82563_80003es2lan,
Bruce Allan94d81862009-11-20 23:25:26 +00001374 .release = e1000_release_phy_80003es2lan,
Bruce Allan55c5f552013-01-12 07:28:24 +00001375 .reset = e1000e_phy_hw_reset_generic,
1376 .set_d0_lplu_state = NULL,
1377 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1378 .write_reg = e1000_write_phy_reg_gg82563_80003es2lan,
1379 .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan,
Auke Kokbc7f75f2007-09-17 12:30:59 -07001380};
1381
Jeff Kirsher8ce9d6c2011-09-24 13:23:52 +00001382static const struct e1000_nvm_operations es2_nvm_ops = {
Bruce Allan94d81862009-11-20 23:25:26 +00001383 .acquire = e1000_acquire_nvm_80003es2lan,
1384 .read = e1000e_read_nvm_eerd,
1385 .release = e1000_release_nvm_80003es2lan,
Bruce Allane85e3632012-02-22 09:03:14 +00001386 .reload = e1000e_reload_nvm_generic,
Bruce Allan94d81862009-11-20 23:25:26 +00001387 .update = e1000e_update_nvm_checksum_generic,
Auke Kokbc7f75f2007-09-17 12:30:59 -07001388 .valid_led_default = e1000e_valid_led_default,
Bruce Allan94d81862009-11-20 23:25:26 +00001389 .validate = e1000e_validate_nvm_checksum_generic,
1390 .write = e1000_write_nvm_80003es2lan,
Auke Kokbc7f75f2007-09-17 12:30:59 -07001391};
1392
Jeff Kirsher8ce9d6c2011-09-24 13:23:52 +00001393const struct e1000_info e1000_es2_info = {
Auke Kokbc7f75f2007-09-17 12:30:59 -07001394 .mac = e1000_80003es2lan,
1395 .flags = FLAG_HAS_HW_VLAN_FILTER
1396 | FLAG_HAS_JUMBO_FRAMES
Auke Kokbc7f75f2007-09-17 12:30:59 -07001397 | FLAG_HAS_WOL
1398 | FLAG_APME_IN_CTRL3
Auke Kokbc7f75f2007-09-17 12:30:59 -07001399 | FLAG_HAS_CTRLEXT_ON_LOAD
Auke Kokbc7f75f2007-09-17 12:30:59 -07001400 | FLAG_RX_NEEDS_RESTART /* errata */
1401 | FLAG_TARC_SET_BIT_ZERO /* errata */
1402 | FLAG_APME_CHECK_PORT_B
Bruce Allan6a92f732011-12-16 00:46:12 +00001403 | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */
Jesse Brandeburg3a3b7582010-09-29 21:38:49 +00001404 .flags2 = FLAG2_DMA_BURST,
Auke Kokbc7f75f2007-09-17 12:30:59 -07001405 .pba = 38,
Bruce Allan2adc55c2009-06-02 11:28:58 +00001406 .max_hw_frame_size = DEFAULT_JUMBO,
Jeff Kirsher69e3fd82008-04-02 13:48:18 -07001407 .get_variants = e1000_get_variants_80003es2lan,
Auke Kokbc7f75f2007-09-17 12:30:59 -07001408 .mac_ops = &es2_mac_ops,
1409 .phy_ops = &es2_phy_ops,
1410 .nvm_ops = &es2_nvm_ops,
1411};