blob: 16ca427cf4c3f4325cc6942efefc2c9d68237d27 [file] [log] [blame]
Thomas Gleixner8e8e69d2019-05-29 07:17:59 -07001// SPDX-License-Identifier: GPL-2.0-only
2/*
John Crispin656e7052016-03-08 11:29:55 +01003 *
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
7 */
8
Rob Herring3d40aed2023-07-26 19:49:39 -06009#include <linux/of.h>
John Crispin656e7052016-03-08 11:29:55 +010010#include <linux/of_mdio.h>
11#include <linux/of_net.h>
Felix Fietkaud776a572022-04-05 21:57:43 +020012#include <linux/of_address.h>
John Crispin656e7052016-03-08 11:29:55 +010013#include <linux/mfd/syscon.h>
Rob Herring3d40aed2023-07-26 19:49:39 -060014#include <linux/platform_device.h>
John Crispin656e7052016-03-08 11:29:55 +010015#include <linux/regmap.h>
16#include <linux/clk.h>
Sean Wang26a2ad82016-09-14 23:13:18 +080017#include <linux/pm_runtime.h>
John Crispin656e7052016-03-08 11:29:55 +010018#include <linux/if_vlan.h>
19#include <linux/reset.h>
20#include <linux/tcp.h>
Mark Brown70dba202017-07-20 11:06:31 +010021#include <linux/interrupt.h>
Thierry Reding140995c2018-02-05 13:54:36 +010022#include <linux/pinctrl/devinfo.h>
René van Dorstb8fc9f32019-08-25 19:43:39 +020023#include <linux/phylink.h>
Daniel Golle2a3ec7a2023-03-19 12:58:02 +000024#include <linux/pcs/pcs-mtk-lynxi.h>
Felix Fietkaufa8172722021-04-22 22:21:07 -070025#include <linux/jhash.h>
Felix Fietkauc4f033d2022-04-05 21:57:53 +020026#include <linux/bitfield.h>
Felix Fietkaud5c53da2021-03-24 02:30:52 +010027#include <net/dsa.h>
Felix Fietkau2d7605a2022-11-14 13:42:14 +010028#include <net/dst_metadata.h>
Yunsheng Lina9ca9f92023-08-04 20:05:24 +020029#include <net/page_pool/helpers.h>
John Crispin656e7052016-03-08 11:29:55 +010030
31#include "mtk_eth_soc.h"
Felix Fietkau804775d2022-04-05 21:57:47 +020032#include "mtk_wed.h"
John Crispin656e7052016-03-08 11:29:55 +010033
34static int mtk_msg_level = -1;
35module_param_named(msg_level, mtk_msg_level, int, 0);
36MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
37
38#define MTK_ETHTOOL_STAT(x) { #x, \
39 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
40
Lorenzo Bianconi916a6ee2022-07-22 09:19:38 +020041#define MTK_ETHTOOL_XDP_STAT(x) { #x, \
42 offsetof(struct mtk_hw_stats, xdp_stats.x) / \
43 sizeof(u64) }
44
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +020045static const struct mtk_reg_map mtk_reg_map = {
46 .tx_irq_mask = 0x1a1c,
47 .tx_irq_status = 0x1a18,
48 .pdma = {
49 .rx_ptr = 0x0900,
50 .rx_cnt_cfg = 0x0904,
51 .pcrx_ptr = 0x0908,
52 .glo_cfg = 0x0a04,
53 .rst_idx = 0x0a08,
54 .delay_irq = 0x0a0c,
55 .irq_status = 0x0a20,
56 .irq_mask = 0x0a28,
Lorenzo Bianconi93b25912023-01-14 18:01:31 +010057 .adma_rx_dbg0 = 0x0a38,
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +020058 .int_grp = 0x0a50,
59 },
60 .qdma = {
61 .qtx_cfg = 0x1800,
Felix Fietkauf63959c2022-11-16 09:07:32 +010062 .qtx_sch = 0x1804,
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +020063 .rx_ptr = 0x1900,
64 .rx_cnt_cfg = 0x1904,
65 .qcrx_ptr = 0x1908,
66 .glo_cfg = 0x1a04,
67 .rst_idx = 0x1a08,
68 .delay_irq = 0x1a0c,
69 .fc_th = 0x1a10,
Felix Fietkauf63959c2022-11-16 09:07:32 +010070 .tx_sch_rate = 0x1a14,
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +020071 .int_grp = 0x1a20,
72 .hred = 0x1a44,
73 .ctx_ptr = 0x1b00,
74 .dtx_ptr = 0x1b04,
75 .crx_ptr = 0x1b10,
76 .drx_ptr = 0x1b14,
77 .fq_head = 0x1b20,
78 .fq_tail = 0x1b24,
79 .fq_count = 0x1b28,
80 .fq_blen = 0x1b2c,
81 },
82 .gdm1_cnt = 0x2400,
Elad Yifeedee4dd12024-06-07 11:21:50 +030083 .gdma_to_ppe = {
84 [0] = 0x4444,
85 },
Lorenzo Bianconi329bce52022-09-20 12:11:15 +020086 .ppe_base = 0x0c00,
Lorenzo Bianconi0c1d3fb2022-09-20 12:11:18 +020087 .wdma_base = {
88 [0] = 0x2800,
89 [1] = 0x2c00,
90 },
Lorenzo Bianconi93b25912023-01-14 18:01:31 +010091 .pse_iq_sta = 0x0110,
92 .pse_oq_sta = 0x0118,
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +020093};
94
95static const struct mtk_reg_map mt7628_reg_map = {
96 .tx_irq_mask = 0x0a28,
97 .tx_irq_status = 0x0a20,
98 .pdma = {
99 .rx_ptr = 0x0900,
100 .rx_cnt_cfg = 0x0904,
101 .pcrx_ptr = 0x0908,
102 .glo_cfg = 0x0a04,
103 .rst_idx = 0x0a08,
104 .delay_irq = 0x0a0c,
105 .irq_status = 0x0a20,
106 .irq_mask = 0x0a28,
107 .int_grp = 0x0a50,
108 },
109};
110
Lorenzo Bianconi197c9e92022-05-20 20:11:39 +0200111static const struct mtk_reg_map mt7986_reg_map = {
112 .tx_irq_mask = 0x461c,
113 .tx_irq_status = 0x4618,
114 .pdma = {
Daniel Golle5e69ff82024-05-08 11:43:56 +0100115 .rx_ptr = 0x4100,
116 .rx_cnt_cfg = 0x4104,
117 .pcrx_ptr = 0x4108,
118 .glo_cfg = 0x4204,
119 .rst_idx = 0x4208,
120 .delay_irq = 0x420c,
121 .irq_status = 0x4220,
122 .irq_mask = 0x4228,
123 .adma_rx_dbg0 = 0x4238,
124 .int_grp = 0x4250,
Lorenzo Bianconi197c9e92022-05-20 20:11:39 +0200125 },
126 .qdma = {
127 .qtx_cfg = 0x4400,
Felix Fietkauf63959c2022-11-16 09:07:32 +0100128 .qtx_sch = 0x4404,
Lorenzo Bianconi197c9e92022-05-20 20:11:39 +0200129 .rx_ptr = 0x4500,
130 .rx_cnt_cfg = 0x4504,
131 .qcrx_ptr = 0x4508,
132 .glo_cfg = 0x4604,
133 .rst_idx = 0x4608,
134 .delay_irq = 0x460c,
135 .fc_th = 0x4610,
136 .int_grp = 0x4620,
137 .hred = 0x4644,
138 .ctx_ptr = 0x4700,
139 .dtx_ptr = 0x4704,
140 .crx_ptr = 0x4710,
141 .drx_ptr = 0x4714,
142 .fq_head = 0x4720,
143 .fq_tail = 0x4724,
144 .fq_count = 0x4728,
145 .fq_blen = 0x472c,
Felix Fietkauf63959c2022-11-16 09:07:32 +0100146 .tx_sch_rate = 0x4798,
Lorenzo Bianconi197c9e92022-05-20 20:11:39 +0200147 },
148 .gdm1_cnt = 0x1c00,
Elad Yifeedee4dd12024-06-07 11:21:50 +0300149 .gdma_to_ppe = {
150 [0] = 0x3333,
151 [1] = 0x4444,
152 },
Lorenzo Bianconi329bce52022-09-20 12:11:15 +0200153 .ppe_base = 0x2000,
Lorenzo Bianconi0c1d3fb2022-09-20 12:11:18 +0200154 .wdma_base = {
155 [0] = 0x4800,
156 [1] = 0x4c00,
157 },
Lorenzo Bianconi93b25912023-01-14 18:01:31 +0100158 .pse_iq_sta = 0x0180,
159 .pse_oq_sta = 0x01a0,
Lorenzo Bianconi197c9e92022-05-20 20:11:39 +0200160};
161
Lorenzo Bianconi445eb642023-07-25 01:57:42 +0100162static const struct mtk_reg_map mt7988_reg_map = {
163 .tx_irq_mask = 0x461c,
164 .tx_irq_status = 0x4618,
165 .pdma = {
166 .rx_ptr = 0x6900,
167 .rx_cnt_cfg = 0x6904,
168 .pcrx_ptr = 0x6908,
169 .glo_cfg = 0x6a04,
170 .rst_idx = 0x6a08,
171 .delay_irq = 0x6a0c,
172 .irq_status = 0x6a20,
173 .irq_mask = 0x6a28,
174 .adma_rx_dbg0 = 0x6a38,
175 .int_grp = 0x6a50,
176 },
177 .qdma = {
178 .qtx_cfg = 0x4400,
179 .qtx_sch = 0x4404,
180 .rx_ptr = 0x4500,
181 .rx_cnt_cfg = 0x4504,
182 .qcrx_ptr = 0x4508,
183 .glo_cfg = 0x4604,
184 .rst_idx = 0x4608,
185 .delay_irq = 0x460c,
186 .fc_th = 0x4610,
187 .int_grp = 0x4620,
188 .hred = 0x4644,
189 .ctx_ptr = 0x4700,
190 .dtx_ptr = 0x4704,
191 .crx_ptr = 0x4710,
192 .drx_ptr = 0x4714,
193 .fq_head = 0x4720,
194 .fq_tail = 0x4724,
195 .fq_count = 0x4728,
196 .fq_blen = 0x472c,
197 .tx_sch_rate = 0x4798,
198 },
199 .gdm1_cnt = 0x1c00,
Elad Yifeedee4dd12024-06-07 11:21:50 +0300200 .gdma_to_ppe = {
201 [0] = 0x3333,
202 [1] = 0x4444,
203 [2] = 0xcccc,
204 },
Lorenzo Bianconi445eb642023-07-25 01:57:42 +0100205 .ppe_base = 0x2000,
206 .wdma_base = {
207 [0] = 0x4800,
208 [1] = 0x4c00,
Sujuan Chene2f64db2023-09-18 12:29:13 +0200209 [2] = 0x5000,
Lorenzo Bianconi445eb642023-07-25 01:57:42 +0100210 },
211 .pse_iq_sta = 0x0180,
212 .pse_oq_sta = 0x01a0,
213};
214
John Crispin656e7052016-03-08 11:29:55 +0100215/* strings used by ethtool */
216static const struct mtk_ethtool_stats {
217 char str[ETH_GSTRING_LEN];
218 u32 offset;
219} mtk_ethtool_stats[] = {
220 MTK_ETHTOOL_STAT(tx_bytes),
221 MTK_ETHTOOL_STAT(tx_packets),
222 MTK_ETHTOOL_STAT(tx_skip),
223 MTK_ETHTOOL_STAT(tx_collisions),
224 MTK_ETHTOOL_STAT(rx_bytes),
225 MTK_ETHTOOL_STAT(rx_packets),
226 MTK_ETHTOOL_STAT(rx_overflow),
227 MTK_ETHTOOL_STAT(rx_fcs_errors),
228 MTK_ETHTOOL_STAT(rx_short_errors),
229 MTK_ETHTOOL_STAT(rx_long_errors),
230 MTK_ETHTOOL_STAT(rx_checksum_errors),
231 MTK_ETHTOOL_STAT(rx_flow_control_packets),
Lorenzo Bianconi916a6ee2022-07-22 09:19:38 +0200232 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect),
233 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass),
234 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop),
235 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx),
236 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors),
237 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit),
238 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors),
John Crispin656e7052016-03-08 11:29:55 +0100239};
240
Sean Wang549e5492016-09-01 10:47:28 +0800241static const char * const mtk_clks_source_name[] = {
Lorenzo Bianconi445eb642023-07-25 01:57:42 +0100242 "ethif",
243 "sgmiitop",
244 "esw",
245 "gp0",
246 "gp1",
247 "gp2",
248 "gp3",
249 "xgp1",
250 "xgp2",
251 "xgp3",
252 "crypto",
253 "fe",
254 "trgpll",
255 "sgmii_tx250m",
256 "sgmii_rx250m",
257 "sgmii_cdr_ref",
258 "sgmii_cdr_fb",
259 "sgmii2_tx250m",
260 "sgmii2_rx250m",
261 "sgmii2_cdr_ref",
262 "sgmii2_cdr_fb",
263 "sgmii_ck",
264 "eth2pll",
265 "wocpu0",
266 "wocpu1",
267 "netsys0",
268 "netsys1",
269 "ethwarp_wocpu2",
270 "ethwarp_wocpu1",
271 "ethwarp_wocpu0",
272 "top_usxgmii0_sel",
273 "top_usxgmii1_sel",
274 "top_sgm0_sel",
275 "top_sgm1_sel",
276 "top_xfi_phy0_xtal_sel",
277 "top_xfi_phy1_xtal_sel",
278 "top_eth_gmii_sel",
279 "top_eth_refck_50m_sel",
280 "top_eth_sys_200m_sel",
281 "top_eth_sys_sel",
282 "top_eth_xgmii_sel",
283 "top_eth_mii_sel",
284 "top_netsys_sel",
285 "top_netsys_500m_sel",
286 "top_netsys_pao_2x_sel",
287 "top_netsys_sync_250m_sel",
288 "top_netsys_ppefb_250m_sel",
289 "top_netsys_warp_sel",
Sean Wang549e5492016-09-01 10:47:28 +0800290};
291
John Crispin656e7052016-03-08 11:29:55 +0100292void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
293{
294 __raw_writel(val, eth->base + reg);
295}
296
297u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
298{
299 return __raw_readl(eth->base + reg);
300}
301
Lorenzo Bianconi445eb642023-07-25 01:57:42 +0100302u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg)
René van Dorsta5d755382020-04-06 05:42:54 +0800303{
304 u32 val;
305
306 val = mtk_r32(eth, reg);
307 val &= ~mask;
308 val |= set;
309 mtk_w32(eth, val, reg);
310 return reg;
311}
312
John Crispin656e7052016-03-08 11:29:55 +0100313static int mtk_mdio_busy_wait(struct mtk_eth *eth)
314{
315 unsigned long t_start = jiffies;
316
317 while (1) {
318 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
319 return 0;
320 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
321 break;
Felix Fietkau3630d512021-04-22 22:20:58 -0700322 cond_resched();
John Crispin656e7052016-03-08 11:29:55 +0100323 }
324
325 dev_err(eth->dev, "mdio: MDIO timeout\n");
Daniel Golleeda80b22022-01-04 12:06:22 +0000326 return -ETIMEDOUT;
John Crispin656e7052016-03-08 11:29:55 +0100327}
328
Andrew Lunn90088832023-01-12 16:15:12 +0100329static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg,
330 u32 write_data)
John Crispin656e7052016-03-08 11:29:55 +0100331{
Daniel Golleeda80b22022-01-04 12:06:22 +0000332 int ret;
John Crispin656e7052016-03-08 11:29:55 +0100333
Daniel Golleeda80b22022-01-04 12:06:22 +0000334 ret = mtk_mdio_busy_wait(eth);
335 if (ret < 0)
336 return ret;
John Crispin656e7052016-03-08 11:29:55 +0100337
Andrew Lunn90088832023-01-12 16:15:12 +0100338 mtk_w32(eth, PHY_IAC_ACCESS |
339 PHY_IAC_START_C22 |
340 PHY_IAC_CMD_WRITE |
341 PHY_IAC_REG(phy_reg) |
342 PHY_IAC_ADDR(phy_addr) |
343 PHY_IAC_DATA(write_data),
344 MTK_PHY_IAC);
John Crispin656e7052016-03-08 11:29:55 +0100345
Daniel Golleeda80b22022-01-04 12:06:22 +0000346 ret = mtk_mdio_busy_wait(eth);
347 if (ret < 0)
348 return ret;
John Crispin656e7052016-03-08 11:29:55 +0100349
350 return 0;
351}
352
Andrew Lunn90088832023-01-12 16:15:12 +0100353static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr,
354 u32 devad, u32 phy_reg, u32 write_data)
John Crispin656e7052016-03-08 11:29:55 +0100355{
Daniel Golleeda80b22022-01-04 12:06:22 +0000356 int ret;
John Crispin656e7052016-03-08 11:29:55 +0100357
Daniel Golleeda80b22022-01-04 12:06:22 +0000358 ret = mtk_mdio_busy_wait(eth);
359 if (ret < 0)
360 return ret;
John Crispin656e7052016-03-08 11:29:55 +0100361
Andrew Lunn90088832023-01-12 16:15:12 +0100362 mtk_w32(eth, PHY_IAC_ACCESS |
363 PHY_IAC_START_C45 |
364 PHY_IAC_CMD_C45_ADDR |
365 PHY_IAC_REG(devad) |
366 PHY_IAC_ADDR(phy_addr) |
367 PHY_IAC_DATA(phy_reg),
368 MTK_PHY_IAC);
Daniel Gollee2e7f6e2022-01-04 12:07:46 +0000369
Andrew Lunn90088832023-01-12 16:15:12 +0100370 ret = mtk_mdio_busy_wait(eth);
371 if (ret < 0)
372 return ret;
Daniel Gollee2e7f6e2022-01-04 12:07:46 +0000373
Andrew Lunn90088832023-01-12 16:15:12 +0100374 mtk_w32(eth, PHY_IAC_ACCESS |
375 PHY_IAC_START_C45 |
376 PHY_IAC_CMD_WRITE |
377 PHY_IAC_REG(devad) |
378 PHY_IAC_ADDR(phy_addr) |
379 PHY_IAC_DATA(write_data),
380 MTK_PHY_IAC);
381
382 ret = mtk_mdio_busy_wait(eth);
383 if (ret < 0)
384 return ret;
385
386 return 0;
387}
388
389static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg)
390{
391 int ret;
392
393 ret = mtk_mdio_busy_wait(eth);
394 if (ret < 0)
395 return ret;
396
397 mtk_w32(eth, PHY_IAC_ACCESS |
398 PHY_IAC_START_C22 |
399 PHY_IAC_CMD_C22_READ |
400 PHY_IAC_REG(phy_reg) |
401 PHY_IAC_ADDR(phy_addr),
402 MTK_PHY_IAC);
John Crispin656e7052016-03-08 11:29:55 +0100403
Daniel Golleeda80b22022-01-04 12:06:22 +0000404 ret = mtk_mdio_busy_wait(eth);
405 if (ret < 0)
406 return ret;
John Crispin656e7052016-03-08 11:29:55 +0100407
Daniel Golleeda80b22022-01-04 12:06:22 +0000408 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK;
John Crispin656e7052016-03-08 11:29:55 +0100409}
410
Andrew Lunn90088832023-01-12 16:15:12 +0100411static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr,
412 u32 devad, u32 phy_reg)
John Crispin656e7052016-03-08 11:29:55 +0100413{
Andrew Lunn90088832023-01-12 16:15:12 +0100414 int ret;
John Crispin656e7052016-03-08 11:29:55 +0100415
Andrew Lunn90088832023-01-12 16:15:12 +0100416 ret = mtk_mdio_busy_wait(eth);
417 if (ret < 0)
418 return ret;
419
420 mtk_w32(eth, PHY_IAC_ACCESS |
421 PHY_IAC_START_C45 |
422 PHY_IAC_CMD_C45_ADDR |
423 PHY_IAC_REG(devad) |
424 PHY_IAC_ADDR(phy_addr) |
425 PHY_IAC_DATA(phy_reg),
426 MTK_PHY_IAC);
427
428 ret = mtk_mdio_busy_wait(eth);
429 if (ret < 0)
430 return ret;
431
432 mtk_w32(eth, PHY_IAC_ACCESS |
433 PHY_IAC_START_C45 |
434 PHY_IAC_CMD_C45_READ |
435 PHY_IAC_REG(devad) |
436 PHY_IAC_ADDR(phy_addr),
437 MTK_PHY_IAC);
438
439 ret = mtk_mdio_busy_wait(eth);
440 if (ret < 0)
441 return ret;
442
443 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK;
John Crispin656e7052016-03-08 11:29:55 +0100444}
445
Andrew Lunn90088832023-01-12 16:15:12 +0100446static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr,
447 int phy_reg, u16 val)
John Crispin656e7052016-03-08 11:29:55 +0100448{
449 struct mtk_eth *eth = bus->priv;
450
Andrew Lunn90088832023-01-12 16:15:12 +0100451 return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, val);
452}
453
454static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr,
455 int devad, int phy_reg, u16 val)
456{
457 struct mtk_eth *eth = bus->priv;
458
459 return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, val);
460}
461
462static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg)
463{
464 struct mtk_eth *eth = bus->priv;
465
466 return _mtk_mdio_read_c22(eth, phy_addr, phy_reg);
467}
468
469static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad,
470 int phy_reg)
471{
472 struct mtk_eth *eth = bus->priv;
473
474 return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg);
John Crispin656e7052016-03-08 11:29:55 +0100475}
476
René van Dorst8efaa652019-06-20 14:21:54 +0200477static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth,
478 phy_interface_t interface)
479{
480 u32 val;
481
René van Dorst8efaa652019-06-20 14:21:54 +0200482 val = (interface == PHY_INTERFACE_MODE_TRGMII) ?
483 ETHSYS_TRGMII_MT7621_DDR_PLL : 0;
484
485 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
486 ETHSYS_TRGMII_MT7621_MASK, val);
487
488 return 0;
489}
490
René van Dorst19016d92020-07-23 20:07:10 +0100491static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
Russell King (Oracle)76a4cb72023-07-22 21:32:49 +0100492 phy_interface_t interface)
Sean Wangf430dea2016-09-22 10:33:55 +0800493{
Sean Wangf430dea2016-09-22 10:33:55 +0800494 int ret;
495
René van Dorst19016d92020-07-23 20:07:10 +0100496 if (interface == PHY_INTERFACE_MODE_TRGMII) {
497 mtk_w32(eth, TRGMII_MODE, INTF_MODE);
Russell King (Oracle)04eb3d12023-03-07 16:19:26 +0000498 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 500000000);
René van Dorst19016d92020-07-23 20:07:10 +0100499 if (ret)
500 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
501 return;
502 }
503
Russell King (Oracle)76a4cb72023-07-22 21:32:49 +0100504 dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n");
Sean Wangf430dea2016-09-22 10:33:55 +0800505}
506
Lorenzo Bianconi445eb642023-07-25 01:57:42 +0100507static void mtk_setup_bridge_switch(struct mtk_eth *eth)
508{
509 /* Force Port1 XGMAC Link Up */
510 mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID),
511 MTK_XGMAC_STS(MTK_GMAC1_ID));
512
513 /* Adjust GSW bridge IPG to 11 */
514 mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK,
515 (GSW_IPG_11 << GSWTX_IPG_SHIFT) |
516 (GSW_IPG_11 << GSWRX_IPG_SHIFT),
517 MTK_GSW_CFG);
518}
519
Russell King (Oracle)14a44ab2022-05-18 15:55:28 +0100520static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
521 phy_interface_t interface)
522{
523 struct mtk_mac *mac = container_of(config, struct mtk_mac,
524 phylink_config);
525 struct mtk_eth *eth = mac->hw;
526 unsigned int sid;
527
528 if (interface == PHY_INTERFACE_MODE_SGMII ||
529 phy_interface_mode_is_8023z(interface)) {
530 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
531 0 : mac->id;
532
Daniel Golle2a3ec7a2023-03-19 12:58:02 +0000533 return eth->sgmii_pcs[sid];
Russell King (Oracle)14a44ab2022-05-18 15:55:28 +0100534 }
535
536 return NULL;
537}
538
René van Dorstb8fc9f32019-08-25 19:43:39 +0200539static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
540 const struct phylink_link_state *state)
John Crispin656e7052016-03-08 11:29:55 +0100541{
René van Dorstb8fc9f32019-08-25 19:43:39 +0200542 struct mtk_mac *mac = container_of(config, struct mtk_mac,
543 phylink_config);
544 struct mtk_eth *eth = mac->hw;
Tom Rix214b3362022-01-15 09:49:18 -0800545 int val, ge_mode, err = 0;
Russell King (Oracle)14a44ab2022-05-18 15:55:28 +0100546 u32 i;
John Crispin656e7052016-03-08 11:29:55 +0100547
René van Dorstb8fc9f32019-08-25 19:43:39 +0200548 /* MT76x8 has no hardware settings between for the MAC */
549 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
550 mac->interface != state->interface) {
551 /* Setup soc pin functions */
552 switch (state->interface) {
553 case PHY_INTERFACE_MODE_TRGMII:
René van Dorstb8fc9f32019-08-25 19:43:39 +0200554 case PHY_INTERFACE_MODE_RGMII_TXID:
555 case PHY_INTERFACE_MODE_RGMII_RXID:
556 case PHY_INTERFACE_MODE_RGMII_ID:
557 case PHY_INTERFACE_MODE_RGMII:
René van Dorstb8fc9f32019-08-25 19:43:39 +0200558 case PHY_INTERFACE_MODE_MII:
René van Dorst7e538372019-08-25 19:43:40 +0200559 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) {
560 err = mtk_gmac_rgmii_path_setup(eth, mac->id);
561 if (err)
562 goto init_err;
563 }
564 break;
565 case PHY_INTERFACE_MODE_1000BASEX:
566 case PHY_INTERFACE_MODE_2500BASEX:
567 case PHY_INTERFACE_MODE_SGMII:
Russell King (Oracle)c9f9e3a2023-03-07 16:19:36 +0000568 err = mtk_gmac_sgmii_path_setup(eth, mac->id);
569 if (err)
570 goto init_err;
René van Dorst7e538372019-08-25 19:43:40 +0200571 break;
572 case PHY_INTERFACE_MODE_GMII:
573 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) {
574 err = mtk_gmac_gephy_path_setup(eth, mac->id);
575 if (err)
576 goto init_err;
577 }
René van Dorstb8fc9f32019-08-25 19:43:39 +0200578 break;
Lorenzo Bianconi445eb642023-07-25 01:57:42 +0100579 case PHY_INTERFACE_MODE_INTERNAL:
580 break;
René van Dorstb8fc9f32019-08-25 19:43:39 +0200581 default:
sean.wang@mediatek.com8ca7f4f2016-08-16 13:55:13 +0800582 goto err_phy;
René van Dorstb8fc9f32019-08-25 19:43:39 +0200583 }
John Crispin656e7052016-03-08 11:29:55 +0100584
René van Dorstb8fc9f32019-08-25 19:43:39 +0200585 /* Setup clock for 1st gmac */
René van Dorst7e538372019-08-25 19:43:40 +0200586 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII &&
587 !phy_interface_mode_is_8023z(state->interface) &&
René van Dorstb8fc9f32019-08-25 19:43:39 +0200588 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) {
589 if (MTK_HAS_CAPS(mac->hw->soc->caps,
590 MTK_TRGMII_MT7621_CLK)) {
591 if (mt7621_gmac0_rgmii_adjust(mac->hw,
592 state->interface))
593 goto err_phy;
594 } else {
René van Dorst19016d92020-07-23 20:07:10 +0100595 mtk_gmac0_rgmii_adjust(mac->hw,
Russell King (Oracle)76a4cb72023-07-22 21:32:49 +0100596 state->interface);
René van Dorsta5d755382020-04-06 05:42:54 +0800597
598 /* mt7623_pad_clk_setup */
599 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
600 mtk_w32(mac->hw,
601 TD_DM_DRVP(8) | TD_DM_DRVN(8),
602 TRGMII_TD_ODT(i));
603
604 /* Assert/release MT7623 RXC reset */
605 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL,
606 TRGMII_RCK_CTRL);
607 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL);
René van Dorstb8fc9f32019-08-25 19:43:39 +0200608 }
609 }
610
René van Dorst7e538372019-08-25 19:43:40 +0200611 switch (state->interface) {
612 case PHY_INTERFACE_MODE_MII:
MarkLee4e3eff52019-10-14 15:15:17 +0800613 case PHY_INTERFACE_MODE_GMII:
René van Dorst7e538372019-08-25 19:43:40 +0200614 ge_mode = 1;
615 break;
René van Dorst7e538372019-08-25 19:43:40 +0200616 default:
Russell King (Oracle)8cd9de02023-03-07 16:19:41 +0000617 ge_mode = 0;
René van Dorst7e538372019-08-25 19:43:40 +0200618 break;
619 }
620
Stefan Roese296c9122019-08-16 15:23:25 +0200621 /* put the gmac into the right mode */
622 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
623 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
René van Dorstb8fc9f32019-08-25 19:43:39 +0200624 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
Stefan Roese296c9122019-08-16 15:23:25 +0200625 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
René van Dorstb8fc9f32019-08-25 19:43:39 +0200626
627 mac->interface = state->interface;
Stefan Roese296c9122019-08-16 15:23:25 +0200628 }
John Crispin656e7052016-03-08 11:29:55 +0100629
René van Dorst7e538372019-08-25 19:43:40 +0200630 /* SGMII */
631 if (state->interface == PHY_INTERFACE_MODE_SGMII ||
632 phy_interface_mode_is_8023z(state->interface)) {
633 /* The path GMAC to SGMII will be enabled once the SGMIISYS is
634 * being setup done.
635 */
636 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
637
638 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
639 SYSCFG0_SGMII_MASK,
640 ~(u32)SYSCFG0_SGMII_MASK);
641
Russell King (Oracle)21089862022-05-18 15:55:17 +0100642 /* Save the syscfg0 value for mac_finish */
643 mac->syscfg0 = val;
René van Dorst7e538372019-08-25 19:43:40 +0200644 } else if (phylink_autoneg_inband(mode)) {
645 dev_err(eth->dev,
646 "In-band mode not supported in non SGMII mode!\n");
647 return;
648 }
649
Lorenzo Bianconi445eb642023-07-25 01:57:42 +0100650 /* Setup gmac */
651 if (mtk_is_netsys_v3_or_greater(eth) &&
652 mac->interface == PHY_INTERFACE_MODE_INTERNAL) {
653 mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
654 mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
655
656 mtk_setup_bridge_switch(eth);
657 }
658
René van Dorstb8fc9f32019-08-25 19:43:39 +0200659 return;
sean.wang@mediatek.com8ca7f4f2016-08-16 13:55:13 +0800660
661err_phy:
René van Dorstb8fc9f32019-08-25 19:43:39 +0200662 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__,
663 mac->id, phy_modes(state->interface));
René van Dorst7e538372019-08-25 19:43:40 +0200664 return;
665
666init_err:
667 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__,
668 mac->id, phy_modes(state->interface), err);
John Crispin656e7052016-03-08 11:29:55 +0100669}
670
Russell King (Oracle)0e37ad72022-05-18 15:55:12 +0100671static int mtk_mac_finish(struct phylink_config *config, unsigned int mode,
672 phy_interface_t interface)
673{
674 struct mtk_mac *mac = container_of(config, struct mtk_mac,
675 phylink_config);
Russell King (Oracle)21089862022-05-18 15:55:17 +0100676 struct mtk_eth *eth = mac->hw;
Russell King (Oracle)0e37ad72022-05-18 15:55:12 +0100677 u32 mcr_cur, mcr_new;
678
Russell King (Oracle)21089862022-05-18 15:55:17 +0100679 /* Enable SGMII */
680 if (interface == PHY_INTERFACE_MODE_SGMII ||
681 phy_interface_mode_is_8023z(interface))
682 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
683 SYSCFG0_SGMII_MASK, mac->syscfg0);
684
Russell King (Oracle)0e37ad72022-05-18 15:55:12 +0100685 /* Setup gmac */
686 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
687 mcr_new = mcr_cur;
688 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE |
Daniel Gollef1b85ef2024-03-13 22:50:18 +0000689 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_RX_FIFO_CLR_DIS;
Russell King (Oracle)0e37ad72022-05-18 15:55:12 +0100690
691 /* Only update control register when needed! */
692 if (mcr_new != mcr_cur)
693 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
694
695 return 0;
696}
697
René van Dorstb8fc9f32019-08-25 19:43:39 +0200698static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
699 phy_interface_t interface)
700{
701 struct mtk_mac *mac = container_of(config, struct mtk_mac,
702 phylink_config);
703 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
704
Daniel Gollef1b85ef2024-03-13 22:50:18 +0000705 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK);
René van Dorstb8fc9f32019-08-25 19:43:39 +0200706 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
707}
708
Felix Fietkauf63959c2022-11-16 09:07:32 +0100709static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
710 int speed)
711{
712 const struct mtk_soc_data *soc = eth->soc;
713 u32 ofs, val;
714
715 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA))
716 return;
717
718 val = MTK_QTX_SCH_MIN_RATE_EN |
719 /* minimum: 10 Mbps */
720 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
721 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
722 MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
Lorenzo Bianconia008e2a2023-07-25 01:52:02 +0100723 if (mtk_is_netsys_v1(eth))
Felix Fietkauf63959c2022-11-16 09:07:32 +0100724 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
725
726 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
727 switch (speed) {
728 case SPEED_10:
729 val |= MTK_QTX_SCH_MAX_RATE_EN |
730 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) |
731 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) |
732 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
733 break;
734 case SPEED_100:
735 val |= MTK_QTX_SCH_MAX_RATE_EN |
736 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) |
737 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3);
738 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
739 break;
740 case SPEED_1000:
741 val |= MTK_QTX_SCH_MAX_RATE_EN |
742 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) |
743 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) |
744 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10);
745 break;
746 default:
747 break;
748 }
749 } else {
750 switch (speed) {
751 case SPEED_10:
752 val |= MTK_QTX_SCH_MAX_RATE_EN |
753 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) |
754 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) |
755 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
756 break;
757 case SPEED_100:
758 val |= MTK_QTX_SCH_MAX_RATE_EN |
759 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) |
760 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5);
761 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
762 break;
763 case SPEED_1000:
764 val |= MTK_QTX_SCH_MAX_RATE_EN |
765 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 10) |
766 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) |
767 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10);
768 break;
769 default:
770 break;
771 }
772 }
773
774 ofs = MTK_QTX_OFFSET * idx;
775 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
776}
777
Russell King91a208f2020-02-26 10:23:41 +0000778static void mtk_mac_link_up(struct phylink_config *config,
779 struct phy_device *phy,
780 unsigned int mode, phy_interface_t interface,
781 int speed, int duplex, bool tx_pause, bool rx_pause)
René van Dorstb8fc9f32019-08-25 19:43:39 +0200782{
783 struct mtk_mac *mac = container_of(config, struct mtk_mac,
784 phylink_config);
Russell Kinga4591872022-05-18 15:54:52 +0100785 u32 mcr;
René van Dorstb8fc9f32019-08-25 19:43:39 +0200786
Russell Kinga4591872022-05-18 15:54:52 +0100787 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
Russell King75674e32020-06-21 15:36:39 +0100788 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 |
789 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC |
790 MAC_MCR_FORCE_RX_FC);
791
792 /* Configure speed */
Felix Fietkaue669ce42023-03-31 14:49:59 +0200793 mac->speed = speed;
Russell King75674e32020-06-21 15:36:39 +0100794 switch (speed) {
795 case SPEED_2500:
796 case SPEED_1000:
797 mcr |= MAC_MCR_SPEED_1000;
798 break;
799 case SPEED_100:
800 mcr |= MAC_MCR_SPEED_100;
801 break;
802 }
803
804 /* Configure duplex */
805 if (duplex == DUPLEX_FULL)
806 mcr |= MAC_MCR_FORCE_DPX;
807
808 /* Configure pause modes - phylink will avoid these for half duplex */
809 if (tx_pause)
810 mcr |= MAC_MCR_FORCE_TX_FC;
811 if (rx_pause)
812 mcr |= MAC_MCR_FORCE_RX_FC;
813
Daniel Gollef1b85ef2024-03-13 22:50:18 +0000814 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK;
René van Dorstb8fc9f32019-08-25 19:43:39 +0200815 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
816}
817
René van Dorstb8fc9f32019-08-25 19:43:39 +0200818static const struct phylink_mac_ops mtk_phylink_ops = {
Russell King (Oracle)14a44ab2022-05-18 15:55:28 +0100819 .mac_select_pcs = mtk_mac_select_pcs,
René van Dorstb8fc9f32019-08-25 19:43:39 +0200820 .mac_config = mtk_mac_config,
Russell King (Oracle)0e37ad72022-05-18 15:55:12 +0100821 .mac_finish = mtk_mac_finish,
René van Dorstb8fc9f32019-08-25 19:43:39 +0200822 .mac_link_down = mtk_mac_link_down,
823 .mac_link_up = mtk_mac_link_up,
824};
825
John Crispin656e7052016-03-08 11:29:55 +0100826static int mtk_mdio_init(struct mtk_eth *eth)
827{
Daniel Gollec0a44002023-03-19 12:57:15 +0000828 unsigned int max_clk = 2500000, divider;
John Crispin656e7052016-03-08 11:29:55 +0100829 struct device_node *mii_np;
Sean Wang1e515b72016-09-01 10:47:34 +0800830 int ret;
Daniel Gollec0a44002023-03-19 12:57:15 +0000831 u32 val;
John Crispin656e7052016-03-08 11:29:55 +0100832
833 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
834 if (!mii_np) {
835 dev_err(eth->dev, "no %s child node found", "mdio-bus");
836 return -ENODEV;
837 }
838
839 if (!of_device_is_available(mii_np)) {
Sean Wangaa6e8a52016-09-01 10:47:35 +0800840 ret = -ENODEV;
John Crispin656e7052016-03-08 11:29:55 +0100841 goto err_put_node;
842 }
843
Sean Wang1e515b72016-09-01 10:47:34 +0800844 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
John Crispin656e7052016-03-08 11:29:55 +0100845 if (!eth->mii_bus) {
Sean Wang1e515b72016-09-01 10:47:34 +0800846 ret = -ENOMEM;
John Crispin656e7052016-03-08 11:29:55 +0100847 goto err_put_node;
848 }
849
850 eth->mii_bus->name = "mdio";
Andrew Lunn90088832023-01-12 16:15:12 +0100851 eth->mii_bus->read = mtk_mdio_read_c22;
852 eth->mii_bus->write = mtk_mdio_write_c22;
853 eth->mii_bus->read_c45 = mtk_mdio_read_c45;
854 eth->mii_bus->write_c45 = mtk_mdio_write_c45;
John Crispin656e7052016-03-08 11:29:55 +0100855 eth->mii_bus->priv = eth;
856 eth->mii_bus->parent = eth->dev;
857
Rob Herring21c328d2018-08-28 10:44:30 -0500858 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
Daniel Gollec0a44002023-03-19 12:57:15 +0000859
860 if (!of_property_read_u32(mii_np, "clock-frequency", &val)) {
861 if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) {
862 dev_err(eth->dev, "MDIO clock frequency out of range");
863 ret = -EINVAL;
864 goto err_put_node;
865 }
866 max_clk = val;
867 }
868 divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
869
Lorenzo Bianconi445eb642023-07-25 01:57:42 +0100870 /* Configure MDC Turbo Mode */
871 if (mtk_is_netsys_v3_or_greater(eth))
872 mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3);
873
Daniel Gollec0a44002023-03-19 12:57:15 +0000874 /* Configure MDC Divider */
Lorenzo Bianconi445eb642023-07-25 01:57:42 +0100875 val = FIELD_PREP(PPSC_MDC_CFG, divider);
876 if (!mtk_is_netsys_v3_or_greater(eth))
877 val |= PPSC_MDC_TURBO;
878 mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC);
Daniel Gollec0a44002023-03-19 12:57:15 +0000879
880 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
881
Sean Wang1e515b72016-09-01 10:47:34 +0800882 ret = of_mdiobus_register(eth->mii_bus, mii_np);
John Crispin656e7052016-03-08 11:29:55 +0100883
884err_put_node:
885 of_node_put(mii_np);
Sean Wang1e515b72016-09-01 10:47:34 +0800886 return ret;
John Crispin656e7052016-03-08 11:29:55 +0100887}
888
889static void mtk_mdio_cleanup(struct mtk_eth *eth)
890{
891 if (!eth->mii_bus)
892 return;
893
894 mdiobus_unregister(eth->mii_bus);
John Crispin656e7052016-03-08 11:29:55 +0100895}
896
John Crispin5cce0322017-06-19 15:37:05 +0200897static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
John Crispin656e7052016-03-08 11:29:55 +0100898{
John Crispin7bc9cce2016-06-29 13:38:10 +0200899 unsigned long flags;
John Crispin656e7052016-03-08 11:29:55 +0100900 u32 val;
901
John Crispin5cce0322017-06-19 15:37:05 +0200902 spin_lock_irqsave(&eth->tx_irq_lock, flags);
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +0200903 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask);
904 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask);
John Crispin5cce0322017-06-19 15:37:05 +0200905 spin_unlock_irqrestore(&eth->tx_irq_lock, flags);
John Crispin656e7052016-03-08 11:29:55 +0100906}
907
John Crispin5cce0322017-06-19 15:37:05 +0200908static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
John Crispin656e7052016-03-08 11:29:55 +0100909{
John Crispin7bc9cce2016-06-29 13:38:10 +0200910 unsigned long flags;
John Crispin656e7052016-03-08 11:29:55 +0100911 u32 val;
912
John Crispin5cce0322017-06-19 15:37:05 +0200913 spin_lock_irqsave(&eth->tx_irq_lock, flags);
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +0200914 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask);
915 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask);
John Crispin5cce0322017-06-19 15:37:05 +0200916 spin_unlock_irqrestore(&eth->tx_irq_lock, flags);
917}
918
919static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
920{
921 unsigned long flags;
922 u32 val;
923
924 spin_lock_irqsave(&eth->rx_irq_lock, flags);
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +0200925 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);
926 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask);
John Crispin5cce0322017-06-19 15:37:05 +0200927 spin_unlock_irqrestore(&eth->rx_irq_lock, flags);
928}
929
930static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
931{
932 unsigned long flags;
933 u32 val;
934
935 spin_lock_irqsave(&eth->rx_irq_lock, flags);
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +0200936 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);
937 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask);
John Crispin5cce0322017-06-19 15:37:05 +0200938 spin_unlock_irqrestore(&eth->rx_irq_lock, flags);
John Crispin656e7052016-03-08 11:29:55 +0100939}
940
941static int mtk_set_mac_address(struct net_device *dev, void *p)
942{
943 int ret = eth_mac_addr(dev, p);
944 struct mtk_mac *mac = netdev_priv(dev);
Stefan Roese296c9122019-08-16 15:23:25 +0200945 struct mtk_eth *eth = mac->hw;
John Crispin656e7052016-03-08 11:29:55 +0100946 const char *macaddr = dev->dev_addr;
John Crispin656e7052016-03-08 11:29:55 +0100947
948 if (ret)
949 return ret;
950
Sean Wangdce6fa42016-09-14 23:13:21 +0800951 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
952 return -EBUSY;
953
Sean Wange3e96522016-08-11 17:51:00 +0800954 spin_lock_bh(&mac->hw->page_lock);
Stefan Roese296c9122019-08-16 15:23:25 +0200955 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
956 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
957 MT7628_SDM_MAC_ADRH);
958 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
959 (macaddr[4] << 8) | macaddr[5],
960 MT7628_SDM_MAC_ADRL);
961 } else {
962 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
963 MTK_GDMA_MAC_ADRH(mac->id));
964 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
965 (macaddr[4] << 8) | macaddr[5],
966 MTK_GDMA_MAC_ADRL(mac->id));
967 }
Sean Wange3e96522016-08-11 17:51:00 +0800968 spin_unlock_bh(&mac->hw->page_lock);
John Crispin656e7052016-03-08 11:29:55 +0100969
970 return 0;
971}
972
973void mtk_stats_update_mac(struct mtk_mac *mac)
974{
975 struct mtk_hw_stats *hw_stats = mac->hw_stats;
Stefan Roesead79fd22021-05-22 09:56:30 +0200976 struct mtk_eth *eth = mac->hw;
John Crispin656e7052016-03-08 11:29:55 +0100977
978 u64_stats_update_begin(&hw_stats->syncp);
979
Stefan Roesead79fd22021-05-22 09:56:30 +0200980 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
981 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT);
982 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT);
983 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT);
984 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT);
985 hw_stats->rx_checksum_errors +=
986 mtk_r32(mac->hw, MT7628_SDM_CS_ERR);
987 } else {
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +0200988 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
Stefan Roesead79fd22021-05-22 09:56:30 +0200989 unsigned int offs = hw_stats->reg_offset;
990 u64 stats;
991
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +0200992 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs);
993 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs);
Stefan Roesead79fd22021-05-22 09:56:30 +0200994 if (stats)
995 hw_stats->rx_bytes += (stats << 32);
996 hw_stats->rx_packets +=
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +0200997 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs);
Stefan Roesead79fd22021-05-22 09:56:30 +0200998 hw_stats->rx_overflow +=
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +0200999 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs);
Stefan Roesead79fd22021-05-22 09:56:30 +02001000 hw_stats->rx_fcs_errors +=
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02001001 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs);
Stefan Roesead79fd22021-05-22 09:56:30 +02001002 hw_stats->rx_short_errors +=
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02001003 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs);
Stefan Roesead79fd22021-05-22 09:56:30 +02001004 hw_stats->rx_long_errors +=
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02001005 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs);
Stefan Roesead79fd22021-05-22 09:56:30 +02001006 hw_stats->rx_checksum_errors +=
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02001007 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs);
Stefan Roesead79fd22021-05-22 09:56:30 +02001008 hw_stats->rx_flow_control_packets +=
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02001009 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs);
Lorenzo Bianconi1953f132023-07-25 01:52:59 +01001010
1011 if (mtk_is_netsys_v3_or_greater(eth)) {
1012 hw_stats->tx_skip +=
1013 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs);
1014 hw_stats->tx_collisions +=
1015 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs);
1016 hw_stats->tx_bytes +=
1017 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs);
1018 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs);
1019 if (stats)
1020 hw_stats->tx_bytes += (stats << 32);
1021 hw_stats->tx_packets +=
1022 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs);
1023 } else {
1024 hw_stats->tx_skip +=
1025 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs);
1026 hw_stats->tx_collisions +=
1027 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs);
1028 hw_stats->tx_bytes +=
1029 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs);
1030 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs);
1031 if (stats)
1032 hw_stats->tx_bytes += (stats << 32);
1033 hw_stats->tx_packets +=
1034 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs);
1035 }
Stefan Roesead79fd22021-05-22 09:56:30 +02001036 }
1037
John Crispin656e7052016-03-08 11:29:55 +01001038 u64_stats_update_end(&hw_stats->syncp);
1039}
1040
1041static void mtk_stats_update(struct mtk_eth *eth)
1042{
1043 int i;
1044
Lorenzo Bianconie05fd622023-07-25 01:52:44 +01001045 for (i = 0; i < MTK_MAX_DEVS; i++) {
John Crispin656e7052016-03-08 11:29:55 +01001046 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
1047 continue;
1048 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
1049 mtk_stats_update_mac(eth->mac[i]);
1050 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
1051 }
1052 }
1053}
1054
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001055static void mtk_get_stats64(struct net_device *dev,
1056 struct rtnl_link_stats64 *storage)
John Crispin656e7052016-03-08 11:29:55 +01001057{
1058 struct mtk_mac *mac = netdev_priv(dev);
1059 struct mtk_hw_stats *hw_stats = mac->hw_stats;
1060 unsigned int start;
1061
1062 if (netif_running(dev) && netif_device_present(dev)) {
Sean Wang8d32e062017-07-04 11:17:36 +08001063 if (spin_trylock_bh(&hw_stats->stats_lock)) {
John Crispin656e7052016-03-08 11:29:55 +01001064 mtk_stats_update_mac(mac);
Sean Wang8d32e062017-07-04 11:17:36 +08001065 spin_unlock_bh(&hw_stats->stats_lock);
John Crispin656e7052016-03-08 11:29:55 +01001066 }
1067 }
1068
1069 do {
Thomas Gleixner068c38a2022-10-26 15:22:14 +02001070 start = u64_stats_fetch_begin(&hw_stats->syncp);
John Crispin656e7052016-03-08 11:29:55 +01001071 storage->rx_packets = hw_stats->rx_packets;
1072 storage->tx_packets = hw_stats->tx_packets;
1073 storage->rx_bytes = hw_stats->rx_bytes;
1074 storage->tx_bytes = hw_stats->tx_bytes;
1075 storage->collisions = hw_stats->tx_collisions;
1076 storage->rx_length_errors = hw_stats->rx_short_errors +
1077 hw_stats->rx_long_errors;
1078 storage->rx_over_errors = hw_stats->rx_overflow;
1079 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
1080 storage->rx_errors = hw_stats->rx_checksum_errors;
1081 storage->tx_aborted_errors = hw_stats->tx_skip;
Thomas Gleixner068c38a2022-10-26 15:22:14 +02001082 } while (u64_stats_fetch_retry(&hw_stats->syncp, start));
John Crispin656e7052016-03-08 11:29:55 +01001083
1084 storage->tx_errors = dev->stats.tx_errors;
1085 storage->rx_dropped = dev->stats.rx_dropped;
1086 storage->tx_dropped = dev->stats.tx_dropped;
John Crispin656e7052016-03-08 11:29:55 +01001087}
1088
1089static inline int mtk_max_frag_size(int mtu)
1090{
1091 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
DENG Qingfang4fd59792021-01-25 12:20:46 +08001092 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K)
1093 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
John Crispin656e7052016-03-08 11:29:55 +01001094
1095 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
1096 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1097}
1098
1099static inline int mtk_max_buf_size(int frag_size)
1100{
1101 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
1102 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1103
DENG Qingfang4fd59792021-01-25 12:20:46 +08001104 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K);
John Crispin656e7052016-03-08 11:29:55 +01001105
1106 return buf_size;
1107}
1108
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02001109static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd,
1110 struct mtk_rx_dma_v2 *dma_rxd)
John Crispin656e7052016-03-08 11:29:55 +01001111{
John Crispin656e7052016-03-08 11:29:55 +01001112 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
Felix Fietkau816ac3e2021-04-22 22:21:04 -07001113 if (!(rxd->rxd2 & RX_DMA_DONE))
1114 return false;
1115
1116 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
John Crispin656e7052016-03-08 11:29:55 +01001117 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
1118 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
Daniel Golle5e69ff82024-05-08 11:43:56 +01001119 if (mtk_is_netsys_v3_or_greater(eth)) {
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02001120 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
1121 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
1122 }
Felix Fietkau816ac3e2021-04-22 22:21:04 -07001123
1124 return true;
John Crispin656e7052016-03-08 11:29:55 +01001125}
1126
Chen Lin2f2c0d22022-06-08 20:46:53 +08001127static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask)
1128{
1129 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH);
1130 unsigned long data;
1131
1132 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN,
1133 get_order(size));
1134
1135 return (void *)data;
1136}
1137
John Crispin656e7052016-03-08 11:29:55 +01001138/* the qdma core needs scratch memory to be setup */
1139static int mtk_init_fq_dma(struct mtk_eth *eth)
1140{
Lorenzo Bianconieb067342022-05-20 20:11:28 +02001141 const struct mtk_soc_data *soc = eth->soc;
John Crispin605e4fe2016-06-10 13:27:59 +02001142 dma_addr_t phy_ring_tail;
Frank Wunderlichc57e5582024-06-03 21:25:05 +02001143 int cnt = soc->tx.fq_dma_size;
John Crispin656e7052016-03-08 11:29:55 +01001144 dma_addr_t dma_addr;
Frank Wunderlichc57e5582024-06-03 21:25:05 +02001145 int i, j, len;
John Crispin656e7052016-03-08 11:29:55 +01001146
Daniel Golleebb1e4f2023-08-22 17:32:54 +01001147 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM))
1148 eth->scratch_ring = eth->sram_base;
1149 else
1150 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01001151 cnt * soc->tx.desc_size,
Daniel Golleebb1e4f2023-08-22 17:32:54 +01001152 &eth->phy_scratch_ring,
1153 GFP_KERNEL);
Frank Wunderlichc57e5582024-06-03 21:25:05 +02001154
John Crispin656e7052016-03-08 11:29:55 +01001155 if (unlikely(!eth->scratch_ring))
1156 return -ENOMEM;
1157
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01001158 phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1);
John Crispin656e7052016-03-08 11:29:55 +01001159
Frank Wunderlichc57e5582024-06-03 21:25:05 +02001160 for (j = 0; j < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); j++) {
1161 len = min_t(int, cnt - j * MTK_FQ_DMA_LENGTH, MTK_FQ_DMA_LENGTH);
1162 eth->scratch_head[j] = kcalloc(len, MTK_QDMA_PAGE_SIZE, GFP_KERNEL);
Lorenzo Bianconieb067342022-05-20 20:11:28 +02001163
Frank Wunderlichc57e5582024-06-03 21:25:05 +02001164 if (unlikely(!eth->scratch_head[j]))
1165 return -ENOMEM;
Lorenzo Bianconieb067342022-05-20 20:11:28 +02001166
Frank Wunderlichc57e5582024-06-03 21:25:05 +02001167 dma_addr = dma_map_single(eth->dma_dev,
1168 eth->scratch_head[j], len * MTK_QDMA_PAGE_SIZE,
1169 DMA_FROM_DEVICE);
1170
1171 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
1172 return -ENOMEM;
1173
1174 for (i = 0; i < cnt; i++) {
1175 struct mtk_tx_dma_v2 *txd;
1176
1177 txd = eth->scratch_ring + (j * MTK_FQ_DMA_LENGTH + i) * soc->tx.desc_size;
1178 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
1179 if (j * MTK_FQ_DMA_LENGTH + i < cnt)
1180 txd->txd2 = eth->phy_scratch_ring +
1181 (j * MTK_FQ_DMA_LENGTH + i + 1) * soc->tx.desc_size;
1182
1183 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
1184 if (MTK_HAS_CAPS(soc->caps, MTK_36BIT_DMA))
1185 txd->txd3 |= TX_DMA_PREP_ADDR64(dma_addr + i * MTK_QDMA_PAGE_SIZE);
1186
1187 txd->txd4 = 0;
1188 if (mtk_is_netsys_v2_or_greater(eth)) {
1189 txd->txd5 = 0;
1190 txd->txd6 = 0;
1191 txd->txd7 = 0;
1192 txd->txd8 = 0;
1193 }
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02001194 }
John Crispin656e7052016-03-08 11:29:55 +01001195 }
1196
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02001197 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head);
1198 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail);
1199 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count);
1200 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen);
John Crispin656e7052016-03-08 11:29:55 +01001201
1202 return 0;
1203}
1204
Lorenzo Bianconi7173eca2022-05-20 20:11:37 +02001205static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
John Crispin656e7052016-03-08 11:29:55 +01001206{
Lorenzo Bianconi7173eca2022-05-20 20:11:37 +02001207 return ring->dma + (desc - ring->phys);
John Crispin656e7052016-03-08 11:29:55 +01001208}
1209
Lorenzo Bianconic4fd06c2022-05-20 20:11:30 +02001210static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
Lorenzo Bianconi7173eca2022-05-20 20:11:37 +02001211 void *txd, u32 txd_size)
John Crispin656e7052016-03-08 11:29:55 +01001212{
Lorenzo Bianconi7173eca2022-05-20 20:11:37 +02001213 int idx = (txd - ring->dma) / txd_size;
John Crispin656e7052016-03-08 11:29:55 +01001214
1215 return &ring->buf[idx];
1216}
1217
Stefan Roese296c9122019-08-16 15:23:25 +02001218static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring,
1219 struct mtk_tx_dma *dma)
1220{
Lorenzo Bianconi7173eca2022-05-20 20:11:37 +02001221 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma;
Stefan Roese296c9122019-08-16 15:23:25 +02001222}
1223
Lorenzo Bianconi7173eca2022-05-20 20:11:37 +02001224static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size)
Stefan Roese296c9122019-08-16 15:23:25 +02001225{
Lorenzo Bianconi7173eca2022-05-20 20:11:37 +02001226 return (dma - ring->dma) / txd_size;
Stefan Roese296c9122019-08-16 15:23:25 +02001227}
1228
Felix Fietkauc30c4a82021-04-22 22:20:57 -07001229static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
Lorenzo Bianconi853246d2022-07-27 23:20:52 +02001230 struct xdp_frame_bulk *bq, bool napi)
John Crispin656e7052016-03-08 11:29:55 +01001231{
Stefan Roese296c9122019-08-16 15:23:25 +02001232 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1233 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
Felix Fietkaud776a572022-04-05 21:57:43 +02001234 dma_unmap_single(eth->dma_dev,
Stefan Roese296c9122019-08-16 15:23:25 +02001235 dma_unmap_addr(tx_buf, dma_addr0),
1236 dma_unmap_len(tx_buf, dma_len0),
1237 DMA_TO_DEVICE);
1238 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
Felix Fietkaud776a572022-04-05 21:57:43 +02001239 dma_unmap_page(eth->dma_dev,
Stefan Roese296c9122019-08-16 15:23:25 +02001240 dma_unmap_addr(tx_buf, dma_addr0),
1241 dma_unmap_len(tx_buf, dma_len0),
1242 DMA_TO_DEVICE);
1243 }
1244 } else {
1245 if (dma_unmap_len(tx_buf, dma_len0)) {
Felix Fietkaud776a572022-04-05 21:57:43 +02001246 dma_unmap_page(eth->dma_dev,
Stefan Roese296c9122019-08-16 15:23:25 +02001247 dma_unmap_addr(tx_buf, dma_addr0),
1248 dma_unmap_len(tx_buf, dma_len0),
1249 DMA_TO_DEVICE);
1250 }
1251
1252 if (dma_unmap_len(tx_buf, dma_len1)) {
Felix Fietkaud776a572022-04-05 21:57:43 +02001253 dma_unmap_page(eth->dma_dev,
Stefan Roese296c9122019-08-16 15:23:25 +02001254 dma_unmap_addr(tx_buf, dma_addr1),
1255 dma_unmap_len(tx_buf, dma_len1),
1256 DMA_TO_DEVICE);
1257 }
John Crispin656e7052016-03-08 11:29:55 +01001258 }
Stefan Roese296c9122019-08-16 15:23:25 +02001259
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001260 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
1261 if (tx_buf->type == MTK_TYPE_SKB) {
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001262 struct sk_buff *skb = tx_buf->data;
1263
1264 if (napi)
1265 napi_consume_skb(skb, napi);
1266 else
1267 dev_kfree_skb_any(skb);
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001268 } else {
1269 struct xdp_frame *xdpf = tx_buf->data;
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001270
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001271 if (napi && tx_buf->type == MTK_TYPE_XDP_TX)
1272 xdp_return_frame_rx_napi(xdpf);
Lorenzo Bianconi853246d2022-07-27 23:20:52 +02001273 else if (bq)
1274 xdp_return_frame_bulk(xdpf, bq);
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001275 else
1276 xdp_return_frame(xdpf);
1277 }
Felix Fietkauc30c4a82021-04-22 22:20:57 -07001278 }
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001279 tx_buf->flags = 0;
1280 tx_buf->data = NULL;
John Crispin656e7052016-03-08 11:29:55 +01001281}
1282
Stefan Roese296c9122019-08-16 15:23:25 +02001283static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
1284 struct mtk_tx_dma *txd, dma_addr_t mapped_addr,
1285 size_t size, int idx)
1286{
1287 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1288 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
1289 dma_unmap_len_set(tx_buf, dma_len0, size);
1290 } else {
1291 if (idx & 1) {
1292 txd->txd3 = mapped_addr;
1293 txd->txd2 |= TX_DMA_PLEN1(size);
1294 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
1295 dma_unmap_len_set(tx_buf, dma_len1, size);
1296 } else {
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001297 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
Stefan Roese296c9122019-08-16 15:23:25 +02001298 txd->txd1 = mapped_addr;
1299 txd->txd2 = TX_DMA_PLEN0(size);
1300 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
1301 dma_unmap_len_set(tx_buf, dma_len0, size);
1302 }
1303 }
1304}
1305
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02001306static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd,
1307 struct mtk_tx_dma_desc_info *info)
Lorenzo Bianconi731f3fd2022-05-20 20:11:27 +02001308{
1309 struct mtk_mac *mac = netdev_priv(dev);
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02001310 struct mtk_eth *eth = mac->hw;
1311 struct mtk_tx_dma *desc = txd;
Lorenzo Bianconi731f3fd2022-05-20 20:11:27 +02001312 u32 data;
1313
1314 WRITE_ONCE(desc->txd1, info->addr);
1315
Felix Fietkauf63959c2022-11-16 09:07:32 +01001316 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) |
1317 FIELD_PREP(TX_DMA_PQID, info->qid);
Lorenzo Bianconi731f3fd2022-05-20 20:11:27 +02001318 if (info->last)
1319 data |= TX_DMA_LS0;
1320 WRITE_ONCE(desc->txd3, data);
1321
1322 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */
1323 if (info->first) {
1324 if (info->gso)
1325 data |= TX_DMA_TSO;
1326 /* tx checksum offload */
1327 if (info->csum)
1328 data |= TX_DMA_CHKSUM;
1329 /* vlan header offload */
1330 if (info->vlan)
1331 data |= TX_DMA_INS_VLAN | info->vlan_tci;
1332 }
1333 WRITE_ONCE(desc->txd4, data);
1334}
1335
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02001336static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd,
1337 struct mtk_tx_dma_desc_info *info)
1338{
1339 struct mtk_mac *mac = netdev_priv(dev);
1340 struct mtk_tx_dma_v2 *desc = txd;
1341 struct mtk_eth *eth = mac->hw;
1342 u32 data;
1343
1344 WRITE_ONCE(desc->txd1, info->addr);
1345
1346 data = TX_DMA_PLEN0(info->size);
1347 if (info->last)
1348 data |= TX_DMA_LS0;
Daniel Golle2d75891e2023-08-22 17:33:12 +01001349
1350 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
1351 data |= TX_DMA_PREP_ADDR64(info->addr);
1352
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02001353 WRITE_ONCE(desc->txd3, data);
1354
Lorenzo Bianconi445eb642023-07-25 01:57:42 +01001355 /* set forward port */
1356 switch (mac->id) {
1357 case MTK_GMAC1_ID:
1358 data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2;
1359 break;
1360 case MTK_GMAC2_ID:
1361 data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2;
1362 break;
1363 case MTK_GMAC3_ID:
1364 data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2;
1365 break;
1366 }
1367
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02001368 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
1369 WRITE_ONCE(desc->txd4, data);
1370
1371 data = 0;
1372 if (info->first) {
1373 if (info->gso)
1374 data |= TX_DMA_TSO_V2;
1375 /* tx checksum offload */
1376 if (info->csum)
1377 data |= TX_DMA_CHKSUM_V2;
Lorenzo Bianconi1953f132023-07-25 01:52:59 +01001378 if (mtk_is_netsys_v3_or_greater(eth) && netdev_uses_dsa(dev))
1379 data |= TX_DMA_SPTAG_V3;
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02001380 }
1381 WRITE_ONCE(desc->txd5, data);
1382
1383 data = 0;
1384 if (info->first && info->vlan)
1385 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci;
1386 WRITE_ONCE(desc->txd6, data);
1387
1388 WRITE_ONCE(desc->txd7, 0);
1389 WRITE_ONCE(desc->txd8, 0);
1390}
1391
1392static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd,
1393 struct mtk_tx_dma_desc_info *info)
1394{
1395 struct mtk_mac *mac = netdev_priv(dev);
1396 struct mtk_eth *eth = mac->hw;
1397
Lorenzo Bianconia008e2a2023-07-25 01:52:02 +01001398 if (mtk_is_netsys_v2_or_greater(eth))
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02001399 mtk_tx_set_dma_desc_v2(dev, txd, info);
1400 else
1401 mtk_tx_set_dma_desc_v1(dev, txd, info);
1402}
1403
John Crispin656e7052016-03-08 11:29:55 +01001404static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
1405 int tx_num, struct mtk_tx_ring *ring, bool gso)
1406{
Lorenzo Bianconi731f3fd2022-05-20 20:11:27 +02001407 struct mtk_tx_dma_desc_info txd_info = {
1408 .size = skb_headlen(skb),
1409 .gso = gso,
1410 .csum = skb->ip_summed == CHECKSUM_PARTIAL,
1411 .vlan = skb_vlan_tag_present(skb),
Felix Fietkauf63959c2022-11-16 09:07:32 +01001412 .qid = skb_get_queue_mapping(skb),
Lorenzo Bianconi731f3fd2022-05-20 20:11:27 +02001413 .vlan_tci = skb_vlan_tag_get(skb),
1414 .first = true,
1415 .last = !skb_is_nonlinear(skb),
1416 };
Felix Fietkauf63959c2022-11-16 09:07:32 +01001417 struct netdev_queue *txq;
John Crispin656e7052016-03-08 11:29:55 +01001418 struct mtk_mac *mac = netdev_priv(dev);
1419 struct mtk_eth *eth = mac->hw;
Lorenzo Bianconic4fd06c2022-05-20 20:11:30 +02001420 const struct mtk_soc_data *soc = eth->soc;
John Crispin656e7052016-03-08 11:29:55 +01001421 struct mtk_tx_dma *itxd, *txd;
Stefan Roese296c9122019-08-16 15:23:25 +02001422 struct mtk_tx_dma *itxd_pdma, *txd_pdma;
Sean Wang81d2dd02017-04-14 11:19:11 +08001423 struct mtk_tx_buf *itx_buf, *tx_buf;
John Crispin656e7052016-03-08 11:29:55 +01001424 int i, n_desc = 1;
Felix Fietkauf63959c2022-11-16 09:07:32 +01001425 int queue = skb_get_queue_mapping(skb);
Stefan Roese296c9122019-08-16 15:23:25 +02001426 int k = 0;
John Crispin656e7052016-03-08 11:29:55 +01001427
Felix Fietkauf63959c2022-11-16 09:07:32 +01001428 txq = netdev_get_tx_queue(dev, queue);
John Crispin656e7052016-03-08 11:29:55 +01001429 itxd = ring->next_free;
Stefan Roese296c9122019-08-16 15:23:25 +02001430 itxd_pdma = qdma_to_pdma(ring, itxd);
John Crispin656e7052016-03-08 11:29:55 +01001431 if (itxd == ring->last_free)
1432 return -ENOMEM;
1433
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01001434 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
Sean Wang81d2dd02017-04-14 11:19:11 +08001435 memset(itx_buf, 0, sizeof(*itx_buf));
John Crispin656e7052016-03-08 11:29:55 +01001436
Lorenzo Bianconi731f3fd2022-05-20 20:11:27 +02001437 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
1438 DMA_TO_DEVICE);
1439 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr)))
John Crispin656e7052016-03-08 11:29:55 +01001440 return -ENOMEM;
1441
Lorenzo Bianconi731f3fd2022-05-20 20:11:27 +02001442 mtk_tx_set_dma_desc(dev, itxd, &txd_info);
1443
Sean Wang81d2dd02017-04-14 11:19:11 +08001444 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
Lorenzo Bianconi1953f132023-07-25 01:52:59 +01001445 itx_buf->mac_id = mac->id;
Lorenzo Bianconi731f3fd2022-05-20 20:11:27 +02001446 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size,
Stefan Roese296c9122019-08-16 15:23:25 +02001447 k++);
John Crispin656e7052016-03-08 11:29:55 +01001448
1449 /* TX SG offload */
1450 txd = itxd;
Stefan Roese296c9122019-08-16 15:23:25 +02001451 txd_pdma = qdma_to_pdma(ring, txd);
Stefan Roese296c9122019-08-16 15:23:25 +02001452
Lorenzo Bianconi731f3fd2022-05-20 20:11:27 +02001453 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
Matthew Wilcox (Oracle)d7840972019-07-22 20:08:25 -07001454 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
John Crispin656e7052016-03-08 11:29:55 +01001455 unsigned int offset = 0;
1456 int frag_size = skb_frag_size(frag);
1457
1458 while (frag_size) {
Stefan Roese296c9122019-08-16 15:23:25 +02001459 bool new_desc = true;
John Crispin656e7052016-03-08 11:29:55 +01001460
Lorenzo Bianconic4fd06c2022-05-20 20:11:30 +02001461 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) ||
Stefan Roese296c9122019-08-16 15:23:25 +02001462 (i & 0x1)) {
1463 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
1464 txd_pdma = qdma_to_pdma(ring, txd);
1465 if (txd == ring->last_free)
1466 goto err_dma;
John Crispin656e7052016-03-08 11:29:55 +01001467
Stefan Roese296c9122019-08-16 15:23:25 +02001468 n_desc++;
1469 } else {
1470 new_desc = false;
1471 }
1472
Lorenzo Bianconi731f3fd2022-05-20 20:11:27 +02001473 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02001474 txd_info.size = min_t(unsigned int, frag_size,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01001475 soc->tx.dma_max_len);
Felix Fietkauf63959c2022-11-16 09:07:32 +01001476 txd_info.qid = queue;
Lorenzo Bianconi731f3fd2022-05-20 20:11:27 +02001477 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
1478 !(frag_size - txd_info.size);
1479 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag,
1480 offset, txd_info.size,
1481 DMA_TO_DEVICE);
1482 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr)))
John Crispin656e7052016-03-08 11:29:55 +01001483 goto err_dma;
1484
Lorenzo Bianconi731f3fd2022-05-20 20:11:27 +02001485 mtk_tx_set_dma_desc(dev, txd, &txd_info);
John Crispin656e7052016-03-08 11:29:55 +01001486
Lorenzo Bianconic4fd06c2022-05-20 20:11:30 +02001487 tx_buf = mtk_desc_to_tx_buf(ring, txd,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01001488 soc->tx.desc_size);
Stefan Roese296c9122019-08-16 15:23:25 +02001489 if (new_desc)
1490 memset(tx_buf, 0, sizeof(*tx_buf));
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001491 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
John Crispin656e7052016-03-08 11:29:55 +01001492 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
Lorenzo Bianconi1953f132023-07-25 01:52:59 +01001493 tx_buf->mac_id = mac->id;
Sean Wang134d2152017-04-14 11:19:12 +08001494
Lorenzo Bianconi731f3fd2022-05-20 20:11:27 +02001495 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr,
1496 txd_info.size, k++);
Stefan Roese296c9122019-08-16 15:23:25 +02001497
Lorenzo Bianconi731f3fd2022-05-20 20:11:27 +02001498 frag_size -= txd_info.size;
1499 offset += txd_info.size;
John Crispin656e7052016-03-08 11:29:55 +01001500 }
1501 }
1502
1503 /* store skb to cleanup */
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001504 itx_buf->type = MTK_TYPE_SKB;
1505 itx_buf->data = skb;
John Crispin656e7052016-03-08 11:29:55 +01001506
Lorenzo Bianconic4fd06c2022-05-20 20:11:30 +02001507 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
Stefan Roese296c9122019-08-16 15:23:25 +02001508 if (k & 0x1)
1509 txd_pdma->txd2 |= TX_DMA_LS0;
1510 else
1511 txd_pdma->txd2 |= TX_DMA_LS1;
1512 }
John Crispin656e7052016-03-08 11:29:55 +01001513
Felix Fietkauf63959c2022-11-16 09:07:32 +01001514 netdev_tx_sent_queue(txq, skb->len);
John Crispin656e7052016-03-08 11:29:55 +01001515 skb_tx_timestamp(skb);
1516
1517 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1518 atomic_sub(n_desc, &ring->free_count);
1519
1520 /* make sure that all changes to the dma ring are flushed before we
1521 * continue
1522 */
1523 wmb();
1524
Lorenzo Bianconic4fd06c2022-05-20 20:11:30 +02001525 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
Felix Fietkauf63959c2022-11-16 09:07:32 +01001526 if (netif_xmit_stopped(txq) || !netdev_xmit_more())
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02001527 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
Stefan Roese296c9122019-08-16 15:23:25 +02001528 } else {
Lorenzo Bianconie70a5632022-05-20 20:11:31 +02001529 int next_idx;
1530
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01001531 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size),
Lorenzo Bianconie70a5632022-05-20 20:11:31 +02001532 ring->dma_size);
Stefan Roese296c9122019-08-16 15:23:25 +02001533 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
1534 }
John Crispin656e7052016-03-08 11:29:55 +01001535
1536 return 0;
1537
1538err_dma:
1539 do {
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01001540 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
John Crispin656e7052016-03-08 11:29:55 +01001541
1542 /* unmap dma */
Lorenzo Bianconi853246d2022-07-27 23:20:52 +02001543 mtk_tx_unmap(eth, tx_buf, NULL, false);
John Crispin656e7052016-03-08 11:29:55 +01001544
1545 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
Lorenzo Bianconic4fd06c2022-05-20 20:11:30 +02001546 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA))
Stefan Roese296c9122019-08-16 15:23:25 +02001547 itxd_pdma->txd2 = TX_DMA_DESP2_DEF;
1548
John Crispin656e7052016-03-08 11:29:55 +01001549 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
Stefan Roese296c9122019-08-16 15:23:25 +02001550 itxd_pdma = qdma_to_pdma(ring, itxd);
John Crispin656e7052016-03-08 11:29:55 +01001551 } while (itxd != txd);
1552
1553 return -ENOMEM;
1554}
1555
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02001556static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb)
John Crispin656e7052016-03-08 11:29:55 +01001557{
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02001558 int i, nfrags = 1;
Matthew Wilcox (Oracle)d7840972019-07-22 20:08:25 -07001559 skb_frag_t *frag;
John Crispin656e7052016-03-08 11:29:55 +01001560
John Crispin656e7052016-03-08 11:29:55 +01001561 if (skb_is_gso(skb)) {
1562 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1563 frag = &skb_shinfo(skb)->frags[i];
Matthew Wilcox (Oracle)92493a22019-07-24 04:36:15 -07001564 nfrags += DIV_ROUND_UP(skb_frag_size(frag),
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01001565 eth->soc->tx.dma_max_len);
John Crispin656e7052016-03-08 11:29:55 +01001566 }
1567 } else {
1568 nfrags += skb_shinfo(skb)->nr_frags;
1569 }
1570
John Crispinbeeb4ca2016-04-08 00:54:05 +02001571 return nfrags;
John Crispin656e7052016-03-08 11:29:55 +01001572}
1573
John Crispinad3cba92016-06-10 13:28:07 +02001574static int mtk_queue_stopped(struct mtk_eth *eth)
1575{
1576 int i;
1577
Lorenzo Bianconie05fd622023-07-25 01:52:44 +01001578 for (i = 0; i < MTK_MAX_DEVS; i++) {
John Crispinad3cba92016-06-10 13:28:07 +02001579 if (!eth->netdev[i])
1580 continue;
1581 if (netif_queue_stopped(eth->netdev[i]))
1582 return 1;
1583 }
1584
1585 return 0;
1586}
1587
John Crispin13c822f2016-04-08 00:54:07 +02001588static void mtk_wake_queue(struct mtk_eth *eth)
1589{
1590 int i;
1591
Lorenzo Bianconie05fd622023-07-25 01:52:44 +01001592 for (i = 0; i < MTK_MAX_DEVS; i++) {
John Crispin13c822f2016-04-08 00:54:07 +02001593 if (!eth->netdev[i])
1594 continue;
Felix Fietkauf63959c2022-11-16 09:07:32 +01001595 netif_tx_wake_all_queues(eth->netdev[i]);
John Crispin13c822f2016-04-08 00:54:07 +02001596 }
1597}
1598
Yunjian Wange910a392020-05-06 19:13:08 +08001599static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
John Crispin656e7052016-03-08 11:29:55 +01001600{
1601 struct mtk_mac *mac = netdev_priv(dev);
1602 struct mtk_eth *eth = mac->hw;
1603 struct mtk_tx_ring *ring = &eth->tx_ring;
1604 struct net_device_stats *stats = &dev->stats;
1605 bool gso = false;
1606 int tx_num;
1607
John Crispin34c2e4c2016-04-08 00:54:08 +02001608 /* normally we can rely on the stack not calling this more than once,
1609 * however we have 2 queues running on the same ring so we need to lock
1610 * the ring access
1611 */
Sean Wange3e96522016-08-11 17:51:00 +08001612 spin_lock(&eth->page_lock);
John Crispin34c2e4c2016-04-08 00:54:08 +02001613
Sean Wangdce6fa42016-09-14 23:13:21 +08001614 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
1615 goto drop;
1616
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02001617 tx_num = mtk_cal_txd_req(eth, skb);
John Crispin656e7052016-03-08 11:29:55 +01001618 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
Felix Fietkauf63959c2022-11-16 09:07:32 +01001619 netif_tx_stop_all_queues(dev);
John Crispin656e7052016-03-08 11:29:55 +01001620 netif_err(eth, tx_queued, dev,
1621 "Tx Ring full when queue awake!\n");
Sean Wange3e96522016-08-11 17:51:00 +08001622 spin_unlock(&eth->page_lock);
John Crispin656e7052016-03-08 11:29:55 +01001623 return NETDEV_TX_BUSY;
1624 }
1625
1626 /* TSO: fill MSS info in tcp checksum field */
1627 if (skb_is_gso(skb)) {
1628 if (skb_cow_head(skb, 0)) {
1629 netif_warn(eth, tx_err, dev,
1630 "GSO expand head fail.\n");
1631 goto drop;
1632 }
1633
1634 if (skb_shinfo(skb)->gso_type &
1635 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1636 gso = true;
1637 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
1638 }
1639 }
1640
1641 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
1642 goto drop;
1643
John Crispin82c65442016-06-10 13:28:08 +02001644 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
Felix Fietkauf63959c2022-11-16 09:07:32 +01001645 netif_tx_stop_all_queues(dev);
John Crispin82c65442016-06-10 13:28:08 +02001646
Sean Wange3e96522016-08-11 17:51:00 +08001647 spin_unlock(&eth->page_lock);
John Crispin656e7052016-03-08 11:29:55 +01001648
1649 return NETDEV_TX_OK;
1650
1651drop:
Sean Wange3e96522016-08-11 17:51:00 +08001652 spin_unlock(&eth->page_lock);
John Crispin656e7052016-03-08 11:29:55 +01001653 stats->tx_dropped++;
Wei Yongjun81ad2b72016-10-20 17:00:32 +00001654 dev_kfree_skb_any(skb);
John Crispin656e7052016-03-08 11:29:55 +01001655 return NETDEV_TX_OK;
1656}
1657
Nelson Changee406812016-09-17 23:50:55 +08001658static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
1659{
1660 int i;
1661 struct mtk_rx_ring *ring;
1662 int idx;
1663
1664 if (!eth->hwlro)
1665 return &eth->rx_ring[0];
1666
1667 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
Lorenzo Bianconi649a7522022-05-20 20:11:33 +02001668 struct mtk_rx_dma *rxd;
1669
Nelson Changee406812016-09-17 23:50:55 +08001670 ring = &eth->rx_ring[i];
Stefan Roese08df5fa2019-08-16 15:23:24 +02001671 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01001672 rxd = ring->dma + idx * eth->soc->rx.desc_size;
Lorenzo Bianconi649a7522022-05-20 20:11:33 +02001673 if (rxd->rxd2 & RX_DMA_DONE) {
Nelson Changee406812016-09-17 23:50:55 +08001674 ring->calc_idx_update = true;
1675 return ring;
1676 }
1677 }
1678
1679 return NULL;
1680}
1681
1682static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
1683{
1684 struct mtk_rx_ring *ring;
1685 int i;
1686
1687 if (!eth->hwlro) {
1688 ring = &eth->rx_ring[0];
1689 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1690 } else {
1691 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1692 ring = &eth->rx_ring[i];
1693 if (ring->calc_idx_update) {
1694 ring->calc_idx_update = false;
1695 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1696 }
1697 }
1698 }
1699}
1700
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02001701static bool mtk_page_pool_enabled(struct mtk_eth *eth)
1702{
Lorenzo Bianconi58ea4612023-07-27 09:02:26 +02001703 return mtk_is_netsys_v2_or_greater(eth);
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02001704}
1705
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02001706static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth,
1707 struct xdp_rxq_info *xdp_q,
1708 int id, int size)
1709{
1710 struct page_pool_params pp_params = {
1711 .order = 0,
1712 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
1713 .pool_size = size,
1714 .nid = NUMA_NO_NODE,
1715 .dev = eth->dma_dev,
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02001716 .offset = MTK_PP_HEADROOM,
1717 .max_len = MTK_PP_MAX_BUF_SIZE,
1718 };
1719 struct page_pool *pp;
1720 int err;
1721
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001722 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL
1723 : DMA_FROM_DEVICE;
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02001724 pp = page_pool_create(&pp_params);
1725 if (IS_ERR(pp))
1726 return pp;
1727
Breno Leitaob209bd62024-04-22 05:38:58 -07001728 err = __xdp_rxq_info_reg(xdp_q, eth->dummy_dev, id,
Tariq Toukanc9661532023-02-06 22:47:03 +02001729 eth->rx_napi.napi_id, PAGE_SIZE);
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02001730 if (err < 0)
1731 goto err_free_pp;
1732
1733 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp);
1734 if (err)
1735 goto err_unregister_rxq;
1736
1737 return pp;
1738
1739err_unregister_rxq:
1740 xdp_rxq_info_unreg(xdp_q);
1741err_free_pp:
1742 page_pool_destroy(pp);
1743
1744 return ERR_PTR(err);
1745}
1746
1747static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr,
1748 gfp_t gfp_mask)
1749{
1750 struct page *page;
1751
1752 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN);
1753 if (!page)
1754 return NULL;
1755
1756 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM;
1757 return page_address(page);
1758}
1759
1760static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi)
1761{
1762 if (ring->page_pool)
1763 page_pool_put_full_page(ring->page_pool,
1764 virt_to_head_page(data), napi);
1765 else
1766 skb_free_frag(data);
1767}
1768
Lorenzo Bianconib16fe6d2022-07-27 23:20:50 +02001769static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev,
1770 struct mtk_tx_dma_desc_info *txd_info,
1771 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf,
1772 void *data, u16 headroom, int index, bool dma_map)
1773{
1774 struct mtk_tx_ring *ring = &eth->tx_ring;
1775 struct mtk_mac *mac = netdev_priv(dev);
1776 struct mtk_tx_dma *txd_pdma;
1777
1778 if (dma_map) { /* ndo_xdp_xmit */
1779 txd_info->addr = dma_map_single(eth->dma_dev, data,
1780 txd_info->size, DMA_TO_DEVICE);
1781 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr)))
1782 return -ENOMEM;
1783
1784 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
1785 } else {
1786 struct page *page = virt_to_head_page(data);
1787
1788 txd_info->addr = page_pool_get_dma_addr(page) +
1789 sizeof(struct xdp_frame) + headroom;
1790 dma_sync_single_for_device(eth->dma_dev, txd_info->addr,
1791 txd_info->size, DMA_BIDIRECTIONAL);
1792 }
1793 mtk_tx_set_dma_desc(dev, txd, txd_info);
1794
Lorenzo Bianconi1953f132023-07-25 01:52:59 +01001795 tx_buf->mac_id = mac->id;
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001796 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX;
1797 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
Lorenzo Bianconib16fe6d2022-07-27 23:20:50 +02001798
1799 txd_pdma = qdma_to_pdma(ring, txd);
1800 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size,
1801 index);
1802
1803 return 0;
1804}
1805
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001806static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf,
1807 struct net_device *dev, bool dma_map)
1808{
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001809 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001810 const struct mtk_soc_data *soc = eth->soc;
1811 struct mtk_tx_ring *ring = &eth->tx_ring;
Felix Fietkauf63959c2022-11-16 09:07:32 +01001812 struct mtk_mac *mac = netdev_priv(dev);
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001813 struct mtk_tx_dma_desc_info txd_info = {
1814 .size = xdpf->len,
1815 .first = true,
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001816 .last = !xdp_frame_has_frags(xdpf),
Felix Fietkauf63959c2022-11-16 09:07:32 +01001817 .qid = mac->id,
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001818 };
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001819 int err, index = 0, n_desc = 1, nr_frags;
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001820 struct mtk_tx_buf *htx_buf, *tx_buf;
Lorenzo Bianconia64bb2b2022-08-16 19:14:30 +02001821 struct mtk_tx_dma *htxd, *txd;
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001822 void *data = xdpf->data;
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001823
1824 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
1825 return -EBUSY;
1826
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001827 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0;
1828 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags))
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001829 return -EBUSY;
1830
1831 spin_lock(&eth->page_lock);
1832
1833 txd = ring->next_free;
1834 if (txd == ring->last_free) {
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001835 spin_unlock(&eth->page_lock);
1836 return -ENOMEM;
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001837 }
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001838 htxd = txd;
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001839
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01001840 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size);
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001841 memset(tx_buf, 0, sizeof(*tx_buf));
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001842 htx_buf = tx_buf;
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001843
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001844 for (;;) {
1845 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf,
1846 data, xdpf->headroom, index, dma_map);
1847 if (err < 0)
1848 goto unmap;
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001849
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001850 if (txd_info.last)
1851 break;
1852
1853 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) {
1854 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001855 if (txd == ring->last_free)
1856 goto unmap;
1857
1858 tx_buf = mtk_desc_to_tx_buf(ring, txd,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01001859 soc->tx.desc_size);
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001860 memset(tx_buf, 0, sizeof(*tx_buf));
1861 n_desc++;
1862 }
1863
1864 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
1865 txd_info.size = skb_frag_size(&sinfo->frags[index]);
1866 txd_info.last = index + 1 == nr_frags;
Felix Fietkauf63959c2022-11-16 09:07:32 +01001867 txd_info.qid = mac->id;
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001868 data = skb_frag_address(&sinfo->frags[index]);
1869
1870 index++;
1871 }
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001872 /* store xdpf for cleanup */
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001873 htx_buf->data = xdpf;
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001874
1875 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
Lorenzo Bianconia64bb2b2022-08-16 19:14:30 +02001876 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd);
1877
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001878 if (index & 1)
1879 txd_pdma->txd2 |= TX_DMA_LS0;
1880 else
1881 txd_pdma->txd2 |= TX_DMA_LS1;
1882 }
1883
1884 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1885 atomic_sub(n_desc, &ring->free_count);
1886
1887 /* make sure that all changes to the dma ring are flushed before we
1888 * continue
1889 */
1890 wmb();
1891
1892 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1893 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
1894 } else {
1895 int idx;
1896
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01001897 idx = txd_to_idx(ring, txd, soc->tx.desc_size);
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001898 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
1899 MT7628_TX_CTX_IDX0);
1900 }
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001901
1902 spin_unlock(&eth->page_lock);
1903
1904 return 0;
1905
1906unmap:
1907 while (htxd != txd) {
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01001908 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size);
Lorenzo Bianconi853246d2022-07-27 23:20:52 +02001909 mtk_tx_unmap(eth, tx_buf, NULL, false);
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001910
1911 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
Lorenzo Bianconia64bb2b2022-08-16 19:14:30 +02001912 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1913 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd);
1914
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001915 txd_pdma->txd2 = TX_DMA_DESP2_DEF;
Lorenzo Bianconia64bb2b2022-08-16 19:14:30 +02001916 }
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02001917
1918 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2);
1919 }
1920
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001921 spin_unlock(&eth->page_lock);
1922
1923 return err;
1924}
1925
1926static int mtk_xdp_xmit(struct net_device *dev, int num_frame,
1927 struct xdp_frame **frames, u32 flags)
1928{
1929 struct mtk_mac *mac = netdev_priv(dev);
1930 struct mtk_hw_stats *hw_stats = mac->hw_stats;
1931 struct mtk_eth *eth = mac->hw;
1932 int i, nxmit = 0;
1933
1934 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
1935 return -EINVAL;
1936
1937 for (i = 0; i < num_frame; i++) {
1938 if (mtk_xdp_submit_frame(eth, frames[i], dev, true))
1939 break;
1940 nxmit++;
1941 }
1942
1943 u64_stats_update_begin(&hw_stats->syncp);
1944 hw_stats->xdp_stats.tx_xdp_xmit += nxmit;
1945 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit;
1946 u64_stats_update_end(&hw_stats->syncp);
1947
1948 return nxmit;
1949}
1950
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02001951static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring,
1952 struct xdp_buff *xdp, struct net_device *dev)
1953{
Lorenzo Bianconi916a6ee2022-07-22 09:19:38 +02001954 struct mtk_mac *mac = netdev_priv(dev);
1955 struct mtk_hw_stats *hw_stats = mac->hw_stats;
1956 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop;
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02001957 struct bpf_prog *prog;
1958 u32 act = XDP_PASS;
1959
1960 rcu_read_lock();
1961
1962 prog = rcu_dereference(eth->prog);
1963 if (!prog)
1964 goto out;
1965
1966 act = bpf_prog_run_xdp(prog, xdp);
1967 switch (act) {
1968 case XDP_PASS:
Lorenzo Bianconi916a6ee2022-07-22 09:19:38 +02001969 count = &hw_stats->xdp_stats.rx_xdp_pass;
1970 goto update_stats;
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02001971 case XDP_REDIRECT:
1972 if (unlikely(xdp_do_redirect(dev, xdp, prog))) {
1973 act = XDP_DROP;
1974 break;
1975 }
Lorenzo Bianconi916a6ee2022-07-22 09:19:38 +02001976
1977 count = &hw_stats->xdp_stats.rx_xdp_redirect;
1978 goto update_stats;
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001979 case XDP_TX: {
1980 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
1981
Lorenzo Bianconia617ccc2022-08-16 16:16:15 +02001982 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) {
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02001983 count = &hw_stats->xdp_stats.rx_xdp_tx_errors;
1984 act = XDP_DROP;
1985 break;
1986 }
1987
1988 count = &hw_stats->xdp_stats.rx_xdp_tx;
1989 goto update_stats;
1990 }
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02001991 default:
1992 bpf_warn_invalid_xdp_action(dev, prog, act);
1993 fallthrough;
1994 case XDP_ABORTED:
1995 trace_xdp_exception(dev, prog, act);
1996 fallthrough;
1997 case XDP_DROP:
1998 break;
1999 }
2000
2001 page_pool_put_full_page(ring->page_pool,
2002 virt_to_head_page(xdp->data), true);
Lorenzo Bianconi916a6ee2022-07-22 09:19:38 +02002003
2004update_stats:
2005 u64_stats_update_begin(&hw_stats->syncp);
2006 *count = *count + 1;
2007 u64_stats_update_end(&hw_stats->syncp);
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02002008out:
2009 rcu_read_unlock();
2010
2011 return act;
2012}
2013
John Crispin656e7052016-03-08 11:29:55 +01002014static int mtk_poll_rx(struct napi_struct *napi, int budget,
John Crispineece71e2016-06-29 13:38:09 +02002015 struct mtk_eth *eth)
John Crispin656e7052016-03-08 11:29:55 +01002016{
Felix Fietkaue9229ff2021-04-22 22:21:02 -07002017 struct dim_sample dim_sample = {};
Nelson Changee406812016-09-17 23:50:55 +08002018 struct mtk_rx_ring *ring;
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02002019 bool xdp_flush = false;
Nelson Changee406812016-09-17 23:50:55 +08002020 int idx;
John Crispin656e7052016-03-08 11:29:55 +01002021 struct sk_buff *skb;
Daniel Golle2d75891e2023-08-22 17:33:12 +01002022 u64 addr64 = 0;
John Crispin656e7052016-03-08 11:29:55 +01002023 u8 *data, *new_data;
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02002024 struct mtk_rx_dma_v2 *rxd, trxd;
Felix Fietkaue9229ff2021-04-22 22:21:02 -07002025 int done = 0, bytes = 0;
Daniel Gollee10a35a2023-09-10 22:40:30 +01002026 dma_addr_t dma_addr = DMA_MAPPING_ERROR;
Elad Yifeedee4dd12024-06-07 11:21:50 +03002027 int ppe_idx = 0;
John Crispin656e7052016-03-08 11:29:55 +01002028
2029 while (done < budget) {
Lorenzo Bianconida6e1132022-06-06 21:49:00 +02002030 unsigned int pktlen, *rxdcsum;
John Crispin656e7052016-03-08 11:29:55 +01002031 struct net_device *netdev;
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02002032 u32 hash, reason;
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02002033 int mac = 0;
John Crispin656e7052016-03-08 11:29:55 +01002034
Nelson Changee406812016-09-17 23:50:55 +08002035 ring = mtk_get_rx_ring(eth);
2036 if (unlikely(!ring))
2037 goto rx_done;
2038
Stefan Roese08df5fa2019-08-16 15:23:24 +02002039 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01002040 rxd = ring->dma + idx * eth->soc->rx.desc_size;
John Crispin656e7052016-03-08 11:29:55 +01002041 data = ring->data[idx];
2042
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02002043 if (!mtk_rx_get_desc(eth, &trxd, rxd))
John Crispin656e7052016-03-08 11:29:55 +01002044 break;
2045
2046 /* find out which mac the packet come from. values start at 1 */
Daniel Golle5e69ff82024-05-08 11:43:56 +01002047 if (mtk_is_netsys_v3_or_greater(eth)) {
Lorenzo Bianconi1953f132023-07-25 01:52:59 +01002048 u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
2049
2050 switch (val) {
2051 case PSE_GDM1_PORT:
2052 case PSE_GDM2_PORT:
2053 mac = val - 1;
2054 break;
2055 case PSE_GDM3_PORT:
2056 mac = MTK_GMAC3_ID;
2057 break;
2058 default:
2059 break;
2060 }
2061 } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
2062 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) {
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02002063 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
Lorenzo Bianconi1953f132023-07-25 01:52:59 +01002064 }
John Crispin656e7052016-03-08 11:29:55 +01002065
Lorenzo Bianconie05fd622023-07-25 01:52:44 +01002066 if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS ||
Sean Wang6c7fce62017-07-22 20:45:55 +08002067 !eth->netdev[mac]))
2068 goto release_desc;
2069
John Crispin656e7052016-03-08 11:29:55 +01002070 netdev = eth->netdev[mac];
Elad Yifeedee4dd12024-06-07 11:21:50 +03002071 ppe_idx = eth->mac[mac]->ppe_idx;
John Crispin656e7052016-03-08 11:29:55 +01002072
Sean Wangdce6fa42016-09-14 23:13:21 +08002073 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
2074 goto release_desc;
2075
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02002076 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
2077
John Crispin656e7052016-03-08 11:29:55 +01002078 /* alloc new buffer */
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02002079 if (ring->page_pool) {
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02002080 struct page *page = virt_to_head_page(data);
2081 struct xdp_buff xdp;
2082 u32 ret;
2083
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02002084 new_data = mtk_page_pool_get_buff(ring->page_pool,
2085 &dma_addr,
2086 GFP_ATOMIC);
2087 if (unlikely(!new_data)) {
2088 netdev->stats.rx_dropped++;
2089 goto release_desc;
2090 }
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02002091
2092 dma_sync_single_for_cpu(eth->dma_dev,
2093 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM,
2094 pktlen, page_pool_get_dma_dir(ring->page_pool));
2095
2096 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q);
2097 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen,
2098 false);
2099 xdp_buff_clear_frags_flag(&xdp);
2100
2101 ret = mtk_xdp_run(eth, ring, &xdp, netdev);
2102 if (ret == XDP_REDIRECT)
2103 xdp_flush = true;
2104
2105 if (ret != XDP_PASS)
2106 goto skip_rx;
2107
2108 skb = build_skb(data, PAGE_SIZE);
2109 if (unlikely(!skb)) {
2110 page_pool_put_full_page(ring->page_pool,
2111 page, true);
2112 netdev->stats.rx_dropped++;
2113 goto skip_rx;
2114 }
2115
2116 skb_reserve(skb, xdp.data - xdp.data_hard_start);
2117 skb_put(skb, xdp.data_end - xdp.data);
2118 skb_mark_for_recycle(skb);
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02002119 } else {
2120 if (ring->frag_size <= PAGE_SIZE)
2121 new_data = napi_alloc_frag(ring->frag_size);
2122 else
2123 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC);
John Crispin656e7052016-03-08 11:29:55 +01002124
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02002125 if (unlikely(!new_data)) {
2126 netdev->stats.rx_dropped++;
2127 goto release_desc;
2128 }
2129
2130 dma_addr = dma_map_single(eth->dma_dev,
2131 new_data + NET_SKB_PAD + eth->ip_align,
2132 ring->buf_size, DMA_FROM_DEVICE);
2133 if (unlikely(dma_mapping_error(eth->dma_dev,
2134 dma_addr))) {
2135 skb_free_frag(new_data);
2136 netdev->stats.rx_dropped++;
2137 goto release_desc;
2138 }
2139
Daniel Golle2d75891e2023-08-22 17:33:12 +01002140 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
2141 addr64 = RX_DMA_GET_ADDR64(trxd.rxd2);
2142
2143 dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64),
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02002144 ring->buf_size, DMA_FROM_DEVICE);
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02002145
2146 skb = build_skb(data, ring->frag_size);
2147 if (unlikely(!skb)) {
2148 netdev->stats.rx_dropped++;
2149 skb_free_frag(data);
2150 goto skip_rx;
2151 }
2152
2153 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
2154 skb_put(skb, pktlen);
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02002155 }
Felix Fietkau5196c412021-04-22 22:20:55 -07002156
John Crispin656e7052016-03-08 11:29:55 +01002157 skb->dev = netdev;
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02002158 bytes += skb->len;
Lorenzo Bianconida6e1132022-06-06 21:49:00 +02002159
Daniel Golle5e69ff82024-05-08 11:43:56 +01002160 if (mtk_is_netsys_v3_or_greater(eth)) {
Lorenzo Bianconi03a31802022-09-20 12:11:23 +02002161 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
Lorenzo Bianconi0cf731f2022-08-23 14:24:07 +02002162 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
2163 if (hash != MTK_RXD5_FOE_ENTRY)
2164 skb_set_hash(skb, jhash_1word(hash, 0),
2165 PKT_HASH_TYPE_L4);
Lorenzo Bianconida6e1132022-06-06 21:49:00 +02002166 rxdcsum = &trxd.rxd3;
Lorenzo Bianconi0cf731f2022-08-23 14:24:07 +02002167 } else {
Lorenzo Bianconi03a31802022-09-20 12:11:23 +02002168 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4);
Lorenzo Bianconi0cf731f2022-08-23 14:24:07 +02002169 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY;
2170 if (hash != MTK_RXD4_FOE_ENTRY)
2171 skb_set_hash(skb, jhash_1word(hash, 0),
2172 PKT_HASH_TYPE_L4);
Lorenzo Bianconida6e1132022-06-06 21:49:00 +02002173 rxdcsum = &trxd.rxd4;
Lorenzo Bianconi0cf731f2022-08-23 14:24:07 +02002174 }
Lorenzo Bianconida6e1132022-06-06 21:49:00 +02002175
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01002176 if (*rxdcsum & eth->soc->rx.dma_l4_valid)
John Crispin656e7052016-03-08 11:29:55 +01002177 skb->ip_summed = CHECKSUM_UNNECESSARY;
2178 else
2179 skb_checksum_none_assert(skb);
2180 skb->protocol = eth_type_trans(skb, netdev);
2181
Felix Fietkau2d7605a2022-11-14 13:42:14 +01002182 /* When using VLAN untagging in combination with DSA, the
2183 * hardware treats the MTK special tag as a VLAN and untags it.
2184 */
Lorenzo Bianconia008e2a2023-07-25 01:52:02 +01002185 if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) &&
2186 netdev_uses_dsa(netdev)) {
Felix Fietkauc6d96df2023-04-26 19:21:53 +02002187 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0);
Felix Fietkau2d7605a2022-11-14 13:42:14 +01002188
2189 if (port < ARRAY_SIZE(eth->dsa_meta) &&
2190 eth->dsa_meta[port])
2191 skb_dst_set_noref(skb, &eth->dsa_meta[port]->dst);
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02002192 }
2193
Felix Fietkau5f36ca12023-03-30 14:08:39 +02002194 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
Elad Yifeedee4dd12024-06-07 11:21:50 +03002195 mtk_ppe_check_skb(eth->ppe[ppe_idx], skb, hash);
Felix Fietkau5f36ca12023-03-30 14:08:39 +02002196
John Crispina2d5e7b2017-06-19 15:37:06 +02002197 skb_record_rx_queue(skb, 0);
John Crispin656e7052016-03-08 11:29:55 +01002198 napi_gro_receive(napi, skb);
2199
Ilya Lipnitskiy787082a2021-04-22 22:20:56 -07002200skip_rx:
John Crispin656e7052016-03-08 11:29:55 +01002201 ring->data[idx] = new_data;
2202 rxd->rxd1 = (unsigned int)dma_addr;
John Crispin656e7052016-03-08 11:29:55 +01002203release_desc:
Stefan Roese296c9122019-08-16 15:23:25 +02002204 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
2205 rxd->rxd2 = RX_DMA_LSO;
2206 else
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02002207 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
John Crispin656e7052016-03-08 11:29:55 +01002208
Daniel Gollee10a35a2023-09-10 22:40:30 +01002209 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA) &&
2210 likely(dma_addr != DMA_MAPPING_ERROR))
Daniel Golle2d75891e2023-08-22 17:33:12 +01002211 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr);
2212
John Crispin656e7052016-03-08 11:29:55 +01002213 ring->calc_idx = idx;
John Crispin656e7052016-03-08 11:29:55 +01002214 done++;
2215 }
2216
Nelson Changee406812016-09-17 23:50:55 +08002217rx_done:
Sean Wang41156cea2016-09-03 17:59:27 +08002218 if (done) {
2219 /* make sure that all changes to the dma ring are flushed before
2220 * we continue
2221 */
2222 wmb();
Nelson Changee406812016-09-17 23:50:55 +08002223 mtk_update_rx_cpu_idx(eth);
Sean Wang41156cea2016-09-03 17:59:27 +08002224 }
John Crispin656e7052016-03-08 11:29:55 +01002225
Felix Fietkaue9229ff2021-04-22 22:21:02 -07002226 eth->rx_packets += done;
2227 eth->rx_bytes += bytes;
2228 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes,
2229 &dim_sample);
2230 net_dim(&eth->rx_dim, dim_sample);
2231
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02002232 if (xdp_flush)
Sebastian Andrzej Siewior7f04bd12023-09-08 16:32:14 +02002233 xdp_do_flush();
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02002234
John Crispin656e7052016-03-08 11:29:55 +01002235 return done;
2236}
2237
Felix Fietkauf63959c2022-11-16 09:07:32 +01002238struct mtk_poll_state {
2239 struct netdev_queue *txq;
2240 unsigned int total;
2241 unsigned int done;
2242 unsigned int bytes;
2243};
2244
2245static void
2246mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac,
2247 struct sk_buff *skb)
2248{
2249 struct netdev_queue *txq;
2250 struct net_device *dev;
2251 unsigned int bytes = skb->len;
2252
2253 state->total++;
2254 eth->tx_packets++;
2255 eth->tx_bytes += bytes;
2256
2257 dev = eth->netdev[mac];
2258 if (!dev)
2259 return;
2260
2261 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
2262 if (state->txq == txq) {
2263 state->done++;
2264 state->bytes += bytes;
2265 return;
2266 }
2267
2268 if (state->txq)
2269 netdev_tx_completed_queue(state->txq, state->done, state->bytes);
2270
2271 state->txq = txq;
2272 state->done = 1;
2273 state->bytes = bytes;
2274}
2275
Stefan Roese296c9122019-08-16 15:23:25 +02002276static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget,
Felix Fietkauf63959c2022-11-16 09:07:32 +01002277 struct mtk_poll_state *state)
John Crispin656e7052016-03-08 11:29:55 +01002278{
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02002279 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
John Crispin656e7052016-03-08 11:29:55 +01002280 struct mtk_tx_ring *ring = &eth->tx_ring;
John Crispin656e7052016-03-08 11:29:55 +01002281 struct mtk_tx_buf *tx_buf;
Lorenzo Bianconi853246d2022-07-27 23:20:52 +02002282 struct xdp_frame_bulk bq;
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02002283 struct mtk_tx_dma *desc;
John Crispin656e7052016-03-08 11:29:55 +01002284 u32 cpu, dma;
John Crispin656e7052016-03-08 11:29:55 +01002285
Felix Fietkau4e6bf602021-04-22 22:21:03 -07002286 cpu = ring->last_free_ptr;
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02002287 dma = mtk_r32(eth, reg_map->qdma.drx_ptr);
John Crispin656e7052016-03-08 11:29:55 +01002288
2289 desc = mtk_qdma_phys_to_virt(ring, cpu);
Lorenzo Bianconi853246d2022-07-27 23:20:52 +02002290 xdp_frame_bulk_init(&bq);
John Crispin656e7052016-03-08 11:29:55 +01002291
2292 while ((cpu != dma) && budget) {
2293 u32 next_cpu = desc->txd2;
John Crispin656e7052016-03-08 11:29:55 +01002294
2295 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
2296 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
2297 break;
2298
Lorenzo Bianconic4fd06c2022-05-20 20:11:30 +02002299 tx_buf = mtk_desc_to_tx_buf(ring, desc,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01002300 eth->soc->tx.desc_size);
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02002301 if (!tx_buf->data)
John Crispin656e7052016-03-08 11:29:55 +01002302 break;
John Crispin656e7052016-03-08 11:29:55 +01002303
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02002304 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
Felix Fietkauf63959c2022-11-16 09:07:32 +01002305 if (tx_buf->type == MTK_TYPE_SKB)
Lorenzo Bianconi1953f132023-07-25 01:52:59 +01002306 mtk_poll_tx_done(eth, state, tx_buf->mac_id,
2307 tx_buf->data);
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02002308
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02002309 budget--;
John Crispin656e7052016-03-08 11:29:55 +01002310 }
Lorenzo Bianconi853246d2022-07-27 23:20:52 +02002311 mtk_tx_unmap(eth, tx_buf, &bq, true);
John Crispin656e7052016-03-08 11:29:55 +01002312
John Crispin656e7052016-03-08 11:29:55 +01002313 ring->last_free = desc;
2314 atomic_inc(&ring->free_count);
2315
2316 cpu = next_cpu;
2317 }
Lorenzo Bianconi853246d2022-07-27 23:20:52 +02002318 xdp_flush_frame_bulk(&bq);
John Crispin656e7052016-03-08 11:29:55 +01002319
Felix Fietkau4e6bf602021-04-22 22:21:03 -07002320 ring->last_free_ptr = cpu;
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02002321 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr);
John Crispin656e7052016-03-08 11:29:55 +01002322
Stefan Roese296c9122019-08-16 15:23:25 +02002323 return budget;
2324}
2325
2326static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget,
Felix Fietkauf63959c2022-11-16 09:07:32 +01002327 struct mtk_poll_state *state)
Stefan Roese296c9122019-08-16 15:23:25 +02002328{
2329 struct mtk_tx_ring *ring = &eth->tx_ring;
Stefan Roese296c9122019-08-16 15:23:25 +02002330 struct mtk_tx_buf *tx_buf;
Lorenzo Bianconi853246d2022-07-27 23:20:52 +02002331 struct xdp_frame_bulk bq;
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02002332 struct mtk_tx_dma *desc;
Stefan Roese296c9122019-08-16 15:23:25 +02002333 u32 cpu, dma;
2334
2335 cpu = ring->cpu_idx;
2336 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0);
Lorenzo Bianconi853246d2022-07-27 23:20:52 +02002337 xdp_frame_bulk_init(&bq);
Stefan Roese296c9122019-08-16 15:23:25 +02002338
2339 while ((cpu != dma) && budget) {
2340 tx_buf = &ring->buf[cpu];
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02002341 if (!tx_buf->data)
Stefan Roese296c9122019-08-16 15:23:25 +02002342 break;
2343
Lorenzo Bianconi155738a2022-07-27 23:20:51 +02002344 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
Felix Fietkauf63959c2022-11-16 09:07:32 +01002345 if (tx_buf->type == MTK_TYPE_SKB)
2346 mtk_poll_tx_done(eth, state, 0, tx_buf->data);
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02002347 budget--;
Stefan Roese296c9122019-08-16 15:23:25 +02002348 }
Lorenzo Bianconi853246d2022-07-27 23:20:52 +02002349 mtk_tx_unmap(eth, tx_buf, &bq, true);
Stefan Roese296c9122019-08-16 15:23:25 +02002350
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01002351 desc = ring->dma + cpu * eth->soc->tx.desc_size;
Stefan Roese296c9122019-08-16 15:23:25 +02002352 ring->last_free = desc;
2353 atomic_inc(&ring->free_count);
2354
2355 cpu = NEXT_DESP_IDX(cpu, ring->dma_size);
2356 }
Lorenzo Bianconi853246d2022-07-27 23:20:52 +02002357 xdp_flush_frame_bulk(&bq);
Stefan Roese296c9122019-08-16 15:23:25 +02002358
2359 ring->cpu_idx = cpu;
2360
2361 return budget;
2362}
2363
2364static int mtk_poll_tx(struct mtk_eth *eth, int budget)
2365{
2366 struct mtk_tx_ring *ring = &eth->tx_ring;
Felix Fietkaue9229ff2021-04-22 22:21:02 -07002367 struct dim_sample dim_sample = {};
Felix Fietkauf63959c2022-11-16 09:07:32 +01002368 struct mtk_poll_state state = {};
Stefan Roese296c9122019-08-16 15:23:25 +02002369
2370 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
Felix Fietkauf63959c2022-11-16 09:07:32 +01002371 budget = mtk_poll_tx_qdma(eth, budget, &state);
Stefan Roese296c9122019-08-16 15:23:25 +02002372 else
Felix Fietkauf63959c2022-11-16 09:07:32 +01002373 budget = mtk_poll_tx_pdma(eth, budget, &state);
Stefan Roese296c9122019-08-16 15:23:25 +02002374
Felix Fietkauf63959c2022-11-16 09:07:32 +01002375 if (state.txq)
2376 netdev_tx_completed_queue(state.txq, state.done, state.bytes);
John Crispin656e7052016-03-08 11:29:55 +01002377
Felix Fietkaue9229ff2021-04-22 22:21:02 -07002378 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes,
2379 &dim_sample);
2380 net_dim(&eth->tx_dim, dim_sample);
2381
John Crispinad3cba92016-06-10 13:28:07 +02002382 if (mtk_queue_stopped(eth) &&
2383 (atomic_read(&ring->free_count) > ring->thresh))
John Crispin13c822f2016-04-08 00:54:07 +02002384 mtk_wake_queue(eth);
John Crispin656e7052016-03-08 11:29:55 +01002385
Felix Fietkauf63959c2022-11-16 09:07:32 +01002386 return state.total;
John Crispin656e7052016-03-08 11:29:55 +01002387}
2388
John Crispin80673022016-06-29 13:38:11 +02002389static void mtk_handle_status_irq(struct mtk_eth *eth)
John Crispin656e7052016-03-08 11:29:55 +01002390{
John Crispin80673022016-06-29 13:38:11 +02002391 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
John Crispin656e7052016-03-08 11:29:55 +01002392
John Crispineece71e2016-06-29 13:38:09 +02002393 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
John Crispin656e7052016-03-08 11:29:55 +01002394 mtk_stats_update(eth);
John Crispineece71e2016-06-29 13:38:09 +02002395 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
2396 MTK_INT_STATUS2);
John Crispin656e7052016-03-08 11:29:55 +01002397 }
John Crispin80673022016-06-29 13:38:11 +02002398}
2399
2400static int mtk_napi_tx(struct napi_struct *napi, int budget)
2401{
2402 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02002403 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
John Crispin80673022016-06-29 13:38:11 +02002404 int tx_done = 0;
2405
Stefan Roese296c9122019-08-16 15:23:25 +02002406 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2407 mtk_handle_status_irq(eth);
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02002408 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status);
John Crispin80673022016-06-29 13:38:11 +02002409 tx_done = mtk_poll_tx(eth, budget);
John Crispin656e7052016-03-08 11:29:55 +01002410
2411 if (unlikely(netif_msg_intr(eth))) {
John Crispin80673022016-06-29 13:38:11 +02002412 dev_info(eth->dev,
Ilya Lipnitskiydb2c7b32021-04-22 22:21:06 -07002413 "done tx %d, intr 0x%08x/0x%x\n", tx_done,
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02002414 mtk_r32(eth, reg_map->tx_irq_status),
2415 mtk_r32(eth, reg_map->tx_irq_mask));
John Crispin656e7052016-03-08 11:29:55 +01002416 }
2417
John Crispin80673022016-06-29 13:38:11 +02002418 if (tx_done == budget)
John Crispin656e7052016-03-08 11:29:55 +01002419 return budget;
2420
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02002421 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT)
John Crispin656e7052016-03-08 11:29:55 +01002422 return budget;
2423
Ilya Lipnitskiydb2c7b32021-04-22 22:21:06 -07002424 if (napi_complete_done(napi, tx_done))
Felix Fietkau16769a82021-04-22 22:21:05 -07002425 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
John Crispin80673022016-06-29 13:38:11 +02002426
2427 return tx_done;
2428}
2429
2430static int mtk_napi_rx(struct napi_struct *napi, int budget)
2431{
2432 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02002433 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
Ilya Lipnitskiydb2c7b32021-04-22 22:21:06 -07002434 int rx_done_total = 0;
John Crispin80673022016-06-29 13:38:11 +02002435
2436 mtk_handle_status_irq(eth);
Sean Wang41156cea2016-09-03 17:59:27 +08002437
Ilya Lipnitskiydb2c7b32021-04-22 22:21:06 -07002438 do {
2439 int rx_done;
John Crispin80673022016-06-29 13:38:11 +02002440
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01002441 mtk_w32(eth, eth->soc->rx.irq_done_mask,
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02002442 reg_map->pdma.irq_status);
Ilya Lipnitskiydb2c7b32021-04-22 22:21:06 -07002443 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
2444 rx_done_total += rx_done;
John Crispin80673022016-06-29 13:38:11 +02002445
Ilya Lipnitskiydb2c7b32021-04-22 22:21:06 -07002446 if (unlikely(netif_msg_intr(eth))) {
2447 dev_info(eth->dev,
2448 "done rx %d, intr 0x%08x/0x%x\n", rx_done,
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02002449 mtk_r32(eth, reg_map->pdma.irq_status),
2450 mtk_r32(eth, reg_map->pdma.irq_mask));
Ilya Lipnitskiydb2c7b32021-04-22 22:21:06 -07002451 }
Felix Fietkau16769a82021-04-22 22:21:05 -07002452
Ilya Lipnitskiydb2c7b32021-04-22 22:21:06 -07002453 if (rx_done_total == budget)
2454 return budget;
2455
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02002456 } while (mtk_r32(eth, reg_map->pdma.irq_status) &
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01002457 eth->soc->rx.irq_done_mask);
Ilya Lipnitskiydb2c7b32021-04-22 22:21:06 -07002458
2459 if (napi_complete_done(napi, rx_done_total))
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01002460 mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
John Crispin656e7052016-03-08 11:29:55 +01002461
Ilya Lipnitskiydb2c7b32021-04-22 22:21:06 -07002462 return rx_done_total;
John Crispin656e7052016-03-08 11:29:55 +01002463}
2464
2465static int mtk_tx_alloc(struct mtk_eth *eth)
2466{
Lorenzo Bianconi0e057442022-05-20 20:11:29 +02002467 const struct mtk_soc_data *soc = eth->soc;
John Crispin656e7052016-03-08 11:29:55 +01002468 struct mtk_tx_ring *ring = &eth->tx_ring;
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01002469 int i, sz = soc->tx.desc_size;
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02002470 struct mtk_tx_dma_v2 *txd;
Felix Fietkauc30e0b92022-11-16 09:07:29 +01002471 int ring_size;
Felix Fietkauf63959c2022-11-16 09:07:32 +01002472 u32 ofs, val;
John Crispin656e7052016-03-08 11:29:55 +01002473
Felix Fietkauc30e0b92022-11-16 09:07:29 +01002474 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA))
2475 ring_size = MTK_QDMA_RING_SIZE;
2476 else
Frank Wunderlichc57e5582024-06-03 21:25:05 +02002477 ring_size = soc->tx.dma_size;
Felix Fietkauc30e0b92022-11-16 09:07:29 +01002478
2479 ring->buf = kcalloc(ring_size, sizeof(*ring->buf),
John Crispin656e7052016-03-08 11:29:55 +01002480 GFP_KERNEL);
2481 if (!ring->buf)
2482 goto no_tx_mem;
2483
Daniel Golleebb1e4f2023-08-22 17:32:54 +01002484 if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) {
Frank Wunderlichc57e5582024-06-03 21:25:05 +02002485 ring->dma = eth->sram_base + soc->tx.fq_dma_size * sz;
2486 ring->phys = eth->phy_scratch_ring + soc->tx.fq_dma_size * (dma_addr_t)sz;
Daniel Golleebb1e4f2023-08-22 17:32:54 +01002487 } else {
2488 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
2489 &ring->phys, GFP_KERNEL);
2490 }
2491
John Crispin656e7052016-03-08 11:29:55 +01002492 if (!ring->dma)
2493 goto no_tx_mem;
2494
Felix Fietkauc30e0b92022-11-16 09:07:29 +01002495 for (i = 0; i < ring_size; i++) {
2496 int next = (i + 1) % ring_size;
John Crispin656e7052016-03-08 11:29:55 +01002497 u32 next_ptr = ring->phys + next * sz;
2498
Lorenzo Bianconi7173eca2022-05-20 20:11:37 +02002499 txd = ring->dma + i * sz;
Lorenzo Bianconi0e057442022-05-20 20:11:29 +02002500 txd->txd2 = next_ptr;
2501 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
2502 txd->txd4 = 0;
Lorenzo Bianconia008e2a2023-07-25 01:52:02 +01002503 if (mtk_is_netsys_v2_or_greater(eth)) {
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02002504 txd->txd5 = 0;
2505 txd->txd6 = 0;
2506 txd->txd7 = 0;
2507 txd->txd8 = 0;
2508 }
John Crispin656e7052016-03-08 11:29:55 +01002509 }
2510
Stefan Roese296c9122019-08-16 15:23:25 +02002511 /* On MT7688 (PDMA only) this driver uses the ring->dma structs
2512 * only as the framework. The real HW descriptors are the PDMA
2513 * descriptors in ring->dma_pdma.
2514 */
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02002515 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
Felix Fietkauc30e0b92022-11-16 09:07:29 +01002516 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
Lorenzo Bianconi62dfb4c2022-05-20 20:11:26 +02002517 &ring->phys_pdma, GFP_KERNEL);
Stefan Roese296c9122019-08-16 15:23:25 +02002518 if (!ring->dma_pdma)
2519 goto no_tx_mem;
2520
Felix Fietkauc30e0b92022-11-16 09:07:29 +01002521 for (i = 0; i < ring_size; i++) {
Stefan Roese296c9122019-08-16 15:23:25 +02002522 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF;
2523 ring->dma_pdma[i].txd4 = 0;
2524 }
2525 }
2526
Felix Fietkauc30e0b92022-11-16 09:07:29 +01002527 ring->dma_size = ring_size;
2528 atomic_set(&ring->free_count, ring_size - 2);
Lorenzo Bianconi7173eca2022-05-20 20:11:37 +02002529 ring->next_free = ring->dma;
Lorenzo Bianconi0e057442022-05-20 20:11:29 +02002530 ring->last_free = (void *)txd;
Felix Fietkauc30e0b92022-11-16 09:07:29 +01002531 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz));
John Crispin04698cc2016-06-10 13:28:04 +02002532 ring->thresh = MAX_SKB_FRAGS;
John Crispin656e7052016-03-08 11:29:55 +01002533
2534 /* make sure that all changes to the dma ring are flushed before we
2535 * continue
2536 */
2537 wmb();
2538
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02002539 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
2540 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr);
2541 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr);
Stefan Roese296c9122019-08-16 15:23:25 +02002542 mtk_w32(eth,
Felix Fietkauc30e0b92022-11-16 09:07:29 +01002543 ring->phys + ((ring_size - 1) * sz),
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02002544 soc->reg_map->qdma.crx_ptr);
2545 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr);
Felix Fietkauf63959c2022-11-16 09:07:32 +01002546
2547 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) {
2548 val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES;
2549 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs);
2550
2551 val = MTK_QTX_SCH_MIN_RATE_EN |
2552 /* minimum: 10 Mbps */
2553 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
2554 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
2555 MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
Lorenzo Bianconia008e2a2023-07-25 01:52:02 +01002556 if (mtk_is_netsys_v1(eth))
Felix Fietkauf63959c2022-11-16 09:07:32 +01002557 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
2558 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
2559 ofs += MTK_QTX_OFFSET;
2560 }
2561 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16);
2562 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate);
Lorenzo Bianconia008e2a2023-07-25 01:52:02 +01002563 if (mtk_is_netsys_v2_or_greater(eth))
Felix Fietkauf63959c2022-11-16 09:07:32 +01002564 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4);
Stefan Roese296c9122019-08-16 15:23:25 +02002565 } else {
2566 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
Felix Fietkauc30e0b92022-11-16 09:07:29 +01002567 mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0);
Stefan Roese296c9122019-08-16 15:23:25 +02002568 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02002569 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx);
Stefan Roese296c9122019-08-16 15:23:25 +02002570 }
John Crispin656e7052016-03-08 11:29:55 +01002571
2572 return 0;
2573
2574no_tx_mem:
2575 return -ENOMEM;
2576}
2577
2578static void mtk_tx_clean(struct mtk_eth *eth)
2579{
Lorenzo Bianconi0e057442022-05-20 20:11:29 +02002580 const struct mtk_soc_data *soc = eth->soc;
John Crispin656e7052016-03-08 11:29:55 +01002581 struct mtk_tx_ring *ring = &eth->tx_ring;
2582 int i;
2583
2584 if (ring->buf) {
Felix Fietkauc30e0b92022-11-16 09:07:29 +01002585 for (i = 0; i < ring->dma_size; i++)
Lorenzo Bianconi853246d2022-07-27 23:20:52 +02002586 mtk_tx_unmap(eth, &ring->buf[i], NULL, false);
John Crispin656e7052016-03-08 11:29:55 +01002587 kfree(ring->buf);
2588 ring->buf = NULL;
2589 }
Daniel Golleebb1e4f2023-08-22 17:32:54 +01002590 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
Felix Fietkaud776a572022-04-05 21:57:43 +02002591 dma_free_coherent(eth->dma_dev,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01002592 ring->dma_size * soc->tx.desc_size,
Lorenzo Bianconi0e057442022-05-20 20:11:29 +02002593 ring->dma, ring->phys);
John Crispin656e7052016-03-08 11:29:55 +01002594 ring->dma = NULL;
2595 }
Stefan Roese296c9122019-08-16 15:23:25 +02002596
2597 if (ring->dma_pdma) {
Felix Fietkaud776a572022-04-05 21:57:43 +02002598 dma_free_coherent(eth->dma_dev,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01002599 ring->dma_size * soc->tx.desc_size,
Lorenzo Bianconi0e057442022-05-20 20:11:29 +02002600 ring->dma_pdma, ring->phys_pdma);
Stefan Roese296c9122019-08-16 15:23:25 +02002601 ring->dma_pdma = NULL;
2602 }
John Crispin656e7052016-03-08 11:29:55 +01002603}
2604
Nelson Changee406812016-09-17 23:50:55 +08002605static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
John Crispin656e7052016-03-08 11:29:55 +01002606{
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02002607 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
Frank Wunderlichc57e5582024-06-03 21:25:05 +02002608 const struct mtk_soc_data *soc = eth->soc;
John Crispin6427dc12017-08-09 12:09:32 +02002609 struct mtk_rx_ring *ring;
Daniel Golleebb1e4f2023-08-22 17:32:54 +01002610 int rx_data_len, rx_dma_size, tx_ring_size;
John Crispin656e7052016-03-08 11:29:55 +01002611 int i;
John Crispin6427dc12017-08-09 12:09:32 +02002612
Daniel Golleebb1e4f2023-08-22 17:32:54 +01002613 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2614 tx_ring_size = MTK_QDMA_RING_SIZE;
2615 else
Frank Wunderlichc57e5582024-06-03 21:25:05 +02002616 tx_ring_size = soc->tx.dma_size;
Daniel Golleebb1e4f2023-08-22 17:32:54 +01002617
John Crispin6427dc12017-08-09 12:09:32 +02002618 if (rx_flag == MTK_RX_FLAGS_QDMA) {
2619 if (ring_no)
2620 return -EINVAL;
2621 ring = &eth->rx_ring_qdma;
John Crispin6427dc12017-08-09 12:09:32 +02002622 } else {
2623 ring = &eth->rx_ring[ring_no];
2624 }
John Crispin656e7052016-03-08 11:29:55 +01002625
Nelson Changee406812016-09-17 23:50:55 +08002626 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
2627 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
2628 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
2629 } else {
2630 rx_data_len = ETH_DATA_LEN;
Frank Wunderlichc57e5582024-06-03 21:25:05 +02002631 rx_dma_size = soc->rx.dma_size;
Nelson Changee406812016-09-17 23:50:55 +08002632 }
2633
2634 ring->frag_size = mtk_max_frag_size(rx_data_len);
John Crispin656e7052016-03-08 11:29:55 +01002635 ring->buf_size = mtk_max_buf_size(ring->frag_size);
Nelson Changee406812016-09-17 23:50:55 +08002636 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
John Crispin656e7052016-03-08 11:29:55 +01002637 GFP_KERNEL);
2638 if (!ring->data)
2639 return -ENOMEM;
2640
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02002641 if (mtk_page_pool_enabled(eth)) {
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02002642 struct page_pool *pp;
2643
2644 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no,
2645 rx_dma_size);
2646 if (IS_ERR(pp))
2647 return PTR_ERR(pp);
2648
2649 ring->page_pool = pp;
John Crispin656e7052016-03-08 11:29:55 +01002650 }
2651
Daniel Golleebb1e4f2023-08-22 17:32:54 +01002652 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
2653 rx_flag != MTK_RX_FLAGS_NORMAL) {
2654 ring->dma = dma_alloc_coherent(eth->dma_dev,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01002655 rx_dma_size * eth->soc->rx.desc_size,
2656 &ring->phys, GFP_KERNEL);
Daniel Golleebb1e4f2023-08-22 17:32:54 +01002657 } else {
2658 struct mtk_tx_ring *tx_ring = &eth->tx_ring;
2659
2660 ring->dma = tx_ring->dma + tx_ring_size *
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01002661 eth->soc->tx.desc_size * (ring_no + 1);
Daniel Golleebb1e4f2023-08-22 17:32:54 +01002662 ring->phys = tx_ring->phys + tx_ring_size *
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01002663 eth->soc->tx.desc_size * (ring_no + 1);
Daniel Golleebb1e4f2023-08-22 17:32:54 +01002664 }
2665
John Crispin656e7052016-03-08 11:29:55 +01002666 if (!ring->dma)
2667 return -ENOMEM;
2668
Nelson Changee406812016-09-17 23:50:55 +08002669 for (i = 0; i < rx_dma_size; i++) {
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02002670 struct mtk_rx_dma_v2 *rxd;
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02002671 dma_addr_t dma_addr;
2672 void *data;
Lorenzo Bianconi72e27d32022-05-20 20:11:34 +02002673
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01002674 rxd = ring->dma + i * eth->soc->rx.desc_size;
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02002675 if (ring->page_pool) {
2676 data = mtk_page_pool_get_buff(ring->page_pool,
2677 &dma_addr, GFP_KERNEL);
2678 if (!data)
2679 return -ENOMEM;
2680 } else {
2681 if (ring->frag_size <= PAGE_SIZE)
2682 data = netdev_alloc_frag(ring->frag_size);
2683 else
2684 data = mtk_max_lro_buf_alloc(GFP_KERNEL);
2685
2686 if (!data)
2687 return -ENOMEM;
2688
2689 dma_addr = dma_map_single(eth->dma_dev,
2690 data + NET_SKB_PAD + eth->ip_align,
2691 ring->buf_size, DMA_FROM_DEVICE);
2692 if (unlikely(dma_mapping_error(eth->dma_dev,
Ziyang Xuan3213f802022-11-20 11:54:05 +08002693 dma_addr))) {
2694 skb_free_frag(data);
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02002695 return -ENOMEM;
Ziyang Xuan3213f802022-11-20 11:54:05 +08002696 }
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02002697 }
Lorenzo Bianconi72e27d32022-05-20 20:11:34 +02002698 rxd->rxd1 = (unsigned int)dma_addr;
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02002699 ring->data[i] = data;
John Crispin656e7052016-03-08 11:29:55 +01002700
Stefan Roese296c9122019-08-16 15:23:25 +02002701 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
Lorenzo Bianconi72e27d32022-05-20 20:11:34 +02002702 rxd->rxd2 = RX_DMA_LSO;
Stefan Roese296c9122019-08-16 15:23:25 +02002703 else
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02002704 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
Lorenzo Bianconi72e27d32022-05-20 20:11:34 +02002705
Daniel Golle2d75891e2023-08-22 17:33:12 +01002706 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
2707 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr);
2708
Lorenzo Bianconi72e27d32022-05-20 20:11:34 +02002709 rxd->rxd3 = 0;
2710 rxd->rxd4 = 0;
Daniel Golle5e69ff82024-05-08 11:43:56 +01002711 if (mtk_is_netsys_v3_or_greater(eth)) {
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02002712 rxd->rxd5 = 0;
2713 rxd->rxd6 = 0;
2714 rxd->rxd7 = 0;
2715 rxd->rxd8 = 0;
2716 }
John Crispin656e7052016-03-08 11:29:55 +01002717 }
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02002718
Nelson Changee406812016-09-17 23:50:55 +08002719 ring->dma_size = rx_dma_size;
2720 ring->calc_idx_update = false;
2721 ring->calc_idx = rx_dma_size - 1;
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02002722 if (rx_flag == MTK_RX_FLAGS_QDMA)
2723 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr +
2724 ring_no * MTK_QRX_OFFSET;
2725 else
2726 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr +
2727 ring_no * MTK_QRX_OFFSET;
John Crispin656e7052016-03-08 11:29:55 +01002728 /* make sure that all changes to the dma ring are flushed before we
2729 * continue
2730 */
2731 wmb();
2732
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02002733 if (rx_flag == MTK_RX_FLAGS_QDMA) {
2734 mtk_w32(eth, ring->phys,
2735 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET);
2736 mtk_w32(eth, rx_dma_size,
2737 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET);
2738 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no),
2739 reg_map->qdma.rst_idx);
2740 } else {
2741 mtk_w32(eth, ring->phys,
2742 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET);
2743 mtk_w32(eth, rx_dma_size,
2744 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET);
2745 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no),
2746 reg_map->pdma.rst_idx);
2747 }
2748 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
John Crispin656e7052016-03-08 11:29:55 +01002749
2750 return 0;
2751}
2752
Daniel Golleebb1e4f2023-08-22 17:32:54 +01002753static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram)
John Crispin656e7052016-03-08 11:29:55 +01002754{
Daniel Golle2d75891e2023-08-22 17:33:12 +01002755 u64 addr64 = 0;
John Crispin656e7052016-03-08 11:29:55 +01002756 int i;
2757
2758 if (ring->data && ring->dma) {
Nelson Changee406812016-09-17 23:50:55 +08002759 for (i = 0; i < ring->dma_size; i++) {
Lorenzo Bianconi72e27d32022-05-20 20:11:34 +02002760 struct mtk_rx_dma *rxd;
2761
John Crispin656e7052016-03-08 11:29:55 +01002762 if (!ring->data[i])
2763 continue;
Lorenzo Bianconi72e27d32022-05-20 20:11:34 +02002764
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01002765 rxd = ring->dma + i * eth->soc->rx.desc_size;
Lorenzo Bianconi72e27d32022-05-20 20:11:34 +02002766 if (!rxd->rxd1)
John Crispin656e7052016-03-08 11:29:55 +01002767 continue;
Lorenzo Bianconi72e27d32022-05-20 20:11:34 +02002768
Daniel Golle2d75891e2023-08-22 17:33:12 +01002769 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
2770 addr64 = RX_DMA_GET_ADDR64(rxd->rxd2);
2771
2772 dma_unmap_single(eth->dma_dev, ((u64)rxd->rxd1 | addr64),
Lorenzo Bianconi72e27d32022-05-20 20:11:34 +02002773 ring->buf_size, DMA_FROM_DEVICE);
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02002774 mtk_rx_put_buff(ring, ring->data[i], false);
John Crispin656e7052016-03-08 11:29:55 +01002775 }
2776 kfree(ring->data);
2777 ring->data = NULL;
2778 }
2779
Daniel Golleebb1e4f2023-08-22 17:32:54 +01002780 if (!in_sram && ring->dma) {
Felix Fietkaud776a572022-04-05 21:57:43 +02002781 dma_free_coherent(eth->dma_dev,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01002782 ring->dma_size * eth->soc->rx.desc_size,
Lorenzo Bianconi670ff7d2022-05-20 20:11:32 +02002783 ring->dma, ring->phys);
John Crispin656e7052016-03-08 11:29:55 +01002784 ring->dma = NULL;
2785 }
Lorenzo Bianconi23233e52022-07-22 09:19:36 +02002786
2787 if (ring->page_pool) {
2788 if (xdp_rxq_info_is_reg(&ring->xdp_q))
2789 xdp_rxq_info_unreg(&ring->xdp_q);
2790 page_pool_destroy(ring->page_pool);
2791 ring->page_pool = NULL;
2792 }
John Crispin656e7052016-03-08 11:29:55 +01002793}
2794
Nelson Changee406812016-09-17 23:50:55 +08002795static int mtk_hwlro_rx_init(struct mtk_eth *eth)
2796{
2797 int i;
2798 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
2799 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
2800
2801 /* set LRO rings to auto-learn modes */
2802 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
2803
2804 /* validate LRO ring */
2805 ring_ctrl_dw2 |= MTK_RING_VLD;
2806
2807 /* set AGE timer (unit: 20us) */
2808 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
2809 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
2810
2811 /* set max AGG timer (unit: 20us) */
2812 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
2813
2814 /* set max LRO AGG count */
2815 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
2816 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
2817
2818 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
2819 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
2820 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
2821 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
2822 }
2823
2824 /* IPv4 checksum update enable */
2825 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
2826
2827 /* switch priority comparison to packet count mode */
2828 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
2829
2830 /* bandwidth threshold setting */
2831 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
2832
2833 /* auto-learn score delta setting */
2834 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
2835
2836 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
2837 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
2838 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
2839
2840 /* set HW LRO mode & the max aggregation count for rx packets */
2841 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
2842
2843 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
2844 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
2845
2846 /* enable HW LRO */
2847 lro_ctrl_dw0 |= MTK_LRO_EN;
2848
2849 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
2850 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
2851
2852 return 0;
2853}
2854
2855static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
2856{
2857 int i;
2858 u32 val;
2859
2860 /* relinquish lro rings, flush aggregated packets */
2861 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
2862
2863 /* wait for relinquishments done */
2864 for (i = 0; i < 10; i++) {
2865 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
2866 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
2867 msleep(20);
2868 continue;
2869 }
Nelson Changca3ba102016-09-26 14:33:50 +08002870 break;
Nelson Changee406812016-09-17 23:50:55 +08002871 }
2872
2873 /* invalidate lro rings */
2874 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
2875 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
2876
2877 /* disable HW LRO */
2878 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
2879}
2880
Nelson Chang7aab7472016-09-17 23:50:56 +08002881static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
2882{
2883 u32 reg_val;
2884
2885 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
2886
2887 /* invalidate the IP setting */
2888 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2889
2890 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
2891
2892 /* validate the IP setting */
2893 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2894}
2895
2896static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
2897{
2898 u32 reg_val;
2899
2900 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
2901
2902 /* invalidate the IP setting */
2903 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2904
2905 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
2906}
2907
2908static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
2909{
2910 int cnt = 0;
2911 int i;
2912
2913 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2914 if (mac->hwlro_ip[i])
2915 cnt++;
2916 }
2917
2918 return cnt;
2919}
2920
2921static int mtk_hwlro_add_ipaddr(struct net_device *dev,
2922 struct ethtool_rxnfc *cmd)
2923{
2924 struct ethtool_rx_flow_spec *fsp =
2925 (struct ethtool_rx_flow_spec *)&cmd->fs;
2926 struct mtk_mac *mac = netdev_priv(dev);
2927 struct mtk_eth *eth = mac->hw;
2928 int hwlro_idx;
2929
2930 if ((fsp->flow_type != TCP_V4_FLOW) ||
2931 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
2932 (fsp->location > 1))
2933 return -EINVAL;
2934
2935 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
2936 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
2937
2938 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2939
2940 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
2941
2942 return 0;
2943}
2944
2945static int mtk_hwlro_del_ipaddr(struct net_device *dev,
2946 struct ethtool_rxnfc *cmd)
2947{
2948 struct ethtool_rx_flow_spec *fsp =
2949 (struct ethtool_rx_flow_spec *)&cmd->fs;
2950 struct mtk_mac *mac = netdev_priv(dev);
2951 struct mtk_eth *eth = mac->hw;
2952 int hwlro_idx;
2953
2954 if (fsp->location > 1)
2955 return -EINVAL;
2956
2957 mac->hwlro_ip[fsp->location] = 0;
2958 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
2959
2960 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2961
2962 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
2963
2964 return 0;
2965}
2966
2967static void mtk_hwlro_netdev_disable(struct net_device *dev)
2968{
2969 struct mtk_mac *mac = netdev_priv(dev);
2970 struct mtk_eth *eth = mac->hw;
2971 int i, hwlro_idx;
2972
2973 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2974 mac->hwlro_ip[i] = 0;
2975 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
2976
2977 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
2978 }
2979
2980 mac->hwlro_ip_cnt = 0;
2981}
2982
2983static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
2984 struct ethtool_rxnfc *cmd)
2985{
2986 struct mtk_mac *mac = netdev_priv(dev);
2987 struct ethtool_rx_flow_spec *fsp =
2988 (struct ethtool_rx_flow_spec *)&cmd->fs;
2989
Dan Carpentere7e71042022-05-26 11:02:42 +03002990 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip))
2991 return -EINVAL;
2992
Nelson Chang7aab7472016-09-17 23:50:56 +08002993 /* only tcp dst ipv4 is meaningful, others are meaningless */
2994 fsp->flow_type = TCP_V4_FLOW;
2995 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
2996 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
2997
2998 fsp->h_u.tcp_ip4_spec.ip4src = 0;
2999 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
3000 fsp->h_u.tcp_ip4_spec.psrc = 0;
3001 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
3002 fsp->h_u.tcp_ip4_spec.pdst = 0;
3003 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
3004 fsp->h_u.tcp_ip4_spec.tos = 0;
3005 fsp->m_u.tcp_ip4_spec.tos = 0xff;
3006
3007 return 0;
3008}
3009
3010static int mtk_hwlro_get_fdir_all(struct net_device *dev,
3011 struct ethtool_rxnfc *cmd,
3012 u32 *rule_locs)
3013{
3014 struct mtk_mac *mac = netdev_priv(dev);
3015 int cnt = 0;
3016 int i;
3017
3018 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
Hangyu Huae4c79812023-09-08 14:19:50 +08003019 if (cnt == cmd->rule_cnt)
3020 return -EMSGSIZE;
3021
Nelson Chang7aab7472016-09-17 23:50:56 +08003022 if (mac->hwlro_ip[i]) {
3023 rule_locs[cnt] = i;
3024 cnt++;
3025 }
3026 }
3027
3028 cmd->rule_cnt = cnt;
3029
3030 return 0;
3031}
3032
3033static netdev_features_t mtk_fix_features(struct net_device *dev,
3034 netdev_features_t features)
3035{
3036 if (!(features & NETIF_F_LRO)) {
3037 struct mtk_mac *mac = netdev_priv(dev);
3038 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
3039
3040 if (ip_cnt) {
3041 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
3042
3043 features |= NETIF_F_LRO;
3044 }
3045 }
3046
3047 return features;
3048}
3049
3050static int mtk_set_features(struct net_device *dev, netdev_features_t features)
3051{
Felix Fietkau08666cb2022-11-14 13:42:13 +01003052 netdev_features_t diff = dev->features ^ features;
Nelson Chang7aab7472016-09-17 23:50:56 +08003053
Felix Fietkau08666cb2022-11-14 13:42:13 +01003054 if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO))
Nelson Chang7aab7472016-09-17 23:50:56 +08003055 mtk_hwlro_netdev_disable(dev);
3056
Felix Fietkau08666cb2022-11-14 13:42:13 +01003057 return 0;
Nelson Chang7aab7472016-09-17 23:50:56 +08003058}
3059
John Crispin656e7052016-03-08 11:29:55 +01003060/* wait for DMA to finish whatever it is doing before we start using it again */
3061static int mtk_dma_busy_wait(struct mtk_eth *eth)
3062{
Ilya Lipnitskiy3bc8e0a2021-04-22 22:21:08 -07003063 unsigned int reg;
3064 int ret;
3065 u32 val;
John Crispin656e7052016-03-08 11:29:55 +01003066
Ilya Lipnitskiy3bc8e0a2021-04-22 22:21:08 -07003067 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003068 reg = eth->soc->reg_map->qdma.glo_cfg;
Ilya Lipnitskiy3bc8e0a2021-04-22 22:21:08 -07003069 else
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003070 reg = eth->soc->reg_map->pdma.glo_cfg;
Stefan Roese296c9122019-08-16 15:23:25 +02003071
Ilya Lipnitskiy3bc8e0a2021-04-22 22:21:08 -07003072 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val,
3073 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)),
3074 5, MTK_DMA_BUSY_TIMEOUT_US);
3075 if (ret)
3076 dev_err(eth->dev, "DMA init timeout\n");
John Crispin656e7052016-03-08 11:29:55 +01003077
Ilya Lipnitskiy3bc8e0a2021-04-22 22:21:08 -07003078 return ret;
John Crispin656e7052016-03-08 11:29:55 +01003079}
3080
3081static int mtk_dma_init(struct mtk_eth *eth)
3082{
3083 int err;
Nelson Changee406812016-09-17 23:50:55 +08003084 u32 i;
John Crispin656e7052016-03-08 11:29:55 +01003085
3086 if (mtk_dma_busy_wait(eth))
3087 return -EBUSY;
3088
Stefan Roese296c9122019-08-16 15:23:25 +02003089 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
3090 /* QDMA needs scratch memory for internal reordering of the
3091 * descriptors
3092 */
3093 err = mtk_init_fq_dma(eth);
3094 if (err)
3095 return err;
3096 }
John Crispin656e7052016-03-08 11:29:55 +01003097
3098 err = mtk_tx_alloc(eth);
3099 if (err)
3100 return err;
3101
Stefan Roese296c9122019-08-16 15:23:25 +02003102 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
3103 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
3104 if (err)
3105 return err;
3106 }
John Crispin6427dc12017-08-09 12:09:32 +02003107
Nelson Changee406812016-09-17 23:50:55 +08003108 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
John Crispin656e7052016-03-08 11:29:55 +01003109 if (err)
3110 return err;
3111
Nelson Changee406812016-09-17 23:50:55 +08003112 if (eth->hwlro) {
3113 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
3114 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
3115 if (err)
3116 return err;
3117 }
3118 err = mtk_hwlro_rx_init(eth);
3119 if (err)
3120 return err;
3121 }
3122
Stefan Roese296c9122019-08-16 15:23:25 +02003123 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
3124 /* Enable random early drop and set drop threshold
3125 * automatically
3126 */
3127 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN |
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003128 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th);
3129 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred);
Stefan Roese296c9122019-08-16 15:23:25 +02003130 }
John Crispin656e7052016-03-08 11:29:55 +01003131
3132 return 0;
3133}
3134
3135static void mtk_dma_free(struct mtk_eth *eth)
3136{
Lorenzo Bianconieb067342022-05-20 20:11:28 +02003137 const struct mtk_soc_data *soc = eth->soc;
John Crispin656e7052016-03-08 11:29:55 +01003138 int i;
3139
Lorenzo Bianconie05fd622023-07-25 01:52:44 +01003140 for (i = 0; i < MTK_MAX_DEVS; i++)
John Crispin656e7052016-03-08 11:29:55 +01003141 if (eth->netdev[i])
3142 netdev_reset_queue(eth->netdev[i]);
Daniel Golleebb1e4f2023-08-22 17:32:54 +01003143 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
Felix Fietkaud776a572022-04-05 21:57:43 +02003144 dma_free_coherent(eth->dma_dev,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01003145 MTK_QDMA_RING_SIZE * soc->tx.desc_size,
Lorenzo Bianconieb067342022-05-20 20:11:28 +02003146 eth->scratch_ring, eth->phy_scratch_ring);
John Crispin605e4fe2016-06-10 13:27:59 +02003147 eth->scratch_ring = NULL;
3148 eth->phy_scratch_ring = 0;
3149 }
John Crispin656e7052016-03-08 11:29:55 +01003150 mtk_tx_clean(eth);
Daniel Golleebb1e4f2023-08-22 17:32:54 +01003151 mtk_rx_clean(eth, &eth->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM));
3152 mtk_rx_clean(eth, &eth->rx_ring_qdma, false);
Nelson Changee406812016-09-17 23:50:55 +08003153
3154 if (eth->hwlro) {
3155 mtk_hwlro_rx_uninit(eth);
3156 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
Daniel Golleebb1e4f2023-08-22 17:32:54 +01003157 mtk_rx_clean(eth, &eth->rx_ring[i], false);
Nelson Changee406812016-09-17 23:50:55 +08003158 }
3159
Frank Wunderlichc57e5582024-06-03 21:25:05 +02003160 for (i = 0; i < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); i++) {
3161 kfree(eth->scratch_head[i]);
3162 eth->scratch_head[i] = NULL;
3163 }
John Crispin656e7052016-03-08 11:29:55 +01003164}
3165
Lorenzo Bianconi06127502023-01-14 18:01:30 +01003166static bool mtk_hw_reset_check(struct mtk_eth *eth)
3167{
3168 u32 val = mtk_r32(eth, MTK_INT_STATUS2);
3169
3170 return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) ||
3171 (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) ||
3172 (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL);
3173}
3174
Michael S. Tsirkin0290bd22019-12-10 09:23:51 -05003175static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue)
John Crispin656e7052016-03-08 11:29:55 +01003176{
3177 struct mtk_mac *mac = netdev_priv(dev);
3178 struct mtk_eth *eth = mac->hw;
3179
Lorenzo Bianconi06127502023-01-14 18:01:30 +01003180 if (test_bit(MTK_RESETTING, &eth->state))
3181 return;
3182
3183 if (!mtk_hw_reset_check(eth))
3184 return;
3185
John Crispin656e7052016-03-08 11:29:55 +01003186 eth->netdev[mac->id]->stats.tx_errors++;
Lorenzo Bianconi06127502023-01-14 18:01:30 +01003187 netif_err(eth, tx_err, dev, "transmit timed out\n");
3188
John Crispin7c78b4a2016-04-08 00:54:10 +02003189 schedule_work(&eth->pending_work);
John Crispin656e7052016-03-08 11:29:55 +01003190}
3191
John Crispin80673022016-06-29 13:38:11 +02003192static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
John Crispin656e7052016-03-08 11:29:55 +01003193{
3194 struct mtk_eth *eth = _eth;
John Crispin656e7052016-03-08 11:29:55 +01003195
Felix Fietkaue9229ff2021-04-22 22:21:02 -07003196 eth->rx_events++;
John Crispin80673022016-06-29 13:38:11 +02003197 if (likely(napi_schedule_prep(&eth->rx_napi))) {
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01003198 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
Christian Marangifcdfc462023-10-02 16:08:05 +02003199 __napi_schedule(&eth->rx_napi);
John Crispin656e7052016-03-08 11:29:55 +01003200 }
John Crispin80673022016-06-29 13:38:11 +02003201
3202 return IRQ_HANDLED;
3203}
3204
3205static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
3206{
3207 struct mtk_eth *eth = _eth;
3208
Felix Fietkaue9229ff2021-04-22 22:21:02 -07003209 eth->tx_events++;
John Crispin80673022016-06-29 13:38:11 +02003210 if (likely(napi_schedule_prep(&eth->tx_napi))) {
John Crispin5cce0322017-06-19 15:37:05 +02003211 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
Christian Marangifcdfc462023-10-02 16:08:05 +02003212 __napi_schedule(&eth->tx_napi);
John Crispin80673022016-06-29 13:38:11 +02003213 }
John Crispin656e7052016-03-08 11:29:55 +01003214
3215 return IRQ_HANDLED;
3216}
3217
Bjørn Mork889bcbd2019-01-30 11:24:04 +10003218static irqreturn_t mtk_handle_irq(int irq, void *_eth)
3219{
3220 struct mtk_eth *eth = _eth;
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003221 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
Bjørn Mork889bcbd2019-01-30 11:24:04 +10003222
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02003223 if (mtk_r32(eth, reg_map->pdma.irq_mask) &
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01003224 eth->soc->rx.irq_done_mask) {
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02003225 if (mtk_r32(eth, reg_map->pdma.irq_status) &
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01003226 eth->soc->rx.irq_done_mask)
Bjørn Mork889bcbd2019-01-30 11:24:04 +10003227 mtk_handle_irq_rx(irq, _eth);
3228 }
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003229 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
3230 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT)
Bjørn Mork889bcbd2019-01-30 11:24:04 +10003231 mtk_handle_irq_tx(irq, _eth);
3232 }
3233
3234 return IRQ_HANDLED;
3235}
3236
John Crispin656e7052016-03-08 11:29:55 +01003237#ifdef CONFIG_NET_POLL_CONTROLLER
3238static void mtk_poll_controller(struct net_device *dev)
3239{
3240 struct mtk_mac *mac = netdev_priv(dev);
3241 struct mtk_eth *eth = mac->hw;
John Crispin656e7052016-03-08 11:29:55 +01003242
John Crispin5cce0322017-06-19 15:37:05 +02003243 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01003244 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
John Crispin8186f6e2016-07-02 08:00:50 +02003245 mtk_handle_irq_rx(eth->irq[2], dev);
John Crispin5cce0322017-06-19 15:37:05 +02003246 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01003247 mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
John Crispin656e7052016-03-08 11:29:55 +01003248}
3249#endif
3250
3251static int mtk_start_dma(struct mtk_eth *eth)
3252{
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02003253 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003254 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
John Crispin656e7052016-03-08 11:29:55 +01003255 int err;
3256
3257 err = mtk_dma_init(eth);
3258 if (err) {
3259 mtk_dma_free(eth);
3260 return err;
3261 }
3262
Stefan Roese296c9122019-08-16 15:23:25 +02003263 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02003264 val = mtk_r32(eth, reg_map->qdma.glo_cfg);
3265 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN |
3266 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
3267 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
3268
Lorenzo Bianconia008e2a2023-07-25 01:52:02 +01003269 if (mtk_is_netsys_v2_or_greater(eth))
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02003270 val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
3271 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
Felix Fietkauf63959c2022-11-16 09:07:32 +01003272 MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN;
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02003273 else
3274 val |= MTK_RX_BT_32DWORDS;
3275 mtk_w32(eth, val, reg_map->qdma.glo_cfg);
3276
Stefan Roese296c9122019-08-16 15:23:25 +02003277 mtk_w32(eth,
3278 MTK_RX_DMA_EN | rx_2b_offset |
3279 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003280 reg_map->pdma.glo_cfg);
Stefan Roese296c9122019-08-16 15:23:25 +02003281 } else {
3282 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN |
3283 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS,
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003284 reg_map->pdma.glo_cfg);
Stefan Roese296c9122019-08-16 15:23:25 +02003285 }
Nelson Changbacfd112016-08-26 01:09:42 +08003286
John Crispin656e7052016-03-08 11:29:55 +01003287 return 0;
3288}
3289
Elad Yifeedee4dd12024-06-07 11:21:50 +03003290static void mtk_gdm_config(struct mtk_eth *eth, u32 id, u32 config)
MarkLee8d3f4a92019-11-13 10:38:42 +08003291{
Elad Yifeedee4dd12024-06-07 11:21:50 +03003292 u32 val;
MarkLee8d3f4a92019-11-13 10:38:42 +08003293
MarkLee5ac9eda2019-11-13 10:38:43 +08003294 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3295 return;
3296
Elad Yifeedee4dd12024-06-07 11:21:50 +03003297 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(id));
Lorenzo Bianconie05fd622023-07-25 01:52:44 +01003298
Elad Yifeedee4dd12024-06-07 11:21:50 +03003299 /* default setup the forward port to send frame to PDMA */
3300 val &= ~0xffff;
Lorenzo Bianconie05fd622023-07-25 01:52:44 +01003301
Elad Yifeedee4dd12024-06-07 11:21:50 +03003302 /* Enable RX checksum */
3303 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
MarkLee8d3f4a92019-11-13 10:38:42 +08003304
Elad Yifeedee4dd12024-06-07 11:21:50 +03003305 val |= config;
MarkLee8d3f4a92019-11-13 10:38:42 +08003306
Elad Yifeedee4dd12024-06-07 11:21:50 +03003307 if (eth->netdev[id] && netdev_uses_dsa(eth->netdev[id]))
3308 val |= MTK_GDMA_SPECIAL_TAG;
MarkLee8d3f4a92019-11-13 10:38:42 +08003309
Elad Yifeedee4dd12024-06-07 11:21:50 +03003310 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(id));
MarkLee8d3f4a92019-11-13 10:38:42 +08003311}
3312
Felix Fietkau2d7605a2022-11-14 13:42:14 +01003313
3314static bool mtk_uses_dsa(struct net_device *dev)
3315{
3316#if IS_ENABLED(CONFIG_NET_DSA)
3317 return netdev_uses_dsa(dev) &&
3318 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK;
3319#else
3320 return false;
3321#endif
3322}
3323
Felix Fietkauf63959c2022-11-16 09:07:32 +01003324static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr)
3325{
3326 struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier);
3327 struct mtk_eth *eth = mac->hw;
3328 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3329 struct ethtool_link_ksettings s;
3330 struct net_device *ldev;
3331 struct list_head *iter;
3332 struct dsa_port *dp;
3333
3334 if (event != NETDEV_CHANGE)
3335 return NOTIFY_DONE;
3336
3337 netdev_for_each_lower_dev(dev, ldev, iter) {
3338 if (netdev_priv(ldev) == mac)
3339 goto found;
3340 }
3341
3342 return NOTIFY_DONE;
3343
3344found:
Florian Fainelli6ca80632023-10-23 11:17:28 -07003345 if (!dsa_user_dev_check(dev))
Felix Fietkauf63959c2022-11-16 09:07:32 +01003346 return NOTIFY_DONE;
3347
3348 if (__ethtool_get_link_ksettings(dev, &s))
3349 return NOTIFY_DONE;
3350
3351 if (s.base.speed == 0 || s.base.speed == ((__u32)-1))
3352 return NOTIFY_DONE;
3353
3354 dp = dsa_port_from_netdev(dev);
3355 if (dp->index >= MTK_QDMA_NUM_QUEUES)
3356 return NOTIFY_DONE;
3357
Felix Fietkaue669ce42023-03-31 14:49:59 +02003358 if (mac->speed > 0 && mac->speed <= s.base.speed)
3359 s.base.speed = 0;
3360
Felix Fietkauf63959c2022-11-16 09:07:32 +01003361 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed);
3362
3363 return NOTIFY_DONE;
3364}
3365
John Crispin656e7052016-03-08 11:29:55 +01003366static int mtk_open(struct net_device *dev)
3367{
3368 struct mtk_mac *mac = netdev_priv(dev);
3369 struct mtk_eth *eth = mac->hw;
Elad Yifeedee4dd12024-06-07 11:21:50 +03003370 struct mtk_mac *target_mac;
3371 int i, err, ppe_num;
3372
3373 ppe_num = eth->soc->ppe_num;
Felix Fietkau2d7605a2022-11-14 13:42:14 +01003374
René van Dorstb8fc9f32019-08-25 19:43:39 +02003375 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
3376 if (err) {
3377 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
3378 err);
3379 return err;
3380 }
John Crispin656e7052016-03-08 11:29:55 +01003381
3382 /* we run 2 netdevs on the same dma ring so we only bring it up once */
Elena Reshetovac6d4e632017-10-20 10:23:36 +03003383 if (!refcount_read(&eth->dma_refcnt)) {
Lorenzo Bianconi329bce52022-09-20 12:11:15 +02003384 const struct mtk_soc_data *soc = eth->soc;
Lorenzo Bianconi4ff1a3f2022-09-20 12:11:17 +02003385 u32 gdm_config;
3386 int i;
John Crispin656e7052016-03-08 11:29:55 +01003387
Felix Fietkauba37b7c2021-03-24 02:30:53 +01003388 err = mtk_start_dma(eth);
Liu Jianf7007412022-11-17 19:13:56 +08003389 if (err) {
3390 phylink_disconnect_phy(mac->phylink);
John Crispin656e7052016-03-08 11:29:55 +01003391 return err;
Liu Jianf7007412022-11-17 19:13:56 +08003392 }
John Crispin656e7052016-03-08 11:29:55 +01003393
Lorenzo Bianconi4ff1a3f2022-09-20 12:11:17 +02003394 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
3395 mtk_ppe_start(eth->ppe[i]);
Felix Fietkauba37b7c2021-03-24 02:30:53 +01003396
Elad Yifeedee4dd12024-06-07 11:21:50 +03003397 for (i = 0; i < MTK_MAX_DEVS; i++) {
3398 if (!eth->netdev[i])
Daniel Golle3b2aef92024-07-01 20:28:14 +01003399 continue;
Elad Yifeedee4dd12024-06-07 11:21:50 +03003400
3401 target_mac = netdev_priv(eth->netdev[i]);
3402 if (!soc->offload_version) {
3403 target_mac->ppe_idx = 0;
3404 gdm_config = MTK_GDMA_TO_PDMA;
3405 } else if (ppe_num >= 3 && target_mac->id == 2) {
3406 target_mac->ppe_idx = 2;
3407 gdm_config = soc->reg_map->gdma_to_ppe[2];
3408 } else if (ppe_num >= 2 && target_mac->id == 1) {
3409 target_mac->ppe_idx = 1;
3410 gdm_config = soc->reg_map->gdma_to_ppe[1];
3411 } else {
3412 target_mac->ppe_idx = 0;
3413 gdm_config = soc->reg_map->gdma_to_ppe[0];
3414 }
3415 mtk_gdm_config(eth, target_mac->id, gdm_config);
3416 }
3417 /* Reset and enable PSE */
3418 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
3419 mtk_w32(eth, 0, MTK_RST_GL);
MarkLee5ac9eda2019-11-13 10:38:43 +08003420
John Crispin80673022016-06-29 13:38:11 +02003421 napi_enable(&eth->tx_napi);
John Crispin656e7052016-03-08 11:29:55 +01003422 napi_enable(&eth->rx_napi);
John Crispin5cce0322017-06-19 15:37:05 +02003423 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01003424 mtk_rx_irq_enable(eth, soc->rx.irq_done_mask);
Elena Reshetovac6d4e632017-10-20 10:23:36 +03003425 refcount_set(&eth->dma_refcnt, 1);
Elad Yifeedee4dd12024-06-07 11:21:50 +03003426 } else {
Elena Reshetovac6d4e632017-10-20 10:23:36 +03003427 refcount_inc(&eth->dma_refcnt);
Elad Yifeedee4dd12024-06-07 11:21:50 +03003428 }
John Crispin656e7052016-03-08 11:29:55 +01003429
René van Dorstb8fc9f32019-08-25 19:43:39 +02003430 phylink_start(mac->phylink);
Felix Fietkauf63959c2022-11-16 09:07:32 +01003431 netif_tx_start_all_queues(dev);
3432
Lorenzo Bianconia008e2a2023-07-25 01:52:02 +01003433 if (mtk_is_netsys_v2_or_greater(eth))
Felix Fietkauc6d96df2023-04-26 19:21:53 +02003434 return 0;
3435
3436 if (mtk_uses_dsa(dev) && !eth->prog) {
3437 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) {
3438 struct metadata_dst *md_dst = eth->dsa_meta[i];
3439
3440 if (md_dst)
3441 continue;
3442
3443 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX,
3444 GFP_KERNEL);
3445 if (!md_dst)
3446 return -ENOMEM;
3447
3448 md_dst->u.port_info.port_id = i;
3449 eth->dsa_meta[i] = md_dst;
3450 }
3451 } else {
Arınç ÜNAL04910d82023-05-22 13:57:43 +03003452 /* Hardware DSA untagging and VLAN RX offloading need to be
3453 * disabled if at least one MAC does not use DSA.
Felix Fietkauc6d96df2023-04-26 19:21:53 +02003454 */
3455 u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
3456
3457 val &= ~MTK_CDMP_STAG_EN;
3458 mtk_w32(eth, val, MTK_CDMP_IG_CTRL);
3459
Felix Fietkauc6d96df2023-04-26 19:21:53 +02003460 mtk_w32(eth, 0, MTK_CDMP_EG_CTRL);
3461 }
3462
John Crispin656e7052016-03-08 11:29:55 +01003463 return 0;
3464}
3465
3466static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
3467{
John Crispin656e7052016-03-08 11:29:55 +01003468 u32 val;
3469 int i;
3470
3471 /* stop the dma engine */
Sean Wange3e96522016-08-11 17:51:00 +08003472 spin_lock_bh(&eth->page_lock);
John Crispin656e7052016-03-08 11:29:55 +01003473 val = mtk_r32(eth, glo_cfg);
3474 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
3475 glo_cfg);
Sean Wange3e96522016-08-11 17:51:00 +08003476 spin_unlock_bh(&eth->page_lock);
John Crispin656e7052016-03-08 11:29:55 +01003477
3478 /* wait for dma stop */
3479 for (i = 0; i < 10; i++) {
3480 val = mtk_r32(eth, glo_cfg);
3481 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
3482 msleep(20);
3483 continue;
3484 }
3485 break;
3486 }
3487}
3488
3489static int mtk_stop(struct net_device *dev)
3490{
3491 struct mtk_mac *mac = netdev_priv(dev);
3492 struct mtk_eth *eth = mac->hw;
Lorenzo Bianconi4ff1a3f2022-09-20 12:11:17 +02003493 int i;
John Crispin656e7052016-03-08 11:29:55 +01003494
René van Dorstb8fc9f32019-08-25 19:43:39 +02003495 phylink_stop(mac->phylink);
3496
John Crispin656e7052016-03-08 11:29:55 +01003497 netif_tx_disable(dev);
René van Dorstb8fc9f32019-08-25 19:43:39 +02003498
3499 phylink_disconnect_phy(mac->phylink);
John Crispin656e7052016-03-08 11:29:55 +01003500
3501 /* only shutdown DMA if this is the last user */
Elena Reshetovac6d4e632017-10-20 10:23:36 +03003502 if (!refcount_dec_and_test(&eth->dma_refcnt))
John Crispin656e7052016-03-08 11:29:55 +01003503 return 0;
3504
Elad Yifeedee4dd12024-06-07 11:21:50 +03003505 for (i = 0; i < MTK_MAX_DEVS; i++)
3506 mtk_gdm_config(eth, i, MTK_GDMA_DROP_ALL);
MarkLee8d66a812019-11-13 10:38:44 +08003507
John Crispin5cce0322017-06-19 15:37:05 +02003508 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01003509 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
John Crispin80673022016-06-29 13:38:11 +02003510 napi_disable(&eth->tx_napi);
John Crispin656e7052016-03-08 11:29:55 +01003511 napi_disable(&eth->rx_napi);
3512
Felix Fietkaue9229ff2021-04-22 22:21:02 -07003513 cancel_work_sync(&eth->rx_dim.work);
3514 cancel_work_sync(&eth->tx_dim.work);
3515
Stefan Roese296c9122019-08-16 15:23:25 +02003516 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003517 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg);
3518 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg);
John Crispin656e7052016-03-08 11:29:55 +01003519
3520 mtk_dma_free(eth);
3521
Lorenzo Bianconi4ff1a3f2022-09-20 12:11:17 +02003522 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
3523 mtk_ppe_stop(eth->ppe[i]);
Felix Fietkauba37b7c2021-03-24 02:30:53 +01003524
John Crispin656e7052016-03-08 11:29:55 +01003525 return 0;
3526}
3527
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02003528static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog,
3529 struct netlink_ext_ack *extack)
3530{
3531 struct mtk_mac *mac = netdev_priv(dev);
3532 struct mtk_eth *eth = mac->hw;
3533 struct bpf_prog *old_prog;
3534 bool need_update;
3535
3536 if (eth->hwlro) {
3537 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO");
3538 return -EOPNOTSUPP;
3539 }
3540
3541 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) {
3542 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP");
3543 return -EOPNOTSUPP;
3544 }
3545
3546 need_update = !!eth->prog != !!prog;
3547 if (netif_running(dev) && need_update)
3548 mtk_stop(dev);
3549
3550 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held());
3551 if (old_prog)
3552 bpf_prog_put(old_prog);
3553
3554 if (netif_running(dev) && need_update)
3555 return mtk_open(dev);
3556
3557 return 0;
3558}
3559
3560static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp)
3561{
3562 switch (xdp->command) {
3563 case XDP_SETUP_PROG:
3564 return mtk_xdp_setup(dev, xdp->prog, xdp->extack);
3565 default:
3566 return -EINVAL;
3567 }
3568}
3569
Sean Wang2a8307a2016-09-14 23:13:20 +08003570static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
3571{
3572 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
3573 reset_bits,
3574 reset_bits);
3575
3576 usleep_range(1000, 1100);
3577 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
3578 reset_bits,
3579 ~reset_bits);
3580 mdelay(10);
3581}
3582
Sean Wang2ec50f52017-07-31 18:05:09 +08003583static void mtk_clk_disable(struct mtk_eth *eth)
3584{
3585 int clk;
3586
3587 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)
3588 clk_disable_unprepare(eth->clks[clk]);
3589}
3590
3591static int mtk_clk_enable(struct mtk_eth *eth)
3592{
3593 int clk, ret;
3594
3595 for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
3596 ret = clk_prepare_enable(eth->clks[clk]);
3597 if (ret)
3598 goto err_disable_clks;
3599 }
3600
3601 return 0;
3602
3603err_disable_clks:
3604 while (--clk >= 0)
3605 clk_disable_unprepare(eth->clks[clk]);
3606
3607 return ret;
3608}
3609
Felix Fietkaue9229ff2021-04-22 22:21:02 -07003610static void mtk_dim_rx(struct work_struct *work)
3611{
3612 struct dim *dim = container_of(work, struct dim, work);
3613 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim);
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003614 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
Felix Fietkaue9229ff2021-04-22 22:21:02 -07003615 struct dim_cq_moder cur_profile;
3616 u32 val, cur;
3617
3618 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode,
3619 dim->profile_ix);
3620 spin_lock_bh(&eth->dim_lock);
3621
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003622 val = mtk_r32(eth, reg_map->pdma.delay_irq);
Felix Fietkaue9229ff2021-04-22 22:21:02 -07003623 val &= MTK_PDMA_DELAY_TX_MASK;
3624 val |= MTK_PDMA_DELAY_RX_EN;
3625
3626 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);
3627 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT;
3628
3629 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
3630 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT;
3631
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003632 mtk_w32(eth, val, reg_map->pdma.delay_irq);
Stefan Roese430bfe02021-05-20 10:43:18 +02003633 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003634 mtk_w32(eth, val, reg_map->qdma.delay_irq);
Felix Fietkaue9229ff2021-04-22 22:21:02 -07003635
3636 spin_unlock_bh(&eth->dim_lock);
3637
3638 dim->state = DIM_START_MEASURE;
3639}
3640
3641static void mtk_dim_tx(struct work_struct *work)
3642{
3643 struct dim *dim = container_of(work, struct dim, work);
3644 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim);
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003645 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
Felix Fietkaue9229ff2021-04-22 22:21:02 -07003646 struct dim_cq_moder cur_profile;
3647 u32 val, cur;
3648
3649 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode,
3650 dim->profile_ix);
3651 spin_lock_bh(&eth->dim_lock);
3652
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003653 val = mtk_r32(eth, reg_map->pdma.delay_irq);
Felix Fietkaue9229ff2021-04-22 22:21:02 -07003654 val &= MTK_PDMA_DELAY_RX_MASK;
3655 val |= MTK_PDMA_DELAY_TX_EN;
3656
3657 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);
3658 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT;
3659
3660 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
3661 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT;
3662
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003663 mtk_w32(eth, val, reg_map->pdma.delay_irq);
Stefan Roese430bfe02021-05-20 10:43:18 +02003664 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003665 mtk_w32(eth, val, reg_map->qdma.delay_irq);
Felix Fietkaue9229ff2021-04-22 22:21:02 -07003666
3667 spin_unlock_bh(&eth->dim_lock);
3668
3669 dim->state = DIM_START_MEASURE;
3670}
3671
Lorenzo Bianconib677d6c2022-11-17 00:35:04 +01003672static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val)
3673{
3674 struct mtk_eth *eth = mac->hw;
3675 u32 mcr_cur, mcr_new;
3676
3677 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3678 return;
3679
3680 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
3681 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK;
3682
3683 if (val <= 1518)
3684 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518);
3685 else if (val <= 1536)
3686 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536);
3687 else if (val <= 1552)
3688 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552);
3689 else
3690 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048);
3691
3692 if (mcr_new != mcr_cur)
3693 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
3694}
3695
Lorenzo Bianconibccd19b2023-01-14 18:01:28 +01003696static void mtk_hw_reset(struct mtk_eth *eth)
3697{
3698 u32 val;
3699
Daniel Golle88c1e6e2023-08-22 17:32:03 +01003700 if (mtk_is_netsys_v2_or_greater(eth))
Lorenzo Bianconibccd19b2023-01-14 18:01:28 +01003701 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
Daniel Golle88c1e6e2023-08-22 17:32:03 +01003702
3703 if (mtk_is_netsys_v3_or_greater(eth)) {
3704 val = RSTCTRL_PPE0_V3;
3705
3706 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3707 val |= RSTCTRL_PPE1_V3;
3708
3709 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
3710 val |= RSTCTRL_PPE2;
3711
3712 val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
3713 } else if (mtk_is_netsys_v2_or_greater(eth)) {
Lorenzo Bianconibccd19b2023-01-14 18:01:28 +01003714 val = RSTCTRL_PPE0_V2;
Daniel Golle88c1e6e2023-08-22 17:32:03 +01003715
3716 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3717 val |= RSTCTRL_PPE1;
Lorenzo Bianconibccd19b2023-01-14 18:01:28 +01003718 } else {
3719 val = RSTCTRL_PPE0;
3720 }
3721
Lorenzo Bianconibccd19b2023-01-14 18:01:28 +01003722 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
3723
Daniel Golle88c1e6e2023-08-22 17:32:03 +01003724 if (mtk_is_netsys_v3_or_greater(eth))
3725 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
3726 0x6f8ff);
3727 else if (mtk_is_netsys_v2_or_greater(eth))
Lorenzo Bianconibccd19b2023-01-14 18:01:28 +01003728 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
3729 0x3ffffff);
3730}
3731
Lorenzo Bianconia9724b92023-01-14 18:01:29 +01003732static u32 mtk_hw_reset_read(struct mtk_eth *eth)
3733{
3734 u32 val;
3735
3736 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val);
3737 return val;
3738}
3739
3740static void mtk_hw_warm_reset(struct mtk_eth *eth)
3741{
3742 u32 rst_mask, val;
3743
3744 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE,
3745 RSTCTRL_FE);
3746 if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val,
3747 val & RSTCTRL_FE, 1, 1000)) {
3748 dev_err(eth->dev, "warm reset failed\n");
3749 mtk_hw_reset(eth);
3750 return;
3751 }
3752
Daniel Golle88c1e6e2023-08-22 17:32:03 +01003753 if (mtk_is_netsys_v3_or_greater(eth)) {
3754 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3;
3755 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3756 rst_mask |= RSTCTRL_PPE1_V3;
3757 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
3758 rst_mask |= RSTCTRL_PPE2;
Lorenzo Bianconia9724b92023-01-14 18:01:29 +01003759
Daniel Golle88c1e6e2023-08-22 17:32:03 +01003760 rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
3761 } else if (mtk_is_netsys_v2_or_greater(eth)) {
3762 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
3763 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3764 rst_mask |= RSTCTRL_PPE1;
3765 } else {
3766 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
3767 }
Lorenzo Bianconia9724b92023-01-14 18:01:29 +01003768
3769 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask);
3770
3771 udelay(1);
3772 val = mtk_hw_reset_read(eth);
3773 if (!(val & rst_mask))
3774 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n",
3775 val, rst_mask);
3776
3777 rst_mask |= RSTCTRL_FE;
3778 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask);
3779
3780 udelay(1);
3781 val = mtk_hw_reset_read(eth);
3782 if (val & rst_mask)
3783 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n",
3784 val, rst_mask);
3785}
3786
Lorenzo Bianconi93b25912023-01-14 18:01:31 +01003787static bool mtk_hw_check_dma_hang(struct mtk_eth *eth)
3788{
3789 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3790 bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx;
3791 bool oq_hang, cdm1_busy, adma_busy;
3792 bool wtx_busy, cdm_full, oq_free;
3793 u32 wdidx, val, gdm1_fc, gdm2_fc;
3794 bool qfsm_hang, qfwd_hang;
3795 bool ret = false;
3796
3797 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3798 return false;
3799
3800 /* WDMA sanity checks */
3801 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc);
3802
3803 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204);
3804 wtx_busy = FIELD_GET(MTK_TX_DMA_BUSY, val);
3805
3806 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230);
3807 cdm_full = !FIELD_GET(MTK_CDM_TXFIFO_RDY, val);
3808
3809 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) &&
3810 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) &&
3811 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16)));
3812
3813 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) {
3814 if (++eth->reset.wdma_hang_count > 2) {
3815 eth->reset.wdma_hang_count = 0;
3816 ret = true;
3817 }
3818 goto out;
3819 }
3820
3821 /* QDMA sanity checks */
3822 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234);
3823 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308);
3824
3825 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0;
3826 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0;
3827 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1;
3828 gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1;
3829 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24);
3830 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64);
3831
3832 if (qfsm_hang && qfwd_hang &&
3833 ((gdm1_tx && gmac1_tx && gdm1_fc < 1) ||
3834 (gdm2_tx && gmac2_tx && gdm2_fc < 1))) {
3835 if (++eth->reset.qdma_hang_count > 2) {
3836 eth->reset.qdma_hang_count = 0;
3837 ret = true;
3838 }
3839 goto out;
3840 }
3841
3842 /* ADMA sanity checks */
3843 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0));
3844 cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16));
3845 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) &&
3846 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6));
3847
3848 if (oq_hang && cdm1_busy && adma_busy) {
3849 if (++eth->reset.adma_hang_count > 2) {
3850 eth->reset.adma_hang_count = 0;
3851 ret = true;
3852 }
3853 goto out;
3854 }
3855
3856 eth->reset.wdma_hang_count = 0;
3857 eth->reset.qdma_hang_count = 0;
3858 eth->reset.adma_hang_count = 0;
3859out:
3860 eth->reset.wdidx = wdidx;
3861
3862 return ret;
3863}
3864
3865static void mtk_hw_reset_monitor_work(struct work_struct *work)
3866{
3867 struct delayed_work *del_work = to_delayed_work(work);
3868 struct mtk_eth *eth = container_of(del_work, struct mtk_eth,
3869 reset.monitor_work);
3870
3871 if (test_bit(MTK_RESETTING, &eth->state))
3872 goto out;
3873
3874 /* DMA stuck checks */
3875 if (mtk_hw_check_dma_hang(eth))
3876 schedule_work(&eth->pending_work);
3877
3878out:
3879 schedule_delayed_work(&eth->reset.monitor_work,
3880 MTK_DMA_MONITOR_TIMEOUT);
3881}
3882
Lorenzo Bianconia9724b92023-01-14 18:01:29 +01003883static int mtk_hw_init(struct mtk_eth *eth, bool reset)
John Crispin656e7052016-03-08 11:29:55 +01003884{
Felix Fietkaud776a572022-04-05 21:57:43 +02003885 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
3886 ETHSYS_DMA_AG_MAP_PPE;
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003887 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
Sean Wang2ec50f52017-07-31 18:05:09 +08003888 int i, val, ret;
Sean Wang9ea4d312016-09-14 23:13:19 +08003889
Lorenzo Bianconi06127502023-01-14 18:01:30 +01003890 if (!reset && test_and_set_bit(MTK_HW_INIT, &eth->state))
Sean Wang9ea4d312016-09-14 23:13:19 +08003891 return 0;
Sean Wang85574db2016-09-14 23:13:15 +08003892
Lorenzo Bianconi06127502023-01-14 18:01:30 +01003893 if (!reset) {
3894 pm_runtime_enable(eth->dev);
3895 pm_runtime_get_sync(eth->dev);
Sean Wang26a2ad82016-09-14 23:13:18 +08003896
Lorenzo Bianconi06127502023-01-14 18:01:30 +01003897 ret = mtk_clk_enable(eth);
3898 if (ret)
3899 goto err_disable_pm;
3900 }
Sean Wang2ec50f52017-07-31 18:05:09 +08003901
Felix Fietkaud776a572022-04-05 21:57:43 +02003902 if (eth->ethsys)
3903 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask,
3904 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask);
3905
Stefan Roese296c9122019-08-16 15:23:25 +02003906 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
3907 ret = device_reset(eth->dev);
3908 if (ret) {
3909 dev_err(eth->dev, "MAC reset failed!\n");
3910 goto err_disable_pm;
3911 }
3912
Stefan Roese430bfe02021-05-20 10:43:18 +02003913 /* set interrupt delays based on current Net DIM sample */
3914 mtk_dim_rx(&eth->rx_dim.work);
3915 mtk_dim_tx(&eth->tx_dim.work);
3916
Stefan Roese296c9122019-08-16 15:23:25 +02003917 /* disable delay and normal interrupt */
3918 mtk_tx_irq_disable(eth, ~0);
3919 mtk_rx_irq_disable(eth, ~0);
3920
3921 return 0;
3922 }
3923
Lorenzo Bianconia9724b92023-01-14 18:01:29 +01003924 msleep(100);
3925
3926 if (reset)
3927 mtk_hw_warm_reset(eth);
3928 else
3929 mtk_hw_reset(eth);
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02003930
Daniel Golle5e69ff82024-05-08 11:43:56 +01003931 if (mtk_is_netsys_v3_or_greater(eth)) {
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02003932 /* Set FE to PDMAv2 if necessary */
3933 val = mtk_r32(eth, MTK_FE_GLO_MISC);
3934 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
3935 }
John Crispin656e7052016-03-08 11:29:55 +01003936
Sean Wang243dc5f2017-12-20 17:47:06 +08003937 if (eth->pctl) {
3938 /* Set GE2 driving and slew rate */
3939 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
John Crispin656e7052016-03-08 11:29:55 +01003940
Sean Wang243dc5f2017-12-20 17:47:06 +08003941 /* set GE2 TDSEL */
3942 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
John Crispin656e7052016-03-08 11:29:55 +01003943
Sean Wang243dc5f2017-12-20 17:47:06 +08003944 /* set GE2 TUNE */
3945 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
3946 }
John Crispin656e7052016-03-08 11:29:55 +01003947
Sean Wang7352e252017-12-18 17:00:17 +08003948 /* Set linkdown as the default for each GMAC. Its own MCR would be set
René van Dorstb8fc9f32019-08-25 19:43:39 +02003949 * up with the more appropriate value when mtk_mac_config call is being
3950 * invoked.
Sean Wang7352e252017-12-18 17:00:17 +08003951 */
Lorenzo Bianconie05fd622023-07-25 01:52:44 +01003952 for (i = 0; i < MTK_MAX_DEVS; i++) {
Lorenzo Bianconib677d6c2022-11-17 00:35:04 +01003953 struct net_device *dev = eth->netdev[i];
3954
Lorenzo Bianconie05fd622023-07-25 01:52:44 +01003955 if (!dev)
3956 continue;
Lorenzo Bianconib677d6c2022-11-17 00:35:04 +01003957
Lorenzo Bianconie05fd622023-07-25 01:52:44 +01003958 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
3959 mtk_set_mcr_max_rx(netdev_priv(dev),
3960 dev->mtu + MTK_RX_ETH_HLEN);
Lorenzo Bianconib677d6c2022-11-17 00:35:04 +01003961 }
John Crispin656e7052016-03-08 11:29:55 +01003962
Sean Wang87e3df42017-04-07 16:45:07 +08003963 /* Indicates CDM to parse the MTK special tag from CPU
3964 * which also is working out for untag packets.
3965 */
3966 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
3967 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
Lorenzo Bianconia008e2a2023-07-25 01:52:02 +01003968 if (mtk_is_netsys_v1(eth)) {
Felix Fietkau2d7605a2022-11-14 13:42:14 +01003969 val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
3970 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
Sean Wang87e3df42017-04-07 16:45:07 +08003971
Felix Fietkauc6d96df2023-04-26 19:21:53 +02003972 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
3973 }
John Crispin656e7052016-03-08 11:29:55 +01003974
Felix Fietkaue9229ff2021-04-22 22:21:02 -07003975 /* set interrupt delays based on current Net DIM sample */
3976 mtk_dim_rx(&eth->rx_dim.work);
3977 mtk_dim_tx(&eth->tx_dim.work);
John Crispin671d41e2017-06-19 15:37:04 +02003978
John Crispin656e7052016-03-08 11:29:55 +01003979 /* disable delay and normal interrupt */
John Crispin5cce0322017-06-19 15:37:05 +02003980 mtk_tx_irq_disable(eth, ~0);
3981 mtk_rx_irq_disable(eth, ~0);
John Crispin656e7052016-03-08 11:29:55 +01003982
3983 /* FE int grouping */
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003984 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01003985 mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4);
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02003986 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01003987 mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4);
John Crispin80673022016-06-29 13:38:11 +02003988 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
John Crispin656e7052016-03-08 11:29:55 +01003989
Lorenzo Bianconi1953f132023-07-25 01:52:59 +01003990 if (mtk_is_netsys_v3_or_greater(eth)) {
3991 /* PSE should not drop port1, port8 and port9 packets */
3992 mtk_w32(eth, 0x00000302, PSE_DROP_CFG);
3993
3994 /* GDM and CDM Threshold */
3995 mtk_w32(eth, 0x00000707, MTK_CDMW0_THRES);
3996 mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES);
3997
3998 /* Disable GDM1 RX CRC stripping */
3999 mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0));
4000
4001 /* PSE GDM3 MIB counter has incorrect hw default values,
4002 * so the driver ought to read clear the values beforehand
4003 * in case ethtool retrieve wrong mib values.
4004 */
4005 for (i = 0; i < 0x80; i += 0x4)
4006 mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i);
4007 } else if (!mtk_is_netsys_v1(eth)) {
Felix Fietkauf4b2fa22022-11-16 09:07:30 +01004008 /* PSE should not drop port8 and port9 packets from WDMA Tx */
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02004009 mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
4010
Felix Fietkauf4b2fa22022-11-16 09:07:30 +01004011 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */
4012 mtk_w32(eth, 0x00000300, PSE_PPE0_DROP);
4013
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02004014 /* PSE Free Queue Flow Control */
4015 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2);
4016
4017 /* PSE config input queue threshold */
4018 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1));
4019 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2));
4020 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3));
4021 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4));
4022 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5));
4023 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6));
4024 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7));
4025 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8));
4026
4027 /* PSE config output queue threshold */
4028 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1));
4029 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2));
4030 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3));
4031 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4));
4032 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5));
4033 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6));
4034 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7));
4035 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8));
4036
4037 /* GDM and CDM Threshold */
4038 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES);
4039 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES);
4040 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES);
4041 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES);
4042 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES);
4043 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES);
4044 }
4045
John Crispin656e7052016-03-08 11:29:55 +01004046 return 0;
Sean Wang2ec50f52017-07-31 18:05:09 +08004047
4048err_disable_pm:
Lorenzo Bianconi06127502023-01-14 18:01:30 +01004049 if (!reset) {
4050 pm_runtime_put_sync(eth->dev);
4051 pm_runtime_disable(eth->dev);
4052 }
Sean Wang2ec50f52017-07-31 18:05:09 +08004053
4054 return ret;
John Crispin656e7052016-03-08 11:29:55 +01004055}
4056
Sean Wangbf253fb2016-09-14 23:13:16 +08004057static int mtk_hw_deinit(struct mtk_eth *eth)
4058{
Sean Wang9ea4d312016-09-14 23:13:19 +08004059 if (!test_and_clear_bit(MTK_HW_INIT, &eth->state))
4060 return 0;
4061
Sean Wang2ec50f52017-07-31 18:05:09 +08004062 mtk_clk_disable(eth);
Sean Wangbf253fb2016-09-14 23:13:16 +08004063
Sean Wang26a2ad82016-09-14 23:13:18 +08004064 pm_runtime_put_sync(eth->dev);
4065 pm_runtime_disable(eth->dev);
4066
Sean Wangbf253fb2016-09-14 23:13:16 +08004067 return 0;
4068}
4069
John Crispin656e7052016-03-08 11:29:55 +01004070static void mtk_uninit(struct net_device *dev)
4071{
4072 struct mtk_mac *mac = netdev_priv(dev);
4073 struct mtk_eth *eth = mac->hw;
4074
René van Dorstb8fc9f32019-08-25 19:43:39 +02004075 phylink_disconnect_phy(mac->phylink);
John Crispin5cce0322017-06-19 15:37:05 +02004076 mtk_tx_irq_disable(eth, ~0);
4077 mtk_rx_irq_disable(eth, ~0);
John Crispin656e7052016-03-08 11:29:55 +01004078}
4079
DENG Qingfang4fd59792021-01-25 12:20:46 +08004080static int mtk_change_mtu(struct net_device *dev, int new_mtu)
4081{
4082 int length = new_mtu + MTK_RX_ETH_HLEN;
4083 struct mtk_mac *mac = netdev_priv(dev);
4084 struct mtk_eth *eth = mac->hw;
DENG Qingfang4fd59792021-01-25 12:20:46 +08004085
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02004086 if (rcu_access_pointer(eth->prog) &&
4087 length > MTK_PP_MAX_BUF_SIZE) {
4088 netdev_err(dev, "Invalid MTU for XDP mode\n");
4089 return -EINVAL;
4090 }
4091
Lorenzo Bianconib677d6c2022-11-17 00:35:04 +01004092 mtk_set_mcr_max_rx(mac, length);
Eric Dumazet1eb2cde2024-05-06 10:28:12 +00004093 WRITE_ONCE(dev->mtu, new_mtu);
DENG Qingfang4fd59792021-01-25 12:20:46 +08004094
4095 return 0;
4096}
4097
John Crispin656e7052016-03-08 11:29:55 +01004098static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4099{
René van Dorstb8fc9f32019-08-25 19:43:39 +02004100 struct mtk_mac *mac = netdev_priv(dev);
4101
John Crispin656e7052016-03-08 11:29:55 +01004102 switch (cmd) {
4103 case SIOCGMIIPHY:
4104 case SIOCGMIIREG:
4105 case SIOCSMIIREG:
René van Dorstb8fc9f32019-08-25 19:43:39 +02004106 return phylink_mii_ioctl(mac->phylink, ifr, cmd);
John Crispin656e7052016-03-08 11:29:55 +01004107 default:
4108 break;
4109 }
4110
4111 return -EOPNOTSUPP;
4112}
4113
Lorenzo Bianconi06127502023-01-14 18:01:30 +01004114static void mtk_prepare_for_reset(struct mtk_eth *eth)
4115{
4116 u32 val;
4117 int i;
4118
Daniel Golle88c1e6e2023-08-22 17:32:03 +01004119 /* set FE PPE ports link down */
4120 for (i = MTK_GMAC1_ID;
4121 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID);
4122 i += 2) {
4123 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT);
4124 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
4125 val |= MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT);
4126 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
4127 val |= MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT);
4128 mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
4129 }
Lorenzo Bianconi06127502023-01-14 18:01:30 +01004130
4131 /* adjust PPE configurations to prepare for reset */
4132 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
4133 mtk_ppe_prepare_reset(eth->ppe[i]);
4134
4135 /* disable NETSYS interrupts */
4136 mtk_w32(eth, 0, MTK_FE_INT_ENABLE);
4137
4138 /* force link down GMAC */
4139 for (i = 0; i < 2; i++) {
4140 val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK;
4141 mtk_w32(eth, val, MTK_MAC_MCR(i));
4142 }
4143}
4144
John Crispin656e7052016-03-08 11:29:55 +01004145static void mtk_pending_work(struct work_struct *work)
4146{
John Crispin7c78b4a2016-04-08 00:54:10 +02004147 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
John Crispine7d425d2016-04-08 00:54:09 +02004148 unsigned long restart = 0;
Lorenzo Bianconi06127502023-01-14 18:01:30 +01004149 u32 val;
4150 int i;
John Crispin656e7052016-03-08 11:29:55 +01004151
4152 rtnl_lock();
Lorenzo Bianconiec8cd132022-11-17 00:58:46 +01004153 set_bit(MTK_RESETTING, &eth->state);
Sean Wangdce6fa42016-09-14 23:13:21 +08004154
Lorenzo Bianconi06127502023-01-14 18:01:30 +01004155 mtk_prepare_for_reset(eth);
Lorenzo Bianconi08a764a2023-01-14 18:01:32 +01004156 mtk_wed_fe_reset();
4157 /* Run again reset preliminary configuration in order to avoid any
4158 * possible race during FE reset since it can run releasing RTNL lock.
4159 */
4160 mtk_prepare_for_reset(eth);
Lorenzo Bianconi06127502023-01-14 18:01:30 +01004161
John Crispine7d425d2016-04-08 00:54:09 +02004162 /* stop all devices to make sure that dma is properly shut down */
Lorenzo Bianconie05fd622023-07-25 01:52:44 +01004163 for (i = 0; i < MTK_MAX_DEVS; i++) {
Lorenzo Bianconi06127502023-01-14 18:01:30 +01004164 if (!eth->netdev[i] || !netif_running(eth->netdev[i]))
John Crispine7d425d2016-04-08 00:54:09 +02004165 continue;
Lorenzo Bianconi06127502023-01-14 18:01:30 +01004166
John Crispine7d425d2016-04-08 00:54:09 +02004167 mtk_stop(eth->netdev[i]);
4168 __set_bit(i, &restart);
4169 }
4170
Lorenzo Bianconi06127502023-01-14 18:01:30 +01004171 usleep_range(15000, 16000);
Sean Wang9ea4d312016-09-14 23:13:19 +08004172
4173 if (eth->dev->pins)
4174 pinctrl_select_state(eth->dev->pins->p,
4175 eth->dev->pins->default_state);
Lorenzo Bianconia9724b92023-01-14 18:01:29 +01004176 mtk_hw_init(eth, true);
Sean Wang9ea4d312016-09-14 23:13:19 +08004177
John Crispine7d425d2016-04-08 00:54:09 +02004178 /* restart DMA and enable IRQs */
Lorenzo Bianconie05fd622023-07-25 01:52:44 +01004179 for (i = 0; i < MTK_MAX_DEVS; i++) {
4180 if (!eth->netdev[i] || !test_bit(i, &restart))
John Crispine7d425d2016-04-08 00:54:09 +02004181 continue;
Lorenzo Bianconi06127502023-01-14 18:01:30 +01004182
4183 if (mtk_open(eth->netdev[i])) {
John Crispine7d425d2016-04-08 00:54:09 +02004184 netif_alert(eth, ifup, eth->netdev[i],
Lorenzo Bianconi06127502023-01-14 18:01:30 +01004185 "Driver up/down cycle failed\n");
John Crispine7d425d2016-04-08 00:54:09 +02004186 dev_close(eth->netdev[i]);
4187 }
John Crispin656e7052016-03-08 11:29:55 +01004188 }
Sean Wangdce6fa42016-09-14 23:13:21 +08004189
Daniel Golle88c1e6e2023-08-22 17:32:03 +01004190 /* set FE PPE ports link up */
4191 for (i = MTK_GMAC1_ID;
4192 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID);
4193 i += 2) {
4194 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT);
4195 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
4196 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT);
4197 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
4198 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT);
4199
4200 mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
4201 }
Sean Wangdce6fa42016-09-14 23:13:21 +08004202
Lorenzo Bianconiec8cd132022-11-17 00:58:46 +01004203 clear_bit(MTK_RESETTING, &eth->state);
Sean Wangdce6fa42016-09-14 23:13:21 +08004204
Lorenzo Bianconi08a764a2023-01-14 18:01:32 +01004205 mtk_wed_fe_reset_complete();
4206
John Crispin656e7052016-03-08 11:29:55 +01004207 rtnl_unlock();
4208}
4209
Sean Wang8a8a9e82016-09-14 23:13:17 +08004210static int mtk_free_dev(struct mtk_eth *eth)
John Crispin656e7052016-03-08 11:29:55 +01004211{
4212 int i;
4213
Lorenzo Bianconie05fd622023-07-25 01:52:44 +01004214 for (i = 0; i < MTK_MAX_DEVS; i++) {
John Crispin656e7052016-03-08 11:29:55 +01004215 if (!eth->netdev[i])
4216 continue;
John Crispin656e7052016-03-08 11:29:55 +01004217 free_netdev(eth->netdev[i]);
John Crispin656e7052016-03-08 11:29:55 +01004218 }
Sean Wang8a8a9e82016-09-14 23:13:17 +08004219
Felix Fietkau2d7605a2022-11-14 13:42:14 +01004220 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) {
4221 if (!eth->dsa_meta[i])
4222 break;
4223 metadata_dst_free(eth->dsa_meta[i]);
4224 }
4225
Sean Wang8a8a9e82016-09-14 23:13:17 +08004226 return 0;
4227}
4228
4229static int mtk_unreg_dev(struct mtk_eth *eth)
4230{
4231 int i;
4232
Lorenzo Bianconie05fd622023-07-25 01:52:44 +01004233 for (i = 0; i < MTK_MAX_DEVS; i++) {
Felix Fietkauf63959c2022-11-16 09:07:32 +01004234 struct mtk_mac *mac;
Sean Wang8a8a9e82016-09-14 23:13:17 +08004235 if (!eth->netdev[i])
4236 continue;
Felix Fietkauf63959c2022-11-16 09:07:32 +01004237 mac = netdev_priv(eth->netdev[i]);
4238 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
4239 unregister_netdevice_notifier(&mac->device_notifier);
Sean Wang8a8a9e82016-09-14 23:13:17 +08004240 unregister_netdev(eth->netdev[i]);
4241 }
4242
4243 return 0;
4244}
4245
Daniel Golle2a3ec7a2023-03-19 12:58:02 +00004246static void mtk_sgmii_destroy(struct mtk_eth *eth)
4247{
4248 int i;
4249
4250 for (i = 0; i < MTK_MAX_DEVS; i++)
4251 mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]);
4252}
4253
Sean Wang8a8a9e82016-09-14 23:13:17 +08004254static int mtk_cleanup(struct mtk_eth *eth)
4255{
Daniel Golle2a3ec7a2023-03-19 12:58:02 +00004256 mtk_sgmii_destroy(eth);
Sean Wang8a8a9e82016-09-14 23:13:17 +08004257 mtk_unreg_dev(eth);
4258 mtk_free_dev(eth);
John Crispin7c78b4a2016-04-08 00:54:10 +02004259 cancel_work_sync(&eth->pending_work);
Lorenzo Bianconi93b25912023-01-14 18:01:31 +01004260 cancel_delayed_work_sync(&eth->reset.monitor_work);
John Crispin656e7052016-03-08 11:29:55 +01004261
4262 return 0;
4263}
4264
Baoyou Xie3a82e782016-09-30 15:48:50 +08004265static int mtk_get_link_ksettings(struct net_device *ndev,
4266 struct ethtool_link_ksettings *cmd)
John Crispin656e7052016-03-08 11:29:55 +01004267{
Sean Wang3e60b742016-09-22 16:42:03 +08004268 struct mtk_mac *mac = netdev_priv(ndev);
John Crispin656e7052016-03-08 11:29:55 +01004269
Sean Wangdce6fa42016-09-14 23:13:21 +08004270 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4271 return -EBUSY;
4272
René van Dorstb8fc9f32019-08-25 19:43:39 +02004273 return phylink_ethtool_ksettings_get(mac->phylink, cmd);
John Crispin656e7052016-03-08 11:29:55 +01004274}
4275
Baoyou Xie3a82e782016-09-30 15:48:50 +08004276static int mtk_set_link_ksettings(struct net_device *ndev,
4277 const struct ethtool_link_ksettings *cmd)
John Crispin656e7052016-03-08 11:29:55 +01004278{
Sean Wang3e60b742016-09-22 16:42:03 +08004279 struct mtk_mac *mac = netdev_priv(ndev);
John Crispin656e7052016-03-08 11:29:55 +01004280
Sean Wang3e60b742016-09-22 16:42:03 +08004281 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4282 return -EBUSY;
John Crispin656e7052016-03-08 11:29:55 +01004283
René van Dorstb8fc9f32019-08-25 19:43:39 +02004284 return phylink_ethtool_ksettings_set(mac->phylink, cmd);
John Crispin656e7052016-03-08 11:29:55 +01004285}
4286
4287static void mtk_get_drvinfo(struct net_device *dev,
4288 struct ethtool_drvinfo *info)
4289{
4290 struct mtk_mac *mac = netdev_priv(dev);
4291
Wolfram Sangf029c782022-08-30 22:14:54 +02004292 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
4293 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
John Crispin656e7052016-03-08 11:29:55 +01004294 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
4295}
4296
4297static u32 mtk_get_msglevel(struct net_device *dev)
4298{
4299 struct mtk_mac *mac = netdev_priv(dev);
4300
4301 return mac->hw->msg_enable;
4302}
4303
4304static void mtk_set_msglevel(struct net_device *dev, u32 value)
4305{
4306 struct mtk_mac *mac = netdev_priv(dev);
4307
4308 mac->hw->msg_enable = value;
4309}
4310
4311static int mtk_nway_reset(struct net_device *dev)
4312{
4313 struct mtk_mac *mac = netdev_priv(dev);
4314
Sean Wangdce6fa42016-09-14 23:13:21 +08004315 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4316 return -EBUSY;
4317
René van Dorstb8fc9f32019-08-25 19:43:39 +02004318 if (!mac->phylink)
4319 return -ENOTSUPP;
John Crispin656e7052016-03-08 11:29:55 +01004320
René van Dorstb8fc9f32019-08-25 19:43:39 +02004321 return phylink_ethtool_nway_reset(mac->phylink);
John Crispin656e7052016-03-08 11:29:55 +01004322}
4323
4324static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4325{
4326 int i;
4327
4328 switch (stringset) {
Lorenzo Bianconi84b9cd32022-07-22 09:19:40 +02004329 case ETH_SS_STATS: {
4330 struct mtk_mac *mac = netdev_priv(dev);
4331
John Crispin656e7052016-03-08 11:29:55 +01004332 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
4333 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
4334 data += ETH_GSTRING_LEN;
4335 }
Lorenzo Bianconi84b9cd32022-07-22 09:19:40 +02004336 if (mtk_page_pool_enabled(mac->hw))
4337 page_pool_ethtool_stats_get_strings(data);
4338 break;
4339 }
4340 default:
John Crispin656e7052016-03-08 11:29:55 +01004341 break;
4342 }
4343}
4344
4345static int mtk_get_sset_count(struct net_device *dev, int sset)
4346{
4347 switch (sset) {
Lorenzo Bianconi84b9cd32022-07-22 09:19:40 +02004348 case ETH_SS_STATS: {
4349 int count = ARRAY_SIZE(mtk_ethtool_stats);
4350 struct mtk_mac *mac = netdev_priv(dev);
4351
4352 if (mtk_page_pool_enabled(mac->hw))
4353 count += page_pool_ethtool_stats_get_count();
4354 return count;
4355 }
John Crispin656e7052016-03-08 11:29:55 +01004356 default:
4357 return -EOPNOTSUPP;
4358 }
4359}
4360
Lorenzo Bianconi84b9cd32022-07-22 09:19:40 +02004361static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data)
4362{
4363 struct page_pool_stats stats = {};
4364 int i;
4365
4366 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) {
4367 struct mtk_rx_ring *ring = &eth->rx_ring[i];
4368
4369 if (!ring->page_pool)
4370 continue;
4371
4372 page_pool_get_stats(ring->page_pool, &stats);
4373 }
4374 page_pool_ethtool_stats_get(data, &stats);
4375}
4376
John Crispin656e7052016-03-08 11:29:55 +01004377static void mtk_get_ethtool_stats(struct net_device *dev,
4378 struct ethtool_stats *stats, u64 *data)
4379{
4380 struct mtk_mac *mac = netdev_priv(dev);
4381 struct mtk_hw_stats *hwstats = mac->hw_stats;
4382 u64 *data_src, *data_dst;
4383 unsigned int start;
4384 int i;
4385
Sean Wangdce6fa42016-09-14 23:13:21 +08004386 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4387 return;
4388
John Crispin656e7052016-03-08 11:29:55 +01004389 if (netif_running(dev) && netif_device_present(dev)) {
Sean Wang8d32e062017-07-04 11:17:36 +08004390 if (spin_trylock_bh(&hwstats->stats_lock)) {
John Crispin656e7052016-03-08 11:29:55 +01004391 mtk_stats_update_mac(mac);
Sean Wang8d32e062017-07-04 11:17:36 +08004392 spin_unlock_bh(&hwstats->stats_lock);
John Crispin656e7052016-03-08 11:29:55 +01004393 }
4394 }
4395
Sean Wang94d308d2016-09-20 11:26:48 +08004396 data_src = (u64 *)hwstats;
4397
John Crispin656e7052016-03-08 11:29:55 +01004398 do {
John Crispin656e7052016-03-08 11:29:55 +01004399 data_dst = data;
Thomas Gleixner068c38a2022-10-26 15:22:14 +02004400 start = u64_stats_fetch_begin(&hwstats->syncp);
John Crispin656e7052016-03-08 11:29:55 +01004401
4402 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
4403 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
Lorenzo Bianconi84b9cd32022-07-22 09:19:40 +02004404 if (mtk_page_pool_enabled(mac->hw))
4405 mtk_ethtool_pp_stats(mac->hw, data_dst);
Thomas Gleixner068c38a2022-10-26 15:22:14 +02004406 } while (u64_stats_fetch_retry(&hwstats->syncp, start));
John Crispin656e7052016-03-08 11:29:55 +01004407}
4408
Nelson Chang7aab7472016-09-17 23:50:56 +08004409static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
4410 u32 *rule_locs)
4411{
4412 int ret = -EOPNOTSUPP;
4413
4414 switch (cmd->cmd) {
4415 case ETHTOOL_GRXRINGS:
Sean Wang9e4f56f2019-06-01 08:16:26 +08004416 if (dev->hw_features & NETIF_F_LRO) {
Nelson Chang7aab7472016-09-17 23:50:56 +08004417 cmd->data = MTK_MAX_RX_RING_NUM;
4418 ret = 0;
4419 }
4420 break;
4421 case ETHTOOL_GRXCLSRLCNT:
Sean Wang9e4f56f2019-06-01 08:16:26 +08004422 if (dev->hw_features & NETIF_F_LRO) {
Nelson Chang7aab7472016-09-17 23:50:56 +08004423 struct mtk_mac *mac = netdev_priv(dev);
4424
4425 cmd->rule_cnt = mac->hwlro_ip_cnt;
4426 ret = 0;
4427 }
4428 break;
4429 case ETHTOOL_GRXCLSRULE:
Sean Wang9e4f56f2019-06-01 08:16:26 +08004430 if (dev->hw_features & NETIF_F_LRO)
Nelson Chang7aab7472016-09-17 23:50:56 +08004431 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
4432 break;
4433 case ETHTOOL_GRXCLSRLALL:
Sean Wang9e4f56f2019-06-01 08:16:26 +08004434 if (dev->hw_features & NETIF_F_LRO)
Nelson Chang7aab7472016-09-17 23:50:56 +08004435 ret = mtk_hwlro_get_fdir_all(dev, cmd,
4436 rule_locs);
4437 break;
4438 default:
4439 break;
4440 }
4441
4442 return ret;
4443}
4444
4445static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
4446{
4447 int ret = -EOPNOTSUPP;
4448
4449 switch (cmd->cmd) {
4450 case ETHTOOL_SRXCLSRLINS:
Sean Wang9e4f56f2019-06-01 08:16:26 +08004451 if (dev->hw_features & NETIF_F_LRO)
Nelson Chang7aab7472016-09-17 23:50:56 +08004452 ret = mtk_hwlro_add_ipaddr(dev, cmd);
4453 break;
4454 case ETHTOOL_SRXCLSRLDEL:
Sean Wang9e4f56f2019-06-01 08:16:26 +08004455 if (dev->hw_features & NETIF_F_LRO)
Nelson Chang7aab7472016-09-17 23:50:56 +08004456 ret = mtk_hwlro_del_ipaddr(dev, cmd);
4457 break;
4458 default:
4459 break;
4460 }
4461
4462 return ret;
4463}
4464
Daniel Golle064fbc42024-07-04 11:14:55 +01004465static void mtk_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause)
4466{
4467 struct mtk_mac *mac = netdev_priv(dev);
4468
4469 phylink_ethtool_get_pauseparam(mac->phylink, pause);
4470}
4471
4472static int mtk_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause)
4473{
4474 struct mtk_mac *mac = netdev_priv(dev);
4475
4476 return phylink_ethtool_set_pauseparam(mac->phylink, pause);
4477}
4478
Felix Fietkauf63959c2022-11-16 09:07:32 +01004479static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb,
4480 struct net_device *sb_dev)
4481{
4482 struct mtk_mac *mac = netdev_priv(dev);
4483 unsigned int queue = 0;
4484
4485 if (netdev_uses_dsa(dev))
4486 queue = skb_get_queue_mapping(skb) + 3;
4487 else
4488 queue = mac->id;
4489
4490 if (queue >= dev->num_tx_queues)
4491 queue = 0;
4492
4493 return queue;
4494}
4495
Julia Lawall6a38cb12016-09-01 00:21:19 +02004496static const struct ethtool_ops mtk_ethtool_ops = {
Sean Wang3e60b742016-09-22 16:42:03 +08004497 .get_link_ksettings = mtk_get_link_ksettings,
4498 .set_link_ksettings = mtk_set_link_ksettings,
John Crispin656e7052016-03-08 11:29:55 +01004499 .get_drvinfo = mtk_get_drvinfo,
4500 .get_msglevel = mtk_get_msglevel,
4501 .set_msglevel = mtk_set_msglevel,
4502 .nway_reset = mtk_nway_reset,
René van Dorstb8fc9f32019-08-25 19:43:39 +02004503 .get_link = ethtool_op_get_link,
John Crispin656e7052016-03-08 11:29:55 +01004504 .get_strings = mtk_get_strings,
4505 .get_sset_count = mtk_get_sset_count,
4506 .get_ethtool_stats = mtk_get_ethtool_stats,
Daniel Golle064fbc42024-07-04 11:14:55 +01004507 .get_pauseparam = mtk_get_pauseparam,
4508 .set_pauseparam = mtk_set_pauseparam,
Nelson Chang7aab7472016-09-17 23:50:56 +08004509 .get_rxnfc = mtk_get_rxnfc,
Daniel Golle064fbc42024-07-04 11:14:55 +01004510 .set_rxnfc = mtk_set_rxnfc,
John Crispin656e7052016-03-08 11:29:55 +01004511};
4512
4513static const struct net_device_ops mtk_netdev_ops = {
John Crispin656e7052016-03-08 11:29:55 +01004514 .ndo_uninit = mtk_uninit,
4515 .ndo_open = mtk_open,
4516 .ndo_stop = mtk_stop,
4517 .ndo_start_xmit = mtk_start_xmit,
4518 .ndo_set_mac_address = mtk_set_mac_address,
4519 .ndo_validate_addr = eth_validate_addr,
Arnd Bergmanna7605372021-07-27 15:45:13 +02004520 .ndo_eth_ioctl = mtk_do_ioctl,
DENG Qingfang4fd59792021-01-25 12:20:46 +08004521 .ndo_change_mtu = mtk_change_mtu,
John Crispin656e7052016-03-08 11:29:55 +01004522 .ndo_tx_timeout = mtk_tx_timeout,
4523 .ndo_get_stats64 = mtk_get_stats64,
Nelson Chang7aab7472016-09-17 23:50:56 +08004524 .ndo_fix_features = mtk_fix_features,
4525 .ndo_set_features = mtk_set_features,
John Crispin656e7052016-03-08 11:29:55 +01004526#ifdef CONFIG_NET_POLL_CONTROLLER
4527 .ndo_poll_controller = mtk_poll_controller,
4528#endif
Felix Fietkau502e84e2021-03-24 02:30:54 +01004529 .ndo_setup_tc = mtk_eth_setup_tc,
Lorenzo Bianconi7c26c202022-07-22 09:19:37 +02004530 .ndo_bpf = mtk_xdp,
Lorenzo Bianconi5886d262022-07-22 09:19:39 +02004531 .ndo_xdp_xmit = mtk_xdp_xmit,
Felix Fietkauf63959c2022-11-16 09:07:32 +01004532 .ndo_select_queue = mtk_select_queue,
John Crispin656e7052016-03-08 11:29:55 +01004533};
4534
4535static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
4536{
John Crispin656e7052016-03-08 11:29:55 +01004537 const __be32 *_id = of_get_property(np, "reg", NULL);
Andrew Lunn0c65b2b2019-11-04 02:40:33 +01004538 phy_interface_t phy_mode;
René van Dorstb8fc9f32019-08-25 19:43:39 +02004539 struct phylink *phylink;
René van Dorstb8fc9f32019-08-25 19:43:39 +02004540 struct mtk_mac *mac;
Andrew Lunn0c65b2b2019-11-04 02:40:33 +01004541 int id, err;
Felix Fietkauf63959c2022-11-16 09:07:32 +01004542 int txqs = 1;
Russell King (Oracle)79108982023-03-07 16:19:31 +00004543 u32 val;
John Crispin656e7052016-03-08 11:29:55 +01004544
4545 if (!_id) {
4546 dev_err(eth->dev, "missing mac id\n");
4547 return -EINVAL;
4548 }
4549
4550 id = be32_to_cpup(_id);
Lorenzo Bianconie05fd622023-07-25 01:52:44 +01004551 if (id >= MTK_MAX_DEVS) {
John Crispin656e7052016-03-08 11:29:55 +01004552 dev_err(eth->dev, "%d is not a valid mac id\n", id);
4553 return -EINVAL;
4554 }
4555
4556 if (eth->netdev[id]) {
4557 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
4558 return -EINVAL;
4559 }
4560
Felix Fietkauf63959c2022-11-16 09:07:32 +01004561 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
4562 txqs = MTK_QDMA_NUM_QUEUES;
4563
4564 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1);
John Crispin656e7052016-03-08 11:29:55 +01004565 if (!eth->netdev[id]) {
4566 dev_err(eth->dev, "alloc_etherdev failed\n");
4567 return -ENOMEM;
4568 }
4569 mac = netdev_priv(eth->netdev[id]);
4570 eth->mac[id] = mac;
4571 mac->id = id;
4572 mac->hw = eth;
4573 mac->of_node = np;
John Crispin656e7052016-03-08 11:29:55 +01004574
Daniel Golle1d6d5372023-07-13 03:42:29 +01004575 err = of_get_ethdev_address(mac->of_node, eth->netdev[id]);
4576 if (err == -EPROBE_DEFER)
4577 return err;
4578
4579 if (err) {
4580 /* If the mac address is invalid, use random mac address */
4581 eth_hw_addr_random(eth->netdev[id]);
4582 dev_err(eth->dev, "generated random MAC address %pM\n",
4583 eth->netdev[id]->dev_addr);
4584 }
4585
Nelson Changee406812016-09-17 23:50:55 +08004586 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
4587 mac->hwlro_ip_cnt = 0;
4588
John Crispin656e7052016-03-08 11:29:55 +01004589 mac->hw_stats = devm_kzalloc(eth->dev,
4590 sizeof(*mac->hw_stats),
4591 GFP_KERNEL);
4592 if (!mac->hw_stats) {
4593 dev_err(eth->dev, "failed to allocate counter memory\n");
4594 err = -ENOMEM;
4595 goto free_netdev;
4596 }
4597 spin_lock_init(&mac->hw_stats->stats_lock);
sean.wang@mediatek.comd70056522016-08-13 19:16:18 +08004598 u64_stats_init(&mac->hw_stats->syncp);
Lorenzo Bianconi1953f132023-07-25 01:52:59 +01004599
4600 if (mtk_is_netsys_v3_or_greater(eth))
4601 mac->hw_stats->reg_offset = id * 0x80;
4602 else
4603 mac->hw_stats->reg_offset = id * 0x40;
John Crispin656e7052016-03-08 11:29:55 +01004604
René van Dorstb8fc9f32019-08-25 19:43:39 +02004605 /* phylink create */
Andrew Lunn0c65b2b2019-11-04 02:40:33 +01004606 err = of_get_phy_mode(np, &phy_mode);
4607 if (err) {
René van Dorstb8fc9f32019-08-25 19:43:39 +02004608 dev_err(eth->dev, "incorrect phy-mode\n");
René van Dorstb8fc9f32019-08-25 19:43:39 +02004609 goto free_netdev;
4610 }
4611
4612 /* mac config is not set */
4613 mac->interface = PHY_INTERFACE_MODE_NA;
René van Dorstb8fc9f32019-08-25 19:43:39 +02004614 mac->speed = SPEED_UNKNOWN;
4615
4616 mac->phylink_config.dev = &eth->netdev[id]->dev;
4617 mac->phylink_config.type = PHYLINK_NETDEV;
Russell King (Oracle)a4238f62021-11-16 10:06:58 +00004618 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
4619 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
4620
Russell King (Oracle)76a4cb72023-07-22 21:32:49 +01004621 /* MT7623 gmac0 is now missing its speed-specific PLL configuration
4622 * in its .mac_config method (since state->speed is not valid there.
4623 * Disable support for MII, GMII and RGMII.
4624 */
4625 if (!mac->hw->soc->disable_pll_modes || mac->id != 0) {
4626 __set_bit(PHY_INTERFACE_MODE_MII,
4627 mac->phylink_config.supported_interfaces);
4628 __set_bit(PHY_INTERFACE_MODE_GMII,
4629 mac->phylink_config.supported_interfaces);
Russell King (Oracle)83800d22021-11-16 10:06:43 +00004630
Russell King (Oracle)76a4cb72023-07-22 21:32:49 +01004631 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII))
4632 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces);
4633 }
Russell King (Oracle)83800d22021-11-16 10:06:43 +00004634
4635 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id)
4636 __set_bit(PHY_INTERFACE_MODE_TRGMII,
4637 mac->phylink_config.supported_interfaces);
4638
Russell King (Oracle)79108982023-03-07 16:19:31 +00004639 /* TRGMII is not permitted on MT7621 if using DDR2 */
4640 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) &&
4641 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) {
4642 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val);
4643 if (val & SYSCFG_DRAM_TYPE_DDR2)
4644 __clear_bit(PHY_INTERFACE_MODE_TRGMII,
4645 mac->phylink_config.supported_interfaces);
4646 }
4647
Russell King (Oracle)83800d22021-11-16 10:06:43 +00004648 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) {
4649 __set_bit(PHY_INTERFACE_MODE_SGMII,
4650 mac->phylink_config.supported_interfaces);
4651 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
4652 mac->phylink_config.supported_interfaces);
4653 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
4654 mac->phylink_config.supported_interfaces);
4655 }
René van Dorstb8fc9f32019-08-25 19:43:39 +02004656
Lorenzo Bianconi445eb642023-07-25 01:57:42 +01004657 if (mtk_is_netsys_v3_or_greater(mac->hw) &&
4658 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) &&
4659 id == MTK_GMAC1_ID) {
4660 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
4661 MAC_SYM_PAUSE |
4662 MAC_10000FD;
4663 phy_interface_zero(mac->phylink_config.supported_interfaces);
4664 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
4665 mac->phylink_config.supported_interfaces);
4666 }
4667
René van Dorstb8fc9f32019-08-25 19:43:39 +02004668 phylink = phylink_create(&mac->phylink_config,
4669 of_fwnode_handle(mac->of_node),
4670 phy_mode, &mtk_phylink_ops);
4671 if (IS_ERR(phylink)) {
4672 err = PTR_ERR(phylink);
4673 goto free_netdev;
4674 }
4675
4676 mac->phylink = phylink;
4677
John Crispin656e7052016-03-08 11:29:55 +01004678 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
John Crispineaadf9f2016-06-10 13:28:05 +02004679 eth->netdev[id]->watchdog_timeo = 5 * HZ;
John Crispin656e7052016-03-08 11:29:55 +01004680 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
4681 eth->netdev[id]->base_addr = (unsigned long)eth->base;
Nelson Changee406812016-09-17 23:50:55 +08004682
Stefan Roese296c9122019-08-16 15:23:25 +02004683 eth->netdev[id]->hw_features = eth->soc->hw_features;
Nelson Changee406812016-09-17 23:50:55 +08004684 if (eth->hwlro)
4685 eth->netdev[id]->hw_features |= NETIF_F_LRO;
4686
Stefan Roese296c9122019-08-16 15:23:25 +02004687 eth->netdev[id]->vlan_features = eth->soc->hw_features &
Felix Fietkauc6d96df2023-04-26 19:21:53 +02004688 ~NETIF_F_HW_VLAN_CTAG_TX;
Stefan Roese296c9122019-08-16 15:23:25 +02004689 eth->netdev[id]->features |= eth->soc->hw_features;
John Crispin656e7052016-03-08 11:29:55 +01004690 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
4691
John Crispin80673022016-06-29 13:38:11 +02004692 eth->netdev[id]->irq = eth->irq[0];
Sean Wang3174b3b2017-04-07 16:45:08 +08004693 eth->netdev[id]->dev.of_node = np;
4694
DENG Qingfang4fd59792021-01-25 12:20:46 +08004695 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
4696 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
4697 else
4698 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
Landen Chao555a8932020-07-29 10:15:17 +02004699
Felix Fietkauf63959c2022-11-16 09:07:32 +01004700 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
4701 mac->device_notifier.notifier_call = mtk_device_event;
4702 register_netdevice_notifier(&mac->device_notifier);
4703 }
4704
Marek Majtyka66c0e132023-02-01 11:24:18 +01004705 if (mtk_page_pool_enabled(eth))
4706 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC |
4707 NETDEV_XDP_ACT_REDIRECT |
4708 NETDEV_XDP_ACT_NDO_XMIT |
4709 NETDEV_XDP_ACT_NDO_XMIT_SG;
4710
John Crispin656e7052016-03-08 11:29:55 +01004711 return 0;
4712
4713free_netdev:
4714 free_netdev(eth->netdev[id]);
4715 return err;
4716}
4717
Felix Fietkaud776a572022-04-05 21:57:43 +02004718void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
4719{
4720 struct net_device *dev, *tmp;
4721 LIST_HEAD(dev_list);
4722 int i;
4723
4724 rtnl_lock();
4725
Lorenzo Bianconie05fd622023-07-25 01:52:44 +01004726 for (i = 0; i < MTK_MAX_DEVS; i++) {
Felix Fietkaud776a572022-04-05 21:57:43 +02004727 dev = eth->netdev[i];
4728
4729 if (!dev || !(dev->flags & IFF_UP))
4730 continue;
4731
4732 list_add_tail(&dev->close_list, &dev_list);
4733 }
4734
4735 dev_close_many(&dev_list, false);
4736
4737 eth->dma_dev = dma_dev;
4738
4739 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) {
4740 list_del_init(&dev->close_list);
4741 dev_open(dev, NULL);
4742 }
4743
4744 rtnl_unlock();
4745}
4746
Daniel Golle2a3ec7a2023-03-19 12:58:02 +00004747static int mtk_sgmii_init(struct mtk_eth *eth)
4748{
4749 struct device_node *np;
4750 struct regmap *regmap;
4751 u32 flags;
4752 int i;
4753
4754 for (i = 0; i < MTK_MAX_DEVS; i++) {
4755 np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i);
4756 if (!np)
4757 break;
4758
4759 regmap = syscon_node_to_regmap(np);
4760 flags = 0;
4761 if (of_property_read_bool(np, "mediatek,pnswap"))
4762 flags |= MTK_SGMII_FLAG_PN_SWAP;
4763
4764 of_node_put(np);
4765
4766 if (IS_ERR(regmap))
4767 return PTR_ERR(regmap);
4768
4769 eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap,
4770 eth->soc->ana_rgc3,
4771 flags);
4772 }
4773
4774 return 0;
4775}
4776
John Crispin656e7052016-03-08 11:29:55 +01004777static int mtk_probe(struct platform_device *pdev)
4778{
Daniel Golleebb1e4f2023-08-22 17:32:54 +01004779 struct resource *res = NULL, *res_sram;
John Crispin656e7052016-03-08 11:29:55 +01004780 struct device_node *mac_np;
John Crispin656e7052016-03-08 11:29:55 +01004781 struct mtk_eth *eth;
René van Dorstb8fc9f32019-08-25 19:43:39 +02004782 int err, i;
John Crispin656e7052016-03-08 11:29:55 +01004783
John Crispin656e7052016-03-08 11:29:55 +01004784 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
4785 if (!eth)
4786 return -ENOMEM;
4787
Ryder Leeeda7d462018-04-16 10:33:41 +08004788 eth->soc = of_device_get_match_data(&pdev->dev);
Sean Wang2ec50f52017-07-31 18:05:09 +08004789
Sean Wang549e5492016-09-01 10:47:28 +08004790 eth->dev = &pdev->dev;
Felix Fietkaud776a572022-04-05 21:57:43 +02004791 eth->dma_dev = &pdev->dev;
YueHaibing566495d2019-08-01 20:33:08 +08004792 eth->base = devm_platform_ioremap_resource(pdev, 0);
Vladimir Zapolskiy621e49f2016-03-23 01:06:04 +02004793 if (IS_ERR(eth->base))
4794 return PTR_ERR(eth->base);
John Crispin656e7052016-03-08 11:29:55 +01004795
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02004796 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
Stefan Roese296c9122019-08-16 15:23:25 +02004797 eth->ip_align = NET_IP_ALIGN;
Stefan Roese296c9122019-08-16 15:23:25 +02004798
Daniel Golleebb1e4f2023-08-22 17:32:54 +01004799 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) {
4800 /* SRAM is actual memory and supports transparent access just like DRAM.
4801 * Hence we don't require __iomem being set and don't need to use accessor
4802 * functions to read from or write to SRAM.
4803 */
4804 if (mtk_is_netsys_v3_or_greater(eth)) {
4805 eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1);
4806 if (IS_ERR(eth->sram_base))
4807 return PTR_ERR(eth->sram_base);
4808 } else {
4809 eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET;
4810 }
4811 }
4812
Daniel Golle2d75891e2023-08-22 17:33:12 +01004813 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
Daniel Gollecae1f1c2024-01-24 16:22:09 +00004814 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36));
4815 if (!err)
4816 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
4817
Daniel Golle2d75891e2023-08-22 17:33:12 +01004818 if (err) {
4819 dev_err(&pdev->dev, "Wrong DMA config\n");
4820 return -EINVAL;
4821 }
4822 }
4823
John Crispin656e7052016-03-08 11:29:55 +01004824 spin_lock_init(&eth->page_lock);
John Crispin5cce0322017-06-19 15:37:05 +02004825 spin_lock_init(&eth->tx_irq_lock);
4826 spin_lock_init(&eth->rx_irq_lock);
Felix Fietkaue9229ff2021-04-22 22:21:02 -07004827 spin_lock_init(&eth->dim_lock);
4828
4829 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4830 INIT_WORK(&eth->rx_dim.work, mtk_dim_rx);
Lorenzo Bianconi93b25912023-01-14 18:01:31 +01004831 INIT_DELAYED_WORK(&eth->reset.monitor_work, mtk_hw_reset_monitor_work);
Felix Fietkaue9229ff2021-04-22 22:21:02 -07004832
4833 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4834 INIT_WORK(&eth->tx_dim.work, mtk_dim_tx);
John Crispin656e7052016-03-08 11:29:55 +01004835
Stefan Roese296c9122019-08-16 15:23:25 +02004836 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
4837 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4838 "mediatek,ethsys");
4839 if (IS_ERR(eth->ethsys)) {
4840 dev_err(&pdev->dev, "no ethsys regmap found\n");
4841 return PTR_ERR(eth->ethsys);
4842 }
John Crispin656e7052016-03-08 11:29:55 +01004843 }
4844
Sean Wang7093f9d2019-06-01 08:03:13 +08004845 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) {
4846 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4847 "mediatek,infracfg");
4848 if (IS_ERR(eth->infra)) {
4849 dev_err(&pdev->dev, "no infracfg regmap found\n");
4850 return PTR_ERR(eth->infra);
4851 }
4852 }
4853
Felix Fietkaud776a572022-04-05 21:57:43 +02004854 if (of_dma_is_coherent(pdev->dev.of_node)) {
4855 struct regmap *cci;
4856
4857 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
Lorenzo Bianconi4263f772022-04-11 12:13:25 +02004858 "cci-control-port");
Felix Fietkaud776a572022-04-05 21:57:43 +02004859 /* enable CPU/bus coherency */
4860 if (!IS_ERR(cci))
4861 regmap_write(cci, 0, 3);
4862 }
4863
Sean Wang42c03842017-07-31 18:05:10 +08004864 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
Daniel Golle2a3ec7a2023-03-19 12:58:02 +00004865 err = mtk_sgmii_init(eth);
Sean Wang9ffee4a82019-06-01 08:03:12 +08004866
4867 if (err)
4868 return err;
Sean Wang42c03842017-07-31 18:05:10 +08004869 }
4870
Sean Wang243dc5f2017-12-20 17:47:06 +08004871 if (eth->soc->required_pctl) {
4872 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4873 "mediatek,pctl");
4874 if (IS_ERR(eth->pctl)) {
4875 dev_err(&pdev->dev, "no pctl regmap found\n");
Daniel Golle2a3ec7a2023-03-19 12:58:02 +00004876 err = PTR_ERR(eth->pctl);
4877 goto err_destroy_sgmii;
Sean Wang243dc5f2017-12-20 17:47:06 +08004878 }
John Crispin656e7052016-03-08 11:29:55 +01004879 }
4880
Lorenzo Bianconia008e2a2023-07-25 01:52:02 +01004881 if (mtk_is_netsys_v2_or_greater(eth)) {
Lorenzo Bianconide84a092022-09-20 12:11:21 +02004882 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Daniel Golle2a3ec7a2023-03-19 12:58:02 +00004883 if (!res) {
4884 err = -EINVAL;
4885 goto err_destroy_sgmii;
4886 }
Daniel Golleebb1e4f2023-08-22 17:32:54 +01004887 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) {
4888 if (mtk_is_netsys_v3_or_greater(eth)) {
4889 res_sram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
4890 if (!res_sram) {
4891 err = -EINVAL;
4892 goto err_destroy_sgmii;
4893 }
4894 eth->phy_scratch_ring = res_sram->start;
4895 } else {
4896 eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET;
4897 }
4898 }
Lorenzo Bianconide84a092022-09-20 12:11:21 +02004899 }
Felix Fietkau804775d2022-04-05 21:57:47 +02004900
Lorenzo Bianconide84a092022-09-20 12:11:21 +02004901 if (eth->soc->offload_version) {
4902 for (i = 0;; i++) {
4903 struct device_node *np;
4904 phys_addr_t wdma_phy;
4905 u32 wdma_base;
Felix Fietkau804775d2022-04-05 21:57:47 +02004906
Lorenzo Bianconide84a092022-09-20 12:11:21 +02004907 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base))
4908 break;
4909
4910 np = of_parse_phandle(pdev->dev.of_node,
4911 "mediatek,wed", i);
4912 if (!np)
4913 break;
4914
4915 wdma_base = eth->soc->reg_map->wdma_base[i];
4916 wdma_phy = res ? res->start + wdma_base : 0;
4917 mtk_wed_add_hw(np, eth, eth->base + wdma_base,
4918 wdma_phy, i);
4919 }
Felix Fietkau804775d2022-04-05 21:57:47 +02004920 }
4921
John Crispin80673022016-06-29 13:38:11 +02004922 for (i = 0; i < 3; i++) {
Bjørn Mork889bcbd2019-01-30 11:24:04 +10004923 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)
4924 eth->irq[i] = eth->irq[0];
4925 else
4926 eth->irq[i] = platform_get_irq(pdev, i);
John Crispin80673022016-06-29 13:38:11 +02004927 if (eth->irq[i] < 0) {
4928 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
Yang Yingliangb3d0d982022-10-17 11:51:54 +08004929 err = -ENXIO;
4930 goto err_wed_exit;
John Crispin80673022016-06-29 13:38:11 +02004931 }
John Crispin656e7052016-03-08 11:29:55 +01004932 }
Sean Wang549e5492016-09-01 10:47:28 +08004933 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
4934 eth->clks[i] = devm_clk_get(eth->dev,
4935 mtk_clks_source_name[i]);
4936 if (IS_ERR(eth->clks[i])) {
Yang Yingliangb3d0d982022-10-17 11:51:54 +08004937 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) {
4938 err = -EPROBE_DEFER;
4939 goto err_wed_exit;
4940 }
Sean Wang2ec50f52017-07-31 18:05:09 +08004941 if (eth->soc->required_clks & BIT(i)) {
4942 dev_err(&pdev->dev, "clock %s not found\n",
4943 mtk_clks_source_name[i]);
Yang Yingliangb3d0d982022-10-17 11:51:54 +08004944 err = -EINVAL;
4945 goto err_wed_exit;
Sean Wang2ec50f52017-07-31 18:05:09 +08004946 }
4947 eth->clks[i] = NULL;
Sean Wang549e5492016-09-01 10:47:28 +08004948 }
4949 }
John Crispin656e7052016-03-08 11:29:55 +01004950
John Crispin656e7052016-03-08 11:29:55 +01004951 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
John Crispin7c78b4a2016-04-08 00:54:10 +02004952 INIT_WORK(&eth->pending_work, mtk_pending_work);
John Crispin656e7052016-03-08 11:29:55 +01004953
Lorenzo Bianconia9724b92023-01-14 18:01:29 +01004954 err = mtk_hw_init(eth, false);
John Crispin656e7052016-03-08 11:29:55 +01004955 if (err)
Yang Yingliangb3d0d982022-10-17 11:51:54 +08004956 goto err_wed_exit;
John Crispin656e7052016-03-08 11:29:55 +01004957
Sean Wang2d14ba72018-07-28 13:35:56 +08004958 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO);
Nelson Chang983e1a62016-10-06 19:44:02 +08004959
John Crispin656e7052016-03-08 11:29:55 +01004960 for_each_child_of_node(pdev->dev.of_node, mac_np) {
4961 if (!of_device_is_compatible(mac_np,
4962 "mediatek,eth-mac"))
4963 continue;
4964
4965 if (!of_device_is_available(mac_np))
4966 continue;
4967
4968 err = mtk_add_mac(eth, mac_np);
Nishka Dasguptacf36dd22019-07-16 11:25:04 +05304969 if (err) {
4970 of_node_put(mac_np);
Sean Wang8a8a9e82016-09-14 23:13:17 +08004971 goto err_deinit_hw;
Nishka Dasguptacf36dd22019-07-16 11:25:04 +05304972 }
John Crispin656e7052016-03-08 11:29:55 +01004973 }
4974
Bjørn Mork889bcbd2019-01-30 11:24:04 +10004975 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
4976 err = devm_request_irq(eth->dev, eth->irq[0],
4977 mtk_handle_irq, 0,
4978 dev_name(eth->dev), eth);
4979 } else {
4980 err = devm_request_irq(eth->dev, eth->irq[1],
4981 mtk_handle_irq_tx, 0,
4982 dev_name(eth->dev), eth);
4983 if (err)
4984 goto err_free_dev;
Sean Wang85574db2016-09-14 23:13:15 +08004985
Bjørn Mork889bcbd2019-01-30 11:24:04 +10004986 err = devm_request_irq(eth->dev, eth->irq[2],
4987 mtk_handle_irq_rx, 0,
4988 dev_name(eth->dev), eth);
4989 }
Sean Wang85574db2016-09-14 23:13:15 +08004990 if (err)
4991 goto err_free_dev;
4992
Stefan Roese296c9122019-08-16 15:23:25 +02004993 /* No MT7628/88 support yet */
4994 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
4995 err = mtk_mdio_init(eth);
4996 if (err)
4997 goto err_free_dev;
4998 }
Sean Wang85574db2016-09-14 23:13:15 +08004999
Felix Fietkauba37b7c2021-03-24 02:30:53 +01005000 if (eth->soc->offload_version) {
Elad Yifeedee4dd12024-06-07 11:21:50 +03005001 u8 ppe_num = eth->soc->ppe_num;
Lorenzo Bianconi329bce52022-09-20 12:11:15 +02005002
Elad Yifeedee4dd12024-06-07 11:21:50 +03005003 ppe_num = min_t(u8, ARRAY_SIZE(eth->ppe), ppe_num);
5004 for (i = 0; i < ppe_num; i++) {
5005 u32 ppe_addr = eth->soc->reg_map->ppe_base;
Lorenzo Bianconi4ff1a3f2022-09-20 12:11:17 +02005006
Elad Yifeedee4dd12024-06-07 11:21:50 +03005007 ppe_addr += (i == 2 ? 0xc00 : i * 0x400);
Daniel Golle3fbe4d82023-03-19 12:57:35 +00005008 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i);
5009
Lorenzo Bianconi4ff1a3f2022-09-20 12:11:17 +02005010 if (!eth->ppe[i]) {
5011 err = -ENOMEM;
Yan Cangang603ea5e2022-11-20 13:52:59 +08005012 goto err_deinit_ppe;
Lorenzo Bianconi4ff1a3f2022-09-20 12:11:17 +02005013 }
Elad Yifeedee4dd12024-06-07 11:21:50 +03005014 err = mtk_eth_offload_init(eth, i);
Felix Fietkau502e84e2021-03-24 02:30:54 +01005015
Elad Yifeedee4dd12024-06-07 11:21:50 +03005016 if (err)
5017 goto err_deinit_ppe;
5018 }
Felix Fietkauba37b7c2021-03-24 02:30:53 +01005019 }
5020
Sean Wang85574db2016-09-14 23:13:15 +08005021 for (i = 0; i < MTK_MAX_DEVS; i++) {
5022 if (!eth->netdev[i])
5023 continue;
5024
5025 err = register_netdev(eth->netdev[i]);
5026 if (err) {
5027 dev_err(eth->dev, "error bringing up device\n");
Yan Cangang603ea5e2022-11-20 13:52:59 +08005028 goto err_deinit_ppe;
Sean Wang85574db2016-09-14 23:13:15 +08005029 } else
5030 netif_info(eth, probe, eth->netdev[i],
5031 "mediatek frame engine at 0x%08lx, irq %d\n",
5032 eth->netdev[i]->base_addr, eth->irq[0]);
5033 }
5034
John Crispin656e7052016-03-08 11:29:55 +01005035 /* we run 2 devices on the same DMA ring so we need a dummy device
5036 * for NAPI to work
5037 */
Breno Leitaob209bd62024-04-22 05:38:58 -07005038 eth->dummy_dev = alloc_netdev_dummy(0);
5039 if (!eth->dummy_dev) {
5040 err = -ENOMEM;
5041 dev_err(eth->dev, "failed to allocated dummy device\n");
5042 goto err_unreg_netdev;
5043 }
5044 netif_napi_add(eth->dummy_dev, &eth->tx_napi, mtk_napi_tx);
5045 netif_napi_add(eth->dummy_dev, &eth->rx_napi, mtk_napi_rx);
John Crispin656e7052016-03-08 11:29:55 +01005046
5047 platform_set_drvdata(pdev, eth);
Lorenzo Bianconi93b25912023-01-14 18:01:31 +01005048 schedule_delayed_work(&eth->reset.monitor_work,
5049 MTK_DMA_MONITOR_TIMEOUT);
John Crispin656e7052016-03-08 11:29:55 +01005050
5051 return 0;
5052
Breno Leitaob209bd62024-04-22 05:38:58 -07005053err_unreg_netdev:
5054 mtk_unreg_dev(eth);
Yan Cangang603ea5e2022-11-20 13:52:59 +08005055err_deinit_ppe:
5056 mtk_ppe_deinit(eth);
Sean Wang8a8a9e82016-09-14 23:13:17 +08005057 mtk_mdio_cleanup(eth);
John Crispin656e7052016-03-08 11:29:55 +01005058err_free_dev:
Sean Wang8a8a9e82016-09-14 23:13:17 +08005059 mtk_free_dev(eth);
5060err_deinit_hw:
5061 mtk_hw_deinit(eth);
Yang Yingliangb3d0d982022-10-17 11:51:54 +08005062err_wed_exit:
5063 mtk_wed_exit();
Daniel Golle2a3ec7a2023-03-19 12:58:02 +00005064err_destroy_sgmii:
5065 mtk_sgmii_destroy(eth);
Sean Wang8a8a9e82016-09-14 23:13:17 +08005066
John Crispin656e7052016-03-08 11:29:55 +01005067 return err;
5068}
5069
Uwe Kleine-König5b6ce172023-09-18 22:42:02 +02005070static void mtk_remove(struct platform_device *pdev)
John Crispin656e7052016-03-08 11:29:55 +01005071{
5072 struct mtk_eth *eth = platform_get_drvdata(pdev);
René van Dorstb8fc9f32019-08-25 19:43:39 +02005073 struct mtk_mac *mac;
Sean Wang79e9a412016-09-01 10:47:32 +08005074 int i;
John Crispin656e7052016-03-08 11:29:55 +01005075
Sean Wang79e9a412016-09-01 10:47:32 +08005076 /* stop all devices to make sure that dma is properly shut down */
Lorenzo Bianconie05fd622023-07-25 01:52:44 +01005077 for (i = 0; i < MTK_MAX_DEVS; i++) {
Sean Wang79e9a412016-09-01 10:47:32 +08005078 if (!eth->netdev[i])
5079 continue;
5080 mtk_stop(eth->netdev[i]);
René van Dorstb8fc9f32019-08-25 19:43:39 +02005081 mac = netdev_priv(eth->netdev[i]);
5082 phylink_disconnect_phy(mac->phylink);
Sean Wang79e9a412016-09-01 10:47:32 +08005083 }
John Crispin656e7052016-03-08 11:29:55 +01005084
Yang Yingliangb3d0d982022-10-17 11:51:54 +08005085 mtk_wed_exit();
Sean Wangbf253fb2016-09-14 23:13:16 +08005086 mtk_hw_deinit(eth);
John Crispin656e7052016-03-08 11:29:55 +01005087
John Crispin80673022016-06-29 13:38:11 +02005088 netif_napi_del(&eth->tx_napi);
John Crispin656e7052016-03-08 11:29:55 +01005089 netif_napi_del(&eth->rx_napi);
5090 mtk_cleanup(eth);
Breno Leitao16f3a282024-07-24 01:05:23 -07005091 free_netdev(eth->dummy_dev);
Sean Wange82f7142016-09-20 23:53:24 +08005092 mtk_mdio_cleanup(eth);
John Crispin656e7052016-03-08 11:29:55 +01005093}
5094
Sean Wang2ec50f52017-07-31 18:05:09 +08005095static const struct mtk_soc_data mt2701_data = {
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02005096 .reg_map = &mtk_reg_map,
Sean Wang7093f9d2019-06-01 08:03:13 +08005097 .caps = MT7623_CAPS | MTK_HWLRO,
Stefan Roese296c9122019-08-16 15:23:25 +02005098 .hw_features = MTK_HW_FEATURES,
Sean Wang243dc5f2017-12-20 17:47:06 +08005099 .required_clks = MT7623_CLKS_BITMAP,
5100 .required_pctl = true,
Lorenzo Bianconia008e2a2023-07-25 01:52:02 +01005101 .version = 1,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005102 .tx = {
5103 .desc_size = sizeof(struct mtk_tx_dma),
5104 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5105 .dma_len_offset = 16,
Frank Wunderlichc57e5582024-06-03 21:25:05 +02005106 .dma_size = MTK_DMA_SIZE(2K),
5107 .fq_dma_size = MTK_DMA_SIZE(2K),
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005108 },
5109 .rx = {
5110 .desc_size = sizeof(struct mtk_rx_dma),
5111 .irq_done_mask = MTK_RX_DONE_INT,
5112 .dma_l4_valid = RX_DMA_L4_VALID,
Frank Wunderlichc57e5582024-06-03 21:25:05 +02005113 .dma_size = MTK_DMA_SIZE(2K),
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02005114 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5115 .dma_len_offset = 16,
Lorenzo Bianconieb067342022-05-20 20:11:28 +02005116 },
Sean Wang2ec50f52017-07-31 18:05:09 +08005117};
5118
Bjørn Mork889bcbd2019-01-30 11:24:04 +10005119static const struct mtk_soc_data mt7621_data = {
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02005120 .reg_map = &mtk_reg_map,
René van Dorst8efaa652019-06-20 14:21:54 +02005121 .caps = MT7621_CAPS,
Stefan Roese296c9122019-08-16 15:23:25 +02005122 .hw_features = MTK_HW_FEATURES,
Bjørn Mork889bcbd2019-01-30 11:24:04 +10005123 .required_clks = MT7621_CLKS_BITMAP,
5124 .required_pctl = false,
Lorenzo Bianconia008e2a2023-07-25 01:52:02 +01005125 .version = 1,
Felix Fietkau71ba8e42022-11-16 09:07:31 +01005126 .offload_version = 1,
Elad Yifeedee4dd12024-06-07 11:21:50 +03005127 .ppe_num = 1,
Lorenzo Bianconiba2fc482022-09-20 12:11:16 +02005128 .hash_offset = 2,
Lorenzo Bianconia5dc6942023-07-19 12:29:49 +02005129 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005130 .tx = {
5131 .desc_size = sizeof(struct mtk_tx_dma),
5132 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5133 .dma_len_offset = 16,
Frank Wunderlichc57e5582024-06-03 21:25:05 +02005134 .dma_size = MTK_DMA_SIZE(2K),
5135 .fq_dma_size = MTK_DMA_SIZE(2K),
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005136 },
5137 .rx = {
5138 .desc_size = sizeof(struct mtk_rx_dma),
5139 .irq_done_mask = MTK_RX_DONE_INT,
5140 .dma_l4_valid = RX_DMA_L4_VALID,
Frank Wunderlichc57e5582024-06-03 21:25:05 +02005141 .dma_size = MTK_DMA_SIZE(2K),
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02005142 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5143 .dma_len_offset = 16,
Lorenzo Bianconieb067342022-05-20 20:11:28 +02005144 },
Bjørn Mork889bcbd2019-01-30 11:24:04 +10005145};
5146
Sean Wang42c03842017-07-31 18:05:10 +08005147static const struct mtk_soc_data mt7622_data = {
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02005148 .reg_map = &mtk_reg_map,
Sean Wang9ffee4a82019-06-01 08:03:12 +08005149 .ana_rgc3 = 0x2028,
Sean Wang7093f9d2019-06-01 08:03:13 +08005150 .caps = MT7622_CAPS | MTK_HWLRO,
Stefan Roese296c9122019-08-16 15:23:25 +02005151 .hw_features = MTK_HW_FEATURES,
Sean Wang243dc5f2017-12-20 17:47:06 +08005152 .required_clks = MT7622_CLKS_BITMAP,
5153 .required_pctl = false,
Lorenzo Bianconia008e2a2023-07-25 01:52:02 +01005154 .version = 1,
Felix Fietkauba37b7c2021-03-24 02:30:53 +01005155 .offload_version = 2,
Elad Yifeedee4dd12024-06-07 11:21:50 +03005156 .ppe_num = 1,
Lorenzo Bianconiba2fc482022-09-20 12:11:16 +02005157 .hash_offset = 2,
Daniel Golle3fbe4d82023-03-19 12:57:35 +00005158 .has_accounting = true,
Lorenzo Bianconia5dc6942023-07-19 12:29:49 +02005159 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005160 .tx = {
5161 .desc_size = sizeof(struct mtk_tx_dma),
5162 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5163 .dma_len_offset = 16,
Frank Wunderlichc57e5582024-06-03 21:25:05 +02005164 .dma_size = MTK_DMA_SIZE(2K),
5165 .fq_dma_size = MTK_DMA_SIZE(2K),
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005166 },
5167 .rx = {
5168 .desc_size = sizeof(struct mtk_rx_dma),
5169 .irq_done_mask = MTK_RX_DONE_INT,
5170 .dma_l4_valid = RX_DMA_L4_VALID,
Frank Wunderlichc57e5582024-06-03 21:25:05 +02005171 .dma_size = MTK_DMA_SIZE(2K),
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02005172 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5173 .dma_len_offset = 16,
Lorenzo Bianconieb067342022-05-20 20:11:28 +02005174 },
Sean Wang42c03842017-07-31 18:05:10 +08005175};
5176
Sean Wang2ec50f52017-07-31 18:05:09 +08005177static const struct mtk_soc_data mt7623_data = {
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02005178 .reg_map = &mtk_reg_map,
Sean Wang7093f9d2019-06-01 08:03:13 +08005179 .caps = MT7623_CAPS | MTK_HWLRO,
Stefan Roese296c9122019-08-16 15:23:25 +02005180 .hw_features = MTK_HW_FEATURES,
Sean Wang243dc5f2017-12-20 17:47:06 +08005181 .required_clks = MT7623_CLKS_BITMAP,
5182 .required_pctl = true,
Lorenzo Bianconia008e2a2023-07-25 01:52:02 +01005183 .version = 1,
Felix Fietkau71ba8e42022-11-16 09:07:31 +01005184 .offload_version = 1,
Elad Yifeedee4dd12024-06-07 11:21:50 +03005185 .ppe_num = 1,
Lorenzo Bianconiba2fc482022-09-20 12:11:16 +02005186 .hash_offset = 2,
Lorenzo Bianconia5dc6942023-07-19 12:29:49 +02005187 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
Russell King (Oracle)76a4cb72023-07-22 21:32:49 +01005188 .disable_pll_modes = true,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005189 .tx = {
5190 .desc_size = sizeof(struct mtk_tx_dma),
5191 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5192 .dma_len_offset = 16,
Frank Wunderlichc57e5582024-06-03 21:25:05 +02005193 .dma_size = MTK_DMA_SIZE(2K),
5194 .fq_dma_size = MTK_DMA_SIZE(2K),
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005195 },
5196 .rx = {
5197 .desc_size = sizeof(struct mtk_rx_dma),
5198 .irq_done_mask = MTK_RX_DONE_INT,
5199 .dma_l4_valid = RX_DMA_L4_VALID,
Frank Wunderlichc57e5582024-06-03 21:25:05 +02005200 .dma_size = MTK_DMA_SIZE(2K),
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02005201 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5202 .dma_len_offset = 16,
Lorenzo Bianconieb067342022-05-20 20:11:28 +02005203 },
Sean Wang2ec50f52017-07-31 18:05:09 +08005204};
5205
Sean Wangd438e292019-06-01 08:03:14 +08005206static const struct mtk_soc_data mt7629_data = {
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02005207 .reg_map = &mtk_reg_map,
Sean Wangd438e292019-06-01 08:03:14 +08005208 .ana_rgc3 = 0x128,
5209 .caps = MT7629_CAPS | MTK_HWLRO,
Stefan Roese296c9122019-08-16 15:23:25 +02005210 .hw_features = MTK_HW_FEATURES,
Sean Wangd438e292019-06-01 08:03:14 +08005211 .required_clks = MT7629_CLKS_BITMAP,
5212 .required_pctl = false,
Daniel Golle3fbe4d82023-03-19 12:57:35 +00005213 .has_accounting = true,
Lorenzo Bianconia008e2a2023-07-25 01:52:02 +01005214 .version = 1,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005215 .tx = {
5216 .desc_size = sizeof(struct mtk_tx_dma),
5217 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5218 .dma_len_offset = 16,
Frank Wunderlichc57e5582024-06-03 21:25:05 +02005219 .dma_size = MTK_DMA_SIZE(2K),
5220 .fq_dma_size = MTK_DMA_SIZE(2K),
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005221 },
5222 .rx = {
5223 .desc_size = sizeof(struct mtk_rx_dma),
5224 .irq_done_mask = MTK_RX_DONE_INT,
5225 .dma_l4_valid = RX_DMA_L4_VALID,
Frank Wunderlichc57e5582024-06-03 21:25:05 +02005226 .dma_size = MTK_DMA_SIZE(2K),
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02005227 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5228 .dma_len_offset = 16,
Lorenzo Bianconieb067342022-05-20 20:11:28 +02005229 },
Sean Wangd438e292019-06-01 08:03:14 +08005230};
5231
Daniel Gollef5d43dd2023-03-19 12:56:28 +00005232static const struct mtk_soc_data mt7981_data = {
5233 .reg_map = &mt7986_reg_map,
5234 .ana_rgc3 = 0x128,
5235 .caps = MT7981_CAPS,
5236 .hw_features = MTK_HW_FEATURES,
5237 .required_clks = MT7981_CLKS_BITMAP,
5238 .required_pctl = false,
Lorenzo Bianconia008e2a2023-07-25 01:52:02 +01005239 .version = 2,
Daniel Gollef5d43dd2023-03-19 12:56:28 +00005240 .offload_version = 2,
Elad Yifeedee4dd12024-06-07 11:21:50 +03005241 .ppe_num = 2,
Daniel Gollef5d43dd2023-03-19 12:56:28 +00005242 .hash_offset = 4,
Daniel Golle3fbe4d82023-03-19 12:57:35 +00005243 .has_accounting = true,
Lorenzo Bianconia5dc6942023-07-19 12:29:49 +02005244 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005245 .tx = {
5246 .desc_size = sizeof(struct mtk_tx_dma_v2),
Daniel Gollef5d43dd2023-03-19 12:56:28 +00005247 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
5248 .dma_len_offset = 8,
Frank Wunderlichc57e5582024-06-03 21:25:05 +02005249 .dma_size = MTK_DMA_SIZE(2K),
5250 .fq_dma_size = MTK_DMA_SIZE(2K),
Daniel Gollef5d43dd2023-03-19 12:56:28 +00005251 },
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005252 .rx = {
Daniel Golle5e69ff82024-05-08 11:43:56 +01005253 .desc_size = sizeof(struct mtk_rx_dma),
5254 .irq_done_mask = MTK_RX_DONE_INT,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005255 .dma_l4_valid = RX_DMA_L4_VALID_V2,
Daniel Golle5e69ff82024-05-08 11:43:56 +01005256 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5257 .dma_len_offset = 16,
Frank Wunderlichc57e5582024-06-03 21:25:05 +02005258 .dma_size = MTK_DMA_SIZE(2K),
Daniel Gollef5d43dd2023-03-19 12:56:28 +00005259 },
5260};
5261
Lorenzo Bianconi197c9e92022-05-20 20:11:39 +02005262static const struct mtk_soc_data mt7986_data = {
5263 .reg_map = &mt7986_reg_map,
5264 .ana_rgc3 = 0x128,
5265 .caps = MT7986_CAPS,
Lorenzo Bianconi03a31802022-09-20 12:11:23 +02005266 .hw_features = MTK_HW_FEATURES,
Lorenzo Bianconi197c9e92022-05-20 20:11:39 +02005267 .required_clks = MT7986_CLKS_BITMAP,
5268 .required_pctl = false,
Lorenzo Bianconia008e2a2023-07-25 01:52:02 +01005269 .version = 2,
Lorenzo Bianconic9f8d732022-12-03 14:20:37 +01005270 .offload_version = 2,
Elad Yifeedee4dd12024-06-07 11:21:50 +03005271 .ppe_num = 2,
Lorenzo Bianconiba2fc482022-09-20 12:11:16 +02005272 .hash_offset = 4,
Daniel Golle3fbe4d82023-03-19 12:57:35 +00005273 .has_accounting = true,
Lorenzo Bianconia5dc6942023-07-19 12:29:49 +02005274 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005275 .tx = {
5276 .desc_size = sizeof(struct mtk_tx_dma_v2),
Lorenzo Bianconi197c9e92022-05-20 20:11:39 +02005277 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
5278 .dma_len_offset = 8,
Frank Wunderlichc57e5582024-06-03 21:25:05 +02005279 .dma_size = MTK_DMA_SIZE(2K),
5280 .fq_dma_size = MTK_DMA_SIZE(2K),
Lorenzo Bianconi197c9e92022-05-20 20:11:39 +02005281 },
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005282 .rx = {
Daniel Golle5e69ff82024-05-08 11:43:56 +01005283 .desc_size = sizeof(struct mtk_rx_dma),
5284 .irq_done_mask = MTK_RX_DONE_INT,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005285 .dma_l4_valid = RX_DMA_L4_VALID_V2,
Daniel Golle5e69ff82024-05-08 11:43:56 +01005286 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5287 .dma_len_offset = 16,
Frank Wunderlichc57e5582024-06-03 21:25:05 +02005288 .dma_size = MTK_DMA_SIZE(2K),
Lorenzo Bianconi197c9e92022-05-20 20:11:39 +02005289 },
5290};
5291
Lorenzo Bianconi445eb642023-07-25 01:57:42 +01005292static const struct mtk_soc_data mt7988_data = {
5293 .reg_map = &mt7988_reg_map,
5294 .ana_rgc3 = 0x128,
5295 .caps = MT7988_CAPS,
5296 .hw_features = MTK_HW_FEATURES,
5297 .required_clks = MT7988_CLKS_BITMAP,
5298 .required_pctl = false,
5299 .version = 3,
Lorenzo Bianconi88efedf2023-07-27 09:07:28 +02005300 .offload_version = 2,
Elad Yifeedee4dd12024-06-07 11:21:50 +03005301 .ppe_num = 3,
Lorenzo Bianconi88efedf2023-07-27 09:07:28 +02005302 .hash_offset = 4,
Daniel Golle571e9c42023-08-02 04:31:09 +01005303 .has_accounting = true,
Lorenzo Bianconi88efedf2023-07-27 09:07:28 +02005304 .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005305 .tx = {
5306 .desc_size = sizeof(struct mtk_tx_dma_v2),
5307 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
5308 .dma_len_offset = 8,
Frank Wunderlichc57e5582024-06-03 21:25:05 +02005309 .dma_size = MTK_DMA_SIZE(2K),
5310 .fq_dma_size = MTK_DMA_SIZE(4K),
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005311 },
5312 .rx = {
5313 .desc_size = sizeof(struct mtk_rx_dma_v2),
5314 .irq_done_mask = MTK_RX_DONE_INT_V2,
5315 .dma_l4_valid = RX_DMA_L4_VALID_V2,
Lorenzo Bianconi445eb642023-07-25 01:57:42 +01005316 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
5317 .dma_len_offset = 8,
Frank Wunderlichc57e5582024-06-03 21:25:05 +02005318 .dma_size = MTK_DMA_SIZE(2K),
Lorenzo Bianconi445eb642023-07-25 01:57:42 +01005319 },
5320};
5321
Stefan Roese296c9122019-08-16 15:23:25 +02005322static const struct mtk_soc_data rt5350_data = {
Lorenzo Bianconi8cb42712022-05-20 20:11:35 +02005323 .reg_map = &mt7628_reg_map,
Stefan Roese296c9122019-08-16 15:23:25 +02005324 .caps = MT7628_CAPS,
5325 .hw_features = MTK_HW_FEATURES_MT7628,
5326 .required_clks = MT7628_CLKS_BITMAP,
5327 .required_pctl = false,
Lorenzo Bianconia008e2a2023-07-25 01:52:02 +01005328 .version = 1,
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005329 .tx = {
5330 .desc_size = sizeof(struct mtk_tx_dma),
5331 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5332 .dma_len_offset = 16,
Frank Wunderlichc57e5582024-06-03 21:25:05 +02005333 .dma_size = MTK_DMA_SIZE(2K),
Lorenzo Bianconiecb51fa2024-05-08 11:43:34 +01005334 },
5335 .rx = {
5336 .desc_size = sizeof(struct mtk_rx_dma),
5337 .irq_done_mask = MTK_RX_DONE_INT,
5338 .dma_l4_valid = RX_DMA_L4_VALID_PDMA,
Lorenzo Bianconi160d3a92022-05-20 20:11:36 +02005339 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5340 .dma_len_offset = 16,
Frank Wunderlichc57e5582024-06-03 21:25:05 +02005341 .dma_size = MTK_DMA_SIZE(2K),
Lorenzo Bianconieb067342022-05-20 20:11:28 +02005342 },
Stefan Roese296c9122019-08-16 15:23:25 +02005343};
5344
John Crispin656e7052016-03-08 11:29:55 +01005345const struct of_device_id of_mtk_match[] = {
Lorenzo Bianconi445eb642023-07-25 01:57:42 +01005346 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data },
5347 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
5348 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data },
5349 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data },
5350 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data },
5351 { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data },
5352 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data },
5353 { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data },
5354 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
John Crispin656e7052016-03-08 11:29:55 +01005355 {},
5356};
Sean Wang7077dc42016-09-14 21:29:34 +08005357MODULE_DEVICE_TABLE(of, of_mtk_match);
John Crispin656e7052016-03-08 11:29:55 +01005358
5359static struct platform_driver mtk_driver = {
5360 .probe = mtk_probe,
Uwe Kleine-König5b6ce172023-09-18 22:42:02 +02005361 .remove_new = mtk_remove,
John Crispin656e7052016-03-08 11:29:55 +01005362 .driver = {
5363 .name = "mtk_soc_eth",
John Crispin656e7052016-03-08 11:29:55 +01005364 .of_match_table = of_mtk_match,
5365 },
5366};
5367
5368module_platform_driver(mtk_driver);
5369
5370MODULE_LICENSE("GPL");
5371MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
5372MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");