blob: 4cac22633ce4eff45be478581b7598b2c64c0a73 [file] [log] [blame]
Rob Clark7198e6b2013-07-19 12:59:32 -04001/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
Aravind Ganesan91b74e92014-09-08 10:57:28 -06005 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
6 *
Rob Clark7198e6b2013-07-19 12:59:32 -04007 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "adreno_gpu.h"
21#include "msm_gem.h"
Rob Clark871d8122013-11-16 12:56:06 -050022#include "msm_mmu.h"
Rob Clark7198e6b2013-07-19 12:59:32 -040023
Rob Clark7198e6b2013-07-19 12:59:32 -040024#define RB_SIZE SZ_32K
Jordan Crouseb5f103a2016-11-28 12:28:33 -070025#define RB_BLKSIZE 32
Rob Clark7198e6b2013-07-19 12:59:32 -040026
27int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
28{
29 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
30
31 switch (param) {
32 case MSM_PARAM_GPU_ID:
33 *value = adreno_gpu->info->revn;
34 return 0;
35 case MSM_PARAM_GMEM_SIZE:
Rob Clark55459962013-12-05 17:39:53 -050036 *value = adreno_gpu->gmem;
Rob Clark7198e6b2013-07-19 12:59:32 -040037 return 0;
Jordan Crousee3689e42017-03-07 10:02:53 -070038 case MSM_PARAM_GMEM_BASE:
39 *value = 0x100000;
40 return 0;
Rob Clark4e1cbaa2014-02-04 14:16:04 -050041 case MSM_PARAM_CHIP_ID:
42 *value = adreno_gpu->rev.patchid |
43 (adreno_gpu->rev.minor << 8) |
44 (adreno_gpu->rev.major << 16) |
45 (adreno_gpu->rev.core << 24);
46 return 0;
Rob Clark4102a9e52016-02-09 12:05:30 -050047 case MSM_PARAM_MAX_FREQ:
48 *value = adreno_gpu->base.fast_rate;
49 return 0;
Rob Clark6c77d1a2016-02-22 06:26:21 -050050 case MSM_PARAM_TIMESTAMP:
51 if (adreno_gpu->funcs->get_timestamp)
52 return adreno_gpu->funcs->get_timestamp(gpu, value);
53 return -EINVAL;
Rob Clark7198e6b2013-07-19 12:59:32 -040054 default:
55 DBG("%s: invalid param: %u", gpu->name, param);
56 return -EINVAL;
57 }
58}
59
Rob Clark7198e6b2013-07-19 12:59:32 -040060int adreno_hw_init(struct msm_gpu *gpu)
61{
62 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
Rob Clark944fc362014-07-09 22:08:15 -040063 int ret;
Rob Clark7198e6b2013-07-19 12:59:32 -040064
65 DBG("%s", gpu->name);
66
Rob Clarka1ad3522014-07-11 11:59:22 -040067 ret = msm_gem_get_iova(gpu->rb->bo, gpu->id, &gpu->rb_iova);
Rob Clark944fc362014-07-09 22:08:15 -040068 if (ret) {
69 gpu->rb_iova = 0;
70 dev_err(gpu->dev->dev, "could not map ringbuffer: %d\n", ret);
71 return ret;
72 }
73
Rob Clarkde098e52017-02-12 11:42:14 -050074 /* reset ringbuffer: */
75 gpu->rb->cur = gpu->rb->start;
76
77 /* reset completed fence seqno: */
78 adreno_gpu->memptrs->fence = gpu->fctx->completed_fence;
79 adreno_gpu->memptrs->rptr = 0;
80 adreno_gpu->memptrs->wptr = 0;
81
Rob Clark7198e6b2013-07-19 12:59:32 -040082 /* Setup REG_CP_RB_CNTL: */
Aravind Ganesan91b74e92014-09-08 10:57:28 -060083 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
Rob Clark7198e6b2013-07-19 12:59:32 -040084 /* size is log2(quad-words): */
85 AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) |
Craig Stout7d0c5ee2016-02-18 16:50:02 -080086 AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)) |
87 (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
Rob Clark7198e6b2013-07-19 12:59:32 -040088
89 /* Setup ringbuffer address: */
Jordan Crousefb039982016-11-28 12:28:29 -070090 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE,
91 REG_ADRENO_CP_RB_BASE_HI, gpu->rb_iova);
Rob Clark7198e6b2013-07-19 12:59:32 -040092
Jordan Crousefb039982016-11-28 12:28:29 -070093 if (!adreno_is_a430(adreno_gpu)) {
94 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
95 REG_ADRENO_CP_RB_RPTR_ADDR_HI,
96 rbmemptr(adreno_gpu, rptr));
97 }
Rob Clark7198e6b2013-07-19 12:59:32 -040098
99 return 0;
100}
101
102static uint32_t get_wptr(struct msm_ringbuffer *ring)
103{
104 return ring->cur - ring->start;
105}
106
Craig Stout7d0c5ee2016-02-18 16:50:02 -0800107/* Use this helper to read rptr, since a430 doesn't update rptr in memory */
108static uint32_t get_rptr(struct adreno_gpu *adreno_gpu)
109{
110 if (adreno_is_a430(adreno_gpu))
111 return adreno_gpu->memptrs->rptr = adreno_gpu_read(
112 adreno_gpu, REG_ADRENO_CP_RB_RPTR);
113 else
114 return adreno_gpu->memptrs->rptr;
115}
116
Rob Clark7198e6b2013-07-19 12:59:32 -0400117uint32_t adreno_last_fence(struct msm_gpu *gpu)
118{
119 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
120 return adreno_gpu->memptrs->fence;
121}
122
Rob Clarkbd6f82d2013-08-24 14:20:38 -0400123void adreno_recover(struct msm_gpu *gpu)
124{
Rob Clarkbd6f82d2013-08-24 14:20:38 -0400125 struct drm_device *dev = gpu->dev;
126 int ret;
127
Rob Clarkeeb75472017-02-10 15:36:33 -0500128 // XXX pm-runtime?? we *need* the device to be off after this
129 // so maybe continuing to call ->pm_suspend/resume() is better?
130
Rob Clarkbd6f82d2013-08-24 14:20:38 -0400131 gpu->funcs->pm_suspend(gpu);
Rob Clarkbd6f82d2013-08-24 14:20:38 -0400132 gpu->funcs->pm_resume(gpu);
Jordan Crouse4ac277c2016-11-28 12:28:32 -0700133
Rob Clarkeeb75472017-02-10 15:36:33 -0500134 ret = msm_gpu_hw_init(gpu);
Rob Clarkbd6f82d2013-08-24 14:20:38 -0400135 if (ret) {
136 dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
137 /* hmm, oh well? */
138 }
139}
140
Rob Clark1193c3b2016-05-03 09:46:49 -0400141void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
Rob Clark7198e6b2013-07-19 12:59:32 -0400142 struct msm_file_private *ctx)
143{
144 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
145 struct msm_drm_private *priv = gpu->dev->dev_private;
146 struct msm_ringbuffer *ring = gpu->rb;
Rob Clark6b597ce2016-06-01 14:17:40 -0400147 unsigned i;
Rob Clark7198e6b2013-07-19 12:59:32 -0400148
Rob Clark7198e6b2013-07-19 12:59:32 -0400149 for (i = 0; i < submit->nr_cmds; i++) {
150 switch (submit->cmd[i].type) {
151 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
152 /* ignore IB-targets */
153 break;
154 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
155 /* ignore if there has not been a ctx switch: */
156 if (priv->lastctx == ctx)
157 break;
158 case MSM_SUBMIT_CMD_BUF:
Craig Stout357ff002016-02-18 16:50:00 -0800159 OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ?
160 CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
Rob Clark7198e6b2013-07-19 12:59:32 -0400161 OUT_RING(ring, submit->cmd[i].iova);
162 OUT_RING(ring, submit->cmd[i].size);
Rob Clark6b597ce2016-06-01 14:17:40 -0400163 OUT_PKT2(ring);
Rob Clark7198e6b2013-07-19 12:59:32 -0400164 break;
165 }
166 }
167
Rob Clark7198e6b2013-07-19 12:59:32 -0400168 OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
Rob Clarkb6295f92016-03-15 18:26:28 -0400169 OUT_RING(ring, submit->fence->seqno);
Rob Clark7198e6b2013-07-19 12:59:32 -0400170
Aravind Ganesan23bd62f2014-09-08 13:40:16 -0600171 if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) {
Rob Clark7198e6b2013-07-19 12:59:32 -0400172 /* Flush HLSQ lazy updates to make sure there is nothing
173 * pending for indirect loads after the timestamp has
174 * passed:
175 */
176 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
177 OUT_RING(ring, HLSQ_FLUSH);
178
179 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
180 OUT_RING(ring, 0x00000000);
181 }
182
183 OUT_PKT3(ring, CP_EVENT_WRITE, 3);
184 OUT_RING(ring, CACHE_FLUSH_TS);
185 OUT_RING(ring, rbmemptr(adreno_gpu, fence));
Rob Clarkb6295f92016-03-15 18:26:28 -0400186 OUT_RING(ring, submit->fence->seqno);
Rob Clark7198e6b2013-07-19 12:59:32 -0400187
188 /* we could maybe be clever and only CP_COND_EXEC the interrupt: */
189 OUT_PKT3(ring, CP_INTERRUPT, 1);
190 OUT_RING(ring, 0x80000000);
191
Rob Clarkd735fdc2015-05-12 11:29:40 -0400192 /* Workaround for missing irq issue on 8x16/a306. Unsure if the
193 * root cause is a platform issue or some a306 quirk, but this
194 * keeps things humming along:
195 */
196 if (adreno_is_a306(adreno_gpu)) {
197 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
198 OUT_RING(ring, 0x00000000);
199 OUT_PKT3(ring, CP_INTERRUPT, 1);
200 OUT_RING(ring, 0x80000000);
201 }
202
Rob Clark7198e6b2013-07-19 12:59:32 -0400203#if 0
204 if (adreno_is_a3xx(adreno_gpu)) {
205 /* Dummy set-constant to trigger context rollover */
206 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
207 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
208 OUT_RING(ring, 0x00000000);
209 }
210#endif
211
212 gpu->funcs->flush(gpu);
Rob Clark7198e6b2013-07-19 12:59:32 -0400213}
214
215void adreno_flush(struct msm_gpu *gpu)
216{
Aravind Ganesan91b74e92014-09-08 10:57:28 -0600217 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
Jordan Crouse88b333b2016-12-20 08:54:29 -0700218 uint32_t wptr;
219
220 /*
221 * Mask wptr value that we calculate to fit in the HW range. This is
222 * to account for the possibility that the last command fit exactly into
223 * the ringbuffer and rb->next hasn't wrapped to zero yet
224 */
225 wptr = get_wptr(gpu->rb) & ((gpu->rb->size / 4) - 1);
Rob Clark7198e6b2013-07-19 12:59:32 -0400226
227 /* ensure writes to ringbuffer have hit system memory: */
228 mb();
229
Aravind Ganesan91b74e92014-09-08 10:57:28 -0600230 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
Rob Clark7198e6b2013-07-19 12:59:32 -0400231}
232
Jordan Crousec4a8d4752016-11-28 12:28:27 -0700233bool adreno_idle(struct msm_gpu *gpu)
Rob Clark7198e6b2013-07-19 12:59:32 -0400234{
235 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
Rob Clark09637562014-01-11 16:11:59 -0500236 uint32_t wptr = get_wptr(gpu->rb);
Rob Clark7198e6b2013-07-19 12:59:32 -0400237
Rob Clark09637562014-01-11 16:11:59 -0500238 /* wait for CP to drain ringbuffer: */
Jordan Crousec4a8d4752016-11-28 12:28:27 -0700239 if (!spin_until(get_rptr(adreno_gpu) == wptr))
240 return true;
Rob Clark7198e6b2013-07-19 12:59:32 -0400241
242 /* TODO maybe we need to reset GPU here to recover from hang? */
Jordan Crousec4a8d4752016-11-28 12:28:27 -0700243 DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name);
244 return false;
Rob Clark7198e6b2013-07-19 12:59:32 -0400245}
246
247#ifdef CONFIG_DEBUG_FS
248void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
249{
250 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
Rob Clark3bcefb02014-09-05 15:05:38 -0400251 int i;
Rob Clark7198e6b2013-07-19 12:59:32 -0400252
253 seq_printf(m, "revision: %d (%d.%d.%d.%d)\n",
254 adreno_gpu->info->revn, adreno_gpu->rev.core,
255 adreno_gpu->rev.major, adreno_gpu->rev.minor,
256 adreno_gpu->rev.patchid);
257
258 seq_printf(m, "fence: %d/%d\n", adreno_gpu->memptrs->fence,
Rob Clarkca762a82016-03-15 17:22:13 -0400259 gpu->fctx->last_fence);
Craig Stout7d0c5ee2016-02-18 16:50:02 -0800260 seq_printf(m, "rptr: %d\n", get_rptr(adreno_gpu));
Rob Clark7198e6b2013-07-19 12:59:32 -0400261 seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr);
262 seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb));
Rob Clark3bcefb02014-09-05 15:05:38 -0400263
Rob Clark3bcefb02014-09-05 15:05:38 -0400264 /* dump these out in a form that can be parsed by demsm: */
265 seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->name);
266 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
267 uint32_t start = adreno_gpu->registers[i];
268 uint32_t end = adreno_gpu->registers[i+1];
269 uint32_t addr;
270
271 for (addr = start; addr <= end; addr++) {
272 uint32_t val = gpu_read(gpu, addr);
273 seq_printf(m, "IO:R %08x %08x\n", addr<<2, val);
274 }
275 }
Rob Clark7198e6b2013-07-19 12:59:32 -0400276}
277#endif
278
Rob Clark26716182015-04-19 10:14:09 -0400279/* Dump common gpu status and scratch registers on any hang, to make
280 * the hangcheck logs more useful. The scratch registers seem always
281 * safe to read when GPU has hung (unlike some other regs, depending
282 * on how the GPU hung), and they are useful to match up to cmdstream
283 * dumps when debugging hangs:
284 */
285void adreno_dump_info(struct msm_gpu *gpu)
Rob Clark5b6ef082013-12-22 10:29:43 -0500286{
287 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
288
289 printk("revision: %d (%d.%d.%d.%d)\n",
290 adreno_gpu->info->revn, adreno_gpu->rev.core,
291 adreno_gpu->rev.major, adreno_gpu->rev.minor,
292 adreno_gpu->rev.patchid);
293
294 printk("fence: %d/%d\n", adreno_gpu->memptrs->fence,
Rob Clarkca762a82016-03-15 17:22:13 -0400295 gpu->fctx->last_fence);
Craig Stout7d0c5ee2016-02-18 16:50:02 -0800296 printk("rptr: %d\n", get_rptr(adreno_gpu));
Rob Clark5b6ef082013-12-22 10:29:43 -0500297 printk("wptr: %d\n", adreno_gpu->memptrs->wptr);
298 printk("rb wptr: %d\n", get_wptr(gpu->rb));
Rob Clark26716182015-04-19 10:14:09 -0400299}
300
301/* would be nice to not have to duplicate the _show() stuff with printk(): */
302void adreno_dump(struct msm_gpu *gpu)
303{
304 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
305 int i;
306
Rob Clark3bcefb02014-09-05 15:05:38 -0400307 /* dump these out in a form that can be parsed by demsm: */
308 printk("IO:region %s 00000000 00020000\n", gpu->name);
309 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
310 uint32_t start = adreno_gpu->registers[i];
311 uint32_t end = adreno_gpu->registers[i+1];
312 uint32_t addr;
313
314 for (addr = start; addr <= end; addr++) {
315 uint32_t val = gpu_read(gpu, addr);
316 printk("IO:R %08x %08x\n", addr<<2, val);
317 }
318 }
Rob Clark5b6ef082013-12-22 10:29:43 -0500319}
320
Rob Clark09637562014-01-11 16:11:59 -0500321static uint32_t ring_freewords(struct msm_gpu *gpu)
Rob Clark7198e6b2013-07-19 12:59:32 -0400322{
323 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
Rob Clark09637562014-01-11 16:11:59 -0500324 uint32_t size = gpu->rb->size / 4;
325 uint32_t wptr = get_wptr(gpu->rb);
Craig Stout7d0c5ee2016-02-18 16:50:02 -0800326 uint32_t rptr = get_rptr(adreno_gpu);
Rob Clark09637562014-01-11 16:11:59 -0500327 return (rptr + (size - 1) - wptr) % size;
328}
Rob Clark26791c42013-09-03 07:12:03 -0400329
Rob Clark09637562014-01-11 16:11:59 -0500330void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords)
331{
332 if (spin_until(ring_freewords(gpu) >= ndwords))
333 DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name);
Rob Clark7198e6b2013-07-19 12:59:32 -0400334}
335
336static const char *iommu_ports[] = {
337 "gfx3d_user", "gfx3d_priv",
338 "gfx3d1_user", "gfx3d1_priv",
339};
340
Rob Clark7198e6b2013-07-19 12:59:32 -0400341int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
Rob Clark3526e9f2014-09-05 15:03:40 -0400342 struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs)
Rob Clark7198e6b2013-07-19 12:59:32 -0400343{
Rob Clark3526e9f2014-09-05 15:03:40 -0400344 struct adreno_platform_config *config = pdev->dev.platform_data;
345 struct msm_gpu *gpu = &adreno_gpu->base;
Rob Clarke2550b72014-09-05 13:30:27 -0400346 int ret;
Rob Clark7198e6b2013-07-19 12:59:32 -0400347
Rob Clark3526e9f2014-09-05 15:03:40 -0400348 adreno_gpu->funcs = funcs;
349 adreno_gpu->info = adreno_info(config->rev);
350 adreno_gpu->gmem = adreno_gpu->info->gmem;
351 adreno_gpu->revn = adreno_gpu->info->revn;
352 adreno_gpu->rev = config->rev;
Rob Clark7198e6b2013-07-19 12:59:32 -0400353
Rob Clark3526e9f2014-09-05 15:03:40 -0400354 gpu->fast_rate = config->fast_rate;
355 gpu->slow_rate = config->slow_rate;
356 gpu->bus_freq = config->bus_freq;
Rob Clark6490ad42015-06-04 10:26:37 -0400357#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
Rob Clark3526e9f2014-09-05 15:03:40 -0400358 gpu->bus_scale_table = config->bus_scale_table;
359#endif
360
361 DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
362 gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
363
Rob Clark0122f962014-10-31 11:50:55 -0400364 ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
365 adreno_gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq",
366 RB_SIZE);
367 if (ret)
368 return ret;
369
Rob Clarkeeb75472017-02-10 15:36:33 -0500370 pm_runtime_set_autosuspend_delay(&pdev->dev, DRM_MSM_INACTIVE_PERIOD);
371 pm_runtime_use_autosuspend(&pdev->dev);
372 pm_runtime_enable(&pdev->dev);
373
Rob Clark3526e9f2014-09-05 15:03:40 -0400374 ret = request_firmware(&adreno_gpu->pm4, adreno_gpu->info->pm4fw, drm->dev);
Rob Clark7198e6b2013-07-19 12:59:32 -0400375 if (ret) {
376 dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n",
Rob Clark3526e9f2014-09-05 15:03:40 -0400377 adreno_gpu->info->pm4fw, ret);
Rob Clark7198e6b2013-07-19 12:59:32 -0400378 return ret;
379 }
380
Rob Clark3526e9f2014-09-05 15:03:40 -0400381 ret = request_firmware(&adreno_gpu->pfp, adreno_gpu->info->pfpfw, drm->dev);
Rob Clark7198e6b2013-07-19 12:59:32 -0400382 if (ret) {
383 dev_err(drm->dev, "failed to load %s PFP firmware: %d\n",
Rob Clark3526e9f2014-09-05 15:03:40 -0400384 adreno_gpu->info->pfpfw, ret);
Rob Clark7198e6b2013-07-19 12:59:32 -0400385 return ret;
386 }
387
Rob Clarkde85d2b2017-01-12 17:41:44 -0500388 if (gpu->aspace && gpu->aspace->mmu) {
389 struct msm_mmu *mmu = gpu->aspace->mmu;
Rob Clark871d8122013-11-16 12:56:06 -0500390 ret = mmu->funcs->attach(mmu, iommu_ports,
391 ARRAY_SIZE(iommu_ports));
392 if (ret)
393 return ret;
394 }
Rob Clark7198e6b2013-07-19 12:59:32 -0400395
Rob Clarka1ad3522014-07-11 11:59:22 -0400396 mutex_lock(&drm->struct_mutex);
Rob Clark3526e9f2014-09-05 15:03:40 -0400397 adreno_gpu->memptrs_bo = msm_gem_new(drm, sizeof(*adreno_gpu->memptrs),
Rob Clark7198e6b2013-07-19 12:59:32 -0400398 MSM_BO_UNCACHED);
Rob Clarka1ad3522014-07-11 11:59:22 -0400399 mutex_unlock(&drm->struct_mutex);
Rob Clark3526e9f2014-09-05 15:03:40 -0400400 if (IS_ERR(adreno_gpu->memptrs_bo)) {
401 ret = PTR_ERR(adreno_gpu->memptrs_bo);
402 adreno_gpu->memptrs_bo = NULL;
Rob Clark7198e6b2013-07-19 12:59:32 -0400403 dev_err(drm->dev, "could not allocate memptrs: %d\n", ret);
404 return ret;
405 }
406
Rob Clark18f23042016-05-26 16:24:35 -0400407 adreno_gpu->memptrs = msm_gem_get_vaddr(adreno_gpu->memptrs_bo);
Rob Clark69a834c2016-05-24 18:29:38 -0400408 if (IS_ERR(adreno_gpu->memptrs)) {
Rob Clark7198e6b2013-07-19 12:59:32 -0400409 dev_err(drm->dev, "could not vmap memptrs\n");
410 return -ENOMEM;
411 }
412
Rob Clark3526e9f2014-09-05 15:03:40 -0400413 ret = msm_gem_get_iova(adreno_gpu->memptrs_bo, gpu->id,
414 &adreno_gpu->memptrs_iova);
Rob Clark7198e6b2013-07-19 12:59:32 -0400415 if (ret) {
416 dev_err(drm->dev, "could not map memptrs: %d\n", ret);
417 return ret;
418 }
419
420 return 0;
421}
422
Jordan Crouse9873ef02017-02-06 10:39:29 -0700423void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
Rob Clark7198e6b2013-07-19 12:59:32 -0400424{
Jordan Crouse9873ef02017-02-06 10:39:29 -0700425 struct msm_gpu *gpu = &adreno_gpu->base;
Rob Clark18f23042016-05-26 16:24:35 -0400426
Jordan Crouse9873ef02017-02-06 10:39:29 -0700427 if (adreno_gpu->memptrs_bo) {
428 if (adreno_gpu->memptrs)
429 msm_gem_put_vaddr(adreno_gpu->memptrs_bo);
Rob Clark18f23042016-05-26 16:24:35 -0400430
Jordan Crouse9873ef02017-02-06 10:39:29 -0700431 if (adreno_gpu->memptrs_iova)
432 msm_gem_put_iova(adreno_gpu->memptrs_bo, gpu->id);
433
434 drm_gem_object_unreference_unlocked(adreno_gpu->memptrs_bo);
Rob Clark7198e6b2013-07-19 12:59:32 -0400435 }
Jordan Crouse9873ef02017-02-06 10:39:29 -0700436 release_firmware(adreno_gpu->pm4);
437 release_firmware(adreno_gpu->pfp);
438
439 msm_gpu_cleanup(gpu);
440
441 if (gpu->aspace) {
442 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu,
443 iommu_ports, ARRAY_SIZE(iommu_ports));
Jordan Crouseee546cd2017-03-07 10:02:52 -0700444 msm_gem_address_space_put(gpu->aspace);
Jordan Crouse9873ef02017-02-06 10:39:29 -0700445 }
Rob Clark7198e6b2013-07-19 12:59:32 -0400446}