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| <h4 class="subsection">G.5.15 TMS320C6x Features</h4> |
| |
| <p><a name="index-target-descriptions_002c-TIC6x-features-3674"></a><a name="index-target-descriptions_002c-TMS320C6x-features-3675"></a>The ‘<samp><span class="samp">org.gnu.gdb.tic6x.core</span></samp>’ feature is required for TMS320C6x |
| targets. It should contain registers ‘<samp><span class="samp">A0</span></samp>’ through ‘<samp><span class="samp">A15</span></samp>’, |
| registers ‘<samp><span class="samp">B0</span></samp>’ through ‘<samp><span class="samp">B15</span></samp>’, ‘<samp><span class="samp">CSR</span></samp>’ and ‘<samp><span class="samp">PC</span></samp>’. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.tic6x.gp</span></samp>’ feature is optional. It should |
| contain registers ‘<samp><span class="samp">A16</span></samp>’ through ‘<samp><span class="samp">A31</span></samp>’ and ‘<samp><span class="samp">B16</span></samp>’ |
| through ‘<samp><span class="samp">B31</span></samp>’. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.tic6x.c6xp</span></samp>’ feature is optional. It should |
| contain registers ‘<samp><span class="samp">TSR</span></samp>’, ‘<samp><span class="samp">ILC</span></samp>’ and ‘<samp><span class="samp">RILC</span></samp>’. |
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