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Amit S. Kale3d396eb2006-10-21 15:33:03 -04001/*
Dhananjay Phadke5d242f12009-02-25 15:57:56 +00002 * Copyright (C) 2003 - 2009 NetXen, Inc.
Amit S. Kale3d396eb2006-10-21 15:33:03 -04003 * All rights reserved.
Amit S. Kale80922fb2006-12-04 09:18:00 -08004 *
Amit S. Kale3d396eb2006-10-21 15:33:03 -04005 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
Amit S. Kale80922fb2006-12-04 09:18:00 -08009 *
Amit S. Kale3d396eb2006-10-21 15:33:03 -040010 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Amit S. Kale80922fb2006-12-04 09:18:00 -080014 *
Amit S. Kale3d396eb2006-10-21 15:33:03 -040015 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
Amit S. Kale80922fb2006-12-04 09:18:00 -080019 *
Amit S. Kale3d396eb2006-10-21 15:33:03 -040020 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
Amit S. Kale80922fb2006-12-04 09:18:00 -080022 *
Amit S. Kale3d396eb2006-10-21 15:33:03 -040023 * Contact Information:
24 * info@netxen.com
Dhananjay Phadke5d242f12009-02-25 15:57:56 +000025 * NetXen Inc,
26 * 18922 Forge Drive
27 * Cupertino, CA 95014-0701
28 *
Amit S. Kale3d396eb2006-10-21 15:33:03 -040029 */
30
31#ifndef _NETXEN_NIC_H_
32#define _NETXEN_NIC_H_
33
Amit S. Kale3d396eb2006-10-21 15:33:03 -040034#include <linux/module.h>
35#include <linux/kernel.h>
36#include <linux/types.h>
37#include <linux/compiler.h>
38#include <linux/slab.h>
39#include <linux/delay.h>
40#include <linux/init.h>
41#include <linux/ioport.h>
42#include <linux/pci.h>
43#include <linux/netdevice.h>
44#include <linux/etherdevice.h>
45#include <linux/ip.h>
46#include <linux/in.h>
47#include <linux/tcp.h>
48#include <linux/skbuff.h>
Amit S. Kale3d396eb2006-10-21 15:33:03 -040049
50#include <linux/ethtool.h>
51#include <linux/mii.h>
52#include <linux/interrupt.h>
53#include <linux/timer.h>
54
55#include <linux/mm.h>
56#include <linux/mman.h>
David S. Miller42555892008-07-22 18:29:10 -070057#include <linux/vmalloc.h>
Amit S. Kale3d396eb2006-10-21 15:33:03 -040058
59#include <asm/system.h>
60#include <asm/io.h>
61#include <asm/byteorder.h>
62#include <asm/uaccess.h>
63#include <asm/pgtable.h>
64
65#include "netxen_nic_hw.h"
66
Dhananjay Phadke58735562008-07-21 19:44:10 -070067#define _NETXEN_NIC_LINUX_MAJOR 4
68#define _NETXEN_NIC_LINUX_MINOR 0
Dhananjay Phadke11d89d62008-08-08 00:08:45 -070069#define _NETXEN_NIC_LINUX_SUBVERSION 11
70#define NETXEN_NIC_LINUX_VERSIONID "4.0.11"
Dhananjay Phadke58735562008-07-21 19:44:10 -070071
72#define NETXEN_VERSION_CODE(a, b, c) (((a) << 16) + ((b) << 8) + (c))
Amit S. Kale27d2ab52007-02-05 07:40:49 -080073
Mithlesh Thukral0d047612007-06-07 04:36:36 -070074#define NETXEN_NUM_FLASH_SECTORS (64)
75#define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
76#define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
77 * NETXEN_FLASH_SECTOR_SIZE)
Amit S. Kale3d396eb2006-10-21 15:33:03 -040078
Linsys Contractor Mithlesh Thukral0c25cfe2007-02-28 05:14:07 -080079#define PHAN_VENDOR_ID 0x4040
80
Amit S. Kale3d396eb2006-10-21 15:33:03 -040081#define RCV_DESC_RINGSIZE \
82 (sizeof(struct rcv_desc) * adapter->max_rx_desc_count)
83#define STATUS_DESC_RINGSIZE \
84 (sizeof(struct status_desc)* adapter->max_rx_desc_count)
Amit S. Kaleed25ffa2006-12-04 09:23:25 -080085#define LRO_DESC_RINGSIZE \
86 (sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count)
Amit S. Kale3d396eb2006-10-21 15:33:03 -040087#define TX_RINGSIZE \
88 (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count)
89#define RCV_BUFFSIZE \
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -070090 (sizeof(struct netxen_rx_buffer) * rds_ring->max_rx_desc_count)
Dhananjay Phadkeba53e6b2008-03-17 19:59:50 -070091#define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
Amit S. Kale3d396eb2006-10-21 15:33:03 -040092
Amit S. Kaleed25ffa2006-12-04 09:23:25 -080093#define NETXEN_RCV_PRODUCER_OFFSET 0
94#define NETXEN_RCV_PEG_DB_ID 2
95#define NETXEN_HOST_DUMMY_DMA_SIZE 1024
Amit S. Kale27d2ab52007-02-05 07:40:49 -080096#define FLASH_SUCCESS 0
Amit S. Kale3d396eb2006-10-21 15:33:03 -040097
98#define ADDR_IN_WINDOW1(off) \
99 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
100
Jeff Garzik47906542007-11-23 21:23:36 -0500101/*
102 * normalize a 64MB crb address to 32MB PCI window
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400103 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
104 */
Amit S. Kale80922fb2006-12-04 09:18:00 -0800105#define NETXEN_CRB_NORMAL(reg) \
106 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
Amit S. Kalecb8011a2006-11-29 09:00:10 -0800107
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400108#define NETXEN_CRB_NORMALIZE(adapter, reg) \
Amit S. Kalecb8011a2006-11-29 09:00:10 -0800109 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
110
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800111#define DB_NORMALIZE(adapter, off) \
112 (adapter->ahw.db_base + (off))
113
114#define NX_P2_C0 0x24
115#define NX_P2_C1 0x25
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -0700116#define NX_P3_A0 0x30
117#define NX_P3_A2 0x30
118#define NX_P3_B0 0x40
119#define NX_P3_B1 0x41
120
121#define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
122#define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800123
Amit S. Kalecb8011a2006-11-29 09:00:10 -0800124#define FIRST_PAGE_GROUP_START 0
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800125#define FIRST_PAGE_GROUP_END 0x100000
Amit S. Kalecb8011a2006-11-29 09:00:10 -0800126
Mithlesh Thukral78403a92007-04-20 07:57:26 -0700127#define SECOND_PAGE_GROUP_START 0x6000000
128#define SECOND_PAGE_GROUP_END 0x68BC000
Amit S. Kalecb8011a2006-11-29 09:00:10 -0800129
130#define THIRD_PAGE_GROUP_START 0x70E4000
131#define THIRD_PAGE_GROUP_END 0x8000000
132
133#define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
134#define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
135#define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400136
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -0700137#define P2_MAX_MTU (8000)
138#define P3_MAX_MTU (9600)
139#define NX_ETHERMTU 1500
140#define NX_MAX_ETHERHDR 32 /* This contains some padding */
141
142#define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
143#define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
144#define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
Dhananjay Phadked9e651b2008-07-21 19:44:08 -0700145#define NX_CT_DEFAULT_RX_BUF_LEN 2048
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -0700146
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800147#define MAX_RX_BUFFER_LENGTH 1760
Amit S. Kalebd56c6b2006-12-18 05:54:36 -0800148#define MAX_RX_JUMBO_BUFFER_LENGTH 8062
Dhananjay Phadke32ec8032009-01-26 12:35:19 -0800149#define MAX_RX_LRO_BUFFER_LENGTH (8062)
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800150#define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2)
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400151#define RX_JUMBO_DMA_MAP_LEN \
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800152 (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
153#define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2)
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400154
155/*
156 * Maximum number of ring contexts
157 */
158#define MAX_RING_CTX 1
159
160/* Opcodes to be used with the commands */
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -0700161#define TX_ETHER_PKT 0x01
162#define TX_TCP_PKT 0x02
163#define TX_UDP_PKT 0x03
164#define TX_IP_PKT 0x04
165#define TX_TCP_LSO 0x05
166#define TX_TCP_LSO6 0x06
167#define TX_IPSEC 0x07
168#define TX_IPSEC_CMD 0x0a
169#define TX_TCPV6_PKT 0x0b
170#define TX_UDPV6_PKT 0x0c
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400171
172/* The following opcodes are for internal consumption. */
173#define NETXEN_CONTROL_OP 0x10
174#define PEGNET_REQUEST 0x11
175
176#define MAX_NUM_CARDS 4
177
178#define MAX_BUFFERS_PER_CMD 32
179
180/*
181 * Following are the states of the Phantom. Phantom will set them and
182 * Host will read to check if the fields are correct.
183 */
184#define PHAN_INITIALIZE_START 0xff00
185#define PHAN_INITIALIZE_FAILED 0xffff
186#define PHAN_INITIALIZE_COMPLETE 0xff01
187
188/* Host writes the following to notify that it has done the init-handshake */
189#define PHAN_INITIALIZE_ACK 0xf00f
190
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800191#define NUM_RCV_DESC_RINGS 3 /* No of Rcv Descriptor contexts */
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400192
193/* descriptor types */
194#define RCV_DESC_NORMAL 0x01
195#define RCV_DESC_JUMBO 0x02
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800196#define RCV_DESC_LRO 0x04
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400197#define RCV_DESC_NORMAL_CTXID 0
198#define RCV_DESC_JUMBO_CTXID 1
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800199#define RCV_DESC_LRO_CTXID 2
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400200
201#define RCV_DESC_TYPE(ID) \
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800202 ((ID == RCV_DESC_JUMBO_CTXID) \
203 ? RCV_DESC_JUMBO \
204 : ((ID == RCV_DESC_LRO_CTXID) \
205 ? RCV_DESC_LRO : \
206 (RCV_DESC_NORMAL)))
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400207
Dhananjay Phadkeba53e6b2008-03-17 19:59:50 -0700208#define MAX_CMD_DESCRIPTORS 4096
Amit S. Kalebd56c6b2006-12-18 05:54:36 -0800209#define MAX_RCV_DESCRIPTORS 16384
Dhananjay Phadke32ec8032009-01-26 12:35:19 -0800210#define MAX_CMD_DESCRIPTORS_HOST 1024
211#define MAX_RCV_DESCRIPTORS_1G 2048
212#define MAX_RCV_DESCRIPTORS_10G 4096
Dhananjay Phadkee1256462009-01-29 16:05:19 -0800213#define MAX_JUMBO_RCV_DESCRIPTORS 1024
Dhananjay Phadke32ec8032009-01-26 12:35:19 -0800214#define MAX_LRO_RCV_DESCRIPTORS 8
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400215#define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS
216#define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS
217#define MAX_RCV_DESC MAX_RCV_DESCRIPTORS
218#define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400219#define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8)
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800220#define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \
221 MAX_LRO_RCV_DESCRIPTORS)
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400222#define MIN_TX_COUNT 4096
223#define MIN_RX_COUNT 4096
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800224#define NETXEN_CTX_SIGNATURE 0xdee0
225#define NETXEN_RCV_PRODUCER(ringid) (ringid)
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400226#define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */
227
228#define PHAN_PEG_RCV_INITIALIZED 0xff01
229#define PHAN_PEG_RCV_START_INITIALIZE 0xff00
230
231#define get_next_index(index, length) \
232 (((index) + 1) & ((length) - 1))
233
234#define get_index_range(index,length,count) \
235 (((index) + (count)) & ((length) - 1))
236
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800237#define MPORT_SINGLE_FUNCTION_MODE 0x1111
Mithlesh Thukral3176ff32007-04-20 07:52:37 -0700238#define MPORT_MULTI_FUNCTION_MODE 0x2222
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800239
Mithlesh Thukral3176ff32007-04-20 07:52:37 -0700240#include "netxen_nic_phan_reg.h"
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800241
242/*
243 * NetXen host-peg signal message structure
244 *
245 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
246 * Bit 2 : priv_id => must be 1
247 * Bit 3-17 : count => for doorbell
248 * Bit 18-27 : ctx_id => Context id
249 * Bit 28-31 : opcode
250 */
251
252typedef u32 netxen_ctx_msg;
253
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800254#define netxen_set_msg_peg_id(config_word, val) \
Al Viroa608ab9c2007-01-02 10:39:10 +0000255 ((config_word) &= ~3, (config_word) |= val & 3)
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800256#define netxen_set_msg_privid(config_word) \
Al Viroa608ab9c2007-01-02 10:39:10 +0000257 ((config_word) |= 1 << 2)
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800258#define netxen_set_msg_count(config_word, val) \
Al Viroa608ab9c2007-01-02 10:39:10 +0000259 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800260#define netxen_set_msg_ctxid(config_word, val) \
Al Viroa608ab9c2007-01-02 10:39:10 +0000261 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800262#define netxen_set_msg_opcode(config_word, val) \
Amit S. Kale82581172007-02-12 04:33:38 -0800263 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800264
265struct netxen_rcv_context {
Al Viroa608ab9c2007-01-02 10:39:10 +0000266 __le64 rcv_ring_addr;
267 __le32 rcv_ring_size;
268 __le32 rsrvd;
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800269};
270
271struct netxen_ring_ctx {
272
273 /* one command ring */
Al Viroa608ab9c2007-01-02 10:39:10 +0000274 __le64 cmd_consumer_offset;
275 __le64 cmd_ring_addr;
276 __le32 cmd_ring_size;
277 __le32 rsrvd;
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800278
279 /* three receive rings */
280 struct netxen_rcv_context rcv_ctx[3];
281
282 /* one status ring */
Al Viroa608ab9c2007-01-02 10:39:10 +0000283 __le64 sts_ring_addr;
284 __le32 sts_ring_size;
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800285
Al Viroa608ab9c2007-01-02 10:39:10 +0000286 __le32 ctx_id;
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800287} __attribute__ ((aligned(64)));
288
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400289/*
290 * Following data structures describe the descriptors that will be used.
291 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
292 * we are doing LSO (above the 1500 size packet) only.
293 */
294
295/*
296 * The size of reference handle been changed to 16 bits to pass the MSS fields
297 * for the LSO packet
298 */
299
300#define FLAGS_CHECKSUM_ENABLED 0x01
301#define FLAGS_LSO_ENABLED 0x02
302#define FLAGS_IPSEC_SA_ADD 0x04
303#define FLAGS_IPSEC_SA_DELETE 0x08
304#define FLAGS_VLAN_TAGGED 0x10
305
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800306#define netxen_set_cmd_desc_port(cmd_desc, var) \
307 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
Mithlesh Thukral6c80b182007-04-20 07:55:26 -0700308#define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -0700309 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400310
Dhananjay Phadke391587c2009-01-14 20:48:11 -0800311#define netxen_set_tx_port(_desc, _port) \
312 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800313
Dhananjay Phadke391587c2009-01-14 20:48:11 -0800314#define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
315 (_desc)->flags_opcode = \
316 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800317
Dhananjay Phadke391587c2009-01-14 20:48:11 -0800318#define netxen_set_tx_frags_len(_desc, _frags, _len) \
319 (_desc)->num_of_buffers_total_length = \
320 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400321
322struct cmd_desc_type0 {
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800323 u8 tcp_hdr_offset; /* For LSO only */
324 u8 ip_hdr_offset; /* For LSO only */
325 /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
Al Viroa608ab9c2007-01-02 10:39:10 +0000326 __le16 flags_opcode;
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800327 /* Bit pattern: 0-7 total number of segments,
328 8-31 Total size of the packet */
Al Viroa608ab9c2007-01-02 10:39:10 +0000329 __le32 num_of_buffers_total_length;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400330 union {
331 struct {
Al Viroa608ab9c2007-01-02 10:39:10 +0000332 __le32 addr_low_part2;
333 __le32 addr_high_part2;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400334 };
Al Viroa608ab9c2007-01-02 10:39:10 +0000335 __le64 addr_buffer2;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400336 };
337
Al Viroa608ab9c2007-01-02 10:39:10 +0000338 __le16 reference_handle; /* changed to u16 to add mss */
339 __le16 mss; /* passed by NDIS_PACKET for LSO */
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400340 /* Bit pattern 0-3 port, 0-3 ctx id */
341 u8 port_ctxid;
342 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
Al Viroa608ab9c2007-01-02 10:39:10 +0000343 __le16 conn_id; /* IPSec offoad only */
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400344
345 union {
346 struct {
Al Viroa608ab9c2007-01-02 10:39:10 +0000347 __le32 addr_low_part3;
348 __le32 addr_high_part3;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400349 };
Al Viroa608ab9c2007-01-02 10:39:10 +0000350 __le64 addr_buffer3;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400351 };
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400352 union {
353 struct {
Al Viroa608ab9c2007-01-02 10:39:10 +0000354 __le32 addr_low_part1;
355 __le32 addr_high_part1;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400356 };
Al Viroa608ab9c2007-01-02 10:39:10 +0000357 __le64 addr_buffer1;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400358 };
359
Dhananjay Phadked32cc3d2009-03-09 08:50:53 +0000360 __le16 buffer_length[4];
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400361
362 union {
363 struct {
Al Viroa608ab9c2007-01-02 10:39:10 +0000364 __le32 addr_low_part4;
365 __le32 addr_high_part4;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400366 };
Al Viroa608ab9c2007-01-02 10:39:10 +0000367 __le64 addr_buffer4;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400368 };
369
Al Viroa608ab9c2007-01-02 10:39:10 +0000370 __le64 unused;
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800371
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400372} __attribute__ ((aligned(64)));
373
374/* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
375struct rcv_desc {
Al Viroa608ab9c2007-01-02 10:39:10 +0000376 __le16 reference_handle;
377 __le16 reserved;
378 __le32 buffer_length; /* allocated buffer length (usually 2K) */
379 __le64 addr_buffer;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400380};
381
382/* opcode field in status_desc */
Dhananjay Phadked9e651b2008-07-21 19:44:08 -0700383#define NETXEN_NIC_RXPKT_DESC 0x04
384#define NETXEN_OLD_RXPKT_DESC 0x3f
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400385
386/* for status field in status_desc */
387#define STATUS_NEED_CKSUM (1)
388#define STATUS_CKSUM_OK (2)
389
390/* owner bits of status_desc */
Dhananjay Phadke0ddc1102009-03-09 08:50:52 +0000391#define STATUS_OWNER_HOST (0x1ULL << 56)
392#define STATUS_OWNER_PHANTOM (0x2ULL << 56)
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400393
394/* Note: sizeof(status_desc) should always be a mutliple of 2 */
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800395
396#define netxen_get_sts_desc_lro_cnt(status_desc) \
397 ((status_desc)->lro & 0x7F)
398#define netxen_get_sts_desc_lro_last_frag(status_desc) \
399 (((status_desc)->lro & 0x80) >> 7)
400
Dhananjay Phadke5dc16262007-12-31 10:08:57 -0800401#define netxen_get_sts_port(sts_data) \
402 ((sts_data) & 0x0F)
403#define netxen_get_sts_status(sts_data) \
404 (((sts_data) >> 4) & 0x0F)
405#define netxen_get_sts_type(sts_data) \
406 (((sts_data) >> 8) & 0x0F)
407#define netxen_get_sts_totallength(sts_data) \
408 (((sts_data) >> 12) & 0xFFFF)
409#define netxen_get_sts_refhandle(sts_data) \
410 (((sts_data) >> 28) & 0xFFFF)
411#define netxen_get_sts_prot(sts_data) \
412 (((sts_data) >> 44) & 0x0F)
Dhananjay Phadked9e651b2008-07-21 19:44:08 -0700413#define netxen_get_sts_pkt_offset(sts_data) \
414 (((sts_data) >> 48) & 0x1F)
Dhananjay Phadke5dc16262007-12-31 10:08:57 -0800415#define netxen_get_sts_opcode(sts_data) \
416 (((sts_data) >> 58) & 0x03F)
417
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400418struct status_desc {
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800419 /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
Dhananjay Phadked9e651b2008-07-21 19:44:08 -0700420 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800421 53-55 desc_cnt, 56-57 owner, 58-63 opcode
422 */
Al Viroa608ab9c2007-01-02 10:39:10 +0000423 __le64 status_desc_data;
Dhananjay Phadked9e651b2008-07-21 19:44:08 -0700424 union {
425 struct {
426 __le32 hash_value;
427 u8 hash_type;
428 u8 msg_type;
429 u8 unused;
430 union {
431 /* Bit pattern: 0-6 lro_count indicates frag
432 * sequence, 7 last_frag indicates last frag
433 */
434 u8 lro;
435
436 /* chained buffers */
437 u8 nr_frags;
438 };
439 };
440 struct {
441 __le16 frag_handles[4];
442 };
443 };
Mithlesh Thukral6c80b182007-04-20 07:55:26 -0700444} __attribute__ ((aligned(16)));
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400445
446enum {
447 NETXEN_RCV_PEG_0 = 0,
448 NETXEN_RCV_PEG_1
449};
450/* The version of the main data structure */
451#define NETXEN_BDINFO_VERSION 1
452
453/* Magic number to let user know flash is programmed */
454#define NETXEN_BDINFO_MAGIC 0x12345678
455
456/* Max number of Gig ports on a Phantom board */
457#define NETXEN_MAX_PORTS 4
458
459typedef enum {
460 NETXEN_BRDTYPE_P1_BD = 0x0000,
461 NETXEN_BRDTYPE_P1_SB = 0x0001,
462 NETXEN_BRDTYPE_P1_SMAX = 0x0002,
463 NETXEN_BRDTYPE_P1_SOCK = 0x0003,
464
465 NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008,
466 NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009,
467 NETXEN_BRDTYPE_P2_SB35_4G = 0x000a,
468 NETXEN_BRDTYPE_P2_SB31_10G = 0x000b,
469 NETXEN_BRDTYPE_P2_SB31_2G = 0x000c,
470
471 NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
472 NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -0700473 NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f,
474
475 NETXEN_BRDTYPE_P3_REF_QG = 0x0021,
476 NETXEN_BRDTYPE_P3_HMEZ = 0x0022,
477 NETXEN_BRDTYPE_P3_10G_CX4_LP = 0x0023,
478 NETXEN_BRDTYPE_P3_4_GB = 0x0024,
479 NETXEN_BRDTYPE_P3_IMEZ = 0x0025,
480 NETXEN_BRDTYPE_P3_10G_SFP_PLUS = 0x0026,
481 NETXEN_BRDTYPE_P3_10000_BASE_T = 0x0027,
482 NETXEN_BRDTYPE_P3_XG_LOM = 0x0028,
483 NETXEN_BRDTYPE_P3_4_GB_MM = 0x0029,
Dhananjay Phadkea70f9392008-08-01 03:14:56 -0700484 NETXEN_BRDTYPE_P3_10G_SFP_CT = 0x002a,
485 NETXEN_BRDTYPE_P3_10G_SFP_QT = 0x002b,
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -0700486 NETXEN_BRDTYPE_P3_10G_CX4 = 0x0031,
Dhananjay Phadkec7860a22009-01-14 20:48:32 -0800487 NETXEN_BRDTYPE_P3_10G_XFP = 0x0032,
488 NETXEN_BRDTYPE_P3_10G_TP = 0x0080
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -0700489
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400490} netxen_brdtype_t;
491
492typedef enum {
493 NETXEN_BRDMFG_INVENTEC = 1
494} netxen_brdmfg;
495
496typedef enum {
497 MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */
498 MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */
499 MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */
500 MEM_ORG_256Mbx4 = 0x3,
501 MEM_ORG_256Mbx8 = 0x4,
502 MEM_ORG_256Mbx16 = 0x5,
503 MEM_ORG_512Mbx4 = 0x6,
504 MEM_ORG_512Mbx8 = 0x7,
505 MEM_ORG_512Mbx16 = 0x8,
506 MEM_ORG_1Gbx4 = 0x9,
507 MEM_ORG_1Gbx8 = 0xa,
508 MEM_ORG_1Gbx16 = 0xb,
509 MEM_ORG_2Gbx4 = 0xc,
510 MEM_ORG_2Gbx8 = 0xd,
511 MEM_ORG_2Gbx16 = 0xe,
512 MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */
513 MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */
514} netxen_mn_mem_org_t;
515
516typedef enum {
517 MEM_ORG_512Kx36 = 0x0,
518 MEM_ORG_1Mx36 = 0x1,
519 MEM_ORG_2Mx36 = 0x2
520} netxen_sn_mem_org_t;
521
522typedef enum {
523 MEM_DEPTH_4MB = 0x1,
524 MEM_DEPTH_8MB = 0x2,
525 MEM_DEPTH_16MB = 0x3,
526 MEM_DEPTH_32MB = 0x4,
527 MEM_DEPTH_64MB = 0x5,
528 MEM_DEPTH_128MB = 0x6,
529 MEM_DEPTH_256MB = 0x7,
530 MEM_DEPTH_512MB = 0x8,
531 MEM_DEPTH_1GB = 0x9,
532 MEM_DEPTH_2GB = 0xa,
533 MEM_DEPTH_4GB = 0xb,
534 MEM_DEPTH_8GB = 0xc,
535 MEM_DEPTH_16GB = 0xd,
536 MEM_DEPTH_32GB = 0xe
537} netxen_mem_depth_t;
538
539struct netxen_board_info {
540 u32 header_version;
541
542 u32 board_mfg;
543 u32 board_type;
544 u32 board_num;
545 u32 chip_id;
546 u32 chip_minor;
547 u32 chip_major;
548 u32 chip_pkg;
549 u32 chip_lot;
550
551 u32 port_mask; /* available niu ports */
552 u32 peg_mask; /* available pegs */
553 u32 icache_ok; /* can we run with icache? */
554 u32 dcache_ok; /* can we run with dcache? */
555 u32 casper_ok;
556
557 u32 mac_addr_lo_0;
558 u32 mac_addr_lo_1;
559 u32 mac_addr_lo_2;
560 u32 mac_addr_lo_3;
561
562 /* MN-related config */
563 u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
564 u32 mn_sync_shift_cclk;
565 u32 mn_sync_shift_mclk;
566 u32 mn_wb_en;
567 u32 mn_crystal_freq; /* in MHz */
568 u32 mn_speed; /* in MHz */
569 u32 mn_org;
570 u32 mn_depth;
571 u32 mn_ranks_0; /* ranks per slot */
572 u32 mn_ranks_1; /* ranks per slot */
573 u32 mn_rd_latency_0;
574 u32 mn_rd_latency_1;
575 u32 mn_rd_latency_2;
576 u32 mn_rd_latency_3;
577 u32 mn_rd_latency_4;
578 u32 mn_rd_latency_5;
579 u32 mn_rd_latency_6;
580 u32 mn_rd_latency_7;
581 u32 mn_rd_latency_8;
582 u32 mn_dll_val[18];
583 u32 mn_mode_reg; /* MIU DDR Mode Register */
584 u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
585 u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
586 u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
587 u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
588
589 /* SN-related config */
590 u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
591 u32 sn_pt_mode; /* pass through mode */
592 u32 sn_ecc_en;
593 u32 sn_wb_en;
594 u32 sn_crystal_freq;
595 u32 sn_speed;
596 u32 sn_org;
597 u32 sn_depth;
598 u32 sn_dll_tap;
599 u32 sn_rd_latency;
600
601 u32 mac_addr_hi_0;
602 u32 mac_addr_hi_1;
603 u32 mac_addr_hi_2;
604 u32 mac_addr_hi_3;
605
606 u32 magic; /* indicates flash has been initialized */
607
608 u32 mn_rdimm;
609 u32 mn_dll_override;
610
611};
612
613#define FLASH_NUM_PORTS (4)
614
615struct netxen_flash_mac_addr {
616 u32 flash_addr[32];
617};
618
619struct netxen_user_old_info {
620 u8 flash_md5[16];
621 u8 crbinit_md5[16];
622 u8 brdcfg_md5[16];
623 /* bootloader */
624 u32 bootld_version;
625 u32 bootld_size;
626 u8 bootld_md5[16];
627 /* image */
628 u32 image_version;
629 u32 image_size;
630 u8 image_md5[16];
631 /* primary image status */
632 u32 primary_status;
633 u32 secondary_present;
634
635 /* MAC address , 4 ports */
636 struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
637};
638#define FLASH_NUM_MAC_PER_PORT 32
639struct netxen_user_info {
640 u8 flash_md5[16 * 64];
641 /* bootloader */
642 u32 bootld_version;
643 u32 bootld_size;
644 /* image */
645 u32 image_version;
646 u32 image_size;
647 /* primary image status */
648 u32 primary_status;
649 u32 secondary_present;
650
651 /* MAC address , 4 ports, 32 address per port */
652 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
653 u32 sub_sys_id;
654 u8 serial_num[32];
655
656 /* Any user defined data */
657};
658
659/*
660 * Flash Layout - new format.
661 */
662struct netxen_new_user_info {
663 u8 flash_md5[16 * 64];
664 /* bootloader */
665 u32 bootld_version;
666 u32 bootld_size;
667 /* image */
668 u32 image_version;
669 u32 image_size;
670 /* primary image status */
671 u32 primary_status;
672 u32 secondary_present;
673
674 /* MAC address , 4 ports, 32 address per port */
675 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
676 u32 sub_sys_id;
677 u8 serial_num[32];
678
679 /* Any user defined data */
680};
681
682#define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
683#define SECONDARY_IMAGE_ABSENT 0xffffffff
684#define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
685#define PRIMARY_IMAGE_BAD 0xffffffff
686
687/* Flash memory map */
688typedef enum {
Mithlesh Thukral0d047612007-06-07 04:36:36 -0700689 NETXEN_CRBINIT_START = 0, /* Crbinit section */
690 NETXEN_BRDCFG_START = 0x4000, /* board config */
691 NETXEN_INITCODE_START = 0x6000, /* pegtune code */
692 NETXEN_BOOTLD_START = 0x10000, /* bootld */
693 NETXEN_IMAGE_START = 0x43000, /* compressed image */
694 NETXEN_SECONDARY_START = 0x200000, /* backup images */
695 NETXEN_PXE_START = 0x3E0000, /* user defined region */
696 NETXEN_USER_START = 0x3E8000, /* User defined region for new boards */
697 NETXEN_FIXED_START = 0x3F0000 /* backup of crbinit */
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400698} netxen_flash_map_t;
699
Dhananjay Phadkeba599d42009-02-24 16:38:22 -0800700#define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
701#define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
702#define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
703#define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
704#define NX_FW_MIN_SIZE (0x3fffff)
705#define NX_P2_MN_ROMIMAGE "nxromimg.bin"
706#define NX_P3_CT_ROMIMAGE "nx3fwct.bin"
707#define NX_P3_MN_ROMIMAGE "nx3fwmn.bin"
708
Mithlesh Thukral0d047612007-06-07 04:36:36 -0700709#define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400710
Mithlesh Thukral0d047612007-06-07 04:36:36 -0700711#define NETXEN_FLASH_START (NETXEN_CRBINIT_START)
712#define NETXEN_INIT_SECTOR (0)
713#define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START)
714#define NETXEN_FLASH_CRBINIT_SIZE (0x4000)
715#define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
716#define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32))
717#define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START)
718#define NETXEN_NUM_PRIMARY_SECTORS (0x20)
719#define NETXEN_NUM_CONFIG_SECTORS (1)
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800720#define PFX "NetXen: "
721extern char netxen_nic_driver_name[];
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400722
723/* Note: Make sure to not call this before adapter->port is valid */
724#if !defined(NETXEN_DEBUG)
725#define DPRINTK(klevel, fmt, args...) do { \
726 } while (0)
727#else
728#define DPRINTK(klevel, fmt, args...) do { \
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700729 printk(KERN_##klevel PFX "%s: %s: " fmt, __func__,\
Mithlesh Thukral3176ff32007-04-20 07:52:37 -0700730 (adapter != NULL && adapter->netdev != NULL) ? \
731 adapter->netdev->name : NULL, \
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400732 ## args); } while(0)
733#endif
734
735/* Number of status descriptors to handle per interrupt */
736#define MAX_STATUS_HANDLE (128)
737
738/*
739 * netxen_skb_frag{} is to contain mapping info for each SG list. This
740 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
741 */
742struct netxen_skb_frag {
743 u64 dma;
Dhananjay Phadke391587c2009-01-14 20:48:11 -0800744 ulong length;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400745};
746
Mithlesh Thukral6c80b182007-04-20 07:55:26 -0700747#define _netxen_set_bits(config_word, start, bits, val) {\
748 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
749 unsigned long long __tvalue = (val); \
750 (config_word) &= ~__tmask; \
751 (config_word) |= (((__tvalue) << (start)) & __tmask); \
752}
Jeff Garzik47906542007-11-23 21:23:36 -0500753
Mithlesh Thukral6c80b182007-04-20 07:55:26 -0700754#define _netxen_clear_bits(config_word, start, bits) {\
755 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \
756 (config_word) &= ~__tmask; \
Jeff Garzik47906542007-11-23 21:23:36 -0500757}
Mithlesh Thukral6c80b182007-04-20 07:55:26 -0700758
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400759/* Following defines are for the state of the buffers */
760#define NETXEN_BUFFER_FREE 0
761#define NETXEN_BUFFER_BUSY 1
762
763/*
764 * There will be one netxen_buffer per skb packet. These will be
765 * used to save the dma info for pci_unmap_page()
766 */
767struct netxen_cmd_buffer {
768 struct sk_buff *skb;
769 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
Dhananjay Phadke391587c2009-01-14 20:48:11 -0800770 u32 frag_count;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400771};
772
773/* In rx_buffer, we do not need multiple fragments as is a single buffer */
774struct netxen_rx_buffer {
Dhananjay Phadked9e651b2008-07-21 19:44:08 -0700775 struct list_head list;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400776 struct sk_buff *skb;
777 u64 dma;
778 u16 ref_handle;
779 u16 state;
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800780 u32 lro_expected_frags;
781 u32 lro_current_frags;
782 u32 lro_length;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400783};
784
785/* Board types */
786#define NETXEN_NIC_GBE 0x01
787#define NETXEN_NIC_XGBE 0x02
788
789/*
790 * One hardware_context{} per adapter
791 * contains interrupt info as well shared hardware info.
792 */
793struct netxen_hardware_context {
Amit S. Kalecb8011a2006-11-29 09:00:10 -0800794 void __iomem *pci_base0;
795 void __iomem *pci_base1;
796 void __iomem *pci_base2;
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800797 void __iomem *db_base;
798 unsigned long db_len;
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700799 unsigned long pci_len0;
800
801 int qdr_sn_window;
802 int ddr_mn_window;
803 unsigned long mn_win_crb;
804 unsigned long ms_win_crb;
Amit S. Kalecb8011a2006-11-29 09:00:10 -0800805
Dhananjay Phadke1e2d0052009-03-09 08:50:56 +0000806 u8 cut_through;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400807 u8 revision_id;
Dhananjay Phadke1e2d0052009-03-09 08:50:56 +0000808 u16 port_type;
809 int board_type;
Dhananjay Phadkea97342f2008-07-21 19:44:05 -0700810 u32 linkup;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400811 /* Address of cmd ring in Phantom */
812 struct cmd_desc_type0 *cmd_desc_head;
813 dma_addr_t cmd_desc_phys_addr;
814 struct netxen_adapter *adapter;
Mithlesh Thukral13ba9c772007-04-20 07:53:05 -0700815 int pci_func;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400816};
817
Amit S. Kaleed25ffa2006-12-04 09:23:25 -0800818#define RCV_RING_LRO RCV_DESC_LRO
819
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400820#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
821#define ETHERNET_FCS_SIZE 4
822
823struct netxen_adapter_stats {
Mithlesh Thukral3176ff32007-04-20 07:52:37 -0700824 u64 rcvdbadskb;
825 u64 xmitcalled;
826 u64 xmitedframes;
827 u64 xmitfinished;
828 u64 badskblen;
829 u64 nocmddescriptor;
830 u64 polled;
Dhananjay Phadked1847a72008-03-17 19:59:51 -0700831 u64 rxdropped;
Mithlesh Thukral3176ff32007-04-20 07:52:37 -0700832 u64 txdropped;
Mithlesh Thukral3176ff32007-04-20 07:52:37 -0700833 u64 csummed;
834 u64 no_rcv;
835 u64 rxbytes;
836 u64 txbytes;
837 u64 ints;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400838};
839
840/*
841 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
842 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
843 */
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -0700844struct nx_host_rds_ring {
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400845 u32 flags;
846 u32 producer;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400847 dma_addr_t phys_addr;
Dhananjay Phadke7830b222008-07-21 19:44:00 -0700848 u32 crb_rcv_producer; /* reg offset */
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400849 struct rcv_desc *desc_head; /* address of rx ring in Phantom */
850 u32 max_rx_desc_count;
851 u32 dma_size;
852 u32 skb_size;
853 struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */
Dhananjay Phadked9e651b2008-07-21 19:44:08 -0700854 struct list_head free_list;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400855};
856
857/*
858 * Receive context. There is one such structure per instance of the
859 * receive processing. Any state information that is relevant to
860 * the receive, and is must be in this structure. The global data may be
861 * present elsewhere.
862 */
863struct netxen_recv_context {
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -0700864 u32 state;
865 u16 context_id;
866 u16 virt_port;
867
868 struct nx_host_rds_ring rds_rings[NUM_RCV_DESC_RINGS];
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400869 u32 status_rx_consumer;
Dhananjay Phadke7830b222008-07-21 19:44:00 -0700870 u32 crb_sts_consumer; /* reg offset */
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400871 dma_addr_t rcv_status_desc_phys_addr;
872 struct status_desc *rcv_status_desc_head;
873};
874
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -0700875/* New HW context creation */
876
877#define NX_OS_CRB_RETRY_COUNT 4000
878#define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
879 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
880
881#define NX_CDRP_CLEAR 0x00000000
882#define NX_CDRP_CMD_BIT 0x80000000
883
884/*
885 * All responses must have the NX_CDRP_CMD_BIT cleared
886 * in the crb NX_CDRP_CRB_OFFSET.
887 */
888#define NX_CDRP_FORM_RSP(rsp) (rsp)
889#define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
890
891#define NX_CDRP_RSP_OK 0x00000001
892#define NX_CDRP_RSP_FAIL 0x00000002
893#define NX_CDRP_RSP_TIMEOUT 0x00000003
894
895/*
896 * All commands must have the NX_CDRP_CMD_BIT set in
897 * the crb NX_CDRP_CRB_OFFSET.
898 */
899#define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
900#define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
901
902#define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
903#define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
904#define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
905#define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
906#define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
907#define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
908#define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
909#define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
910#define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
911#define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
912#define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
913#define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
914#define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
915#define NX_CDRP_CMD_SET_MTU 0x00000012
916#define NX_CDRP_CMD_MAX 0x00000013
917
918#define NX_RCODE_SUCCESS 0
919#define NX_RCODE_NO_HOST_MEM 1
920#define NX_RCODE_NO_HOST_RESOURCE 2
921#define NX_RCODE_NO_CARD_CRB 3
922#define NX_RCODE_NO_CARD_MEM 4
923#define NX_RCODE_NO_CARD_RESOURCE 5
924#define NX_RCODE_INVALID_ARGS 6
925#define NX_RCODE_INVALID_ACTION 7
926#define NX_RCODE_INVALID_STATE 8
927#define NX_RCODE_NOT_SUPPORTED 9
928#define NX_RCODE_NOT_PERMITTED 10
929#define NX_RCODE_NOT_READY 11
930#define NX_RCODE_DOES_NOT_EXIST 12
931#define NX_RCODE_ALREADY_EXISTS 13
932#define NX_RCODE_BAD_SIGNATURE 14
933#define NX_RCODE_CMD_NOT_IMPL 15
934#define NX_RCODE_CMD_INVALID 16
935#define NX_RCODE_TIMEOUT 17
936#define NX_RCODE_CMD_FAILED 18
937#define NX_RCODE_MAX_EXCEEDED 19
938#define NX_RCODE_MAX 20
939
940#define NX_DESTROY_CTX_RESET 0
941#define NX_DESTROY_CTX_D3_RESET 1
942#define NX_DESTROY_CTX_MAX 2
943
944/*
945 * Capabilities
946 */
947#define NX_CAP_BIT(class, bit) (1 << bit)
948#define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
949#define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
950#define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
951#define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
952#define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
953#define NX_CAP0_LRO NX_CAP_BIT(0, 5)
954#define NX_CAP0_LSO NX_CAP_BIT(0, 6)
955#define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
956#define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
957
958/*
959 * Context state
960 */
961#define NX_HOST_CTX_STATE_FREED 0
962#define NX_HOST_CTX_STATE_ALLOCATED 1
963#define NX_HOST_CTX_STATE_ACTIVE 2
964#define NX_HOST_CTX_STATE_DISABLED 3
965#define NX_HOST_CTX_STATE_QUIESCED 4
966#define NX_HOST_CTX_STATE_MAX 5
967
968/*
969 * Rx context
970 */
971
972typedef struct {
Dhananjay Phadke2edbb452009-01-14 20:47:30 -0800973 __le64 host_phys_addr; /* Ring base addr */
974 __le32 ring_size; /* Ring entries */
975 __le16 msi_index;
976 __le16 rsvd; /* Padding */
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -0700977} nx_hostrq_sds_ring_t;
978
979typedef struct {
Dhananjay Phadke2edbb452009-01-14 20:47:30 -0800980 __le64 host_phys_addr; /* Ring base addr */
981 __le64 buff_size; /* Packet buffer size */
982 __le32 ring_size; /* Ring entries */
983 __le32 ring_kind; /* Class of ring */
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -0700984} nx_hostrq_rds_ring_t;
985
986typedef struct {
Dhananjay Phadke2edbb452009-01-14 20:47:30 -0800987 __le64 host_rsp_dma_addr; /* Response dma'd here */
988 __le32 capabilities[4]; /* Flag bit vector */
989 __le32 host_int_crb_mode; /* Interrupt crb usage */
990 __le32 host_rds_crb_mode; /* RDS crb usage */
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -0700991 /* These ring offsets are relative to data[0] below */
Dhananjay Phadke2edbb452009-01-14 20:47:30 -0800992 __le32 rds_ring_offset; /* Offset to RDS config */
993 __le32 sds_ring_offset; /* Offset to SDS config */
994 __le16 num_rds_rings; /* Count of RDS rings */
995 __le16 num_sds_rings; /* Count of SDS rings */
996 __le16 rsvd1; /* Padding */
997 __le16 rsvd2; /* Padding */
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -0700998 u8 reserved[128]; /* reserve space for future expansion*/
999 /* MUST BE 64-bit aligned.
1000 The following is packed:
1001 - N hostrq_rds_rings
1002 - N hostrq_sds_rings */
1003 char data[0];
1004} nx_hostrq_rx_ctx_t;
1005
1006typedef struct {
Dhananjay Phadke2edbb452009-01-14 20:47:30 -08001007 __le32 host_producer_crb; /* Crb to use */
1008 __le32 rsvd1; /* Padding */
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -07001009} nx_cardrsp_rds_ring_t;
1010
1011typedef struct {
Dhananjay Phadke2edbb452009-01-14 20:47:30 -08001012 __le32 host_consumer_crb; /* Crb to use */
1013 __le32 interrupt_crb; /* Crb to use */
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -07001014} nx_cardrsp_sds_ring_t;
1015
1016typedef struct {
1017 /* These ring offsets are relative to data[0] below */
Dhananjay Phadke2edbb452009-01-14 20:47:30 -08001018 __le32 rds_ring_offset; /* Offset to RDS config */
1019 __le32 sds_ring_offset; /* Offset to SDS config */
1020 __le32 host_ctx_state; /* Starting State */
1021 __le32 num_fn_per_port; /* How many PCI fn share the port */
1022 __le16 num_rds_rings; /* Count of RDS rings */
1023 __le16 num_sds_rings; /* Count of SDS rings */
1024 __le16 context_id; /* Handle for context */
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -07001025 u8 phys_port; /* Physical id of port */
1026 u8 virt_port; /* Virtual/Logical id of port */
1027 u8 reserved[128]; /* save space for future expansion */
1028 /* MUST BE 64-bit aligned.
1029 The following is packed:
1030 - N cardrsp_rds_rings
1031 - N cardrs_sds_rings */
1032 char data[0];
1033} nx_cardrsp_rx_ctx_t;
1034
1035#define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
1036 (sizeof(HOSTRQ_RX) + \
1037 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
1038 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
1039
1040#define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
1041 (sizeof(CARDRSP_RX) + \
1042 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
1043 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
1044
1045/*
1046 * Tx context
1047 */
1048
1049typedef struct {
Dhananjay Phadke2edbb452009-01-14 20:47:30 -08001050 __le64 host_phys_addr; /* Ring base addr */
1051 __le32 ring_size; /* Ring entries */
1052 __le32 rsvd; /* Padding */
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -07001053} nx_hostrq_cds_ring_t;
1054
1055typedef struct {
Dhananjay Phadke2edbb452009-01-14 20:47:30 -08001056 __le64 host_rsp_dma_addr; /* Response dma'd here */
1057 __le64 cmd_cons_dma_addr; /* */
1058 __le64 dummy_dma_addr; /* */
1059 __le32 capabilities[4]; /* Flag bit vector */
1060 __le32 host_int_crb_mode; /* Interrupt crb usage */
1061 __le32 rsvd1; /* Padding */
1062 __le16 rsvd2; /* Padding */
1063 __le16 interrupt_ctl;
1064 __le16 msi_index;
1065 __le16 rsvd3; /* Padding */
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -07001066 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
1067 u8 reserved[128]; /* future expansion */
1068} nx_hostrq_tx_ctx_t;
1069
1070typedef struct {
Dhananjay Phadke2edbb452009-01-14 20:47:30 -08001071 __le32 host_producer_crb; /* Crb to use */
1072 __le32 interrupt_crb; /* Crb to use */
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -07001073} nx_cardrsp_cds_ring_t;
1074
1075typedef struct {
Dhananjay Phadke2edbb452009-01-14 20:47:30 -08001076 __le32 host_ctx_state; /* Starting state */
1077 __le16 context_id; /* Handle for context */
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -07001078 u8 phys_port; /* Physical id of port */
1079 u8 virt_port; /* Virtual/Logical id of port */
1080 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
1081 u8 reserved[128]; /* future expansion */
1082} nx_cardrsp_tx_ctx_t;
1083
1084#define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
1085#define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
1086
1087/* CRB */
1088
1089#define NX_HOST_RDS_CRB_MODE_UNIQUE 0
1090#define NX_HOST_RDS_CRB_MODE_SHARED 1
1091#define NX_HOST_RDS_CRB_MODE_CUSTOM 2
1092#define NX_HOST_RDS_CRB_MODE_MAX 3
1093
1094#define NX_HOST_INT_CRB_MODE_UNIQUE 0
1095#define NX_HOST_INT_CRB_MODE_SHARED 1
1096#define NX_HOST_INT_CRB_MODE_NORX 2
1097#define NX_HOST_INT_CRB_MODE_NOTX 3
1098#define NX_HOST_INT_CRB_MODE_NORXTX 4
1099
1100
1101/* MAC */
1102
1103#define MC_COUNT_P2 16
1104#define MC_COUNT_P3 38
1105
1106#define NETXEN_MAC_NOOP 0
1107#define NETXEN_MAC_ADD 1
1108#define NETXEN_MAC_DEL 2
1109
1110typedef struct nx_mac_list_s {
1111 struct nx_mac_list_s *next;
1112 uint8_t mac_addr[MAX_ADDR_LEN];
1113} nx_mac_list_t;
1114
Dhananjay Phadkecd1f8162008-07-21 19:44:09 -07001115/*
1116 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
1117 * adjusted based on configured MTU.
1118 */
1119#define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
1120#define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
1121#define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
1122#define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
1123
1124#define NETXEN_NIC_INTR_DEFAULT 0x04
1125
1126typedef union {
1127 struct {
1128 uint16_t rx_packets;
1129 uint16_t rx_time_us;
1130 uint16_t tx_packets;
1131 uint16_t tx_time_us;
1132 } data;
1133 uint64_t word;
1134} nx_nic_intr_coalesce_data_t;
1135
1136typedef struct {
1137 uint16_t stats_time_us;
1138 uint16_t rate_sample_time;
1139 uint16_t flags;
1140 uint16_t rsvd_1;
1141 uint32_t low_threshold;
1142 uint32_t high_threshold;
1143 nx_nic_intr_coalesce_data_t normal;
1144 nx_nic_intr_coalesce_data_t low;
1145 nx_nic_intr_coalesce_data_t high;
1146 nx_nic_intr_coalesce_data_t irq;
1147} nx_nic_intr_coalesce_t;
1148
Dhananjay Phadke9ad27642008-08-01 03:14:59 -07001149#define NX_HOST_REQUEST 0x13
1150#define NX_NIC_REQUEST 0x14
1151
1152#define NX_MAC_EVENT 0x1
1153
1154enum {
1155 NX_NIC_H2C_OPCODE_START = 0,
1156 NX_NIC_H2C_OPCODE_CONFIG_RSS,
1157 NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL,
1158 NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE,
1159 NX_NIC_H2C_OPCODE_CONFIG_LED,
1160 NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS,
1161 NX_NIC_H2C_OPCODE_CONFIG_L2_MAC,
1162 NX_NIC_H2C_OPCODE_LRO_REQUEST,
1163 NX_NIC_H2C_OPCODE_GET_SNMP_STATS,
1164 NX_NIC_H2C_OPCODE_PROXY_START_REQUEST,
1165 NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST,
1166 NX_NIC_H2C_OPCODE_PROXY_SET_MTU,
1167 NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE,
1168 NX_H2P_OPCODE_GET_FINGER_PRINT_REQUEST,
1169 NX_H2P_OPCODE_INSTALL_LICENSE_REQUEST,
1170 NX_H2P_OPCODE_GET_LICENSE_CAPABILITY_REQUEST,
1171 NX_NIC_H2C_OPCODE_GET_NET_STATS,
1172 NX_NIC_H2C_OPCODE_LAST
1173};
1174
1175#define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
1176#define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
1177#define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1178
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -07001179typedef struct {
Dhananjay Phadke2edbb452009-01-14 20:47:30 -08001180 __le64 qhdr;
1181 __le64 req_hdr;
1182 __le64 words[6];
Dhananjay Phadkec9fc8912008-07-21 19:44:07 -07001183} nx_nic_req_t;
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -07001184
1185typedef struct {
1186 u8 op;
1187 u8 tag;
1188 u8 mac_addr[6];
1189} nx_mac_req_t;
1190
Dhananjay Phadkec9fc8912008-07-21 19:44:07 -07001191#define MAX_PENDING_DESC_BLOCK_SIZE 64
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -07001192
Dhananjay Phadke29566402008-07-21 19:44:04 -07001193#define NETXEN_NIC_MSI_ENABLED 0x02
1194#define NETXEN_NIC_MSIX_ENABLED 0x04
1195#define NETXEN_IS_MSI_FAMILY(adapter) \
1196 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1197
Dhananjay Phadkeb3df68f2009-02-08 19:20:19 -08001198#define MSIX_ENTRIES_PER_ADAPTER 1
Dhananjay Phadke29566402008-07-21 19:44:04 -07001199#define NETXEN_MSIX_TBL_SPACE 8192
1200#define NETXEN_PCI_REG_MSIX_TBL 0x44
1201
1202#define NETXEN_DB_MAPSIZE_BYTES 0x1000
Amit S. Kaleed25ffa2006-12-04 09:23:25 -08001203
Dhananjay Phadkecd1f8162008-07-21 19:44:09 -07001204#define NETXEN_NETDEV_WEIGHT 120
1205#define NETXEN_ADAPTER_UP_MAGIC 777
1206#define NETXEN_NIC_PEG_TUNE 0
1207
Amit S. Kaleed25ffa2006-12-04 09:23:25 -08001208struct netxen_dummy_dma {
1209 void *addr;
1210 dma_addr_t phys_addr;
1211};
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001212
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001213struct netxen_adapter {
1214 struct netxen_hardware_context ahw;
Jeff Garzik47906542007-11-23 21:23:36 -05001215
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07001216 struct net_device *netdev;
1217 struct pci_dev *pdev;
Dhananjay Phadke29566402008-07-21 19:44:04 -07001218 int pci_using_dac;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001219 struct napi_struct napi;
Mithlesh Thukral6c80b182007-04-20 07:55:26 -07001220 struct net_device_stats net_stats;
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07001221 int mtu;
1222 int portnum;
Dhananjay Phadke3276fba2008-06-15 22:59:44 -07001223 u8 physical_port;
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -07001224 u16 tx_context_id;
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07001225
Dhananjay Phadke623621b2008-07-21 19:44:01 -07001226 uint8_t mc_enabled;
1227 uint8_t max_mc_count;
Dhananjay Phadkec9fc8912008-07-21 19:44:07 -07001228 nx_mac_list_t *mac_list;
Dhananjay Phadke623621b2008-07-21 19:44:01 -07001229
Dhananjay Phadke29566402008-07-21 19:44:04 -07001230 struct netxen_legacy_intr_set legacy_intr;
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -07001231 u32 crb_intr_mask;
Dhananjay Phadke29566402008-07-21 19:44:04 -07001232
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001233 struct work_struct watchdog_task;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001234 struct timer_list watchdog_timer;
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07001235 struct work_struct tx_timeout_task;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001236
1237 u32 curr_window;
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001238 u32 crb_win;
1239 rwlock_t adapter_lock;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001240
1241 u32 cmd_producer;
Al Virof305f782007-12-22 19:44:00 +00001242 __le32 *cmd_consumer;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001243 u32 last_cmd_consumer;
Dhananjay Phadke7830b222008-07-21 19:44:00 -07001244 u32 crb_addr_cmd_producer;
1245 u32 crb_addr_cmd_consumer;
Dhananjay Phadkeba53e6b2008-03-17 19:59:50 -07001246
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001247 u32 max_tx_desc_count;
1248 u32 max_rx_desc_count;
1249 u32 max_jumbo_rx_desc_count;
Amit S. Kaleed25ffa2006-12-04 09:23:25 -08001250 u32 max_lro_rx_desc_count;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001251
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -07001252 int max_rds_rings;
1253
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001254 u32 flags;
1255 u32 irq;
1256 int driver_mismatch;
Amit S. Kalecb8011a2006-11-29 09:00:10 -08001257 u32 temp;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001258
Dhananjay Phadke29566402008-07-21 19:44:04 -07001259 u32 fw_major;
Dhananjay Phadke1e2d0052009-03-09 08:50:56 +00001260 u32 fw_version;
Dhananjay Phadke29566402008-07-21 19:44:04 -07001261
1262 u8 msix_supported;
1263 u8 max_possible_rss_rings;
1264 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1265
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001266 struct netxen_adapter_stats stats;
Jeff Garzik47906542007-11-23 21:23:36 -05001267
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07001268 u16 link_speed;
1269 u16 link_duplex;
1270 u16 state;
1271 u16 link_autoneg;
Dhananjay Phadke200eef22007-09-03 10:33:35 +05301272 int rx_csum;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001273
1274 struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */
1275
1276 /*
1277 * Receive instances. These can be either one per port,
1278 * or one per peg, etc.
1279 */
Dhananjay Phadkebecf46a2009-03-09 08:50:55 +00001280 struct netxen_recv_context recv_ctx;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001281
1282 int is_up;
Amit S. Kaleed25ffa2006-12-04 09:23:25 -08001283 struct netxen_dummy_dma dummy_dma;
Dhananjay Phadkecd1f8162008-07-21 19:44:09 -07001284 nx_nic_intr_coalesce_t coal;
Amit S. Kaleed25ffa2006-12-04 09:23:25 -08001285
1286 /* Context interface shared between card and host */
1287 struct netxen_ring_ctx *ctx_desc;
Amit S. Kaleed25ffa2006-12-04 09:23:25 -08001288 dma_addr_t ctx_desc_phys_addr;
dhananjay.phadke@gmail.com2d1a3bb2007-07-02 00:26:00 +05301289 int intr_scheme;
Dhananjay Phadke443be792008-03-17 19:59:48 -07001290 int msi_mode;
Mithlesh Thukral13ba9c772007-04-20 07:53:05 -07001291 int (*enable_phy_interrupts) (struct netxen_adapter *);
1292 int (*disable_phy_interrupts) (struct netxen_adapter *);
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07001293 int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
1294 int (*set_mtu) (struct netxen_adapter *, int);
Dhananjay Phadke9ad27642008-08-01 03:14:59 -07001295 int (*set_promisc) (struct netxen_adapter *, u32);
Mithlesh Thukral13ba9c772007-04-20 07:53:05 -07001296 int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
1297 int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
Amit S. Kale80922fb2006-12-04 09:18:00 -08001298 int (*init_port) (struct netxen_adapter *, int);
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07001299 int (*stop_port) (struct netxen_adapter *);
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001300
1301 int (*hw_read_wx)(struct netxen_adapter *, ulong, void *, int);
1302 int (*hw_write_wx)(struct netxen_adapter *, ulong, void *, int);
1303 int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1304 int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1305 int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1306 u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1307 void (*pci_write_normalize)(struct netxen_adapter *, u64, u32);
1308 u32 (*pci_read_normalize)(struct netxen_adapter *, u64);
1309 unsigned long (*pci_set_window)(struct netxen_adapter *,
1310 unsigned long long);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001311}; /* netxen_adapter structure */
1312
Dhananjay Phadke96acb6e2007-07-02 09:37:57 +05301313/*
1314 * NetXen dma watchdog control structure
1315 *
1316 * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
1317 * Bit 1 : disable_request => 1 req disable dma watchdog
1318 * Bit 2 : enable_request => 1 req enable dma watchdog
1319 * Bit 3-31 : unused
1320 */
1321
1322#define netxen_set_dma_watchdog_disable_req(config_word) \
1323 _netxen_set_bits(config_word, 1, 1, 1)
1324#define netxen_set_dma_watchdog_enable_req(config_word) \
1325 _netxen_set_bits(config_word, 2, 1, 1)
1326#define netxen_get_dma_watchdog_enabled(config_word) \
1327 ((config_word) & 0x1)
1328#define netxen_get_dma_watchdog_disabled(config_word) \
1329 (((config_word) >> 1) & 0x1)
1330
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001331/* Max number of xmit producer threads that can run simultaneously */
1332#define MAX_XMIT_PRODUCERS 16
1333
Amit S. Kalecb8011a2006-11-29 09:00:10 -08001334#define PCI_OFFSET_FIRST_RANGE(adapter, off) \
1335 ((adapter)->ahw.pci_base0 + (off))
1336#define PCI_OFFSET_SECOND_RANGE(adapter, off) \
1337 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
1338#define PCI_OFFSET_THIRD_RANGE(adapter, off) \
1339 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
1340
1341static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
1342 unsigned long off)
1343{
1344 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1345 return (adapter->ahw.pci_base0 + off);
1346 } else if ((off < SECOND_PAGE_GROUP_END) &&
1347 (off >= SECOND_PAGE_GROUP_START)) {
1348 return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
1349 } else if ((off < THIRD_PAGE_GROUP_END) &&
1350 (off >= THIRD_PAGE_GROUP_START)) {
1351 return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
1352 }
1353 return NULL;
1354}
1355
1356static inline void __iomem *pci_base(struct netxen_adapter *adapter,
1357 unsigned long off)
1358{
1359 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1360 return adapter->ahw.pci_base0;
1361 } else if ((off < SECOND_PAGE_GROUP_END) &&
1362 (off >= SECOND_PAGE_GROUP_START)) {
1363 return adapter->ahw.pci_base1;
1364 } else if ((off < THIRD_PAGE_GROUP_END) &&
1365 (off >= THIRD_PAGE_GROUP_START)) {
1366 return adapter->ahw.pci_base2;
1367 }
1368 return NULL;
1369}
1370
Mithlesh Thukral13ba9c772007-04-20 07:53:05 -07001371int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1372int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1373int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1374int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
Mithlesh Thukral13ba9c772007-04-20 07:53:05 -07001375int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
Al Viroa608ab9c2007-01-02 10:39:10 +00001376 __u32 * readval);
Mithlesh Thukral13ba9c772007-04-20 07:53:05 -07001377int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
Al Viroa608ab9c2007-01-02 10:39:10 +00001378 long reg, __u32 val);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001379
1380/* Functions available from netxen_nic_hw.c */
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07001381int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1382int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001383void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
1384int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
1385void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001386void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value);
1387void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value);
1388void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001389
1390int netxen_nic_get_board_info(struct netxen_adapter *adapter);
Dhananjay Phadke1e2d0052009-03-09 08:50:56 +00001391void netxen_nic_get_firmware_info(struct netxen_adapter *adapter);
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001392
1393int netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1394 ulong off, void *data, int len);
1395int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1396 ulong off, void *data, int len);
1397int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1398 u64 off, void *data, int size);
1399int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1400 u64 off, void *data, int size);
1401int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1402 u64 off, u32 data);
1403u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1404void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1405 u64 off, u32 data);
1406u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1407unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1408 unsigned long long addr);
1409void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1410 u32 wndw);
1411
1412int netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1413 ulong off, void *data, int len);
1414int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1415 ulong off, void *data, int len);
1416int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1417 u64 off, void *data, int size);
1418int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1419 u64 off, void *data, int size);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001420void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
1421 unsigned long off, int data);
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001422int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1423 u64 off, u32 data);
1424u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1425void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1426 u64 off, u32 data);
1427u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1428unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1429 unsigned long long addr);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001430
1431/* Functions from netxen_nic_init.c */
Amit S. Kaleed25ffa2006-12-04 09:23:25 -08001432void netxen_free_adapter_offload(struct netxen_adapter *adapter);
1433int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
Dhananjay Phadke96acb6e2007-07-02 09:37:57 +05301434int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
Dhananjay Phadke29566402008-07-21 19:44:04 -07001435int netxen_receive_peg_ready(struct netxen_adapter *adapter);
Dhananjay Phadke96acb6e2007-07-02 09:37:57 +05301436int netxen_load_firmware(struct netxen_adapter *adapter);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001437int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
Dhananjay Phadke29566402008-07-21 19:44:04 -07001438
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001439int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
Jeff Garzik47906542007-11-23 21:23:36 -05001440int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
Amit S. Kale27d2ab52007-02-05 07:40:49 -08001441 u8 *bytes, size_t size);
Jeff Garzik47906542007-11-23 21:23:36 -05001442int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
Amit S. Kale27d2ab52007-02-05 07:40:49 -08001443 u8 *bytes, size_t size);
1444int netxen_flash_unlock(struct netxen_adapter *adapter);
1445int netxen_backup_crbinit(struct netxen_adapter *adapter);
1446int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1447int netxen_flash_erase_primary(struct netxen_adapter *adapter);
Amit S. Kalee45d9ab2007-02-09 05:49:08 -08001448void netxen_halt_pegs(struct netxen_adapter *adapter);
Amit S. Kale27d2ab52007-02-05 07:40:49 -08001449
Amit S. Kalecb8011a2006-11-29 09:00:10 -08001450int netxen_rom_se(struct netxen_adapter *adapter, int addr);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001451
Dhananjay Phadke29566402008-07-21 19:44:04 -07001452int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1453void netxen_free_sw_resources(struct netxen_adapter *adapter);
1454
1455int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1456void netxen_free_hw_resources(struct netxen_adapter *adapter);
1457
1458void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1459void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1460
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001461void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1462int netxen_init_firmware(struct netxen_adapter *adapter);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001463void netxen_nic_clear_stats(struct netxen_adapter *adapter);
David Howells6d5aefb2006-12-05 19:36:26 +00001464void netxen_watchdog_task(struct work_struct *work);
Dhananjay Phadkebecf46a2009-03-09 08:50:55 +00001465void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid);
Dhananjay Phadke05aaa022008-03-17 19:59:49 -07001466int netxen_process_cmd_ring(struct netxen_adapter *adapter);
Dhananjay Phadkebecf46a2009-03-09 08:50:55 +00001467int netxen_process_rcv_ring(struct netxen_adapter *adapter, int max);
Dhananjay Phadkec9fc8912008-07-21 19:44:07 -07001468void netxen_p2_nic_set_multi(struct net_device *netdev);
1469void netxen_p3_nic_set_multi(struct net_device *netdev);
Dhananjay Phadke06e9d9f2009-01-14 20:49:22 -08001470void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
Dhananjay Phadke9ad27642008-08-01 03:14:59 -07001471int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
Dhananjay Phadkecd1f8162008-07-21 19:44:09 -07001472int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -07001473
Dhananjay Phadke9ad27642008-08-01 03:14:59 -07001474int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001475int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
Dhananjay Phadke48bfd1e2008-07-21 19:44:06 -07001476
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001477int netxen_nic_set_mac(struct net_device *netdev, void *p);
1478struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1479
Dhananjay Phadkec9fc8912008-07-21 19:44:07 -07001480void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1481 uint32_t crb_producer);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001482
Amit S. Kalecb8011a2006-11-29 09:00:10 -08001483/*
1484 * NetXen Board information
1485 */
1486
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -07001487#define NETXEN_MAX_SHORT_NAME 32
Amit S. Kale71bd7872006-12-01 05:36:22 -08001488struct netxen_brdinfo {
Amit S. Kalecb8011a2006-11-29 09:00:10 -08001489 netxen_brdtype_t brdtype; /* type of board */
1490 long ports; /* max no of physical ports */
1491 char short_name[NETXEN_MAX_SHORT_NAME];
Amit S. Kale71bd7872006-12-01 05:36:22 -08001492};
Amit S. Kalecb8011a2006-11-29 09:00:10 -08001493
Amit S. Kale71bd7872006-12-01 05:36:22 -08001494static const struct netxen_brdinfo netxen_boards[] = {
Amit S. Kalecb8011a2006-11-29 09:00:10 -08001495 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1496 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1497 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1498 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1499 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1500 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -07001501 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1502 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1503 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1504 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1505 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1506 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1507 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1508 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
Dhananjay Phadkea70f9392008-08-01 03:14:56 -07001509 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1510 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1511 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -07001512 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1513 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
Amit S. Kalecb8011a2006-11-29 09:00:10 -08001514};
1515
Denis Chengff8ac602007-09-02 18:30:18 +08001516#define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
Amit S. Kalecb8011a2006-11-29 09:00:10 -08001517
Amit S. Kalecb8011a2006-11-29 09:00:10 -08001518static inline void get_brd_name_by_type(u32 type, char *name)
1519{
1520 int i, found = 0;
1521 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1522 if (netxen_boards[i].brdtype == type) {
1523 strcpy(name, netxen_boards[i].short_name);
1524 found = 1;
1525 break;
1526 }
1527
1528 }
1529 if (!found)
1530 name = "Unknown";
1531}
1532
Dhananjay Phadke96acb6e2007-07-02 09:37:57 +05301533static inline int
1534dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
1535{
1536 u32 ctrl;
1537
1538 /* check if already inactive */
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001539 if (adapter->hw_read_wx(adapter,
Dhananjay Phadke96acb6e2007-07-02 09:37:57 +05301540 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1541 printk(KERN_ERR "failed to read dma watchdog status\n");
1542
1543 if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
1544 return 1;
1545
1546 /* Send the disable request */
1547 netxen_set_dma_watchdog_disable_req(ctrl);
1548 netxen_crb_writelit_adapter(adapter,
1549 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1550
1551 return 0;
1552}
1553
1554static inline int
1555dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
1556{
1557 u32 ctrl;
1558
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001559 if (adapter->hw_read_wx(adapter,
Dhananjay Phadke96acb6e2007-07-02 09:37:57 +05301560 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1561 printk(KERN_ERR "failed to read dma watchdog status\n");
1562
dhananjay@netxen.comceded322007-07-19 14:41:09 +05301563 return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
Dhananjay Phadke96acb6e2007-07-02 09:37:57 +05301564}
1565
1566static inline int
1567dma_watchdog_wakeup(struct netxen_adapter *adapter)
1568{
1569 u32 ctrl;
1570
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001571 if (adapter->hw_read_wx(adapter,
Dhananjay Phadke96acb6e2007-07-02 09:37:57 +05301572 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1573 printk(KERN_ERR "failed to read dma watchdog status\n");
1574
1575 if (netxen_get_dma_watchdog_enabled(ctrl))
1576 return 1;
1577
1578 /* send the wakeup request */
1579 netxen_set_dma_watchdog_enable_req(ctrl);
1580
1581 netxen_crb_writelit_adapter(adapter,
1582 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1583
1584 return 0;
1585}
1586
1587
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001588int netxen_is_flash_supported(struct netxen_adapter *adapter);
Dhananjay Phadke9dc28ef2008-08-08 00:08:39 -07001589int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1590int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001591extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1592extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1593 int *valp);
1594
1595extern struct ethtool_ops netxen_nic_ethtool_ops;
1596
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001597#endif /* __NETXEN_NIC_H_ */