blob: 3fe99cb271a9cad44c55dfbf841b9de0e9093974 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
Justin P. Mattock79add622011-04-04 14:15:29 -07006 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */
James Hogan61d73042014-03-04 10:23:57 +000010#include <linux/cpu_pm.h>
Ralf Baechlea754f702007-11-03 01:01:37 +000011#include <linux/hardirq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#include <linux/init.h>
Ralf Baechledb813fe2007-09-27 18:26:43 +010013#include <linux/highmem.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/kernel.h>
Ralf Baechle641e97f2007-10-11 23:46:05 +010015#include <linux/linkage.h>
Ralf Baechleff522052013-09-17 12:44:31 +020016#include <linux/preempt.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/sched.h>
Ralf Baechle631330f2009-06-19 14:05:26 +010018#include <linux/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <linux/mm.h>
Paul Gortmakerd9ba5772016-08-21 15:58:14 -040020#include <linux/export.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <linux/bitops.h>
22
23#include <asm/bcache.h>
24#include <asm/bootinfo.h>
Ralf Baechleec74e362005-07-13 11:48:45 +000025#include <asm/cache.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <asm/cacheops.h>
27#include <asm/cpu.h>
28#include <asm/cpu-features.h>
Ralf Baechle69f24d12013-09-17 10:25:47 +020029#include <asm/cpu-type.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070030#include <asm/io.h>
31#include <asm/page.h>
32#include <asm/pgtable.h>
33#include <asm/r4kcache.h>
Ralf Baechlee001e522007-07-28 12:45:47 +010034#include <asm/sections.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070035#include <asm/mmu_context.h>
36#include <asm/war.h>
Thiemo Seuferba5187d2005-04-25 16:36:23 +000037#include <asm/cacheflush.h> /* for run_uncached() */
David Daney9cd9669b2012-05-15 00:04:49 -070038#include <asm/traps.h>
Steven J. Hillb6d92b42013-03-25 13:47:29 -050039#include <asm/dma-coherence.h>
Markos Chandrascccf34e2015-07-10 09:29:10 +010040#include <asm/mips-cm.h>
Ralf Baechle7f3f1d02006-05-12 13:20:06 +010041
42/*
James Hogand374d932016-07-13 14:12:50 +010043 * Bits describing what cache ops an SMP callback function may perform.
44 *
45 * R4K_HIT - Virtual user or kernel address based cache operations. The
46 * active_mm must be checked before using user addresses, falling
47 * back to kmap.
48 * R4K_INDEX - Index based cache operations.
49 */
50
51#define R4K_HIT BIT(0)
52#define R4K_INDEX BIT(1)
53
54/**
55 * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
56 * @type: Type of cache operations (R4K_HIT or R4K_INDEX).
57 *
58 * Decides whether a cache op needs to be performed on every core in the system.
James Hogan640511a2016-07-13 14:12:52 +010059 * This may change depending on the @type of cache operation, as well as the set
60 * of online CPUs, so preemption should be disabled by the caller to prevent CPU
61 * hotplug from changing the result.
James Hogand374d932016-07-13 14:12:50 +010062 *
63 * Returns: 1 if the cache operation @type should be done on every core in
64 * the system.
65 * 0 if the cache operation @type is globalized and only needs to
66 * be performed on a simple CPU.
67 */
68static inline bool r4k_op_needs_ipi(unsigned int type)
69{
70 /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */
James Hogan11f76902016-07-13 14:12:56 +010071 if (type == R4K_HIT && mips_cm_present())
James Hogand374d932016-07-13 14:12:50 +010072 return false;
73
74 /*
75 * Hardware doesn't globalize the required cache ops, so SMP calls may
James Hogan640511a2016-07-13 14:12:52 +010076 * be needed, but only if there are foreign CPUs (non-siblings with
77 * separate caches).
James Hogand374d932016-07-13 14:12:50 +010078 */
James Hogan640511a2016-07-13 14:12:52 +010079 /* cpu_foreign_map[] undeclared when !CONFIG_SMP */
80#ifdef CONFIG_SMP
81 return !cpumask_empty(&cpu_foreign_map[0]);
82#else
83 return false;
84#endif
James Hogand374d932016-07-13 14:12:50 +010085}
86
87/*
Ralf Baechle7f3f1d02006-05-12 13:20:06 +010088 * Special Variant of smp_call_function for use by cache functions:
89 *
90 * o No return value
91 * o collapses to normal function call on UP kernels
92 * o collapses to normal function call on systems with a single shared
93 * primary cache.
Ralf Baechlec8c5f3f2010-10-29 19:08:25 +010094 * o doesn't disable interrupts on the local CPU
Ralf Baechle7f3f1d02006-05-12 13:20:06 +010095 */
James Hogand374d932016-07-13 14:12:50 +010096static inline void r4k_on_each_cpu(unsigned int type,
97 void (*func)(void *info), void *info)
Ralf Baechle7f3f1d02006-05-12 13:20:06 +010098{
99 preempt_disable();
James Hogand374d932016-07-13 14:12:50 +0100100 if (r4k_op_needs_ipi(type))
James Hogan640511a2016-07-13 14:12:52 +0100101 smp_call_function_many(&cpu_foreign_map[smp_processor_id()],
102 func, info, 1);
Ralf Baechle7f3f1d02006-05-12 13:20:06 +0100103 func(info);
104 preempt_enable();
105}
106
Ralf Baechleec74e362005-07-13 11:48:45 +0000107/*
108 * Must die.
109 */
110static unsigned long icache_size __read_mostly;
111static unsigned long dcache_size __read_mostly;
Huacai Chenb2edcfc2016-03-03 09:45:09 +0800112static unsigned long vcache_size __read_mostly;
Ralf Baechleec74e362005-07-13 11:48:45 +0000113static unsigned long scache_size __read_mostly;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114
115/*
116 * Dummy cache handling routines for machines without boardcaches
117 */
Chris Dearman73f40352006-06-20 18:06:52 +0100118static void cache_noop(void) {}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119
120static struct bcache_ops no_sc_ops = {
Chris Dearman73f40352006-06-20 18:06:52 +0100121 .bc_enable = (void *)cache_noop,
122 .bc_disable = (void *)cache_noop,
123 .bc_wback_inv = (void *)cache_noop,
124 .bc_inv = (void *)cache_noop
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125};
126
127struct bcache_ops *bcops = &no_sc_ops;
128
Thiemo Seufer330cfe02005-09-01 18:33:58 +0000129#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
130#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131
132#define R4600_HIT_CACHEOP_WAR_IMPL \
133do { \
134 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
135 *(volatile unsigned long *)CKSEG1; \
136 if (R4600_V1_HIT_CACHEOP_WAR) \
137 __asm__ __volatile__("nop;nop;nop;nop"); \
138} while (0)
139
140static void (*r4k_blast_dcache_page)(unsigned long addr);
141
142static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
143{
144 R4600_HIT_CACHEOP_WAR_IMPL;
145 blast_dcache32_page(addr);
146}
147
Kevin Cernekee605b7ef2009-04-23 17:36:53 -0700148static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
149{
Kevin Cernekee605b7ef2009-04-23 17:36:53 -0700150 blast_dcache64_page(addr);
151}
152
David Daney18a8cd62014-05-28 23:52:09 +0200153static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
154{
155 blast_dcache128_page(addr);
156}
157
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000158static void r4k_blast_dcache_page_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159{
160 unsigned long dc_lsize = cpu_dcache_line_size();
161
David Daney18a8cd62014-05-28 23:52:09 +0200162 switch (dc_lsize) {
163 case 0:
Chris Dearman73f40352006-06-20 18:06:52 +0100164 r4k_blast_dcache_page = (void *)cache_noop;
David Daney18a8cd62014-05-28 23:52:09 +0200165 break;
166 case 16:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167 r4k_blast_dcache_page = blast_dcache16_page;
David Daney18a8cd62014-05-28 23:52:09 +0200168 break;
169 case 32:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
David Daney18a8cd62014-05-28 23:52:09 +0200171 break;
172 case 64:
Kevin Cernekee605b7ef2009-04-23 17:36:53 -0700173 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
David Daney18a8cd62014-05-28 23:52:09 +0200174 break;
175 case 128:
176 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
177 break;
178 default:
179 break;
180 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181}
182
Leonid Yegoshin4caa9062014-01-15 14:47:28 +0000183#ifndef CONFIG_EVA
184#define r4k_blast_dcache_user_page r4k_blast_dcache_page
185#else
186
187static void (*r4k_blast_dcache_user_page)(unsigned long addr);
188
189static void r4k_blast_dcache_user_page_setup(void)
190{
191 unsigned long dc_lsize = cpu_dcache_line_size();
192
193 if (dc_lsize == 0)
194 r4k_blast_dcache_user_page = (void *)cache_noop;
195 else if (dc_lsize == 16)
196 r4k_blast_dcache_user_page = blast_dcache16_user_page;
197 else if (dc_lsize == 32)
198 r4k_blast_dcache_user_page = blast_dcache32_user_page;
199 else if (dc_lsize == 64)
200 r4k_blast_dcache_user_page = blast_dcache64_user_page;
201}
202
203#endif
204
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
206
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000207static void r4k_blast_dcache_page_indexed_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700208{
209 unsigned long dc_lsize = cpu_dcache_line_size();
210
Chris Dearman73f40352006-06-20 18:06:52 +0100211 if (dc_lsize == 0)
212 r4k_blast_dcache_page_indexed = (void *)cache_noop;
213 else if (dc_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
215 else if (dc_lsize == 32)
216 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
Kevin Cernekee605b7ef2009-04-23 17:36:53 -0700217 else if (dc_lsize == 64)
218 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
David Daney18a8cd62014-05-28 23:52:09 +0200219 else if (dc_lsize == 128)
220 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221}
222
Sanjay Lalf2e36562012-11-21 18:34:10 -0800223void (* r4k_blast_dcache)(void);
224EXPORT_SYMBOL(r4k_blast_dcache);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000226static void r4k_blast_dcache_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227{
228 unsigned long dc_lsize = cpu_dcache_line_size();
229
Chris Dearman73f40352006-06-20 18:06:52 +0100230 if (dc_lsize == 0)
231 r4k_blast_dcache = (void *)cache_noop;
232 else if (dc_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233 r4k_blast_dcache = blast_dcache16;
234 else if (dc_lsize == 32)
235 r4k_blast_dcache = blast_dcache32;
Kevin Cernekee605b7ef2009-04-23 17:36:53 -0700236 else if (dc_lsize == 64)
237 r4k_blast_dcache = blast_dcache64;
David Daney18a8cd62014-05-28 23:52:09 +0200238 else if (dc_lsize == 128)
239 r4k_blast_dcache = blast_dcache128;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240}
241
242/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
243#define JUMP_TO_ALIGN(order) \
244 __asm__ __volatile__( \
245 "b\t1f\n\t" \
246 ".align\t" #order "\n\t" \
247 "1:\n\t" \
248 )
249#define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
Ralf Baechle70342282013-01-22 12:59:30 +0100250#define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251
252static inline void blast_r4600_v1_icache32(void)
253{
254 unsigned long flags;
255
256 local_irq_save(flags);
257 blast_icache32();
258 local_irq_restore(flags);
259}
260
261static inline void tx49_blast_icache32(void)
262{
263 unsigned long start = INDEX_BASE;
264 unsigned long end = start + current_cpu_data.icache.waysize;
265 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
266 unsigned long ws_end = current_cpu_data.icache.ways <<
Ralf Baechle70342282013-01-22 12:59:30 +0100267 current_cpu_data.icache.waybit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268 unsigned long ws, addr;
269
270 CACHE32_UNROLL32_ALIGN2;
271 /* I'm in even chunk. blast odd chunks */
Ralf Baechle42a3b4f22005-09-03 15:56:17 -0700272 for (ws = 0; ws < ws_end; ws += ws_inc)
273 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
Ralf Baechle21a151d2007-10-11 23:46:15 +0100274 cache32_unroll32(addr|ws, Index_Invalidate_I);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275 CACHE32_UNROLL32_ALIGN;
276 /* I'm in odd chunk. blast even chunks */
Ralf Baechle42a3b4f22005-09-03 15:56:17 -0700277 for (ws = 0; ws < ws_end; ws += ws_inc)
278 for (addr = start; addr < end; addr += 0x400 * 2)
Ralf Baechle21a151d2007-10-11 23:46:15 +0100279 cache32_unroll32(addr|ws, Index_Invalidate_I);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280}
281
282static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
283{
284 unsigned long flags;
285
286 local_irq_save(flags);
287 blast_icache32_page_indexed(page);
288 local_irq_restore(flags);
289}
290
291static inline void tx49_blast_icache32_page_indexed(unsigned long page)
292{
Atsushi Nemoto67a3f6de2006-04-04 17:34:14 +0900293 unsigned long indexmask = current_cpu_data.icache.waysize - 1;
294 unsigned long start = INDEX_BASE + (page & indexmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295 unsigned long end = start + PAGE_SIZE;
296 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
297 unsigned long ws_end = current_cpu_data.icache.ways <<
Ralf Baechle70342282013-01-22 12:59:30 +0100298 current_cpu_data.icache.waybit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299 unsigned long ws, addr;
300
301 CACHE32_UNROLL32_ALIGN2;
302 /* I'm in even chunk. blast odd chunks */
Ralf Baechle42a3b4f22005-09-03 15:56:17 -0700303 for (ws = 0; ws < ws_end; ws += ws_inc)
304 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
Ralf Baechle21a151d2007-10-11 23:46:15 +0100305 cache32_unroll32(addr|ws, Index_Invalidate_I);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306 CACHE32_UNROLL32_ALIGN;
307 /* I'm in odd chunk. blast even chunks */
Ralf Baechle42a3b4f22005-09-03 15:56:17 -0700308 for (ws = 0; ws < ws_end; ws += ws_inc)
309 for (addr = start; addr < end; addr += 0x400 * 2)
Ralf Baechle21a151d2007-10-11 23:46:15 +0100310 cache32_unroll32(addr|ws, Index_Invalidate_I);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311}
312
313static void (* r4k_blast_icache_page)(unsigned long addr);
314
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000315static void r4k_blast_icache_page_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316{
317 unsigned long ic_lsize = cpu_icache_line_size();
318
Chris Dearman73f40352006-06-20 18:06:52 +0100319 if (ic_lsize == 0)
320 r4k_blast_icache_page = (void *)cache_noop;
321 else if (ic_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700322 r4k_blast_icache_page = blast_icache16_page;
Aaro Koskinen43a06842014-01-14 17:56:38 -0800323 else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2)
324 r4k_blast_icache_page = loongson2_blast_icache32_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325 else if (ic_lsize == 32)
326 r4k_blast_icache_page = blast_icache32_page;
327 else if (ic_lsize == 64)
328 r4k_blast_icache_page = blast_icache64_page;
David Daney18a8cd62014-05-28 23:52:09 +0200329 else if (ic_lsize == 128)
330 r4k_blast_icache_page = blast_icache128_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331}
332
Leonid Yegoshin4caa9062014-01-15 14:47:28 +0000333#ifndef CONFIG_EVA
334#define r4k_blast_icache_user_page r4k_blast_icache_page
335#else
336
337static void (*r4k_blast_icache_user_page)(unsigned long addr);
338
Paul Gortmaker9a8f4ea2015-04-27 18:47:57 -0400339static void r4k_blast_icache_user_page_setup(void)
Leonid Yegoshin4caa9062014-01-15 14:47:28 +0000340{
341 unsigned long ic_lsize = cpu_icache_line_size();
342
343 if (ic_lsize == 0)
344 r4k_blast_icache_user_page = (void *)cache_noop;
345 else if (ic_lsize == 16)
346 r4k_blast_icache_user_page = blast_icache16_user_page;
347 else if (ic_lsize == 32)
348 r4k_blast_icache_user_page = blast_icache32_user_page;
349 else if (ic_lsize == 64)
350 r4k_blast_icache_user_page = blast_icache64_user_page;
351}
352
353#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700354
355static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
356
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000357static void r4k_blast_icache_page_indexed_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358{
359 unsigned long ic_lsize = cpu_icache_line_size();
360
Chris Dearman73f40352006-06-20 18:06:52 +0100361 if (ic_lsize == 0)
362 r4k_blast_icache_page_indexed = (void *)cache_noop;
363 else if (ic_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
365 else if (ic_lsize == 32) {
Thiemo Seufer02fe2c92005-09-09 19:45:41 +0000366 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 r4k_blast_icache_page_indexed =
368 blast_icache32_r4600_v1_page_indexed;
Thiemo Seufer02fe2c92005-09-09 19:45:41 +0000369 else if (TX49XX_ICACHE_INDEX_INV_WAR)
370 r4k_blast_icache_page_indexed =
371 tx49_blast_icache32_page_indexed;
Aaro Koskinen43a06842014-01-14 17:56:38 -0800372 else if (current_cpu_type() == CPU_LOONGSON2)
373 r4k_blast_icache_page_indexed =
374 loongson2_blast_icache32_page_indexed;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375 else
376 r4k_blast_icache_page_indexed =
377 blast_icache32_page_indexed;
378 } else if (ic_lsize == 64)
379 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
380}
381
Sanjay Lalf2e36562012-11-21 18:34:10 -0800382void (* r4k_blast_icache)(void);
383EXPORT_SYMBOL(r4k_blast_icache);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000385static void r4k_blast_icache_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386{
387 unsigned long ic_lsize = cpu_icache_line_size();
388
Chris Dearman73f40352006-06-20 18:06:52 +0100389 if (ic_lsize == 0)
390 r4k_blast_icache = (void *)cache_noop;
391 else if (ic_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392 r4k_blast_icache = blast_icache16;
393 else if (ic_lsize == 32) {
394 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
395 r4k_blast_icache = blast_r4600_v1_icache32;
396 else if (TX49XX_ICACHE_INDEX_INV_WAR)
397 r4k_blast_icache = tx49_blast_icache32;
Aaro Koskinen43a06842014-01-14 17:56:38 -0800398 else if (current_cpu_type() == CPU_LOONGSON2)
399 r4k_blast_icache = loongson2_blast_icache32;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400 else
401 r4k_blast_icache = blast_icache32;
402 } else if (ic_lsize == 64)
403 r4k_blast_icache = blast_icache64;
David Daney18a8cd62014-05-28 23:52:09 +0200404 else if (ic_lsize == 128)
405 r4k_blast_icache = blast_icache128;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406}
407
408static void (* r4k_blast_scache_page)(unsigned long addr);
409
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000410static void r4k_blast_scache_page_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411{
412 unsigned long sc_lsize = cpu_scache_line_size();
413
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000414 if (scache_size == 0)
Chris Dearman73f40352006-06-20 18:06:52 +0100415 r4k_blast_scache_page = (void *)cache_noop;
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000416 else if (sc_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417 r4k_blast_scache_page = blast_scache16_page;
418 else if (sc_lsize == 32)
419 r4k_blast_scache_page = blast_scache32_page;
420 else if (sc_lsize == 64)
421 r4k_blast_scache_page = blast_scache64_page;
422 else if (sc_lsize == 128)
423 r4k_blast_scache_page = blast_scache128_page;
424}
425
426static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
427
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000428static void r4k_blast_scache_page_indexed_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429{
430 unsigned long sc_lsize = cpu_scache_line_size();
431
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000432 if (scache_size == 0)
Chris Dearman73f40352006-06-20 18:06:52 +0100433 r4k_blast_scache_page_indexed = (void *)cache_noop;
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000434 else if (sc_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
436 else if (sc_lsize == 32)
437 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
438 else if (sc_lsize == 64)
439 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
440 else if (sc_lsize == 128)
441 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
442}
443
444static void (* r4k_blast_scache)(void);
445
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000446static void r4k_blast_scache_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447{
448 unsigned long sc_lsize = cpu_scache_line_size();
449
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000450 if (scache_size == 0)
Chris Dearman73f40352006-06-20 18:06:52 +0100451 r4k_blast_scache = (void *)cache_noop;
Ralf Baechle4debe4f2006-02-27 19:05:55 +0000452 else if (sc_lsize == 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453 r4k_blast_scache = blast_scache16;
454 else if (sc_lsize == 32)
455 r4k_blast_scache = blast_scache32;
456 else if (sc_lsize == 64)
457 r4k_blast_scache = blast_scache64;
458 else if (sc_lsize == 128)
459 r4k_blast_scache = blast_scache128;
460}
461
Linus Torvalds1da177e2005-04-16 15:20:36 -0700462static inline void local_r4k___flush_cache_all(void * args)
463{
Ralf Baechle10cc3522007-10-11 23:46:15 +0100464 switch (current_cpu_type()) {
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200465 case CPU_LOONGSON2:
Huacai Chenc579d312014-03-21 18:44:00 +0800466 case CPU_LOONGSON3:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700467 case CPU_R4000SC:
468 case CPU_R4000MC:
469 case CPU_R4400SC:
470 case CPU_R4400MC:
471 case CPU_R10000:
472 case CPU_R12000:
Kumba44d921b2006-05-16 22:23:59 -0400473 case CPU_R14000:
Joshua Kinard30577392015-01-21 07:59:45 -0500474 case CPU_R16000:
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200475 /*
476 * These caches are inclusive caches, that is, if something
477 * is not cached in the S-cache, we know it also won't be
478 * in one of the primary caches.
479 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700480 r4k_blast_scache();
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200481 break;
482
Florian Fainellif6758432016-04-04 10:55:36 -0700483 case CPU_BMIPS5000:
484 r4k_blast_scache();
485 __sync();
486 break;
487
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200488 default:
489 r4k_blast_dcache();
490 r4k_blast_icache();
491 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492 }
493}
494
495static void r4k___flush_cache_all(void)
496{
James Hogand374d932016-07-13 14:12:50 +0100497 r4k_on_each_cpu(R4K_INDEX, local_r4k___flush_cache_all, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700498}
499
James Hogan6d758bf2016-07-13 14:12:51 +0100500/**
501 * has_valid_asid() - Determine if an mm already has an ASID.
502 * @mm: Memory map.
503 * @type: R4K_HIT or R4K_INDEX, type of cache op.
504 *
505 * Determines whether @mm already has an ASID on any of the CPUs which cache ops
506 * of type @type within an r4k_on_each_cpu() call will affect. If
507 * r4k_on_each_cpu() does an SMP call to a single VPE in each core, then the
508 * scope of the operation is confined to sibling CPUs, otherwise all online CPUs
509 * will need to be checked.
510 *
511 * Must be called in non-preemptive context.
512 *
513 * Returns: 1 if the CPUs affected by @type cache ops have an ASID for @mm.
514 * 0 otherwise.
515 */
516static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type)
Ralf Baechlea76ab5c2007-10-08 16:38:37 +0100517{
James Hogan6d758bf2016-07-13 14:12:51 +0100518 unsigned int i;
519 const cpumask_t *mask = cpu_present_mask;
Ralf Baechlea76ab5c2007-10-08 16:38:37 +0100520
James Hogan6d758bf2016-07-13 14:12:51 +0100521 /* cpu_sibling_map[] undeclared when !CONFIG_SMP */
522#ifdef CONFIG_SMP
523 /*
524 * If r4k_on_each_cpu does SMP calls, it does them to a single VPE in
525 * each foreign core, so we only need to worry about siblings.
526 * Otherwise we need to worry about all present CPUs.
527 */
528 if (r4k_op_needs_ipi(type))
529 mask = &cpu_sibling_map[smp_processor_id()];
530#endif
531 for_each_cpu(i, mask)
Ralf Baechlea76ab5c2007-10-08 16:38:37 +0100532 if (cpu_context(i, mm))
533 return 1;
Ralf Baechlea76ab5c2007-10-08 16:38:37 +0100534 return 0;
Ralf Baechlea76ab5c2007-10-08 16:38:37 +0100535}
536
Ralf Baechle9c5a3d72008-04-05 15:13:23 +0100537static void r4k__flush_cache_vmap(void)
538{
539 r4k_blast_dcache();
540}
541
542static void r4k__flush_cache_vunmap(void)
543{
544 r4k_blast_dcache();
545}
546
James Hogana05c3922016-07-13 14:12:44 +0100547/*
548 * Note: flush_tlb_range() assumes flush_cache_range() sufficiently flushes
549 * whole caches when vma is executable.
550 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700551static inline void local_r4k_flush_cache_range(void * args)
552{
553 struct vm_area_struct *vma = args;
Ralf Baechle2eaa7ec2008-02-11 14:51:40 +0000554 int exec = vma->vm_flags & VM_EXEC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700555
James Hogan6d758bf2016-07-13 14:12:51 +0100556 if (!has_valid_asid(vma->vm_mm, R4K_INDEX))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700557 return;
558
James Hoganb2a3c5b2016-01-22 10:58:25 +0000559 /*
560 * If dcache can alias, we must blast it since mapping is changing.
561 * If executable, we must ensure any dirty lines are written back far
562 * enough to be visible to icache.
563 */
564 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
565 r4k_blast_dcache();
566 /* If executable, blast stale lines from icache */
Ralf Baechle2eaa7ec2008-02-11 14:51:40 +0000567 if (exec)
568 r4k_blast_icache();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700569}
570
571static void r4k_flush_cache_range(struct vm_area_struct *vma,
572 unsigned long start, unsigned long end)
573{
Ralf Baechle2eaa7ec2008-02-11 14:51:40 +0000574 int exec = vma->vm_flags & VM_EXEC;
Atsushi Nemoto0550d9d2006-08-22 21:15:47 +0900575
James Hoganb2a3c5b2016-01-22 10:58:25 +0000576 if (cpu_has_dc_aliases || exec)
James Hogand374d932016-07-13 14:12:50 +0100577 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_range, vma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700578}
579
580static inline void local_r4k_flush_cache_mm(void * args)
581{
582 struct mm_struct *mm = args;
583
James Hogan6d758bf2016-07-13 14:12:51 +0100584 if (!has_valid_asid(mm, R4K_INDEX))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700585 return;
586
Linus Torvalds1da177e2005-04-16 15:20:36 -0700587 /*
588 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
Joshua Kinard30577392015-01-21 07:59:45 -0500589 * only flush the primary caches but R1x000 behave sane ...
Ralf Baechle617667b2006-11-30 01:14:48 +0000590 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
591 * caches, so we can bail out early.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700592 */
Ralf Baechle10cc3522007-10-11 23:46:15 +0100593 if (current_cpu_type() == CPU_R4000SC ||
594 current_cpu_type() == CPU_R4000MC ||
595 current_cpu_type() == CPU_R4400SC ||
596 current_cpu_type() == CPU_R4400MC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700597 r4k_blast_scache();
Ralf Baechle617667b2006-11-30 01:14:48 +0000598 return;
599 }
600
601 r4k_blast_dcache();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700602}
603
604static void r4k_flush_cache_mm(struct mm_struct *mm)
605{
606 if (!cpu_has_dc_aliases)
607 return;
608
James Hogand374d932016-07-13 14:12:50 +0100609 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_mm, mm);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610}
611
612struct flush_cache_page_args {
613 struct vm_area_struct *vma;
Ralf Baechle6ec25802005-10-12 00:02:34 +0100614 unsigned long addr;
Atsushi Nemotode628932006-03-13 18:23:03 +0900615 unsigned long pfn;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616};
617
618static inline void local_r4k_flush_cache_page(void *args)
619{
620 struct flush_cache_page_args *fcp_args = args;
621 struct vm_area_struct *vma = fcp_args->vma;
Ralf Baechle6ec25802005-10-12 00:02:34 +0100622 unsigned long addr = fcp_args->addr;
Ralf Baechledb813fe2007-09-27 18:26:43 +0100623 struct page *page = pfn_to_page(fcp_args->pfn);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700624 int exec = vma->vm_flags & VM_EXEC;
625 struct mm_struct *mm = vma->vm_mm;
Ralf Baechlec9c50232008-06-14 22:22:08 +0100626 int map_coherent = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627 pgd_t *pgdp;
Ralf Baechlec6e8b582005-02-10 12:19:59 +0000628 pud_t *pudp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700629 pmd_t *pmdp;
630 pte_t *ptep;
Ralf Baechledb813fe2007-09-27 18:26:43 +0100631 void *vaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700632
Ralf Baechle79acf832005-02-10 13:54:37 +0000633 /*
James Hogan6d758bf2016-07-13 14:12:51 +0100634 * If owns no valid ASID yet, cannot possibly have gotten
Ralf Baechle79acf832005-02-10 13:54:37 +0000635 * this page into the cache.
636 */
James Hogan6d758bf2016-07-13 14:12:51 +0100637 if (!has_valid_asid(mm, R4K_HIT))
Ralf Baechle79acf832005-02-10 13:54:37 +0000638 return;
639
Ralf Baechle6ec25802005-10-12 00:02:34 +0100640 addr &= PAGE_MASK;
641 pgdp = pgd_offset(mm, addr);
642 pudp = pud_offset(pgdp, addr);
643 pmdp = pmd_offset(pudp, addr);
644 ptep = pte_offset(pmdp, addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645
646 /*
647 * If the page isn't marked valid, the page cannot possibly be
648 * in the cache.
649 */
Ralf Baechle526af352008-01-29 10:14:55 +0000650 if (!(pte_present(*ptep)))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651 return;
652
Ralf Baechledb813fe2007-09-27 18:26:43 +0100653 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
654 vaddr = NULL;
655 else {
656 /*
657 * Use kmap_coherent or kmap_atomic to do flushes for
658 * another ASID than the current one.
659 */
Ralf Baechlec9c50232008-06-14 22:22:08 +0100660 map_coherent = (cpu_has_dc_aliases &&
Kirill A. Shutemove1534ae2016-01-15 16:53:46 -0800661 page_mapcount(page) &&
662 !Page_dcache_dirty(page));
Ralf Baechlec9c50232008-06-14 22:22:08 +0100663 if (map_coherent)
Ralf Baechledb813fe2007-09-27 18:26:43 +0100664 vaddr = kmap_coherent(page, addr);
665 else
Cong Wang9c020482011-11-25 23:14:15 +0800666 vaddr = kmap_atomic(page);
Ralf Baechledb813fe2007-09-27 18:26:43 +0100667 addr = (unsigned long)vaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700668 }
669
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
Markos Chandras80ca69f2014-01-16 13:11:08 +0000671 vaddr ? r4k_blast_dcache_page(addr) :
672 r4k_blast_dcache_user_page(addr);
Ralf Baechle39b8d522008-04-28 17:14:26 +0100673 if (exec && !cpu_icache_snoops_remote_store)
674 r4k_blast_scache_page(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675 }
676 if (exec) {
Ralf Baechledb813fe2007-09-27 18:26:43 +0100677 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678 int cpu = smp_processor_id();
679
Thiemo Seufer26a51b22005-02-19 13:32:02 +0000680 if (cpu_context(cpu, mm) != 0)
681 drop_mmu_context(mm, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700682 } else
Markos Chandras80ca69f2014-01-16 13:11:08 +0000683 vaddr ? r4k_blast_icache_page(addr) :
684 r4k_blast_icache_user_page(addr);
Ralf Baechledb813fe2007-09-27 18:26:43 +0100685 }
686
687 if (vaddr) {
Ralf Baechlec9c50232008-06-14 22:22:08 +0100688 if (map_coherent)
Ralf Baechledb813fe2007-09-27 18:26:43 +0100689 kunmap_coherent();
690 else
Cong Wang9c020482011-11-25 23:14:15 +0800691 kunmap_atomic(vaddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692 }
693}
694
Ralf Baechle6ec25802005-10-12 00:02:34 +0100695static void r4k_flush_cache_page(struct vm_area_struct *vma,
696 unsigned long addr, unsigned long pfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697{
698 struct flush_cache_page_args args;
699
Linus Torvalds1da177e2005-04-16 15:20:36 -0700700 args.vma = vma;
Ralf Baechle6ec25802005-10-12 00:02:34 +0100701 args.addr = addr;
Atsushi Nemotode628932006-03-13 18:23:03 +0900702 args.pfn = pfn;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703
James Hogand374d932016-07-13 14:12:50 +0100704 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_page, &args);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700705}
706
707static inline void local_r4k_flush_data_cache_page(void * addr)
708{
709 r4k_blast_dcache_page((unsigned long) addr);
710}
711
712static void r4k_flush_data_cache_page(unsigned long addr)
713{
Ralf Baechlea754f702007-11-03 01:01:37 +0000714 if (in_atomic())
715 local_r4k_flush_data_cache_page((void *)addr);
716 else
James Hogand374d932016-07-13 14:12:50 +0100717 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_data_cache_page,
718 (void *) addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719}
720
721struct flush_icache_range_args {
Atsushi Nemotod4264f12006-01-29 02:27:51 +0900722 unsigned long start;
723 unsigned long end;
James Hogan27b93d92016-07-13 14:12:54 +0100724 unsigned int type;
James Hoganb2ff7172016-09-01 17:30:15 +0100725 bool user;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726};
727
James Hogan27b93d92016-07-13 14:12:54 +0100728static inline void __local_r4k_flush_icache_range(unsigned long start,
729 unsigned long end,
James Hoganb2ff7172016-09-01 17:30:15 +0100730 unsigned int type,
731 bool user)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700733 if (!cpu_has_ic_fills_f_dc) {
James Hogan27b93d92016-07-13 14:12:54 +0100734 if (type == R4K_INDEX ||
735 (type & R4K_INDEX && end - start >= dcache_size)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700736 r4k_blast_dcache();
737 } else {
Thiemo Seufer10a3dab2005-09-09 20:26:54 +0000738 R4600_HIT_CACHEOP_WAR_IMPL;
James Hoganb2ff7172016-09-01 17:30:15 +0100739 if (user)
740 protected_blast_dcache_range(start, end);
741 else
742 blast_dcache_range(start, end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700743 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700744 }
745
James Hogan27b93d92016-07-13 14:12:54 +0100746 if (type == R4K_INDEX ||
747 (type & R4K_INDEX && end - start > icache_size))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700748 r4k_blast_icache();
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200749 else {
750 switch (boot_cpu_type()) {
751 case CPU_LOONGSON2:
Huacai Chenbad009f2014-01-14 17:56:37 -0800752 protected_loongson2_blast_icache_range(start, end);
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200753 break;
754
755 default:
James Hoganb2ff7172016-09-01 17:30:15 +0100756 if (user)
757 protected_blast_icache_range(start, end);
758 else
759 blast_icache_range(start, end);
Ralf Baechle14bd8c02013-09-25 18:21:26 +0200760 break;
761 }
762 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700763}
764
James Hogan27b93d92016-07-13 14:12:54 +0100765static inline void local_r4k_flush_icache_range(unsigned long start,
766 unsigned long end)
767{
James Hoganb2ff7172016-09-01 17:30:15 +0100768 __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, false);
769}
770
771static inline void local_r4k_flush_icache_user_range(unsigned long start,
772 unsigned long end)
773{
774 __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, true);
James Hogan27b93d92016-07-13 14:12:54 +0100775}
776
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +0200777static inline void local_r4k_flush_icache_range_ipi(void *args)
778{
779 struct flush_icache_range_args *fir_args = args;
780 unsigned long start = fir_args->start;
781 unsigned long end = fir_args->end;
James Hogan27b93d92016-07-13 14:12:54 +0100782 unsigned int type = fir_args->type;
James Hoganb2ff7172016-09-01 17:30:15 +0100783 bool user = fir_args->user;
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +0200784
James Hoganb2ff7172016-09-01 17:30:15 +0100785 __local_r4k_flush_icache_range(start, end, type, user);
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +0200786}
787
James Hoganb2ff7172016-09-01 17:30:15 +0100788static void __r4k_flush_icache_range(unsigned long start, unsigned long end,
789 bool user)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790{
791 struct flush_icache_range_args args;
James Hoganf70ddc02016-07-13 14:12:55 +0100792 unsigned long size, cache_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700793
794 args.start = start;
795 args.end = end;
James Hogan27b93d92016-07-13 14:12:54 +0100796 args.type = R4K_HIT | R4K_INDEX;
James Hoganb2ff7172016-09-01 17:30:15 +0100797 args.user = user;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798
James Hoganf70ddc02016-07-13 14:12:55 +0100799 /*
800 * Indexed cache ops require an SMP call.
801 * Consider if that can or should be avoided.
802 */
803 preempt_disable();
804 if (r4k_op_needs_ipi(R4K_INDEX) && !r4k_op_needs_ipi(R4K_HIT)) {
805 /*
806 * If address-based cache ops don't require an SMP call, then
807 * use them exclusively for small flushes.
808 */
Paul Burton801f8232016-09-05 15:24:54 +0100809 size = end - start;
James Hoganf70ddc02016-07-13 14:12:55 +0100810 cache_size = icache_size;
811 if (!cpu_has_ic_fills_f_dc) {
812 size *= 2;
813 cache_size += dcache_size;
814 }
815 if (size <= cache_size)
816 args.type &= ~R4K_INDEX;
817 }
James Hogan27b93d92016-07-13 14:12:54 +0100818 r4k_on_each_cpu(args.type, local_r4k_flush_icache_range_ipi, &args);
James Hoganf70ddc02016-07-13 14:12:55 +0100819 preempt_enable();
Ralf Baechlecc61c1f2005-07-12 18:35:38 +0000820 instruction_hazard();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700821}
822
James Hoganb2ff7172016-09-01 17:30:15 +0100823static void r4k_flush_icache_range(unsigned long start, unsigned long end)
824{
825 return __r4k_flush_icache_range(start, end, false);
826}
827
828static void r4k_flush_icache_user_range(unsigned long start, unsigned long end)
829{
830 return __r4k_flush_icache_range(start, end, true);
831}
832
Manuel Lauss80057112014-02-20 14:59:22 +0100833#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700834
835static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
836{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700837 /* Catch bad driver code */
838 BUG_ON(size == 0);
839
Ralf Baechleff522052013-09-17 12:44:31 +0200840 preempt_disable();
Ralf Baechlefc5d2d22006-07-06 13:04:01 +0100841 if (cpu_has_inclusive_pcaches) {
Atsushi Nemoto41700e72006-02-10 00:39:06 +0900842 if (size >= scache_size)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700843 r4k_blast_scache();
Atsushi Nemoto41700e72006-02-10 00:39:06 +0900844 else
845 blast_scache_range(addr, addr + size);
Yoichi Yuasa5596b0b2013-10-02 15:03:03 +0900846 preempt_enable();
Kevin Cernekeed0023c42010-09-06 21:03:46 -0700847 __sync();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700848 return;
849 }
850
851 /*
852 * Either no secondary cache or the available caches don't have the
853 * subset property so we have to flush the primary caches
854 * explicitly
855 */
Ralf Baechlec00ab482016-07-02 10:38:05 +0200856 if (size >= dcache_size) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700857 r4k_blast_dcache();
858 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859 R4600_HIT_CACHEOP_WAR_IMPL;
Atsushi Nemoto41700e72006-02-10 00:39:06 +0900860 blast_dcache_range(addr, addr + size);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700861 }
Ralf Baechleff522052013-09-17 12:44:31 +0200862 preempt_enable();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700863
864 bc_wback_inv(addr, size);
Kevin Cernekeed0023c42010-09-06 21:03:46 -0700865 __sync();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700866}
867
868static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
869{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700870 /* Catch bad driver code */
871 BUG_ON(size == 0);
872
Ralf Baechleff522052013-09-17 12:44:31 +0200873 preempt_disable();
Ralf Baechlefc5d2d22006-07-06 13:04:01 +0100874 if (cpu_has_inclusive_pcaches) {
Atsushi Nemoto41700e72006-02-10 00:39:06 +0900875 if (size >= scache_size)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876 r4k_blast_scache();
Ralf Baechlea8ca8b62009-01-11 18:44:49 +0000877 else {
Ralf Baechlea8ca8b62009-01-11 18:44:49 +0000878 /*
879 * There is no clearly documented alignment requirement
880 * for the cache instruction on MIPS processors and
881 * some processors, among them the RM5200 and RM7000
882 * QED processors will throw an address error for cache
Ralf Baechle70342282013-01-22 12:59:30 +0100883 * hit ops with insufficient alignment. Solved by
Ralf Baechlea8ca8b62009-01-11 18:44:49 +0000884 * aligning the address to cache line size.
885 */
Thomas Bogendoerfere9c33572007-11-26 23:40:01 +0100886 blast_inv_scache_range(addr, addr + size);
Ralf Baechlea8ca8b62009-01-11 18:44:49 +0000887 }
Yoichi Yuasa5596b0b2013-10-02 15:03:03 +0900888 preempt_enable();
Kevin Cernekeed0023c42010-09-06 21:03:46 -0700889 __sync();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890 return;
891 }
892
Ralf Baechlec00ab482016-07-02 10:38:05 +0200893 if (size >= dcache_size) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700894 r4k_blast_dcache();
895 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896 R4600_HIT_CACHEOP_WAR_IMPL;
Thomas Bogendoerfere9c33572007-11-26 23:40:01 +0100897 blast_inv_dcache_range(addr, addr + size);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700898 }
Ralf Baechleff522052013-09-17 12:44:31 +0200899 preempt_enable();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700900
901 bc_inv(addr, size);
Kevin Cernekeed0023c42010-09-06 21:03:46 -0700902 __sync();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700903}
Manuel Lauss80057112014-02-20 14:59:22 +0100904#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700905
James Hogane523f282016-07-13 14:12:48 +0100906struct flush_cache_sigtramp_args {
907 struct mm_struct *mm;
908 struct page *page;
909 unsigned long addr;
910};
911
Linus Torvalds1da177e2005-04-16 15:20:36 -0700912/*
913 * While we're protected against bad userland addresses we don't care
914 * very much about what happens in that case. Usually a segmentation
915 * fault will dump the process later on anyway ...
916 */
James Hogane523f282016-07-13 14:12:48 +0100917static void local_r4k_flush_cache_sigtramp(void *args)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700918{
James Hogane523f282016-07-13 14:12:48 +0100919 struct flush_cache_sigtramp_args *fcs_args = args;
920 unsigned long addr = fcs_args->addr;
921 struct page *page = fcs_args->page;
922 struct mm_struct *mm = fcs_args->mm;
923 int map_coherent = 0;
924 void *vaddr;
925
Thiemo Seufer02fe2c92005-09-09 19:45:41 +0000926 unsigned long ic_lsize = cpu_icache_line_size();
927 unsigned long dc_lsize = cpu_dcache_line_size();
928 unsigned long sc_lsize = cpu_scache_line_size();
James Hogane523f282016-07-13 14:12:48 +0100929
930 /*
931 * If owns no valid ASID yet, cannot possibly have gotten
932 * this page into the cache.
933 */
James Hogan6d758bf2016-07-13 14:12:51 +0100934 if (!has_valid_asid(mm, R4K_HIT))
James Hogane523f282016-07-13 14:12:48 +0100935 return;
936
937 if (mm == current->active_mm) {
938 vaddr = NULL;
939 } else {
940 /*
941 * Use kmap_coherent or kmap_atomic to do flushes for
942 * another ASID than the current one.
943 */
944 map_coherent = (cpu_has_dc_aliases &&
945 page_mapcount(page) &&
946 !Page_dcache_dirty(page));
947 if (map_coherent)
948 vaddr = kmap_coherent(page, addr);
949 else
950 vaddr = kmap_atomic(page);
951 addr = (unsigned long)vaddr + (addr & ~PAGE_MASK);
952 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700953
954 R4600_HIT_CACHEOP_WAR_IMPL;
James Hogan8bd646e2016-07-13 14:12:49 +0100955 if (!cpu_has_ic_fills_f_dc) {
956 if (dc_lsize)
957 vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
958 : protected_writeback_dcache_line(
959 addr & ~(dc_lsize - 1));
960 if (!cpu_icache_snoops_remote_store && scache_size)
961 vaddr ? flush_scache_line(addr & ~(sc_lsize - 1))
962 : protected_writeback_scache_line(
963 addr & ~(sc_lsize - 1));
964 }
Chris Dearman73f40352006-06-20 18:06:52 +0100965 if (ic_lsize)
James Hogane523f282016-07-13 14:12:48 +0100966 vaddr ? flush_icache_line(addr & ~(ic_lsize - 1))
967 : protected_flush_icache_line(addr & ~(ic_lsize - 1));
968
969 if (vaddr) {
970 if (map_coherent)
971 kunmap_coherent();
972 else
973 kunmap_atomic(vaddr);
974 }
975
Linus Torvalds1da177e2005-04-16 15:20:36 -0700976 if (MIPS4K_ICACHE_REFILL_WAR) {
977 __asm__ __volatile__ (
978 ".set push\n\t"
979 ".set noat\n\t"
Markos Chandras4ee48622014-12-02 15:30:19 +0000980 ".set "MIPS_ISA_LEVEL"\n\t"
Ralf Baechle875d43e2005-09-03 15:56:16 -0700981#ifdef CONFIG_32BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700982 "la $at,1f\n\t"
983#endif
Ralf Baechle875d43e2005-09-03 15:56:16 -0700984#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700985 "dla $at,1f\n\t"
986#endif
987 "cache %0,($at)\n\t"
988 "nop; nop; nop\n"
989 "1:\n\t"
990 ".set pop"
991 :
992 : "i" (Hit_Invalidate_I));
993 }
994 if (MIPS_CACHE_SYNC_WAR)
995 __asm__ __volatile__ ("sync");
996}
997
998static void r4k_flush_cache_sigtramp(unsigned long addr)
999{
James Hogane523f282016-07-13 14:12:48 +01001000 struct flush_cache_sigtramp_args args;
1001 int npages;
1002
1003 down_read(&current->mm->mmap_sem);
1004
1005 npages = get_user_pages_fast(addr, 1, 0, &args.page);
1006 if (npages < 1)
1007 goto out;
1008
1009 args.mm = current->mm;
1010 args.addr = addr;
1011
James Hogand374d932016-07-13 14:12:50 +01001012 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_sigtramp, &args);
James Hogane523f282016-07-13 14:12:48 +01001013
1014 put_page(args.page);
1015out:
1016 up_read(&current->mm->mmap_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001017}
1018
1019static void r4k_flush_icache_all(void)
1020{
1021 if (cpu_has_vtag_icache)
1022 r4k_blast_icache();
1023}
1024
Ralf Baechled9cdc9012011-06-17 16:20:28 +01001025struct flush_kernel_vmap_range_args {
1026 unsigned long vaddr;
1027 int size;
1028};
1029
James Hogana9341ae2016-07-13 14:12:53 +01001030static inline void local_r4k_flush_kernel_vmap_range_index(void *args)
1031{
1032 /*
1033 * Aliases only affect the primary caches so don't bother with
1034 * S-caches or T-caches.
1035 */
1036 r4k_blast_dcache();
1037}
1038
Ralf Baechled9cdc9012011-06-17 16:20:28 +01001039static inline void local_r4k_flush_kernel_vmap_range(void *args)
1040{
1041 struct flush_kernel_vmap_range_args *vmra = args;
1042 unsigned long vaddr = vmra->vaddr;
1043 int size = vmra->size;
1044
1045 /*
1046 * Aliases only affect the primary caches so don't bother with
1047 * S-caches or T-caches.
1048 */
James Hogana9341ae2016-07-13 14:12:53 +01001049 R4600_HIT_CACHEOP_WAR_IMPL;
1050 blast_dcache_range(vaddr, vaddr + size);
Ralf Baechled9cdc9012011-06-17 16:20:28 +01001051}
1052
1053static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
1054{
1055 struct flush_kernel_vmap_range_args args;
1056
1057 args.vaddr = (unsigned long) vaddr;
1058 args.size = size;
1059
James Hogana9341ae2016-07-13 14:12:53 +01001060 if (size >= dcache_size)
1061 r4k_on_each_cpu(R4K_INDEX,
1062 local_r4k_flush_kernel_vmap_range_index, NULL);
1063 else
1064 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_kernel_vmap_range,
1065 &args);
Ralf Baechled9cdc9012011-06-17 16:20:28 +01001066}
1067
Linus Torvalds1da177e2005-04-16 15:20:36 -07001068static inline void rm7k_erratum31(void)
1069{
1070 const unsigned long ic_lsize = 32;
1071 unsigned long addr;
1072
1073 /* RM7000 erratum #31. The icache is screwed at startup. */
1074 write_c0_taglo(0);
1075 write_c0_taghi(0);
1076
1077 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
1078 __asm__ __volatile__ (
Thiemo Seuferd8748a32005-09-02 09:56:12 +00001079 ".set push\n\t"
Linus Torvalds1da177e2005-04-16 15:20:36 -07001080 ".set noreorder\n\t"
1081 ".set mips3\n\t"
1082 "cache\t%1, 0(%0)\n\t"
1083 "cache\t%1, 0x1000(%0)\n\t"
1084 "cache\t%1, 0x2000(%0)\n\t"
1085 "cache\t%1, 0x3000(%0)\n\t"
1086 "cache\t%2, 0(%0)\n\t"
1087 "cache\t%2, 0x1000(%0)\n\t"
1088 "cache\t%2, 0x2000(%0)\n\t"
1089 "cache\t%2, 0x3000(%0)\n\t"
1090 "cache\t%1, 0(%0)\n\t"
1091 "cache\t%1, 0x1000(%0)\n\t"
1092 "cache\t%1, 0x2000(%0)\n\t"
1093 "cache\t%1, 0x3000(%0)\n\t"
Thiemo Seuferd8748a32005-09-02 09:56:12 +00001094 ".set pop\n"
Linus Torvalds1da177e2005-04-16 15:20:36 -07001095 :
1096 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
1097 }
1098}
1099
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001100static inline int alias_74k_erratum(struct cpuinfo_mips *c)
Steven J. Hill006a8512012-06-26 04:11:03 +00001101{
Maciej W. Rozycki9213ad72013-09-18 19:08:15 +01001102 unsigned int imp = c->processor_id & PRID_IMP_MASK;
1103 unsigned int rev = c->processor_id & PRID_REV_MASK;
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001104 int present = 0;
Maciej W. Rozycki9213ad72013-09-18 19:08:15 +01001105
Steven J. Hill006a8512012-06-26 04:11:03 +00001106 /*
1107 * Early versions of the 74K do not update the cache tags on a
1108 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001109 * aliases. In this case it is better to treat the cache as always
1110 * having aliases. Also disable the synonym tag update feature
1111 * where available. In this case no opportunistic tag update will
1112 * happen where a load causes a virtual address miss but a physical
1113 * address hit during a D-cache look-up.
Steven J. Hill006a8512012-06-26 04:11:03 +00001114 */
Maciej W. Rozycki9213ad72013-09-18 19:08:15 +01001115 switch (imp) {
1116 case PRID_IMP_74K:
1117 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001118 present = 1;
Maciej W. Rozycki9213ad72013-09-18 19:08:15 +01001119 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
1120 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
1121 break;
1122 case PRID_IMP_1074K:
1123 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001124 present = 1;
Maciej W. Rozycki9213ad72013-09-18 19:08:15 +01001125 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
1126 }
1127 break;
1128 default:
1129 BUG();
Steven J. Hill006a8512012-06-26 04:11:03 +00001130 }
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001131
1132 return present;
Steven J. Hill006a8512012-06-26 04:11:03 +00001133}
1134
Kevin Cernekeed74b0172014-10-20 21:28:00 -07001135static void b5k_instruction_hazard(void)
1136{
1137 __sync();
1138 __sync();
1139 __asm__ __volatile__(
1140 " nop; nop; nop; nop; nop; nop; nop; nop\n"
1141 " nop; nop; nop; nop; nop; nop; nop; nop\n"
1142 " nop; nop; nop; nop; nop; nop; nop; nop\n"
1143 " nop; nop; nop; nop; nop; nop; nop; nop\n"
1144 : : : "memory");
1145}
1146
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001147static char *way_string[] = { NULL, "direct mapped", "2-way",
Paul Burton1e18ac72015-07-09 10:40:41 +01001148 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
1149 "9-way", "10-way", "11-way", "12-way",
1150 "13-way", "14-way", "15-way", "16-way",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151};
1152
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001153static void probe_pcache(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001154{
1155 struct cpuinfo_mips *c = &current_cpu_data;
1156 unsigned int config = read_c0_config();
1157 unsigned int prid = read_c0_prid();
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001158 int has_74k_erratum = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001159 unsigned long config1;
1160 unsigned int lsize;
1161
Ralf Baechle69f24d12013-09-17 10:25:47 +02001162 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001163 case CPU_R4600: /* QED style two way caches? */
1164 case CPU_R4700:
1165 case CPU_R5000:
1166 case CPU_NEVADA:
1167 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1168 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1169 c->icache.ways = 2;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001170 c->icache.waybit = __ffs(icache_size/2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001171
1172 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1173 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1174 c->dcache.ways = 2;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001175 c->dcache.waybit= __ffs(dcache_size/2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001176
1177 c->options |= MIPS_CPU_CACHE_CDEX_P;
1178 break;
1179
1180 case CPU_R5432:
1181 case CPU_R5500:
1182 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1183 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1184 c->icache.ways = 2;
1185 c->icache.waybit= 0;
1186
1187 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1188 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1189 c->dcache.ways = 2;
1190 c->dcache.waybit = 0;
1191
Shinya Kuribayashi58648102009-03-18 09:04:01 +09001192 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001193 break;
1194
1195 case CPU_TX49XX:
1196 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1197 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1198 c->icache.ways = 4;
1199 c->icache.waybit= 0;
1200
1201 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1202 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1203 c->dcache.ways = 4;
1204 c->dcache.waybit = 0;
1205
1206 c->options |= MIPS_CPU_CACHE_CDEX_P;
Atsushi Nemotode862b42006-03-17 12:59:22 +09001207 c->options |= MIPS_CPU_PREFETCH;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001208 break;
1209
1210 case CPU_R4000PC:
1211 case CPU_R4000SC:
1212 case CPU_R4000MC:
1213 case CPU_R4400PC:
1214 case CPU_R4400SC:
1215 case CPU_R4400MC:
1216 case CPU_R4300:
1217 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1218 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1219 c->icache.ways = 1;
Ralf Baechle70342282013-01-22 12:59:30 +01001220 c->icache.waybit = 0; /* doesn't matter */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001221
1222 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1223 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1224 c->dcache.ways = 1;
1225 c->dcache.waybit = 0; /* does not matter */
1226
1227 c->options |= MIPS_CPU_CACHE_CDEX_P;
1228 break;
1229
1230 case CPU_R10000:
1231 case CPU_R12000:
Kumba44d921b2006-05-16 22:23:59 -04001232 case CPU_R14000:
Joshua Kinard30577392015-01-21 07:59:45 -05001233 case CPU_R16000:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001234 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
1235 c->icache.linesz = 64;
1236 c->icache.ways = 2;
1237 c->icache.waybit = 0;
1238
1239 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
1240 c->dcache.linesz = 32;
1241 c->dcache.ways = 2;
1242 c->dcache.waybit = 0;
1243
1244 c->options |= MIPS_CPU_PREFETCH;
1245 break;
1246
1247 case CPU_VR4133:
Yoichi Yuasa2874fe52006-07-08 00:42:12 +09001248 write_c0_config(config & ~VR41_CONF_P4K);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001249 case CPU_VR4131:
1250 /* Workaround for cache instruction bug of VR4131 */
1251 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
1252 c->processor_id == 0x0c82U) {
Yoichi Yuasa4e8ab362006-07-04 22:59:41 +09001253 config |= 0x00400000U;
1254 if (c->processor_id == 0x0c80U)
1255 config |= VR41_CONF_BP;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001256 write_c0_config(config);
Yoichi Yuasa1058ecd2006-07-08 00:42:01 +09001257 } else
1258 c->options |= MIPS_CPU_CACHE_CDEX_P;
1259
Linus Torvalds1da177e2005-04-16 15:20:36 -07001260 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1261 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1262 c->icache.ways = 2;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001263 c->icache.waybit = __ffs(icache_size/2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001264
1265 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1266 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1267 c->dcache.ways = 2;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001268 c->dcache.waybit = __ffs(dcache_size/2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001269 break;
1270
1271 case CPU_VR41XX:
1272 case CPU_VR4111:
1273 case CPU_VR4121:
1274 case CPU_VR4122:
1275 case CPU_VR4181:
1276 case CPU_VR4181A:
1277 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1278 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1279 c->icache.ways = 1;
Ralf Baechle70342282013-01-22 12:59:30 +01001280 c->icache.waybit = 0; /* doesn't matter */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001281
1282 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1283 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1284 c->dcache.ways = 1;
1285 c->dcache.waybit = 0; /* does not matter */
1286
1287 c->options |= MIPS_CPU_CACHE_CDEX_P;
1288 break;
1289
1290 case CPU_RM7000:
1291 rm7k_erratum31();
1292
Linus Torvalds1da177e2005-04-16 15:20:36 -07001293 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1294 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1295 c->icache.ways = 4;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001296 c->icache.waybit = __ffs(icache_size / c->icache.ways);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001297
1298 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1299 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1300 c->dcache.ways = 4;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001301 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001302
Linus Torvalds1da177e2005-04-16 15:20:36 -07001303 c->options |= MIPS_CPU_CACHE_CDEX_P;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001304 c->options |= MIPS_CPU_PREFETCH;
1305 break;
1306
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001307 case CPU_LOONGSON2:
1308 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1309 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1310 if (prid & 0x3)
1311 c->icache.ways = 4;
1312 else
1313 c->icache.ways = 2;
1314 c->icache.waybit = 0;
1315
1316 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1317 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1318 if (prid & 0x3)
1319 c->dcache.ways = 4;
1320 else
1321 c->dcache.ways = 2;
1322 c->dcache.waybit = 0;
1323 break;
1324
Huacai Chenc579d312014-03-21 18:44:00 +08001325 case CPU_LOONGSON3:
1326 config1 = read_c0_config1();
1327 lsize = (config1 >> 19) & 7;
1328 if (lsize)
1329 c->icache.linesz = 2 << lsize;
1330 else
1331 c->icache.linesz = 0;
1332 c->icache.sets = 64 << ((config1 >> 22) & 7);
1333 c->icache.ways = 1 + ((config1 >> 16) & 7);
1334 icache_size = c->icache.sets *
1335 c->icache.ways *
1336 c->icache.linesz;
1337 c->icache.waybit = 0;
1338
1339 lsize = (config1 >> 10) & 7;
1340 if (lsize)
1341 c->dcache.linesz = 2 << lsize;
1342 else
1343 c->dcache.linesz = 0;
1344 c->dcache.sets = 64 << ((config1 >> 13) & 7);
1345 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1346 dcache_size = c->dcache.sets *
1347 c->dcache.ways *
1348 c->dcache.linesz;
1349 c->dcache.waybit = 0;
Huacai Chen1e820da32016-03-03 09:45:13 +08001350 if ((prid & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2)
1351 c->options |= MIPS_CPU_PREFETCH;
Huacai Chenc579d312014-03-21 18:44:00 +08001352 break;
1353
David Daney18a8cd62014-05-28 23:52:09 +02001354 case CPU_CAVIUM_OCTEON3:
1355 /* For now lie about the number of ways. */
1356 c->icache.linesz = 128;
1357 c->icache.sets = 16;
1358 c->icache.ways = 8;
1359 c->icache.flags |= MIPS_CACHE_VTAG;
1360 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
1361
1362 c->dcache.linesz = 128;
1363 c->dcache.ways = 8;
1364 c->dcache.sets = 8;
1365 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
1366 c->options |= MIPS_CPU_PREFETCH;
1367 break;
1368
Linus Torvalds1da177e2005-04-16 15:20:36 -07001369 default:
1370 if (!(config & MIPS_CONF_M))
1371 panic("Don't know how to probe P-caches on this cpu.");
1372
1373 /*
1374 * So we seem to be a MIPS32 or MIPS64 CPU
1375 * So let's probe the I-cache ...
1376 */
1377 config1 = read_c0_config1();
1378
Markos Chandras175cba82013-09-19 18:18:41 +01001379 lsize = (config1 >> 19) & 7;
1380
1381 /* IL == 7 is reserved */
1382 if (lsize == 7)
1383 panic("Invalid icache line size");
1384
1385 c->icache.linesz = lsize ? 2 << lsize : 0;
1386
Douglas Leungdc34b052012-07-19 09:11:13 +02001387 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001388 c->icache.ways = 1 + ((config1 >> 16) & 7);
1389
1390 icache_size = c->icache.sets *
Ralf Baechle70342282013-01-22 12:59:30 +01001391 c->icache.ways *
1392 c->icache.linesz;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001393 c->icache.waybit = __ffs(icache_size/c->icache.ways);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001394
James Hogan4b34bca2016-06-15 19:29:59 +01001395 if (config & MIPS_CONF_VI)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001396 c->icache.flags |= MIPS_CACHE_VTAG;
1397
1398 /*
1399 * Now probe the MIPS32 / MIPS64 data cache.
1400 */
1401 c->dcache.flags = 0;
1402
Markos Chandras175cba82013-09-19 18:18:41 +01001403 lsize = (config1 >> 10) & 7;
1404
1405 /* DL == 7 is reserved */
1406 if (lsize == 7)
1407 panic("Invalid dcache line size");
1408
1409 c->dcache.linesz = lsize ? 2 << lsize : 0;
1410
Douglas Leungdc34b052012-07-19 09:11:13 +02001411 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001412 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1413
1414 dcache_size = c->dcache.sets *
Ralf Baechle70342282013-01-22 12:59:30 +01001415 c->dcache.ways *
1416 c->dcache.linesz;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +09001417 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001418
1419 c->options |= MIPS_CPU_PREFETCH;
1420 break;
1421 }
1422
1423 /*
1424 * Processor configuration sanity check for the R4000SC erratum
Ralf Baechle70342282013-01-22 12:59:30 +01001425 * #5. With page sizes larger than 32kB there is no possibility
Linus Torvalds1da177e2005-04-16 15:20:36 -07001426 * to get a VCE exception anymore so we don't care about this
1427 * misconfiguration. The case is rather theoretical anyway;
1428 * presumably no vendor is shipping his hardware in the "bad"
1429 * configuration.
1430 */
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001431 if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1432 (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07001433 !(config & CONF_SC) && c->icache.linesz != 16 &&
1434 PAGE_SIZE <= 0x8000)
1435 panic("Improper R4000SC processor configuration detected");
1436
1437 /* compute a couple of other cache variables */
1438 c->icache.waysize = icache_size / c->icache.ways;
1439 c->dcache.waysize = dcache_size / c->dcache.ways;
1440
Chris Dearman73f40352006-06-20 18:06:52 +01001441 c->icache.sets = c->icache.linesz ?
1442 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1443 c->dcache.sets = c->dcache.linesz ?
1444 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001445
1446 /*
Joshua Kinard30577392015-01-21 07:59:45 -05001447 * R1x000 P-caches are odd in a positive way. They're 32kB 2-way
1448 * virtually indexed so normally would suffer from aliases. So
Linus Torvalds1da177e2005-04-16 15:20:36 -07001449 * normally they'd suffer from aliases but magic in the hardware deals
1450 * with that for us so we don't need to take care ourselves.
1451 */
Ralf Baechle69f24d12013-09-17 10:25:47 +02001452 switch (current_cpu_type()) {
Ralf Baechlea95970f2005-02-07 21:41:32 +00001453 case CPU_20KC:
Ralf Baechle505403b2005-02-07 21:53:39 +00001454 case CPU_25KF:
Paul Burton819da1e2016-08-19 18:13:34 +01001455 case CPU_I6400:
Ralf Baechle641e97f2007-10-11 23:46:05 +01001456 case CPU_SB1:
1457 case CPU_SB1A:
Jayachandran Cefa0f812011-05-07 01:36:21 +05301458 case CPU_XLR:
Atsushi Nemotode628932006-03-13 18:23:03 +09001459 c->dcache.flags |= MIPS_CACHE_PINDEX;
Ralf Baechle641e97f2007-10-11 23:46:05 +01001460 break;
1461
Ralf Baechled1e344e2005-02-04 15:51:26 +00001462 case CPU_R10000:
1463 case CPU_R12000:
Kumba44d921b2006-05-16 22:23:59 -04001464 case CPU_R14000:
Joshua Kinard30577392015-01-21 07:59:45 -05001465 case CPU_R16000:
Ralf Baechled1e344e2005-02-04 15:51:26 +00001466 break;
Ralf Baechle641e97f2007-10-11 23:46:05 +01001467
Maciej W. Rozyckibf4aac02014-06-28 23:28:08 +01001468 case CPU_74K:
1469 case CPU_1074K:
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001470 has_74k_erratum = alias_74k_erratum(c);
Maciej W. Rozyckibf4aac02014-06-28 23:28:08 +01001471 /* Fall through. */
Steven J. Hill113c62d2012-07-06 23:56:00 +02001472 case CPU_M14KC:
Steven J. Hillf8fa4812012-12-07 03:51:35 +00001473 case CPU_M14KEC:
Ralf Baechled1e344e2005-02-04 15:51:26 +00001474 case CPU_24K:
Nigel Stephens98a41de2006-04-27 15:50:32 +01001475 case CPU_34K:
Ralf Baechle39b8d522008-04-28 17:14:26 +01001476 case CPU_1004K:
Leonid Yegoshin26ab96d2013-11-27 10:07:53 +00001477 case CPU_INTERAPTIV:
James Hoganaced4cb2014-01-22 16:19:38 +00001478 case CPU_P5600:
Leonid Yegoshin708ac4b2013-11-14 16:12:27 +00001479 case CPU_PROAPTIV:
Leonid Yegoshinf36c4722014-03-04 13:34:43 +00001480 case CPU_M5150:
Leonid Yegoshin46950892014-11-24 12:59:01 +00001481 case CPU_QEMU_GENERIC:
Paul Burton1091bfa2016-02-03 03:26:38 +00001482 case CPU_P6600:
Paul Burton1dbf6a82016-02-03 16:17:29 +00001483 case CPU_M6250:
Markos Chandras02dc6bf2014-01-30 17:21:29 +00001484 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
1485 (c->icache.waysize > PAGE_SIZE))
1486 c->icache.flags |= MIPS_CACHE_ALIASES;
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001487 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) {
Markos Chandras02dc6bf2014-01-30 17:21:29 +00001488 /*
1489 * Effectively physically indexed dcache,
1490 * thus no virtual aliases.
1491 */
Ralf Baechlebeab3752006-06-19 21:56:25 +01001492 c->dcache.flags |= MIPS_CACHE_PINDEX;
1493 break;
1494 }
Ralf Baechled1e344e2005-02-04 15:51:26 +00001495 default:
Maciej W. Rozyckie2e7f292014-11-16 01:02:29 +00001496 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
Ralf Baechlebeab3752006-06-19 21:56:25 +01001497 c->dcache.flags |= MIPS_CACHE_ALIASES;
Ralf Baechled1e344e2005-02-04 15:51:26 +00001498 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001499
Paul Burtond66f99b2016-08-19 18:13:35 +01001500 /* Physically indexed caches don't suffer from virtual aliasing */
1501 if (c->dcache.flags & MIPS_CACHE_PINDEX)
1502 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1503
Ralf Baechle69f24d12013-09-17 10:25:47 +02001504 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001505 case CPU_20KC:
1506 /*
1507 * Some older 20Kc chips doesn't have the 'VI' bit in
1508 * the config register.
1509 */
1510 c->icache.flags |= MIPS_CACHE_VTAG;
1511 break;
1512
Manuel Lauss270717a2009-03-25 17:49:28 +01001513 case CPU_ALCHEMY:
James Hogan47f2ac52016-01-22 10:58:26 +00001514 case CPU_I6400:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001515 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1516 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001517
Florian Fainellic130d2f2016-04-04 10:55:34 -07001518 case CPU_BMIPS5000:
1519 c->icache.flags |= MIPS_CACHE_IC_F_DC;
Florian Fainelli73c4ca0472016-04-04 10:55:35 -07001520 /* Cache aliases are handled in hardware; allow HIGHMEM */
1521 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
Florian Fainellic130d2f2016-04-04 10:55:34 -07001522 break;
1523
Ralf Baechle14bd8c02013-09-25 18:21:26 +02001524 case CPU_LOONGSON2:
1525 /*
1526 * LOONGSON2 has 4 way icache, but when using indexed cache op,
1527 * one op will act on all 4 ways
1528 */
1529 c->icache.ways = 1;
1530 }
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001531
Linus Torvalds1da177e2005-04-16 15:20:36 -07001532 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1533 icache_size >> 10,
Ralf Baechle7fc73162009-04-01 16:11:53 +02001534 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001535 way_string[c->icache.ways], c->icache.linesz);
1536
Ralf Baechle64bfca52007-10-15 16:35:45 +01001537 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1538 dcache_size >> 10, way_string[c->dcache.ways],
1539 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1540 (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1541 "cache aliases" : "no aliases",
1542 c->dcache.linesz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001543}
1544
Huacai Chenb2edcfc2016-03-03 09:45:09 +08001545static void probe_vcache(void)
1546{
1547 struct cpuinfo_mips *c = &current_cpu_data;
1548 unsigned int config2, lsize;
1549
1550 if (current_cpu_type() != CPU_LOONGSON3)
1551 return;
1552
1553 config2 = read_c0_config2();
1554 if ((lsize = ((config2 >> 20) & 15)))
1555 c->vcache.linesz = 2 << lsize;
1556 else
1557 c->vcache.linesz = lsize;
1558
1559 c->vcache.sets = 64 << ((config2 >> 24) & 15);
1560 c->vcache.ways = 1 + ((config2 >> 16) & 15);
1561
1562 vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz;
1563
1564 c->vcache.waybit = 0;
Huacai Chen0be032c2017-03-16 21:00:29 +08001565 c->vcache.waysize = vcache_size / c->vcache.ways;
Huacai Chenb2edcfc2016-03-03 09:45:09 +08001566
1567 pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n",
1568 vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz);
1569}
1570
Linus Torvalds1da177e2005-04-16 15:20:36 -07001571/*
1572 * If you even _breathe_ on this function, look at the gcc output and make sure
1573 * it does not pop things on and off the stack for the cache sizing loop that
1574 * executes in KSEG1 space or else you will crash and burn badly. You have
1575 * been warned.
1576 */
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001577static int probe_scache(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001578{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001579 unsigned long flags, addr, begin, end, pow2;
1580 unsigned int config = read_c0_config();
1581 struct cpuinfo_mips *c = &current_cpu_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001582
1583 if (config & CONF_SC)
1584 return 0;
1585
Ralf Baechlee001e522007-07-28 12:45:47 +01001586 begin = (unsigned long) &_stext;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001587 begin &= ~((4 * 1024 * 1024) - 1);
1588 end = begin + (4 * 1024 * 1024);
1589
1590 /*
1591 * This is such a bitch, you'd think they would make it easy to do
1592 * this. Away you daemons of stupidity!
1593 */
1594 local_irq_save(flags);
1595
1596 /* Fill each size-multiple cache line with a valid tag. */
1597 pow2 = (64 * 1024);
1598 for (addr = begin; addr < end; addr = (begin + pow2)) {
1599 unsigned long *p = (unsigned long *) addr;
1600 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1601 pow2 <<= 1;
1602 }
1603
1604 /* Load first line with zero (therefore invalid) tag. */
1605 write_c0_taglo(0);
1606 write_c0_taghi(0);
1607 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1608 cache_op(Index_Store_Tag_I, begin);
1609 cache_op(Index_Store_Tag_D, begin);
1610 cache_op(Index_Store_Tag_SD, begin);
1611
1612 /* Now search for the wrap around point. */
1613 pow2 = (128 * 1024);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001614 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1615 cache_op(Index_Load_Tag_SD, addr);
1616 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1617 if (!read_c0_taglo())
1618 break;
1619 pow2 <<= 1;
1620 }
1621 local_irq_restore(flags);
1622 addr -= begin;
1623
1624 scache_size = addr;
1625 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1626 c->scache.ways = 1;
Joshua Kinard755af332015-06-02 16:55:22 -04001627 c->scache.waybit = 0; /* does not matter */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001628
1629 return 1;
1630}
1631
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001632static void __init loongson2_sc_init(void)
1633{
1634 struct cpuinfo_mips *c = &current_cpu_data;
1635
1636 scache_size = 512*1024;
1637 c->scache.linesz = 32;
1638 c->scache.ways = 4;
1639 c->scache.waybit = 0;
1640 c->scache.waysize = scache_size / (c->scache.ways);
1641 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1642 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1643 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1644
1645 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1646}
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001647
Huacai Chenc579d312014-03-21 18:44:00 +08001648static void __init loongson3_sc_init(void)
1649{
1650 struct cpuinfo_mips *c = &current_cpu_data;
1651 unsigned int config2, lsize;
1652
1653 config2 = read_c0_config2();
1654 lsize = (config2 >> 4) & 15;
1655 if (lsize)
1656 c->scache.linesz = 2 << lsize;
1657 else
1658 c->scache.linesz = 0;
1659 c->scache.sets = 64 << ((config2 >> 8) & 15);
1660 c->scache.ways = 1 + (config2 & 15);
1661
1662 scache_size = c->scache.sets *
1663 c->scache.ways *
1664 c->scache.linesz;
1665 /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */
1666 scache_size *= 4;
1667 c->scache.waybit = 0;
Huacai Chen0be032c2017-03-16 21:00:29 +08001668 c->scache.waysize = scache_size / c->scache.ways;
Huacai Chenc579d312014-03-21 18:44:00 +08001669 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1670 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1671 if (scache_size)
1672 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1673 return;
1674}
1675
Linus Torvalds1da177e2005-04-16 15:20:36 -07001676extern int r5k_sc_init(void);
1677extern int rm7k_sc_init(void);
Chris Dearman9318c512006-06-20 17:15:20 +01001678extern int mips_sc_init(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001679
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001680static void setup_scache(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001681{
1682 struct cpuinfo_mips *c = &current_cpu_data;
1683 unsigned int config = read_c0_config();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001684 int sc_present = 0;
1685
1686 /*
1687 * Do the probing thing on R4000SC and R4400SC processors. Other
1688 * processors don't have a S-cache that would be relevant to the
Joe Perches603e82e2008-02-03 16:54:53 +02001689 * Linux memory management.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001690 */
Ralf Baechle69f24d12013-09-17 10:25:47 +02001691 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001692 case CPU_R4000SC:
1693 case CPU_R4000MC:
1694 case CPU_R4400SC:
1695 case CPU_R4400MC:
Thiemo Seuferba5187d2005-04-25 16:36:23 +00001696 sc_present = run_uncached(probe_scache);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001697 if (sc_present)
1698 c->options |= MIPS_CPU_CACHE_CDEX_S;
1699 break;
1700
1701 case CPU_R10000:
1702 case CPU_R12000:
Kumba44d921b2006-05-16 22:23:59 -04001703 case CPU_R14000:
Joshua Kinard30577392015-01-21 07:59:45 -05001704 case CPU_R16000:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001705 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1706 c->scache.linesz = 64 << ((config >> 13) & 1);
1707 c->scache.ways = 2;
1708 c->scache.waybit= 0;
1709 sc_present = 1;
1710 break;
1711
1712 case CPU_R5000:
1713 case CPU_NEVADA:
1714#ifdef CONFIG_R5000_CPU_SCACHE
1715 r5k_sc_init();
1716#endif
Ralf Baechle70342282013-01-22 12:59:30 +01001717 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001718
1719 case CPU_RM7000:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001720#ifdef CONFIG_RM7000_CPU_SCACHE
1721 rm7k_sc_init();
1722#endif
1723 return;
1724
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001725 case CPU_LOONGSON2:
1726 loongson2_sc_init();
1727 return;
Ralf Baechle14bd8c02013-09-25 18:21:26 +02001728
Huacai Chenc579d312014-03-21 18:44:00 +08001729 case CPU_LOONGSON3:
1730 loongson3_sc_init();
1731 return;
1732
David Daney18a8cd62014-05-28 23:52:09 +02001733 case CPU_CAVIUM_OCTEON3:
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001734 case CPU_XLP:
1735 /* don't need to worry about L2, fully coherent */
1736 return;
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001737
Linus Torvalds1da177e2005-04-16 15:20:36 -07001738 default:
Deng-Cheng Zhuadb37892013-04-01 18:14:28 +00001739 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
Markos Chandrasb5ad2c22015-01-15 10:28:29 +00001740 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
1741 MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) {
Chris Dearman9318c512006-06-20 17:15:20 +01001742#ifdef CONFIG_MIPS_CPU_SCACHE
1743 if (mips_sc_init ()) {
1744 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1745 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1746 scache_size >> 10,
1747 way_string[c->scache.ways], c->scache.linesz);
1748 }
1749#else
1750 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1751 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1752#endif
1753 return;
1754 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001755 sc_present = 0;
1756 }
1757
1758 if (!sc_present)
1759 return;
1760
Linus Torvalds1da177e2005-04-16 15:20:36 -07001761 /* compute a couple of other cache variables */
1762 c->scache.waysize = scache_size / c->scache.ways;
1763
1764 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1765
1766 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1767 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1768
Ralf Baechlefc5d2d22006-07-06 13:04:01 +01001769 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001770}
1771
Sergei Shtylyov9370b352006-05-26 19:44:54 +04001772void au1x00_fixup_config_od(void)
1773{
1774 /*
1775 * c0_config.od (bit 19) was write only (and read as 0)
1776 * on the early revisions of Alchemy SOCs. It disables the bus
1777 * transaction overlapping and needs to be set to fix various errata.
1778 */
1779 switch (read_c0_prid()) {
1780 case 0x00030100: /* Au1000 DA */
1781 case 0x00030201: /* Au1000 HA */
1782 case 0x00030202: /* Au1000 HB */
1783 case 0x01030200: /* Au1500 AB */
1784 /*
1785 * Au1100 errata actually keeps silence about this bit, so we set it
1786 * just in case for those revisions that require it to be set according
Manuel Lauss270717a2009-03-25 17:49:28 +01001787 * to the (now gone) cpu table.
Sergei Shtylyov9370b352006-05-26 19:44:54 +04001788 */
1789 case 0x02030200: /* Au1100 AB */
1790 case 0x02030201: /* Au1100 BA */
1791 case 0x02030202: /* Au1100 BC */
1792 set_c0_config(1 << 19);
1793 break;
1794 }
1795}
1796
Ralf Baechle89052bd2008-06-12 17:26:02 +01001797/* CP0 hazard avoidance. */
1798#define NXP_BARRIER() \
1799 __asm__ __volatile__( \
1800 ".set noreorder\n\t" \
1801 "nop; nop; nop; nop; nop; nop;\n\t" \
1802 ".set reorder\n\t")
1803
1804static void nxp_pr4450_fixup_config(void)
1805{
1806 unsigned long config0;
1807
1808 config0 = read_c0_config();
1809
1810 /* clear all three cache coherency fields */
1811 config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1812 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) |
1813 ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1814 ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1815 write_c0_config(config0);
1816 NXP_BARRIER();
1817}
1818
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001819static int cca = -1;
Chris Dearman35133692007-09-19 00:58:24 +01001820
1821static int __init cca_setup(char *str)
1822{
1823 get_option(&str, &cca);
1824
Shane McDonaldb5b64f22012-06-14 02:26:40 +00001825 return 0;
Chris Dearman35133692007-09-19 00:58:24 +01001826}
1827
Shane McDonaldb5b64f22012-06-14 02:26:40 +00001828early_param("cca", cca_setup);
Chris Dearman35133692007-09-19 00:58:24 +01001829
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001830static void coherency_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001831{
Chris Dearman35133692007-09-19 00:58:24 +01001832 if (cca < 0 || cca > 7)
1833 cca = read_c0_config() & CONF_CM_CMASK;
1834 _page_cachable_default = cca << _CACHE_SHIFT;
1835
1836 pr_debug("Using cache attribute %d\n", cca);
1837 change_c0_config(CONF_CM_CMASK, cca);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001838
1839 /*
1840 * c0_status.cu=0 specifies that updates by the sc instruction use
1841 * the coherency mode specified by the TLB; 1 means cachable
1842 * coherent update on write will be used. Not all processors have
1843 * this bit and; some wire it to zero, others like Toshiba had the
1844 * silly idea of putting something else there ...
1845 */
Ralf Baechle10cc3522007-10-11 23:46:15 +01001846 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001847 case CPU_R4000PC:
1848 case CPU_R4000SC:
1849 case CPU_R4000MC:
1850 case CPU_R4400PC:
1851 case CPU_R4400SC:
1852 case CPU_R4400MC:
1853 clear_c0_config(CONF_CU);
1854 break;
Sergei Shtylyov9370b352006-05-26 19:44:54 +04001855 /*
Ralf Baechledf586d52006-08-01 23:42:30 +01001856 * We need to catch the early Alchemy SOCs with
Manuel Lauss270717a2009-03-25 17:49:28 +01001857 * the write-only co_config.od bit and set it back to one on:
1858 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
Sergei Shtylyov9370b352006-05-26 19:44:54 +04001859 */
Manuel Lauss270717a2009-03-25 17:49:28 +01001860 case CPU_ALCHEMY:
Sergei Shtylyov9370b352006-05-26 19:44:54 +04001861 au1x00_fixup_config_od();
1862 break;
Ralf Baechle89052bd2008-06-12 17:26:02 +01001863
1864 case PRID_IMP_PR4450:
1865 nxp_pr4450_fixup_config();
1866 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001867 }
1868}
1869
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001870static void r4k_cache_error_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001871{
Ralf Baechle641e97f2007-10-11 23:46:05 +01001872 extern char __weak except_vec2_generic;
1873 extern char __weak except_vec2_sb1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001874
Ralf Baechle69f24d12013-09-17 10:25:47 +02001875 switch (current_cpu_type()) {
Ralf Baechle641e97f2007-10-11 23:46:05 +01001876 case CPU_SB1:
1877 case CPU_SB1A:
1878 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1879 break;
1880
1881 default:
1882 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1883 break;
1884 }
David Daney9cd9669b2012-05-15 00:04:49 -07001885}
1886
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001887void r4k_cache_init(void)
David Daney9cd9669b2012-05-15 00:04:49 -07001888{
1889 extern void build_clear_page(void);
1890 extern void build_copy_page(void);
1891 struct cpuinfo_mips *c = &current_cpu_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001892
1893 probe_pcache();
Huacai Chenb2edcfc2016-03-03 09:45:09 +08001894 probe_vcache();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001895 setup_scache();
1896
Linus Torvalds1da177e2005-04-16 15:20:36 -07001897 r4k_blast_dcache_page_setup();
1898 r4k_blast_dcache_page_indexed_setup();
1899 r4k_blast_dcache_setup();
1900 r4k_blast_icache_page_setup();
1901 r4k_blast_icache_page_indexed_setup();
1902 r4k_blast_icache_setup();
1903 r4k_blast_scache_page_setup();
1904 r4k_blast_scache_page_indexed_setup();
1905 r4k_blast_scache_setup();
Leonid Yegoshin4caa9062014-01-15 14:47:28 +00001906#ifdef CONFIG_EVA
1907 r4k_blast_dcache_user_page_setup();
1908 r4k_blast_icache_user_page_setup();
1909#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001910
1911 /*
1912 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1913 * This code supports virtually indexed processors and will be
1914 * unnecessarily inefficient on physically indexed processors.
1915 */
Leonid Yegoshincb80b2a2015-11-19 17:38:21 -08001916 if (c->dcache.linesz && cpu_has_dc_aliases)
Chris Dearman73f40352006-06-20 18:06:52 +01001917 shm_align_mask = max_t( unsigned long,
1918 c->dcache.sets * c->dcache.linesz - 1,
1919 PAGE_SIZE - 1);
1920 else
1921 shm_align_mask = PAGE_SIZE-1;
Ralf Baechle9c5a3d72008-04-05 15:13:23 +01001922
1923 __flush_cache_vmap = r4k__flush_cache_vmap;
1924 __flush_cache_vunmap = r4k__flush_cache_vunmap;
1925
Ralf Baechledb813fe2007-09-27 18:26:43 +01001926 flush_cache_all = cache_noop;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001927 __flush_cache_all = r4k___flush_cache_all;
1928 flush_cache_mm = r4k_flush_cache_mm;
1929 flush_cache_page = r4k_flush_cache_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001930 flush_cache_range = r4k_flush_cache_range;
1931
Ralf Baechled9cdc9012011-06-17 16:20:28 +01001932 __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1933
Linus Torvalds1da177e2005-04-16 15:20:36 -07001934 flush_cache_sigtramp = r4k_flush_cache_sigtramp;
1935 flush_icache_all = r4k_flush_icache_all;
Ralf Baechle7e3bfc72006-04-05 20:42:04 +01001936 local_flush_data_cache_page = local_r4k_flush_data_cache_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001937 flush_data_cache_page = r4k_flush_data_cache_page;
1938 flush_icache_range = r4k_flush_icache_range;
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02001939 local_flush_icache_range = local_r4k_flush_icache_range;
James Hoganb2ff7172016-09-01 17:30:15 +01001940 __flush_icache_user_range = r4k_flush_icache_user_range;
1941 __local_flush_icache_user_range = local_r4k_flush_icache_user_range;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001942
Manuel Lauss80057112014-02-20 14:59:22 +01001943#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
Paul Burton20d33062016-10-05 18:18:16 +01001944# if defined(CONFIG_DMA_PERDEV_COHERENT)
1945 if (0) {
1946# else
Paul Burtonf2302022016-10-05 18:18:14 +01001947 if ((coherentio == IO_COHERENCE_ENABLED) ||
1948 ((coherentio == IO_COHERENCE_DEFAULT) && hw_coherentio)) {
Paul Burton20d33062016-10-05 18:18:16 +01001949# endif
Ralf Baechle39b8d522008-04-28 17:14:26 +01001950 _dma_cache_wback_inv = (void *)cache_noop;
1951 _dma_cache_wback = (void *)cache_noop;
1952 _dma_cache_inv = (void *)cache_noop;
1953 } else {
1954 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1955 _dma_cache_wback = r4k_dma_cache_wback_inv;
1956 _dma_cache_inv = r4k_dma_cache_inv;
1957 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001958#endif
1959
Linus Torvalds1da177e2005-04-16 15:20:36 -07001960 build_clear_page();
1961 build_copy_page();
Steven J. Hillb6d92b42013-03-25 13:47:29 -05001962
1963 /*
1964 * We want to run CMP kernels on core with and without coherent
1965 * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1966 * or not to flush caches.
1967 */
Ralf Baechle1d40cfc2005-07-15 15:23:23 +00001968 local_r4k___flush_cache_all(NULL);
Steven J. Hillb6d92b42013-03-25 13:47:29 -05001969
Ralf Baechle1d40cfc2005-07-15 15:23:23 +00001970 coherency_setup();
David Daney9cd9669b2012-05-15 00:04:49 -07001971 board_cache_error_setup = r4k_cache_error_setup;
Kevin Cernekeed74b0172014-10-20 21:28:00 -07001972
1973 /*
1974 * Per-CPU overrides
1975 */
1976 switch (current_cpu_type()) {
1977 case CPU_BMIPS4350:
1978 case CPU_BMIPS4380:
1979 /* No IPI is needed because all CPUs share the same D$ */
1980 flush_data_cache_page = r4k_blast_dcache_page;
1981 break;
1982 case CPU_BMIPS5000:
1983 /* We lose our superpowers if L2 is disabled */
1984 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
1985 break;
1986
1987 /* I$ fills from D$ just by emptying the write buffers */
1988 flush_cache_page = (void *)b5k_instruction_hazard;
1989 flush_cache_range = (void *)b5k_instruction_hazard;
1990 flush_cache_sigtramp = (void *)b5k_instruction_hazard;
1991 local_flush_data_cache_page = (void *)b5k_instruction_hazard;
1992 flush_data_cache_page = (void *)b5k_instruction_hazard;
1993 flush_icache_range = (void *)b5k_instruction_hazard;
1994 local_flush_icache_range = (void *)b5k_instruction_hazard;
1995
Kevin Cernekeed74b0172014-10-20 21:28:00 -07001996
1997 /* Optimization: an L2 flush implicitly flushes the L1 */
1998 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
1999 break;
Huacai Chen37fbe8f2016-03-03 09:45:10 +08002000 case CPU_LOONGSON3:
2001 /* Loongson-3 maintains cache coherency by hardware */
2002 __flush_cache_all = cache_noop;
2003 __flush_cache_vmap = cache_noop;
2004 __flush_cache_vunmap = cache_noop;
2005 __flush_kernel_vmap_range = (void *)cache_noop;
2006 flush_cache_mm = (void *)cache_noop;
2007 flush_cache_page = (void *)cache_noop;
2008 flush_cache_range = (void *)cache_noop;
2009 flush_cache_sigtramp = (void *)cache_noop;
2010 flush_icache_all = (void *)cache_noop;
2011 flush_data_cache_page = (void *)cache_noop;
2012 local_flush_data_cache_page = (void *)cache_noop;
2013 break;
Kevin Cernekeed74b0172014-10-20 21:28:00 -07002014 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002015}
James Hogan61d73042014-03-04 10:23:57 +00002016
2017static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
2018 void *v)
2019{
2020 switch (cmd) {
2021 case CPU_PM_ENTER_FAILED:
2022 case CPU_PM_EXIT:
2023 coherency_setup();
2024 break;
2025 }
2026
2027 return NOTIFY_OK;
2028}
2029
2030static struct notifier_block r4k_cache_pm_notifier_block = {
2031 .notifier_call = r4k_cache_pm_notifier,
2032};
2033
2034int __init r4k_cache_init_pm(void)
2035{
2036 return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block);
2037}
2038arch_initcall(r4k_cache_init_pm);