Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1 | /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 2 | * All Rights Reserved. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the |
| 6 | * "Software"), to deal in the Software without restriction, including |
| 7 | * without limitation the rights to use, copy, modify, merge, publish, |
| 8 | * distribute, sub license, and/or sell copies of the Software, and to |
| 9 | * permit persons to whom the Software is furnished to do so, subject to |
| 10 | * the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice (including the |
| 13 | * next paragraph) shall be included in all copies or substantial portions |
| 14 | * of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 19 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 20 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 21 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 22 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #ifndef _I915_REG_H_ |
| 26 | #define _I915_REG_H_ |
| 27 | |
Matt Roper | 2b25a93 | 2022-01-10 21:15:55 -0800 | [diff] [blame] | 28 | #include "i915_reg_defs.h" |
Jani Nikula | e563531 | 2022-11-09 17:35:21 +0200 | [diff] [blame] | 29 | #include "display/intel_display_reg_defs.h" |
Jani Nikula | 09b434d | 2019-03-15 15:56:18 +0200 | [diff] [blame] | 30 | |
Jani Nikula | 1aa920e | 2017-08-10 15:29:44 +0300 | [diff] [blame] | 31 | /** |
| 32 | * DOC: The i915 register macro definition style guide |
| 33 | * |
| 34 | * Follow the style described here for new macros, and while changing existing |
| 35 | * macros. Do **not** mass change existing definitions just to update the style. |
| 36 | * |
Jani Nikula | 27be41d | 2020-04-17 16:01:09 +0300 | [diff] [blame] | 37 | * File Layout |
| 38 | * ~~~~~~~~~~~ |
Jani Nikula | 1aa920e | 2017-08-10 15:29:44 +0300 | [diff] [blame] | 39 | * |
| 40 | * Keep helper macros near the top. For example, _PIPE() and friends. |
| 41 | * |
| 42 | * Prefix macros that generally should not be used outside of this file with |
| 43 | * underscore '_'. For example, _PIPE() and friends, single instances of |
| 44 | * registers that are defined solely for the use by function-like macros. |
| 45 | * |
| 46 | * Avoid using the underscore prefixed macros outside of this file. There are |
| 47 | * exceptions, but keep them to a minimum. |
| 48 | * |
| 49 | * There are two basic types of register definitions: Single registers and |
| 50 | * register groups. Register groups are registers which have two or more |
| 51 | * instances, for example one per pipe, port, transcoder, etc. Register groups |
| 52 | * should be defined using function-like macros. |
| 53 | * |
| 54 | * For single registers, define the register offset first, followed by register |
| 55 | * contents. |
| 56 | * |
| 57 | * For register groups, define the register instance offsets first, prefixed |
| 58 | * with underscore, followed by a function-like macro choosing the right |
| 59 | * instance based on the parameter, followed by register contents. |
| 60 | * |
| 61 | * Define the register contents (i.e. bit and bit field macros) from most |
| 62 | * significant to least significant bit. Indent the register content macros |
| 63 | * using two extra spaces between ``#define`` and the macro name. |
| 64 | * |
Jani Nikula | baa09e7 | 2019-03-15 15:56:20 +0200 | [diff] [blame] | 65 | * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents |
| 66 | * using ``REG_FIELD_PREP(mask, value)``. This will define the values already |
| 67 | * shifted in place, so they can be directly OR'd together. For convenience, |
| 68 | * function-like macros may be used to define bit fields, but do note that the |
| 69 | * macros may be needed to read as well as write the register contents. |
Jani Nikula | 1aa920e | 2017-08-10 15:29:44 +0300 | [diff] [blame] | 70 | * |
Jani Nikula | 09b434d | 2019-03-15 15:56:18 +0200 | [diff] [blame] | 71 | * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. |
Jani Nikula | 1aa920e | 2017-08-10 15:29:44 +0300 | [diff] [blame] | 72 | * |
| 73 | * Group the register and its contents together without blank lines, separate |
| 74 | * from other registers and their contents with one blank line. |
| 75 | * |
| 76 | * Indent macro values from macro names using TABs. Align values vertically. Use |
| 77 | * braces in macro values as needed to avoid unintended precedence after macro |
| 78 | * substitution. Use spaces in macro values according to kernel coding |
| 79 | * style. Use lower case in hexadecimal values. |
| 80 | * |
| 81 | * Naming |
Jonathan Corbet | 551bd33 | 2019-05-23 10:06:46 -0600 | [diff] [blame] | 82 | * ~~~~~~ |
Jani Nikula | 1aa920e | 2017-08-10 15:29:44 +0300 | [diff] [blame] | 83 | * |
| 84 | * Try to name registers according to the specs. If the register name changes in |
| 85 | * the specs from platform to another, stick to the original name. |
| 86 | * |
| 87 | * Try to re-use existing register macro definitions. Only add new macros for |
| 88 | * new register offsets, or when the register contents have changed enough to |
| 89 | * warrant a full redefinition. |
| 90 | * |
| 91 | * When a register macro changes for a new platform, prefix the new macro using |
| 92 | * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The |
| 93 | * prefix signifies the start platform/generation using the register. |
| 94 | * |
| 95 | * When a bit (field) macro changes or gets added for a new platform, while |
| 96 | * retaining the existing register macro, add a platform acronym or generation |
| 97 | * suffix to the name. For example, ``_SKL`` or ``_GEN8``. |
| 98 | * |
| 99 | * Examples |
Jonathan Corbet | 551bd33 | 2019-05-23 10:06:46 -0600 | [diff] [blame] | 100 | * ~~~~~~~~ |
Jani Nikula | 1aa920e | 2017-08-10 15:29:44 +0300 | [diff] [blame] | 101 | * |
| 102 | * (Note that the values in the example are indented using spaces instead of |
| 103 | * TABs to avoid misalignment in generated documentation. Use TABs in the |
| 104 | * definitions.):: |
| 105 | * |
| 106 | * #define _FOO_A 0xf000 |
| 107 | * #define _FOO_B 0xf001 |
| 108 | * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) |
Jani Nikula | 09b434d | 2019-03-15 15:56:18 +0200 | [diff] [blame] | 109 | * #define FOO_ENABLE REG_BIT(31) |
| 110 | * #define FOO_MODE_MASK REG_GENMASK(19, 16) |
Jani Nikula | baa09e7 | 2019-03-15 15:56:20 +0200 | [diff] [blame] | 111 | * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) |
| 112 | * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) |
| 113 | * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) |
Jani Nikula | 1aa920e | 2017-08-10 15:29:44 +0300 | [diff] [blame] | 114 | * |
| 115 | * #define BAR _MMIO(0xb000) |
| 116 | * #define GEN8_BAR _MMIO(0xb888) |
| 117 | */ |
| 118 | |
Imre Deak | 273e1da | 2023-02-08 13:42:59 +0200 | [diff] [blame] | 119 | #define GU_CNTL_PROTECTED _MMIO(0x10100C) |
| 120 | #define DEPRESENT REG_BIT(9) |
| 121 | |
Matt Roper | c256af0 | 2021-04-20 14:18:42 +0100 | [diff] [blame] | 122 | #define GU_CNTL _MMIO(0x101010) |
| 123 | #define LMEM_INIT REG_BIT(7) |
Daniele Ceraolo Spurio | 5a44fcd | 2022-12-08 12:05:19 -0800 | [diff] [blame] | 124 | #define DRIVERFLR REG_BIT(31) |
| 125 | #define GU_DEBUG _MMIO(0x101018) |
| 126 | #define DRIVERFLR_STATUS REG_BIT(31) |
Matt Roper | c256af0 | 2021-04-20 14:18:42 +0100 | [diff] [blame] | 127 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 128 | #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) |
Paulo Zanoni | 3774eb5 | 2015-08-10 14:57:32 -0300 | [diff] [blame] | 129 | #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) |
| 130 | #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) |
| 131 | #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) |
| 132 | #define GEN6_STOLEN_RESERVED_1M (0 << 4) |
| 133 | #define GEN6_STOLEN_RESERVED_512K (1 << 4) |
| 134 | #define GEN6_STOLEN_RESERVED_256K (2 << 4) |
| 135 | #define GEN6_STOLEN_RESERVED_128K (3 << 4) |
| 136 | #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) |
| 137 | #define GEN7_STOLEN_RESERVED_1M (0 << 5) |
| 138 | #define GEN7_STOLEN_RESERVED_256K (1 << 5) |
| 139 | #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) |
| 140 | #define GEN8_STOLEN_RESERVED_1M (0 << 7) |
| 141 | #define GEN8_STOLEN_RESERVED_2M (1 << 7) |
| 142 | #define GEN8_STOLEN_RESERVED_4M (2 << 7) |
| 143 | #define GEN8_STOLEN_RESERVED_8M (3 << 7) |
Ville Syrjälä | db7fb60 | 2017-11-02 17:17:35 +0200 | [diff] [blame] | 144 | #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) |
Paulo Zanoni | 185441e | 2018-05-04 13:32:52 -0700 | [diff] [blame] | 145 | #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) |
Daniel Vetter | 40bae73 | 2014-09-11 13:28:08 +0200 | [diff] [blame] | 146 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 147 | #define _VGA_MSR_WRITE _MMIO(0x3c2) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 148 | |
Brad Volkin | 220375a | 2014-02-18 10:15:51 -0800 | [diff] [blame] | 149 | #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 |
| 150 | #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 151 | #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) |
Brad Volkin | 220375a | 2014-02-18 10:15:51 -0800 | [diff] [blame] | 152 | |
Brad Volkin | 5947de9 | 2014-02-18 10:15:50 -0800 | [diff] [blame] | 153 | /* |
Chris Wilson | dc96e9b | 2010-10-01 12:05:06 +0100 | [diff] [blame] | 154 | * Reset registers |
| 155 | */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 156 | #define DEBUG_RESET_I830 _MMIO(0x6070) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 157 | #define DEBUG_RESET_FULL (1 << 7) |
| 158 | #define DEBUG_RESET_RENDER (1 << 8) |
| 159 | #define DEBUG_RESET_DISPLAY (1 << 9) |
Chris Wilson | dc96e9b | 2010-10-01 12:05:06 +0100 | [diff] [blame] | 160 | |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 161 | /* |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame] | 162 | * IOSF sideband |
| 163 | */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 164 | #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame] | 165 | #define IOSF_DEVFN_SHIFT 24 |
| 166 | #define IOSF_OPCODE_SHIFT 16 |
| 167 | #define IOSF_PORT_SHIFT 8 |
| 168 | #define IOSF_BYTE_ENABLES_SHIFT 4 |
| 169 | #define IOSF_BAR_SHIFT 1 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 170 | #define IOSF_SB_BUSY (1 << 0) |
Jani Nikula | 4688d45f | 2016-02-04 12:50:53 +0200 | [diff] [blame] | 171 | #define IOSF_PORT_BUNIT 0x03 |
| 172 | #define IOSF_PORT_PUNIT 0x04 |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame] | 173 | #define IOSF_PORT_NC 0x11 |
| 174 | #define IOSF_PORT_DPIO 0x12 |
Jani Nikula | e9f882a | 2013-08-27 15:12:14 +0300 | [diff] [blame] | 175 | #define IOSF_PORT_GPIO_NC 0x13 |
| 176 | #define IOSF_PORT_CCK 0x14 |
Jani Nikula | 4688d45f | 2016-02-04 12:50:53 +0200 | [diff] [blame] | 177 | #define IOSF_PORT_DPIO_2 0x1a |
| 178 | #define IOSF_PORT_FLISDSI 0x1b |
Deepak M | dfb19ed | 2016-02-04 18:55:15 +0200 | [diff] [blame] | 179 | #define IOSF_PORT_GPIO_SC 0x48 |
| 180 | #define IOSF_PORT_GPIO_SUS 0xa8 |
Jani Nikula | 4688d45f | 2016-02-04 12:50:53 +0200 | [diff] [blame] | 181 | #define IOSF_PORT_CCU 0xa9 |
Jani Nikula | 7071af9 | 2016-03-18 13:11:15 +0200 | [diff] [blame] | 182 | #define CHV_IOSF_PORT_GPIO_N 0x13 |
| 183 | #define CHV_IOSF_PORT_GPIO_SE 0x48 |
| 184 | #define CHV_IOSF_PORT_GPIO_E 0xa8 |
| 185 | #define CHV_IOSF_PORT_GPIO_SW 0xb2 |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 186 | #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) |
| 187 | #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame] | 188 | |
Ander Conselvan de Oliveira | f38861b | 2016-10-06 19:22:18 +0300 | [diff] [blame] | 189 | /* DPIO registers */ |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame] | 190 | #define DPIO_DEVFN 0 |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame] | 191 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 192 | #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 193 | #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ |
| 194 | #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ |
| 195 | #define DPIO_SFR_BYPASS (1 << 1) |
| 196 | #define DPIO_CMNRST (1 << 0) |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 197 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 198 | #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) |
Uma Shankar | 1881a42 | 2017-01-25 19:43:23 +0530 | [diff] [blame] | 199 | #define MIPIO_RST_CTRL (1 << 2) |
Vandana Kannan | 5c6706e | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 200 | |
Imre Deak | e93da0a | 2016-06-13 16:44:37 +0300 | [diff] [blame] | 201 | #define _BXT_PHY_CTL_DDI_A 0x64C00 |
| 202 | #define _BXT_PHY_CTL_DDI_B 0x64C10 |
| 203 | #define _BXT_PHY_CTL_DDI_C 0x64C20 |
| 204 | #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) |
| 205 | #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) |
| 206 | #define BXT_PHY_LANE_ENABLED (1 << 8) |
| 207 | #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ |
| 208 | _BXT_PHY_CTL_DDI_B) |
| 209 | |
Vandana Kannan | 5c6706e | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 210 | #define _PHY_CTL_FAMILY_DDI 0x64C90 |
Lucas De Marchi | 7b775d3 | 2023-01-20 11:34:53 -0800 | [diff] [blame] | 211 | #define _PHY_CTL_FAMILY_EDP 0x64C80 |
Ander Conselvan de Oliveira | 0a116ce | 2016-12-02 10:23:51 +0200 | [diff] [blame] | 212 | #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 |
Vandana Kannan | 5c6706e | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 213 | #define COMMON_RESET_DIS (1 << 31) |
Lucas De Marchi | 7b775d3 | 2023-01-20 11:34:53 -0800 | [diff] [blame] | 214 | #define BXT_PHY_CTL_FAMILY(phy) \ |
| 215 | _MMIO(_PICK_EVEN_2RANGES(phy, 1, \ |
| 216 | _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \ |
| 217 | _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C)) |
Vandana Kannan | 5c6706e | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 218 | |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 219 | /* UAIMI scratch pad register 1 */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 220 | #define UAIMI_SPR1 _MMIO(0x4F074) |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 221 | /* SKL VccIO mask */ |
| 222 | #define SKL_VCCIO_MASK 0x1 |
| 223 | /* SKL balance leg register */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 224 | #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 225 | /* I_boost values */ |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 226 | #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) |
| 227 | #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 228 | /* Balance leg disable bits */ |
| 229 | #define BALANCE_LEG_DISABLE_SHIFT 23 |
Ville Syrjälä | a7d8dbc | 2016-07-12 15:59:28 +0300 | [diff] [blame] | 230 | #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 231 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 232 | /* |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 233 | * Fence registers |
Ville Syrjälä | eecf613a4 | 2015-09-21 18:05:14 +0300 | [diff] [blame] | 234 | * [0-7] @ 0x2000 gen2,gen3 |
| 235 | * [8-15] @ 0x3000 945,g33,pnv |
| 236 | * |
| 237 | * [0-15] @ 0x3000 gen4,gen5 |
| 238 | * |
| 239 | * [0-15] @ 0x100000 gen6,vlv,chv |
| 240 | * [0-31] @ 0x100000 gen7+ |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 241 | */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 242 | #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 243 | #define I830_FENCE_START_MASK 0x07f80000 |
| 244 | #define I830_FENCE_TILING_Y_SHIFT 12 |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 245 | #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 246 | #define I830_FENCE_PITCH_SHIFT 4 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 247 | #define I830_FENCE_REG_VALID (1 << 0) |
Daniel Vetter | c36a2a6 | 2010-04-17 15:12:03 +0200 | [diff] [blame] | 248 | #define I915_FENCE_MAX_PITCH_VAL 4 |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 249 | #define I830_FENCE_MAX_PITCH_VAL 6 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 250 | #define I830_FENCE_MAX_SIZE_VAL (1 << 8) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 251 | |
| 252 | #define I915_FENCE_START_MASK 0x0ff00000 |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 253 | #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 254 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 255 | #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) |
| 256 | #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 257 | #define I965_FENCE_PITCH_SHIFT 2 |
| 258 | #define I965_FENCE_TILING_Y_SHIFT 1 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 259 | #define I965_FENCE_REG_VALID (1 << 0) |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 260 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 261 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 262 | #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) |
| 263 | #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) |
Ville Syrjälä | eecf613a4 | 2015-09-21 18:05:14 +0300 | [diff] [blame] | 264 | #define GEN6_FENCE_PITCH_SHIFT 32 |
Ville Syrjälä | 3a06247 | 2013-04-09 11:45:05 +0300 | [diff] [blame] | 265 | #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 266 | |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 267 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 268 | /* control register for cpu gtt access */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 269 | #define TILECTL _MMIO(0x101000) |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 270 | #define TILECTL_SWZCTL (1 << 0) |
Robert Beckett | e3a2905 | 2015-03-11 10:28:25 +0200 | [diff] [blame] | 271 | #define TILECTL_TLBPF (1 << 1) |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 272 | #define TILECTL_TLB_PREFETCH_DIS (1 << 2) |
| 273 | #define TILECTL_BACKSNOOP_DIS (1 << 3) |
| 274 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 275 | /* |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 276 | * Instruction and interrupt control regs |
| 277 | */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 278 | #define PGTBL_CTL _MMIO(0x02020) |
Ville Syrjälä | f1e1c21 | 2014-06-05 20:02:59 +0300 | [diff] [blame] | 279 | #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ |
| 280 | #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 281 | #define PGTBL_ER _MMIO(0x02024) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 282 | #define PRB0_BASE (0x2030 - 0x30) |
| 283 | #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ |
| 284 | #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ |
| 285 | #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ |
| 286 | #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ |
| 287 | #define SRB2_BASE (0x2120 - 0x30) /* 830 */ |
| 288 | #define SRB3_BASE (0x2130 - 0x30) /* 830 */ |
Daniel Vetter | 333e9fe | 2010-08-02 16:24:01 +0200 | [diff] [blame] | 289 | #define RENDER_RING_BASE 0x02000 |
| 290 | #define BSD_RING_BASE 0x04000 |
| 291 | #define GEN6_BSD_RING_BASE 0x12000 |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 292 | #define GEN8_BSD2_RING_BASE 0x1c000 |
Oscar Mateo | 5f79e7c | 2018-03-02 18:14:57 +0200 | [diff] [blame] | 293 | #define GEN11_BSD_RING_BASE 0x1c0000 |
| 294 | #define GEN11_BSD2_RING_BASE 0x1c4000 |
| 295 | #define GEN11_BSD3_RING_BASE 0x1d0000 |
| 296 | #define GEN11_BSD4_RING_BASE 0x1d4000 |
John Harrison | 938c778 | 2021-07-23 12:10:24 -0700 | [diff] [blame] | 297 | #define XEHP_BSD5_RING_BASE 0x1e0000 |
| 298 | #define XEHP_BSD6_RING_BASE 0x1e4000 |
| 299 | #define XEHP_BSD7_RING_BASE 0x1f0000 |
| 300 | #define XEHP_BSD8_RING_BASE 0x1f4000 |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 301 | #define VEBOX_RING_BASE 0x1a000 |
Oscar Mateo | 5f79e7c | 2018-03-02 18:14:57 +0200 | [diff] [blame] | 302 | #define GEN11_VEBOX_RING_BASE 0x1c8000 |
| 303 | #define GEN11_VEBOX2_RING_BASE 0x1d8000 |
John Harrison | 938c778 | 2021-07-23 12:10:24 -0700 | [diff] [blame] | 304 | #define XEHP_VEBOX3_RING_BASE 0x1e8000 |
| 305 | #define XEHP_VEBOX4_RING_BASE 0x1f8000 |
Daniele Ceraolo Spurio | 5fd974d | 2022-11-02 10:10:43 -0700 | [diff] [blame] | 306 | #define MTL_GSC_RING_BASE 0x11a000 |
Matt Roper | 944823c | 2022-03-01 15:15:37 -0800 | [diff] [blame] | 307 | #define GEN12_COMPUTE0_RING_BASE 0x1a000 |
| 308 | #define GEN12_COMPUTE1_RING_BASE 0x1c000 |
| 309 | #define GEN12_COMPUTE2_RING_BASE 0x1e000 |
| 310 | #define GEN12_COMPUTE3_RING_BASE 0x26000 |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 311 | #define BLT_RING_BASE 0x22000 |
Matt Roper | 69f8afd | 2022-05-05 14:38:08 -0700 | [diff] [blame] | 312 | #define XEHPC_BCS1_RING_BASE 0x3e0000 |
| 313 | #define XEHPC_BCS2_RING_BASE 0x3e2000 |
| 314 | #define XEHPC_BCS3_RING_BASE 0x3e4000 |
| 315 | #define XEHPC_BCS4_RING_BASE 0x3e6000 |
| 316 | #define XEHPC_BCS5_RING_BASE 0x3e8000 |
| 317 | #define XEHPC_BCS6_RING_BASE 0x3ea000 |
| 318 | #define XEHPC_BCS7_RING_BASE 0x3ec000 |
| 319 | #define XEHPC_BCS8_RING_BASE 0x3ee000 |
Tomas Winkler | 1e3dc1d | 2022-04-19 12:33:08 -0700 | [diff] [blame] | 320 | #define DG1_GSC_HECI1_BASE 0x00258000 |
| 321 | #define DG1_GSC_HECI2_BASE 0x00259000 |
Tomas Winkler | f15856d | 2022-04-19 12:33:13 -0700 | [diff] [blame] | 322 | #define DG2_GSC_HECI1_BASE 0x00373000 |
| 323 | #define DG2_GSC_HECI2_BASE 0x00374000 |
Daniele Ceraolo Spurio | b7d70b8 | 2023-03-23 16:18:57 -0700 | [diff] [blame] | 324 | #define MTL_GSC_HECI1_BASE 0x00116000 |
| 325 | #define MTL_GSC_HECI2_BASE 0x00117000 |
Ayaz A Siddiqui | d79a1d7 | 2021-09-03 14:51:50 +0530 | [diff] [blame] | 326 | |
Daniele Ceraolo Spurio | b7d70b8 | 2023-03-23 16:18:57 -0700 | [diff] [blame] | 327 | #define HECI_H_CSR(base) _MMIO((base) + 0x4) |
| 328 | #define HECI_H_CSR_IE REG_BIT(0) |
| 329 | #define HECI_H_CSR_IS REG_BIT(1) |
| 330 | #define HECI_H_CSR_IG REG_BIT(2) |
| 331 | #define HECI_H_CSR_RDY REG_BIT(3) |
| 332 | #define HECI_H_CSR_RST REG_BIT(4) |
Ayaz A Siddiqui | d79a1d7 | 2021-09-03 14:51:50 +0530 | [diff] [blame] | 333 | |
Daniele Ceraolo Spurio | b7d70b8 | 2023-03-23 16:18:57 -0700 | [diff] [blame] | 334 | #define HECI_H_GS1(base) _MMIO((base) + 0xc4c) |
| 335 | #define HECI_H_GS1_ER_PREP REG_BIT(0) |
Imre Deak | 9e72b46 | 2014-05-05 15:13:55 +0300 | [diff] [blame] | 336 | |
Daniele Ceraolo Spurio | 561055b | 2023-06-12 11:15:29 -0700 | [diff] [blame] | 337 | /* |
| 338 | * The FWSTS register values are FW defined and can be different between |
| 339 | * HECI1 and HECI2 |
| 340 | */ |
| 341 | #define HECI_FWSTS1 0xc40 |
| 342 | #define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0) |
| 343 | #define HECI1_FWSTS1_CURRENT_STATE_RESET 0 |
| 344 | #define HECI1_FWSTS1_PROXY_STATE_NORMAL 5 |
| 345 | #define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9) |
| 346 | #define HECI_FWSTS2 0xc48 |
| 347 | #define HECI_FWSTS3 0xc60 |
| 348 | #define HECI_FWSTS4 0xc64 |
| 349 | #define HECI_FWSTS5 0xc68 |
| 350 | #define HECI1_FWSTS5_HUC_AUTH_DONE (1 << 19) |
| 351 | #define HECI_FWSTS6 0xc6c |
| 352 | |
| 353 | /* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */ |
| 354 | #define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \ |
| 355 | HECI_FWSTS1, \ |
| 356 | HECI_FWSTS2, \ |
| 357 | HECI_FWSTS3, \ |
| 358 | HECI_FWSTS4, \ |
| 359 | HECI_FWSTS5, \ |
| 360 | HECI_FWSTS6)) |
Daniele Ceraolo Spurio | 98d2722 | 2023-05-31 16:54:12 -0700 | [diff] [blame] | 361 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 362 | #define HSW_GTT_CACHE_EN _MMIO(0x4024) |
Ville Syrjälä | 6d50b06 | 2015-05-19 20:32:57 +0300 | [diff] [blame] | 363 | #define GTT_CACHE_EN_ALL 0xF0007FFF |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 364 | #define GEN7_WR_WATERMARK _MMIO(0x4028) |
| 365 | #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) |
| 366 | #define ARB_MODE _MMIO(0x4030) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 367 | #define ARB_MODE_SWIZZLE_SNB (1 << 4) |
| 368 | #define ARB_MODE_SWIZZLE_IVB (1 << 5) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 369 | #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) |
| 370 | #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) |
Imre Deak | 9e72b46 | 2014-05-05 15:13:55 +0300 | [diff] [blame] | 371 | /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 372 | #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) |
Imre Deak | 9e72b46 | 2014-05-05 15:13:55 +0300 | [diff] [blame] | 373 | #define GEN7_LRA_LIMITS_REG_NUM 13 |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 374 | #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) |
| 375 | #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) |
Imre Deak | 9e72b46 | 2014-05-05 15:13:55 +0300 | [diff] [blame] | 376 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 377 | #define GEN7_ERR_INT _MMIO(0x44040) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 378 | #define ERR_INT_POISON (1 << 31) |
| 379 | #define ERR_INT_MMIO_UNCLAIMED (1 << 13) |
| 380 | #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) |
| 381 | #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) |
| 382 | #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) |
| 383 | #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) |
| 384 | #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) |
| 385 | #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) |
| 386 | #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) |
| 387 | #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) |
Chris Wilson | f406839 | 2010-10-27 20:36:41 +0100 | [diff] [blame] | 388 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 389 | #define FPGA_DBG _MMIO(0x42300) |
Ville Syrjälä | 6bb0a0e | 2021-11-12 21:38:13 +0200 | [diff] [blame] | 390 | #define FPGA_DBG_RM_NOCLAIM REG_BIT(31) |
Paulo Zanoni | 3f1e109 | 2013-02-18 19:00:21 -0300 | [diff] [blame] | 391 | |
Mika Kuoppala | 8ac3e1b | 2015-12-15 19:45:42 +0200 | [diff] [blame] | 392 | #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) |
Ville Syrjälä | 6bb0a0e | 2021-11-12 21:38:13 +0200 | [diff] [blame] | 393 | #define CLAIM_ER_CLR REG_BIT(31) |
| 394 | #define CLAIM_ER_OVERFLOW REG_BIT(16) |
| 395 | #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0) |
Mika Kuoppala | 8ac3e1b | 2015-12-15 19:45:42 +0200 | [diff] [blame] | 396 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 397 | #define DERRMR _MMIO(0x44050) |
Ben Widawsky | 4e0bbc3 | 2013-11-02 21:07:07 -0700 | [diff] [blame] | 398 | /* Note that HBLANK events are reserved on bdw+ */ |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 399 | #define DERRMR_PIPEA_SCANLINE (1 << 0) |
| 400 | #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) |
| 401 | #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) |
| 402 | #define DERRMR_PIPEA_VBLANK (1 << 3) |
| 403 | #define DERRMR_PIPEA_HBLANK (1 << 5) |
Paulo Zanoni | af7187b | 2018-06-12 16:56:53 -0700 | [diff] [blame] | 404 | #define DERRMR_PIPEB_SCANLINE (1 << 8) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 405 | #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) |
| 406 | #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) |
| 407 | #define DERRMR_PIPEB_VBLANK (1 << 11) |
| 408 | #define DERRMR_PIPEB_HBLANK (1 << 13) |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 409 | /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 410 | #define DERRMR_PIPEC_SCANLINE (1 << 14) |
| 411 | #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) |
| 412 | #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) |
| 413 | #define DERRMR_PIPEC_VBLANK (1 << 21) |
| 414 | #define DERRMR_PIPEC_HBLANK (1 << 22) |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 415 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 416 | #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) |
| 417 | #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) |
| 418 | #define SCPD0 _MMIO(0x209c) /* 915+ only */ |
Ville Syrjälä | 5cecf50 | 2020-07-02 18:37:23 +0300 | [diff] [blame] | 419 | #define SCPD_FBC_IGNORE_3D (1 << 6) |
Ville Syrjälä | 7d423af | 2019-10-03 17:02:31 +0300 | [diff] [blame] | 420 | #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) |
Paulo Zanoni | 9d9523d | 2019-04-10 16:53:42 -0700 | [diff] [blame] | 421 | #define GEN2_IER _MMIO(0x20a0) |
| 422 | #define GEN2_IIR _MMIO(0x20a4) |
| 423 | #define GEN2_IMR _MMIO(0x20a8) |
| 424 | #define GEN2_ISR _MMIO(0x20ac) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 425 | #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 426 | #define GINT_DIS (1 << 22) |
| 427 | #define GCFG_DIS (1 << 8) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 428 | #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) |
| 429 | #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) |
| 430 | #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) |
| 431 | #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) |
| 432 | #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) |
| 433 | #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) |
| 434 | #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 435 | #define VLV_PCBR_ADDR_SHIFT 12 |
| 436 | |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 437 | #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 438 | #define EIR _MMIO(0x20b0) |
| 439 | #define EMR _MMIO(0x20b4) |
| 440 | #define ESR _MMIO(0x20b8) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 441 | #define GM45_ERROR_PAGE_TABLE (1 << 5) |
| 442 | #define GM45_ERROR_MEM_PRIV (1 << 4) |
| 443 | #define I915_ERROR_PAGE_TABLE (1 << 4) |
| 444 | #define GM45_ERROR_CP_PRIV (1 << 3) |
| 445 | #define I915_ERROR_MEMORY_REFRESH (1 << 1) |
| 446 | #define I915_ERROR_INSTRUCTION (1 << 0) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 447 | #define INSTPM _MMIO(0x20c0) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 448 | #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ |
| 449 | #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 450 | will not assert AGPBUSY# and will only |
| 451 | be delivered when out of C3. */ |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 452 | #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ |
| 453 | #define INSTPM_TLB_INVALIDATE (1 << 9) |
| 454 | #define INSTPM_SYNC_FLUSH (1 << 5) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 455 | #define MEM_MODE _MMIO(0x20cc) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 456 | #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ |
| 457 | #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ |
| 458 | #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 459 | #define FW_BLC _MMIO(0x20d8) |
| 460 | #define FW_BLC2 _MMIO(0x20dc) |
| 461 | #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 462 | #define FW_BLC_SELF_EN_MASK (1 << 31) |
| 463 | #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ |
| 464 | #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 465 | #define MM_BURST_LENGTH 0x00700000 |
| 466 | #define MM_FIFO_WATERMARK 0x0001F000 |
| 467 | #define LM_BURST_LENGTH 0x00000700 |
| 468 | #define LM_FIFO_WATERMARK 0x0000001F |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 469 | #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ |
Keith Packard | 45503de | 2010-07-19 21:12:35 -0700 | [diff] [blame] | 470 | |
Matt Roper | 62afef2 | 2020-06-05 19:57:34 -0700 | [diff] [blame] | 471 | #define _MBUS_ABOX0_CTL 0x45038 |
| 472 | #define _MBUS_ABOX1_CTL 0x45048 |
| 473 | #define _MBUS_ABOX2_CTL 0x4504C |
Lucas De Marchi | 0d6e08c | 2023-01-20 11:34:56 -0800 | [diff] [blame] | 474 | #define MBUS_ABOX_CTL(x) \ |
| 475 | _MMIO(_PICK_EVEN_2RANGES(x, 2, \ |
| 476 | _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL, \ |
| 477 | _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL)) |
| 478 | |
Mahesh Kumar | 7800549 | 2018-01-30 11:49:14 -0200 | [diff] [blame] | 479 | #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) |
| 480 | #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) |
| 481 | #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) |
| 482 | #define MBUS_ABOX_B_CREDIT(x) ((x) << 16) |
| 483 | #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) |
| 484 | #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) |
| 485 | #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) |
| 486 | #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) |
| 487 | |
Keith Packard | 45503de | 2010-07-19 21:12:35 -0700 | [diff] [blame] | 488 | /* Make render/texture TLB fetches lower priorty than associated data |
| 489 | * fetches. This is not turned on by default |
| 490 | */ |
| 491 | #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) |
| 492 | |
| 493 | /* Isoch request wait on GTT enable (Display A/B/C streams). |
| 494 | * Make isoch requests stall on the TLB update. May cause |
| 495 | * display underruns (test mode only) |
| 496 | */ |
| 497 | #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) |
| 498 | |
| 499 | /* Block grant count for isoch requests when block count is |
| 500 | * set to a finite value. |
| 501 | */ |
| 502 | #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) |
| 503 | #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ |
| 504 | #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ |
| 505 | #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ |
| 506 | #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ |
| 507 | |
| 508 | /* Enable render writes to complete in C2/C3/C4 power states. |
| 509 | * If this isn't enabled, render writes are prevented in low |
| 510 | * power states. That seems bad to me. |
| 511 | */ |
| 512 | #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) |
| 513 | |
| 514 | /* This acknowledges an async flip immediately instead |
| 515 | * of waiting for 2TLB fetches. |
| 516 | */ |
| 517 | #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) |
| 518 | |
| 519 | /* Enables non-sequential data reads through arbiter |
| 520 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 521 | #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) |
Keith Packard | 45503de | 2010-07-19 21:12:35 -0700 | [diff] [blame] | 522 | |
| 523 | /* Disable FSB snooping of cacheable write cycles from binner/render |
| 524 | * command stream |
| 525 | */ |
| 526 | #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) |
| 527 | |
| 528 | /* Arbiter time slice for non-isoch streams */ |
| 529 | #define MI_ARB_TIME_SLICE_MASK (7 << 5) |
| 530 | #define MI_ARB_TIME_SLICE_1 (0 << 5) |
| 531 | #define MI_ARB_TIME_SLICE_2 (1 << 5) |
| 532 | #define MI_ARB_TIME_SLICE_4 (2 << 5) |
| 533 | #define MI_ARB_TIME_SLICE_6 (3 << 5) |
| 534 | #define MI_ARB_TIME_SLICE_8 (4 << 5) |
| 535 | #define MI_ARB_TIME_SLICE_10 (5 << 5) |
| 536 | #define MI_ARB_TIME_SLICE_14 (6 << 5) |
| 537 | #define MI_ARB_TIME_SLICE_16 (7 << 5) |
| 538 | |
| 539 | /* Low priority grace period page size */ |
| 540 | #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ |
| 541 | #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) |
| 542 | |
| 543 | /* Disable display A/B trickle feed */ |
| 544 | #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) |
| 545 | |
| 546 | /* Set display plane priority */ |
| 547 | #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ |
| 548 | #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ |
| 549 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 550 | #define MI_STATE _MMIO(0x20e4) /* gen2 only */ |
Ville Syrjälä | 54e472a | 2014-02-25 15:13:40 +0200 | [diff] [blame] | 551 | #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ |
| 552 | #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ |
| 553 | |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 554 | /* On modern GEN architectures interrupt control consists of two sets |
| 555 | * of registers. The first set pertains to the ring generating the |
| 556 | * interrupt. The second control is for the functional block generating the |
| 557 | * interrupt. These are PM, GT, DE, etc. |
| 558 | * |
| 559 | * Luckily *knocks on wood* all the ring interrupt bits match up with the |
| 560 | * GT interrupt bits, so we don't need to duplicate the defines. |
| 561 | * |
| 562 | * These defines should cover us well from SNB->HSW with minor exceptions |
| 563 | * it can also work on ILK. |
| 564 | */ |
| 565 | #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) |
| 566 | #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) |
| 567 | #define GT_BLT_USER_INTERRUPT (1 << 22) |
| 568 | #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) |
| 569 | #define GT_BSD_USER_INTERRUPT (1 << 12) |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 570 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ |
Chris Wilson | c4e8ba7 | 2020-04-07 14:08:11 +0100 | [diff] [blame] | 571 | #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */ |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 572 | #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 573 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ |
| 574 | #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) |
Chris Wilson | 70a76a9 | 2020-01-28 20:43:15 +0000 | [diff] [blame] | 575 | #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 576 | #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) |
| 577 | #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) |
| 578 | #define GT_RENDER_USER_INTERRUPT (1 << 0) |
| 579 | |
Ben Widawsky | 12638c5 | 2013-05-28 19:22:31 -0700 | [diff] [blame] | 580 | #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ |
| 581 | #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ |
| 582 | |
Tvrtko Ursulin | 772c2a5 | 2016-10-13 11:03:01 +0100 | [diff] [blame] | 583 | #define GT_PARITY_ERROR(dev_priv) \ |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 584 | (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ |
Tvrtko Ursulin | 772c2a5 | 2016-10-13 11:03:01 +0100 | [diff] [blame] | 585 | (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 586 | |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 587 | /* These are all the "old" interrupts */ |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 588 | #define ILK_BSD_USER_INTERRUPT (1 << 5) |
Ville Syrjälä | fac12f6 | 2014-04-09 13:28:06 +0300 | [diff] [blame] | 589 | |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 590 | #define I915_PM_INTERRUPT (1 << 31) |
| 591 | #define I915_ISP_INTERRUPT (1 << 22) |
| 592 | #define I915_LPE_PIPE_B_INTERRUPT (1 << 21) |
| 593 | #define I915_LPE_PIPE_A_INTERRUPT (1 << 20) |
| 594 | #define I915_MIPIC_INTERRUPT (1 << 19) |
| 595 | #define I915_MIPIA_INTERRUPT (1 << 18) |
| 596 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) |
| 597 | #define I915_DISPLAY_PORT_INTERRUPT (1 << 17) |
| 598 | #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) |
| 599 | #define I915_MASTER_ERROR_INTERRUPT (1 << 15) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 600 | #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) |
| 601 | #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ |
| 602 | #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) |
| 603 | #define I915_HWB_OOM_INTERRUPT (1 << 13) |
| 604 | #define I915_LPE_PIPE_C_INTERRUPT (1 << 12) |
| 605 | #define I915_SYNC_STATUS_INTERRUPT (1 << 12) |
| 606 | #define I915_MISC_INTERRUPT (1 << 11) |
| 607 | #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) |
| 608 | #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) |
| 609 | #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) |
| 610 | #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) |
| 611 | #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) |
| 612 | #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) |
| 613 | #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) |
| 614 | #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) |
| 615 | #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) |
| 616 | #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) |
| 617 | #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) |
| 618 | #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) |
| 619 | #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) |
| 620 | #define I915_DEBUG_INTERRUPT (1 << 2) |
| 621 | #define I915_WINVALID_INTERRUPT (1 << 1) |
| 622 | #define I915_USER_INTERRUPT (1 << 1) |
| 623 | #define I915_ASLE_INTERRUPT (1 << 0) |
| 624 | #define I915_BSD_USER_INTERRUPT (1 << 25) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 625 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 626 | #define GEN6_BSD_RNCID _MMIO(0x12198) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 627 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 628 | #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) |
Ben Widawsky | a1e969e | 2012-04-14 18:41:32 -0700 | [diff] [blame] | 629 | #define GEN7_FF_SCHED_MASK 0x0077070 |
Ben Widawsky | ab57fff | 2013-12-12 15:28:04 -0800 | [diff] [blame] | 630 | #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) |
Mika Kuoppala | 561db82 | 2020-02-07 17:51:37 +0200 | [diff] [blame] | 631 | #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 632 | #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) |
| 633 | #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) |
| 634 | #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) |
| 635 | #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ |
Ben Widawsky | 41c0b3a | 2013-01-26 11:52:00 -0800 | [diff] [blame] | 636 | #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 637 | #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) |
| 638 | #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) |
| 639 | #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ |
| 640 | #define GEN7_FF_VS_SCHED_HW (0x0 << 12) |
| 641 | #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) |
| 642 | #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) |
| 643 | #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ |
| 644 | #define GEN7_FF_DS_SCHED_HW (0x0 << 4) |
Ben Widawsky | a1e969e | 2012-04-14 18:41:32 -0700 | [diff] [blame] | 645 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 646 | #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) |
Ville Syrjälä | 3df3c589 | 2023-04-11 22:14:23 +0300 | [diff] [blame] | 647 | #define ILK_FBCQ_DIS REG_BIT(22) |
Ville Syrjälä | 3d0d333 | 2023-04-11 22:14:22 +0300 | [diff] [blame] | 648 | #define ILK_PABSTRETCH_DIS REG_BIT(21) |
| 649 | #define ILK_SABSTRETCH_DIS REG_BIT(20) |
Ville Syrjälä | b7a7053 | 2021-02-20 12:33:03 +0200 | [diff] [blame] | 650 | #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20) |
| 651 | #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0) |
| 652 | #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1) |
| 653 | #define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2) |
| 654 | #define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3) |
| 655 | #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18) |
| 656 | #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0) |
| 657 | #define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1) |
| 658 | #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2) |
| 659 | #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3) |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 660 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 661 | #define IPS_CTL _MMIO(0x43408) |
Ville Syrjälä | 42b4c47 | 2023-03-27 16:39:42 +0300 | [diff] [blame] | 662 | #define IPS_ENABLE REG_BIT(31) |
| 663 | #define IPS_FALSE_COLOR REG_BIT(4) |
Yuanhan Liu | 9c04f01 | 2010-12-15 15:42:32 +0800 | [diff] [blame] | 664 | |
| 665 | /* |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 666 | * Clock control & power management |
| 667 | */ |
Jani Nikula | 7322aed | 2024-04-23 19:44:59 +0300 | [diff] [blame] | 668 | #define _DPLL_A 0x6014 |
| 669 | #define _DPLL_B 0x6018 |
| 670 | #define _CHV_DPLL_C 0x6030 |
| 671 | #define DPLL(pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \ |
| 672 | (pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 673 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 674 | #define VGA0 _MMIO(0x6000) |
| 675 | #define VGA1 _MMIO(0x6004) |
| 676 | #define VGA_PD _MMIO(0x6010) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 677 | #define VGA0_PD_P2_DIV_4 (1 << 7) |
| 678 | #define VGA0_PD_P1_DIV_2 (1 << 5) |
| 679 | #define VGA0_PD_P1_SHIFT 0 |
| 680 | #define VGA0_PD_P1_MASK (0x1f << 0) |
| 681 | #define VGA1_PD_P2_DIV_4 (1 << 15) |
| 682 | #define VGA1_PD_P1_DIV_2 (1 << 13) |
| 683 | #define VGA1_PD_P1_SHIFT 8 |
| 684 | #define VGA1_PD_P1_MASK (0x1f << 8) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 685 | #define DPLL_VCO_ENABLE (1 << 31) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 686 | #define DPLL_SDVO_HIGH_SPEED (1 << 30) |
| 687 | #define DPLL_DVO_2X_MODE (1 << 30) |
Jesse Barnes | 25eb05fc | 2012-03-28 13:39:23 -0700 | [diff] [blame] | 688 | #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 689 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) |
Ville Syrjälä | 60bfe44 | 2015-06-29 15:25:49 +0300 | [diff] [blame] | 690 | #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 691 | #define DPLL_VGA_MODE_DIS (1 << 28) |
| 692 | #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ |
| 693 | #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ |
| 694 | #define DPLL_MODE_MASK (3 << 26) |
| 695 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ |
| 696 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ |
| 697 | #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ |
| 698 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ |
| 699 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ |
| 700 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 701 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 702 | #define DPLL_LOCK_VLV (1 << 15) |
| 703 | #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) |
| 704 | #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) |
| 705 | #define DPLL_SSC_REF_CLK_CHV (1 << 13) |
Daniel Vetter | 598fac6 | 2013-04-18 22:01:46 +0200 | [diff] [blame] | 706 | #define DPLL_PORTC_READY_MASK (0xf << 4) |
| 707 | #define DPLL_PORTB_READY_MASK (0xf) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 708 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 709 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 |
Chon Ming Lee | 00fc31b | 2014-04-09 13:28:15 +0300 | [diff] [blame] | 710 | |
| 711 | /* Additional CHV pll/phy registers */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 712 | #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) |
Chon Ming Lee | 00fc31b | 2014-04-09 13:28:15 +0300 | [diff] [blame] | 713 | #define DPLL_PORTD_READY_MASK (0xf) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 714 | #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 715 | #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) |
Ville Syrjälä | bc28454 | 2015-05-26 20:22:38 +0300 | [diff] [blame] | 716 | #define PHY_LDO_DELAY_0NS 0x0 |
| 717 | #define PHY_LDO_DELAY_200NS 0x1 |
| 718 | #define PHY_LDO_DELAY_600NS 0x2 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 719 | #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) |
| 720 | #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) |
Ville Syrjälä | 7072246 | 2015-04-10 18:21:28 +0300 | [diff] [blame] | 721 | #define PHY_CH_SU_PSR 0x1 |
| 722 | #define PHY_CH_DEEP_PSR 0x7 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 723 | #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) |
Ville Syrjälä | 7072246 | 2015-04-10 18:21:28 +0300 | [diff] [blame] | 724 | #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 725 | #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 726 | #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) |
| 727 | #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) |
| 728 | #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) |
Chon Ming Lee | 076ed3b | 2014-04-09 13:28:17 +0300 | [diff] [blame] | 729 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 730 | /* |
| 731 | * The i830 generation, in LVDS mode, defines P1 as the bit number set within |
| 732 | * this field (only one bit may be set). |
| 733 | */ |
| 734 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 |
| 735 | #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 736 | #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 737 | /* i830, required in DVO non-gang */ |
| 738 | #define PLL_P2_DIVIDE_BY_4 (1 << 23) |
| 739 | #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ |
| 740 | #define PLL_REF_INPUT_DREFCLK (0 << 13) |
| 741 | #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ |
| 742 | #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ |
| 743 | #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) |
| 744 | #define PLL_REF_INPUT_MASK (3 << 13) |
| 745 | #define PLL_LOAD_PULSE_PHASE_SHIFT 9 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 746 | /* Ironlake */ |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 747 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 |
| 748 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 749 | # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 750 | # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 |
| 751 | # define DPLL_FPA1_P1_POST_DIV_MASK 0xff |
| 752 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 753 | /* |
| 754 | * Parallel to Serial Load Pulse phase selection. |
| 755 | * Selects the phase for the 10X DPLL clock for the PCIe |
| 756 | * digital display port. The range is 4 to 13; 10 or more |
| 757 | * is just a flip delay. The default is 6 |
| 758 | */ |
| 759 | #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) |
| 760 | #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) |
| 761 | /* |
| 762 | * SDVO multiplier for 945G/GM. Not used on 965. |
| 763 | */ |
| 764 | #define SDVO_MULTIPLIER_MASK 0x000000ff |
| 765 | #define SDVO_MULTIPLIER_SHIFT_HIRES 4 |
| 766 | #define SDVO_MULTIPLIER_SHIFT_VGA 0 |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 767 | |
Jani Nikula | 7322aed | 2024-04-23 19:44:59 +0300 | [diff] [blame] | 768 | #define _DPLL_A_MD 0x601c |
| 769 | #define _DPLL_B_MD 0x6020 |
| 770 | #define _CHV_DPLL_C_MD 0x603c |
| 771 | #define DPLL_MD(pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \ |
| 772 | (pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 773 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 774 | /* |
| 775 | * UDI pixel divider, controlling how many pixels are stuffed into a packet. |
| 776 | * |
| 777 | * Value is pixels minus 1. Must be set to 1 pixel for SDVO. |
| 778 | */ |
| 779 | #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 |
| 780 | #define DPLL_MD_UDI_DIVIDER_SHIFT 24 |
| 781 | /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ |
| 782 | #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 |
| 783 | #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 |
| 784 | /* |
| 785 | * SDVO/UDI pixel multiplier. |
| 786 | * |
| 787 | * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus |
| 788 | * clock rate is 10 times the DPLL clock. At low resolution/refresh rate |
| 789 | * modes, the bus rate would be below the limits, so SDVO allows for stuffing |
| 790 | * dummy bytes in the datastream at an increased clock rate, with both sides of |
| 791 | * the link knowing how many bytes are fill. |
| 792 | * |
| 793 | * So, for a mode with a dotclock of 65Mhz, we would want to double the clock |
| 794 | * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be |
| 795 | * set to 130Mhz, and the SDVO multiplier set to 2x in this register and |
| 796 | * through an SDVO command. |
| 797 | * |
| 798 | * This register field has values of multiplication factor minus 1, with |
| 799 | * a maximum multiplier of 5 for SDVO. |
| 800 | */ |
| 801 | #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 |
| 802 | #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 |
| 803 | /* |
| 804 | * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. |
| 805 | * This best be set to the default value (3) or the CRT won't work. No, |
| 806 | * I don't entirely understand what this does... |
| 807 | */ |
| 808 | #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f |
| 809 | #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 |
Jesse Barnes | 25eb05fc | 2012-03-28 13:39:23 -0700 | [diff] [blame] | 810 | |
Ville Syrjälä | 19ab4ed | 2016-04-27 17:43:22 +0300 | [diff] [blame] | 811 | #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) |
| 812 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 813 | #define _FPA0 0x6040 |
| 814 | #define _FPA1 0x6044 |
| 815 | #define _FPB0 0x6048 |
| 816 | #define _FPB1 0x604c |
| 817 | #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) |
| 818 | #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 819 | #define FP_N_DIV_MASK 0x003f0000 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 820 | #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 821 | #define FP_N_DIV_SHIFT 16 |
| 822 | #define FP_M1_DIV_MASK 0x00003f00 |
| 823 | #define FP_M1_DIV_SHIFT 8 |
| 824 | #define FP_M2_DIV_MASK 0x0000003f |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 825 | #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 826 | #define FP_M2_DIV_SHIFT 0 |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 827 | #define DPLL_TEST _MMIO(0x606c) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 828 | #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) |
| 829 | #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) |
| 830 | #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) |
| 831 | #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) |
| 832 | #define DPLLB_TEST_N_BYPASS (1 << 19) |
| 833 | #define DPLLB_TEST_M_BYPASS (1 << 18) |
| 834 | #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) |
| 835 | #define DPLLA_TEST_N_BYPASS (1 << 3) |
| 836 | #define DPLLA_TEST_M_BYPASS (1 << 2) |
| 837 | #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 838 | #define D_STATE _MMIO(0x6104) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 839 | #define DSTATE_GFX_RESET_I830 (1 << 6) |
| 840 | #define DSTATE_PLL_D3_OFF (1 << 3) |
| 841 | #define DSTATE_GFX_CLOCK_GATING (1 << 1) |
| 842 | #define DSTATE_DOT_CLOCK_GATING (1 << 0) |
Jani Nikula | 3721d4f | 2022-08-30 13:28:01 +0300 | [diff] [blame] | 843 | #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 844 | # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ |
| 845 | # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ |
| 846 | # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ |
| 847 | # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ |
| 848 | # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ |
| 849 | # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ |
| 850 | # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ |
Ville Syrjälä | ad8059c | 2017-12-08 23:37:38 +0200 | [diff] [blame] | 851 | # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 852 | # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ |
| 853 | # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ |
| 854 | # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ |
| 855 | # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ |
| 856 | # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ |
| 857 | # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ |
| 858 | # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ |
| 859 | # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ |
| 860 | # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ |
| 861 | # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ |
| 862 | # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ |
| 863 | # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ |
| 864 | # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) |
| 865 | # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) |
| 866 | # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) |
| 867 | # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) |
| 868 | # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ |
| 869 | # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ |
| 870 | # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ |
| 871 | # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) |
| 872 | # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) |
Ville Syrjälä | 646b426 | 2014-04-25 20:14:30 +0300 | [diff] [blame] | 873 | /* |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 874 | * This bit must be set on the 830 to prevent hangs when turning off the |
| 875 | * overlay scaler. |
| 876 | */ |
| 877 | # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) |
| 878 | # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) |
| 879 | # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) |
| 880 | # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ |
| 881 | # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ |
| 882 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 883 | #define RENCLK_GATE_D1 _MMIO(0x6204) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 884 | # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ |
| 885 | # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ |
| 886 | # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) |
| 887 | # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) |
| 888 | # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) |
| 889 | # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) |
| 890 | # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) |
| 891 | # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) |
| 892 | # define MAG_CLOCK_GATE_DISABLE (1 << 5) |
Ville Syrjälä | 646b426 | 2014-04-25 20:14:30 +0300 | [diff] [blame] | 893 | /* This bit must be unset on 855,865 */ |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 894 | # define MECI_CLOCK_GATE_DISABLE (1 << 4) |
| 895 | # define DCMP_CLOCK_GATE_DISABLE (1 << 3) |
| 896 | # define MEC_CLOCK_GATE_DISABLE (1 << 2) |
| 897 | # define MECO_CLOCK_GATE_DISABLE (1 << 1) |
Ville Syrjälä | 646b426 | 2014-04-25 20:14:30 +0300 | [diff] [blame] | 898 | /* This bit must be set on 855,865. */ |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 899 | # define SV_CLOCK_GATE_DISABLE (1 << 0) |
| 900 | # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) |
| 901 | # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) |
| 902 | # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) |
| 903 | # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) |
| 904 | # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) |
| 905 | # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) |
| 906 | # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) |
| 907 | # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) |
| 908 | # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) |
| 909 | # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) |
| 910 | # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) |
| 911 | # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) |
| 912 | # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) |
| 913 | # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) |
| 914 | # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) |
| 915 | # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) |
| 916 | # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) |
| 917 | |
| 918 | # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) |
Ville Syrjälä | 646b426 | 2014-04-25 20:14:30 +0300 | [diff] [blame] | 919 | /* This bit must always be set on 965G/965GM */ |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 920 | # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) |
| 921 | # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) |
| 922 | # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) |
| 923 | # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) |
| 924 | # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) |
| 925 | # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) |
Ville Syrjälä | 646b426 | 2014-04-25 20:14:30 +0300 | [diff] [blame] | 926 | /* This bit must always be set on 965G */ |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 927 | # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) |
| 928 | # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) |
| 929 | # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) |
| 930 | # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) |
| 931 | # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) |
| 932 | # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) |
| 933 | # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) |
| 934 | # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) |
| 935 | # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) |
| 936 | # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) |
| 937 | # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) |
| 938 | # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) |
| 939 | # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) |
| 940 | # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) |
| 941 | # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) |
| 942 | # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) |
| 943 | # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) |
| 944 | # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) |
| 945 | # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) |
| 946 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 947 | #define RENCLK_GATE_D2 _MMIO(0x6208) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 948 | #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) |
| 949 | #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) |
| 950 | #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) |
Ville Syrjälä | fa4f53c | 2014-05-19 19:23:27 +0300 | [diff] [blame] | 951 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 952 | #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ |
Ville Syrjälä | fa4f53c | 2014-05-19 19:23:27 +0300 | [diff] [blame] | 953 | #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) |
| 954 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 955 | #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ |
| 956 | #define DEUC _MMIO(0x6214) /* CRL only */ |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 957 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 958 | #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 959 | #define FW_CSPWRDWNEN (1 << 15) |
Jesse Barnes | ceb0424 | 2012-03-28 13:39:22 -0700 | [diff] [blame] | 960 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 961 | #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) |
Ville Syrjälä | e0d8d59 | 2013-06-12 22:11:18 +0300 | [diff] [blame] | 962 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 963 | #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) |
Chon Ming Lee | 24eb2d5 | 2013-09-27 15:31:00 +0800 | [diff] [blame] | 964 | #define CDCLK_FREQ_SHIFT 4 |
| 965 | #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) |
| 966 | #define CZCLK_FREQ_MASK 0xf |
Vidya Srinivas | 1e69cd7 | 2015-03-05 21:19:50 +0200 | [diff] [blame] | 967 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 968 | #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) |
Vidya Srinivas | 1e69cd7 | 2015-03-05 21:19:50 +0200 | [diff] [blame] | 969 | #define PFI_CREDIT_63 (9 << 28) /* chv only */ |
| 970 | #define PFI_CREDIT_31 (8 << 28) /* chv only */ |
| 971 | #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ |
| 972 | #define PFI_CREDIT_RESEND (1 << 27) |
| 973 | #define VGA_FAST_MODE_DISABLE (1 << 14) |
| 974 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 975 | #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) |
Chon Ming Lee | 24eb2d5 | 2013-09-27 15:31:00 +0800 | [diff] [blame] | 976 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 977 | #define PEG_BAND_GAP_DATA _MMIO(0x14d68) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 978 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 979 | #define BXT_RP_STATE_CAP _MMIO(0x138170) |
Chris Wilson | 9938ee2 | 2020-04-20 18:27:36 +0100 | [diff] [blame] | 980 | #define GEN9_RP_STATE_LIMITS _MMIO(0x138148) |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 981 | |
Ashutosh Dixit | 835a4d1 | 2022-09-10 07:38:44 -0700 | [diff] [blame] | 982 | #define MTL_RP_STATE_CAP _MMIO(0x138000) |
| 983 | #define MTL_MEDIAP_STATE_CAP _MMIO(0x138020) |
| 984 | #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0) |
| 985 | #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16) |
| 986 | |
| 987 | #define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c) |
| 988 | #define MTL_MPE_FREQUENCY _MMIO(0x13802c) |
| 989 | #define MTL_RPE_MASK REG_GENMASK(8, 0) |
| 990 | |
Sujaritha Sundaresan | fa68bff | 2022-03-19 01:39:37 +0200 | [diff] [blame] | 991 | #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) |
| 992 | #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 |
Ashutosh Dixit | 60017f3 | 2022-09-08 08:58:21 -0700 | [diff] [blame] | 993 | #define PROCHOT_MASK REG_BIT(0) |
| 994 | #define THERMAL_LIMIT_MASK REG_BIT(1) |
| 995 | #define RATL_MASK REG_BIT(5) |
| 996 | #define VR_THERMALERT_MASK REG_BIT(6) |
| 997 | #define VR_TDC_MASK REG_BIT(7) |
| 998 | #define POWER_LIMIT_4_MASK REG_BIT(8) |
| 999 | #define POWER_LIMIT_1_MASK REG_BIT(10) |
| 1000 | #define POWER_LIMIT_2_MASK REG_BIT(11) |
Tilak Tangudu | fe59796 | 2022-09-10 07:38:42 -0700 | [diff] [blame] | 1001 | #define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16) |
Ashutosh Dixit | 1551b91 | 2022-09-10 07:38:43 -0700 | [diff] [blame] | 1002 | #define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030) |
Keith Packard | 881ee98 | 2008-11-02 23:08:44 -0800 | [diff] [blame] | 1003 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1004 | #define CHV_CLK_CTL1 _MMIO(0x101100) |
| 1005 | #define VLV_CLK_CTL2 _MMIO(0x101104) |
Jesse Barnes | e454a05 | 2013-09-26 17:55:58 -0700 | [diff] [blame] | 1006 | #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 |
| 1007 | |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 1008 | /* |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1009 | * Overlay regs |
| 1010 | */ |
| 1011 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1012 | #define OVADD _MMIO(0x30000) |
| 1013 | #define DOVSTA _MMIO(0x30008) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 1014 | #define OC_BUF (0x3 << 20) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1015 | #define OGAMC5 _MMIO(0x30010) |
| 1016 | #define OGAMC4 _MMIO(0x30014) |
| 1017 | #define OGAMC3 _MMIO(0x30018) |
| 1018 | #define OGAMC2 _MMIO(0x3001c) |
| 1019 | #define OGAMC1 _MMIO(0x30020) |
| 1020 | #define OGAMC0 _MMIO(0x30024) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1021 | |
| 1022 | /* |
Imre Deak | d965e7ac | 2015-12-01 10:23:52 +0200 | [diff] [blame] | 1023 | * GEN9 clock gating regs |
| 1024 | */ |
| 1025 | #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) |
Radhakrishna Sripada | 0188be50 | 2023-03-01 12:10:49 -0800 | [diff] [blame] | 1026 | #define DARBF_GATING_DIS REG_BIT(27) |
| 1027 | #define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15) |
| 1028 | #define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14) |
| 1029 | #define PWM2_GATING_DIS REG_BIT(14) |
| 1030 | #define PWM1_GATING_DIS REG_BIT(13) |
Imre Deak | d965e7ac | 2015-12-01 10:23:52 +0200 | [diff] [blame] | 1031 | |
Radhakrishna Sripada | f78d5da | 2020-01-09 14:37:27 -0800 | [diff] [blame] | 1032 | #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) |
| 1033 | #define TGL_VRH_GATING_DIS REG_BIT(31) |
Stuart Summers | da942750 | 2020-10-14 12:19:34 -0700 | [diff] [blame] | 1034 | #define DPT_GATING_DIS REG_BIT(22) |
Radhakrishna Sripada | f78d5da | 2020-01-09 14:37:27 -0800 | [diff] [blame] | 1035 | |
Ville Syrjälä | 6481d5e | 2017-12-21 22:24:32 +0200 | [diff] [blame] | 1036 | #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) |
| 1037 | #define BXT_GMBUS_GATING_DIS (1 << 14) |
| 1038 | |
José Roberto de Souza | a8a56da | 2021-05-14 08:37:09 -0700 | [diff] [blame] | 1039 | #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540) |
| 1040 | #define DPCE_GATING_DIS REG_BIT(17) |
| 1041 | |
Imre Deak | ed69cd4 | 2017-10-02 10:55:57 +0300 | [diff] [blame] | 1042 | #define _CLKGATE_DIS_PSL_A 0x46520 |
| 1043 | #define _CLKGATE_DIS_PSL_B 0x46524 |
| 1044 | #define _CLKGATE_DIS_PSL_C 0x46528 |
Vidya Srinivas | c4a4efa | 2018-04-09 09:11:09 +0530 | [diff] [blame] | 1045 | #define DUPS1_GATING_DIS (1 << 15) |
| 1046 | #define DUPS2_GATING_DIS (1 << 19) |
| 1047 | #define DUPS3_GATING_DIS (1 << 23) |
Tejas Upadhyay | 11408ea | 2021-09-29 10:54:42 +0530 | [diff] [blame] | 1048 | #define CURSOR_GATING_DIS REG_BIT(28) |
Imre Deak | ed69cd4 | 2017-10-02 10:55:57 +0300 | [diff] [blame] | 1049 | #define DPF_GATING_DIS (1 << 10) |
| 1050 | #define DPF_RAM_GATING_DIS (1 << 9) |
| 1051 | #define DPFR_GATING_DIS (1 << 8) |
| 1052 | |
| 1053 | #define CLKGATE_DIS_PSL(pipe) \ |
| 1054 | _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) |
| 1055 | |
Imre Deak | f31bccd | 2022-07-27 19:45:23 +0300 | [diff] [blame] | 1056 | #define _CLKGATE_DIS_PSL_EXT_A 0x4654C |
| 1057 | #define _CLKGATE_DIS_PSL_EXT_B 0x46550 |
| 1058 | #define PIPEDMC_GATING_DIS REG_BIT(12) |
| 1059 | |
| 1060 | #define CLKGATE_DIS_PSL_EXT(pipe) \ |
| 1061 | _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B) |
| 1062 | |
Radhakrishna Sripada | 51390cc | 2023-04-13 14:24:37 -0700 | [diff] [blame] | 1063 | /* DDI Buffer Control */ |
| 1064 | #define _DDI_CLK_VALFREQ_A 0x64030 |
| 1065 | #define _DDI_CLK_VALFREQ_B 0x64130 |
| 1066 | #define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B) |
| 1067 | |
Imre Deak | d965e7ac | 2015-12-01 10:23:52 +0200 | [diff] [blame] | 1068 | /* |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1069 | * Display engine regs |
| 1070 | */ |
| 1071 | |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1072 | /* Pipe A CRC regs */ |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 1073 | #define _PIPE_CRC_CTL_A 0x60050 |
Ville Syrjälä | 51707f2 | 2021-11-12 21:38:11 +0200 | [diff] [blame] | 1074 | #define PIPE_CRC_ENABLE REG_BIT(31) |
Ville Syrjälä | 207a815 | 2019-02-14 21:22:19 +0200 | [diff] [blame] | 1075 | /* skl+ source selection */ |
Ville Syrjälä | 51707f2 | 2021-11-12 21:38:11 +0200 | [diff] [blame] | 1076 | #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) |
| 1077 | #define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0) |
| 1078 | #define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2) |
| 1079 | #define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4) |
| 1080 | #define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6) |
| 1081 | #define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7) |
| 1082 | #define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5) |
| 1083 | #define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3) |
| 1084 | #define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1) |
Daniel Vetter | b4437a4 | 2013-10-16 22:55:54 +0200 | [diff] [blame] | 1085 | /* ivb+ source selection */ |
Ville Syrjälä | 51707f2 | 2021-11-12 21:38:11 +0200 | [diff] [blame] | 1086 | #define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29) |
| 1087 | #define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0) |
| 1088 | #define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1) |
| 1089 | #define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2) |
Daniel Vetter | b4437a4 | 2013-10-16 22:55:54 +0200 | [diff] [blame] | 1090 | /* ilk+ source selection */ |
Ville Syrjälä | 51707f2 | 2021-11-12 21:38:11 +0200 | [diff] [blame] | 1091 | #define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28) |
| 1092 | #define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0) |
| 1093 | #define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1) |
| 1094 | #define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2) |
| 1095 | /* embedded DP port on the north display block */ |
| 1096 | #define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4) |
| 1097 | #define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5) |
Daniel Vetter | b4437a4 | 2013-10-16 22:55:54 +0200 | [diff] [blame] | 1098 | /* vlv source selection */ |
Ville Syrjälä | 51707f2 | 2021-11-12 21:38:11 +0200 | [diff] [blame] | 1099 | #define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27) |
| 1100 | #define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0) |
| 1101 | #define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1) |
| 1102 | #define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2) |
Daniel Vetter | b4437a4 | 2013-10-16 22:55:54 +0200 | [diff] [blame] | 1103 | /* with DP port the pipe source is invalid */ |
Ville Syrjälä | 51707f2 | 2021-11-12 21:38:11 +0200 | [diff] [blame] | 1104 | #define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3) |
| 1105 | #define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6) |
| 1106 | #define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7) |
Daniel Vetter | b4437a4 | 2013-10-16 22:55:54 +0200 | [diff] [blame] | 1107 | /* gen3+ source selection */ |
Ville Syrjälä | 51707f2 | 2021-11-12 21:38:11 +0200 | [diff] [blame] | 1108 | #define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28) |
| 1109 | #define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0) |
| 1110 | #define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1) |
| 1111 | #define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2) |
Daniel Vetter | b4437a4 | 2013-10-16 22:55:54 +0200 | [diff] [blame] | 1112 | /* with DP/TV port the pipe source is invalid */ |
Ville Syrjälä | 51707f2 | 2021-11-12 21:38:11 +0200 | [diff] [blame] | 1113 | #define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3) |
| 1114 | #define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4) |
| 1115 | #define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5) |
| 1116 | #define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6) |
| 1117 | #define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7) |
Daniel Vetter | b4437a4 | 2013-10-16 22:55:54 +0200 | [diff] [blame] | 1118 | /* gen2 doesn't have source selection bits */ |
Ville Syrjälä | 51707f2 | 2021-11-12 21:38:11 +0200 | [diff] [blame] | 1119 | #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) |
Daniel Vetter | b4437a4 | 2013-10-16 22:55:54 +0200 | [diff] [blame] | 1120 | |
Daniel Vetter | 5a6b5c8 | 2013-10-16 22:55:47 +0200 | [diff] [blame] | 1121 | #define _PIPE_CRC_RES_1_A_IVB 0x60064 |
| 1122 | #define _PIPE_CRC_RES_2_A_IVB 0x60068 |
| 1123 | #define _PIPE_CRC_RES_3_A_IVB 0x6006c |
| 1124 | #define _PIPE_CRC_RES_4_A_IVB 0x60070 |
| 1125 | #define _PIPE_CRC_RES_5_A_IVB 0x60074 |
| 1126 | |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 1127 | #define _PIPE_CRC_RES_RED_A 0x60060 |
| 1128 | #define _PIPE_CRC_RES_GREEN_A 0x60064 |
| 1129 | #define _PIPE_CRC_RES_BLUE_A 0x60068 |
| 1130 | #define _PIPE_CRC_RES_RES1_A_I915 0x6006c |
| 1131 | #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1132 | |
| 1133 | /* Pipe B CRC regs */ |
Daniel Vetter | 5a6b5c8 | 2013-10-16 22:55:47 +0200 | [diff] [blame] | 1134 | #define _PIPE_CRC_RES_1_B_IVB 0x61064 |
| 1135 | #define _PIPE_CRC_RES_2_B_IVB 0x61068 |
| 1136 | #define _PIPE_CRC_RES_3_B_IVB 0x6106c |
| 1137 | #define _PIPE_CRC_RES_4_B_IVB 0x61070 |
| 1138 | #define _PIPE_CRC_RES_5_B_IVB 0x61074 |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1139 | |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 1140 | #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) |
| 1141 | #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB) |
| 1142 | #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB) |
| 1143 | #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) |
| 1144 | #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB) |
| 1145 | #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1146 | |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 1147 | #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) |
| 1148 | #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) |
| 1149 | #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) |
| 1150 | #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) |
| 1151 | #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) |
Daniel Vetter | 5a6b5c8 | 2013-10-16 22:55:47 +0200 | [diff] [blame] | 1152 | |
Ville Syrjälä | 5ac421a | 2023-02-14 00:52:49 +0200 | [diff] [blame] | 1153 | /* Pipe/transcoder A timing regs */ |
| 1154 | #define _TRANS_HTOTAL_A 0x60000 |
Ville Syrjälä | 050db7d | 2023-02-14 00:52:55 +0200 | [diff] [blame] | 1155 | #define HTOTAL_MASK REG_GENMASK(31, 16) |
| 1156 | #define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal)) |
| 1157 | #define HACTIVE_MASK REG_GENMASK(15, 0) |
| 1158 | #define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay)) |
Ville Syrjälä | 5ac421a | 2023-02-14 00:52:49 +0200 | [diff] [blame] | 1159 | #define _TRANS_HBLANK_A 0x60004 |
Ville Syrjälä | 050db7d | 2023-02-14 00:52:55 +0200 | [diff] [blame] | 1160 | #define HBLANK_END_MASK REG_GENMASK(31, 16) |
| 1161 | #define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end)) |
| 1162 | #define HBLANK_START_MASK REG_GENMASK(15, 0) |
| 1163 | #define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start)) |
Ville Syrjälä | 5ac421a | 2023-02-14 00:52:49 +0200 | [diff] [blame] | 1164 | #define _TRANS_HSYNC_A 0x60008 |
Ville Syrjälä | 050db7d | 2023-02-14 00:52:55 +0200 | [diff] [blame] | 1165 | #define HSYNC_END_MASK REG_GENMASK(31, 16) |
| 1166 | #define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end)) |
| 1167 | #define HSYNC_START_MASK REG_GENMASK(15, 0) |
| 1168 | #define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start)) |
Ville Syrjälä | 5ac421a | 2023-02-14 00:52:49 +0200 | [diff] [blame] | 1169 | #define _TRANS_VTOTAL_A 0x6000c |
Ville Syrjälä | 050db7d | 2023-02-14 00:52:55 +0200 | [diff] [blame] | 1170 | #define VTOTAL_MASK REG_GENMASK(31, 16) |
| 1171 | #define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal)) |
| 1172 | #define VACTIVE_MASK REG_GENMASK(15, 0) |
| 1173 | #define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay)) |
Ville Syrjälä | 5ac421a | 2023-02-14 00:52:49 +0200 | [diff] [blame] | 1174 | #define _TRANS_VBLANK_A 0x60010 |
Ville Syrjälä | 050db7d | 2023-02-14 00:52:55 +0200 | [diff] [blame] | 1175 | #define VBLANK_END_MASK REG_GENMASK(31, 16) |
| 1176 | #define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end)) |
| 1177 | #define VBLANK_START_MASK REG_GENMASK(15, 0) |
| 1178 | #define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start)) |
Ville Syrjälä | 5ac421a | 2023-02-14 00:52:49 +0200 | [diff] [blame] | 1179 | #define _TRANS_VSYNC_A 0x60014 |
Ville Syrjälä | 050db7d | 2023-02-14 00:52:55 +0200 | [diff] [blame] | 1180 | #define VSYNC_END_MASK REG_GENMASK(31, 16) |
| 1181 | #define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end)) |
| 1182 | #define VSYNC_START_MASK REG_GENMASK(15, 0) |
| 1183 | #define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start)) |
Ville Syrjälä | 5ac421a | 2023-02-14 00:52:49 +0200 | [diff] [blame] | 1184 | #define _TRANS_EXITLINE_A 0x60018 |
| 1185 | #define _PIPEASRC 0x6001c |
Ville Syrjälä | 62236df | 2021-11-12 21:38:10 +0200 | [diff] [blame] | 1186 | #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16) |
| 1187 | #define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w)) |
| 1188 | #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0) |
| 1189 | #define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h)) |
Ville Syrjälä | 5ac421a | 2023-02-14 00:52:49 +0200 | [diff] [blame] | 1190 | #define _BCLRPAT_A 0x60020 |
| 1191 | #define _TRANS_VSYNCSHIFT_A 0x60028 |
| 1192 | #define _TRANS_MULT_A 0x6002c |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1193 | |
Ville Syrjälä | 5ac421a | 2023-02-14 00:52:49 +0200 | [diff] [blame] | 1194 | /* Pipe/transcoder B timing regs */ |
| 1195 | #define _TRANS_HTOTAL_B 0x61000 |
| 1196 | #define _TRANS_HBLANK_B 0x61004 |
| 1197 | #define _TRANS_HSYNC_B 0x61008 |
| 1198 | #define _TRANS_VTOTAL_B 0x6100c |
| 1199 | #define _TRANS_VBLANK_B 0x61010 |
| 1200 | #define _TRANS_VSYNC_B 0x61014 |
| 1201 | #define _PIPEBSRC 0x6101c |
| 1202 | #define _BCLRPAT_B 0x61020 |
| 1203 | #define _TRANS_VSYNCSHIFT_B 0x61028 |
| 1204 | #define _TRANS_MULT_B 0x6102c |
Daniel Vetter | 0529a0d | 2012-01-28 14:49:24 +0100 | [diff] [blame] | 1205 | |
Madhav Chauhan | 7b56caf | 2018-10-15 17:28:02 +0300 | [diff] [blame] | 1206 | /* DSI 0 timing regs */ |
Ville Syrjälä | 5ac421a | 2023-02-14 00:52:49 +0200 | [diff] [blame] | 1207 | #define _TRANS_HTOTAL_DSI0 0x6b000 |
| 1208 | #define _TRANS_HSYNC_DSI0 0x6b008 |
| 1209 | #define _TRANS_VTOTAL_DSI0 0x6b00c |
| 1210 | #define _TRANS_VSYNC_DSI0 0x6b014 |
| 1211 | #define _TRANS_VSYNCSHIFT_DSI0 0x6b028 |
Madhav Chauhan | 7b56caf | 2018-10-15 17:28:02 +0300 | [diff] [blame] | 1212 | |
| 1213 | /* DSI 1 timing regs */ |
Ville Syrjälä | 5ac421a | 2023-02-14 00:52:49 +0200 | [diff] [blame] | 1214 | #define _TRANS_HTOTAL_DSI1 0x6b800 |
| 1215 | #define _TRANS_HSYNC_DSI1 0x6b808 |
| 1216 | #define _TRANS_VTOTAL_DSI1 0x6b80c |
| 1217 | #define _TRANS_VSYNC_DSI1 0x6b814 |
| 1218 | #define _TRANS_VSYNCSHIFT_DSI1 0x6b828 |
Madhav Chauhan | 7b56caf | 2018-10-15 17:28:02 +0300 | [diff] [blame] | 1219 | |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 1220 | #define TRANS_HTOTAL(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A) |
| 1221 | #define TRANS_HBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A) |
| 1222 | #define TRANS_HSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A) |
| 1223 | #define TRANS_VTOTAL(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A) |
| 1224 | #define TRANS_VBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A) |
| 1225 | #define TRANS_VSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) |
| 1226 | #define BCLRPAT(trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) |
| 1227 | #define TRANS_VSYNCSHIFT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A) |
| 1228 | #define PIPESRC(pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC) |
| 1229 | #define TRANS_MULT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1230 | |
Aditya Swarup | 106d4ffd | 2020-03-18 18:59:41 -0700 | [diff] [blame] | 1231 | /* VRR registers */ |
| 1232 | #define _TRANS_VRR_CTL_A 0x60420 |
| 1233 | #define _TRANS_VRR_CTL_B 0x61420 |
| 1234 | #define _TRANS_VRR_CTL_C 0x62420 |
| 1235 | #define _TRANS_VRR_CTL_D 0x63420 |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 1236 | #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) |
Ville Syrjälä | dc89bb8 | 2021-01-22 15:26:38 -0800 | [diff] [blame] | 1237 | #define VRR_CTL_VRR_ENABLE REG_BIT(31) |
| 1238 | #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) |
| 1239 | #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) |
| 1240 | #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) |
| 1241 | #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) |
| 1242 | #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) |
Manasi Navare | bb265db | 2021-05-25 17:06:55 -0700 | [diff] [blame] | 1243 | #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) |
| 1244 | #define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) |
Aditya Swarup | 106d4ffd | 2020-03-18 18:59:41 -0700 | [diff] [blame] | 1245 | |
| 1246 | #define _TRANS_VRR_VMAX_A 0x60424 |
| 1247 | #define _TRANS_VRR_VMAX_B 0x61424 |
| 1248 | #define _TRANS_VRR_VMAX_C 0x62424 |
| 1249 | #define _TRANS_VRR_VMAX_D 0x63424 |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 1250 | #define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A) |
Aditya Swarup | 106d4ffd | 2020-03-18 18:59:41 -0700 | [diff] [blame] | 1251 | #define VRR_VMAX_MASK REG_GENMASK(19, 0) |
| 1252 | |
| 1253 | #define _TRANS_VRR_VMIN_A 0x60434 |
| 1254 | #define _TRANS_VRR_VMIN_B 0x61434 |
| 1255 | #define _TRANS_VRR_VMIN_C 0x62434 |
| 1256 | #define _TRANS_VRR_VMIN_D 0x63434 |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 1257 | #define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A) |
Aditya Swarup | 106d4ffd | 2020-03-18 18:59:41 -0700 | [diff] [blame] | 1258 | #define VRR_VMIN_MASK REG_GENMASK(15, 0) |
| 1259 | |
| 1260 | #define _TRANS_VRR_VMAXSHIFT_A 0x60428 |
| 1261 | #define _TRANS_VRR_VMAXSHIFT_B 0x61428 |
| 1262 | #define _TRANS_VRR_VMAXSHIFT_C 0x62428 |
| 1263 | #define _TRANS_VRR_VMAXSHIFT_D 0x63428 |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 1264 | #define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(dev_priv, trans, \ |
Aditya Swarup | 106d4ffd | 2020-03-18 18:59:41 -0700 | [diff] [blame] | 1265 | _TRANS_VRR_VMAXSHIFT_A) |
| 1266 | #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) |
| 1267 | #define VRR_VMAXSHIFT_DEC REG_BIT(16) |
| 1268 | #define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) |
| 1269 | |
| 1270 | #define _TRANS_VRR_STATUS_A 0x6042C |
| 1271 | #define _TRANS_VRR_STATUS_B 0x6142C |
| 1272 | #define _TRANS_VRR_STATUS_C 0x6242C |
| 1273 | #define _TRANS_VRR_STATUS_D 0x6342C |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 1274 | #define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) |
Aditya Swarup | 106d4ffd | 2020-03-18 18:59:41 -0700 | [diff] [blame] | 1275 | #define VRR_STATUS_VMAX_REACHED REG_BIT(31) |
| 1276 | #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) |
| 1277 | #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) |
| 1278 | #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) |
| 1279 | #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) |
| 1280 | #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) |
| 1281 | #define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) |
| 1282 | #define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) |
| 1283 | #define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) |
| 1284 | #define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) |
| 1285 | #define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) |
| 1286 | #define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) |
| 1287 | #define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) |
| 1288 | #define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) |
| 1289 | |
| 1290 | #define _TRANS_VRR_VTOTAL_PREV_A 0x60480 |
| 1291 | #define _TRANS_VRR_VTOTAL_PREV_B 0x61480 |
| 1292 | #define _TRANS_VRR_VTOTAL_PREV_C 0x62480 |
| 1293 | #define _TRANS_VRR_VTOTAL_PREV_D 0x63480 |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 1294 | #define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(dev_priv, trans, \ |
Aditya Swarup | 106d4ffd | 2020-03-18 18:59:41 -0700 | [diff] [blame] | 1295 | _TRANS_VRR_VTOTAL_PREV_A) |
| 1296 | #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) |
| 1297 | #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) |
| 1298 | #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) |
| 1299 | #define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) |
| 1300 | |
| 1301 | #define _TRANS_VRR_FLIPLINE_A 0x60438 |
| 1302 | #define _TRANS_VRR_FLIPLINE_B 0x61438 |
| 1303 | #define _TRANS_VRR_FLIPLINE_C 0x62438 |
| 1304 | #define _TRANS_VRR_FLIPLINE_D 0x63438 |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 1305 | #define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(dev_priv, trans, \ |
Aditya Swarup | 106d4ffd | 2020-03-18 18:59:41 -0700 | [diff] [blame] | 1306 | _TRANS_VRR_FLIPLINE_A) |
| 1307 | #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) |
| 1308 | |
| 1309 | #define _TRANS_VRR_STATUS2_A 0x6043C |
| 1310 | #define _TRANS_VRR_STATUS2_B 0x6143C |
| 1311 | #define _TRANS_VRR_STATUS2_C 0x6243C |
| 1312 | #define _TRANS_VRR_STATUS2_D 0x6343C |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 1313 | #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A) |
Aditya Swarup | 106d4ffd | 2020-03-18 18:59:41 -0700 | [diff] [blame] | 1314 | #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) |
| 1315 | |
| 1316 | #define _TRANS_PUSH_A 0x60A70 |
| 1317 | #define _TRANS_PUSH_B 0x61A70 |
| 1318 | #define _TRANS_PUSH_C 0x62A70 |
| 1319 | #define _TRANS_PUSH_D 0x63A70 |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 1320 | #define TRANS_PUSH(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A) |
Aditya Swarup | 106d4ffd | 2020-03-18 18:59:41 -0700 | [diff] [blame] | 1321 | #define TRANS_PUSH_EN REG_BIT(31) |
| 1322 | #define TRANS_PUSH_SEND REG_BIT(30) |
| 1323 | |
Mitul Golani | e8cd188 | 2024-03-22 08:41:56 +0530 | [diff] [blame] | 1324 | #define _TRANS_VRR_VSYNC_A 0x60078 |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 1325 | #define TRANS_VRR_VSYNC(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) |
Mitul Golani | e8cd188 | 2024-03-22 08:41:56 +0530 | [diff] [blame] | 1326 | #define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) |
| 1327 | #define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end)) |
| 1328 | #define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) |
| 1329 | #define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start)) |
| 1330 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1331 | /* VGA port control */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1332 | #define ADPA _MMIO(0x61100) |
| 1333 | #define PCH_ADPA _MMIO(0xe1100) |
| 1334 | #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) |
Daniel Vetter | ebc0fd8 | 2012-07-11 16:27:56 +0200 | [diff] [blame] | 1335 | |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 1336 | #define ADPA_DAC_ENABLE (1 << 31) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1337 | #define ADPA_DAC_DISABLE 0 |
Ville Syrjälä | 6102a8e | 2018-05-14 20:24:19 +0300 | [diff] [blame] | 1338 | #define ADPA_PIPE_SEL_SHIFT 30 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 1339 | #define ADPA_PIPE_SEL_MASK (1 << 30) |
Ville Syrjälä | 6102a8e | 2018-05-14 20:24:19 +0300 | [diff] [blame] | 1340 | #define ADPA_PIPE_SEL(pipe) ((pipe) << 30) |
| 1341 | #define ADPA_PIPE_SEL_SHIFT_CPT 29 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 1342 | #define ADPA_PIPE_SEL_MASK_CPT (3 << 29) |
Ville Syrjälä | 6102a8e | 2018-05-14 20:24:19 +0300 | [diff] [blame] | 1343 | #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29) |
Daniel Vetter | ebc0fd8 | 2012-07-11 16:27:56 +0200 | [diff] [blame] | 1344 | #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 1345 | #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24) |
| 1346 | #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24) |
| 1347 | #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24) |
| 1348 | #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24) |
| 1349 | #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23) |
| 1350 | #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22) |
| 1351 | #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22) |
| 1352 | #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21) |
| 1353 | #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21) |
| 1354 | #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20) |
| 1355 | #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20) |
| 1356 | #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18) |
| 1357 | #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18) |
| 1358 | #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18) |
| 1359 | #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18) |
| 1360 | #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17) |
| 1361 | #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17) |
| 1362 | #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16) |
| 1363 | #define ADPA_USE_VGA_HVPOLARITY (1 << 15) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1364 | #define ADPA_SETS_HVPOLARITY 0 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 1365 | #define ADPA_VSYNC_CNTL_DISABLE (1 << 10) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1366 | #define ADPA_VSYNC_CNTL_ENABLE 0 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 1367 | #define ADPA_HSYNC_CNTL_DISABLE (1 << 11) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1368 | #define ADPA_HSYNC_CNTL_ENABLE 0 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 1369 | #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1370 | #define ADPA_VSYNC_ACTIVE_LOW 0 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 1371 | #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1372 | #define ADPA_HSYNC_ACTIVE_LOW 0 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 1373 | #define ADPA_DPMS_MASK (~(3 << 10)) |
| 1374 | #define ADPA_DPMS_ON (0 << 10) |
| 1375 | #define ADPA_DPMS_SUSPEND (1 << 10) |
| 1376 | #define ADPA_DPMS_STANDBY (2 << 10) |
| 1377 | #define ADPA_DPMS_OFF (3 << 10) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1378 | |
Chris Wilson | 939fe4d | 2010-10-09 10:33:26 +0100 | [diff] [blame] | 1379 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1380 | /* Hotplug control (945+ only) */ |
Jani Nikula | ed5eb1b | 2018-12-31 16:56:42 +0200 | [diff] [blame] | 1381 | #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) |
Daniel Vetter | 26739f1 | 2013-02-07 12:42:32 +0100 | [diff] [blame] | 1382 | #define PORTB_HOTPLUG_INT_EN (1 << 29) |
| 1383 | #define PORTC_HOTPLUG_INT_EN (1 << 28) |
| 1384 | #define PORTD_HOTPLUG_INT_EN (1 << 27) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1385 | #define SDVOB_HOTPLUG_INT_EN (1 << 26) |
| 1386 | #define SDVOC_HOTPLUG_INT_EN (1 << 25) |
| 1387 | #define TV_HOTPLUG_INT_EN (1 << 18) |
| 1388 | #define CRT_HOTPLUG_INT_EN (1 << 9) |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 1389 | #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ |
| 1390 | PORTC_HOTPLUG_INT_EN | \ |
| 1391 | PORTD_HOTPLUG_INT_EN | \ |
| 1392 | SDVOC_HOTPLUG_INT_EN | \ |
| 1393 | SDVOB_HOTPLUG_INT_EN | \ |
| 1394 | CRT_HOTPLUG_INT_EN) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1395 | #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 1396 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) |
| 1397 | /* must use period 64 on GM45 according to docs */ |
| 1398 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) |
| 1399 | #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) |
| 1400 | #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) |
| 1401 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) |
| 1402 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) |
| 1403 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) |
| 1404 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) |
| 1405 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) |
| 1406 | #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) |
| 1407 | #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) |
| 1408 | #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) |
| 1409 | #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1410 | |
Jani Nikula | ed5eb1b | 2018-12-31 16:56:42 +0200 | [diff] [blame] | 1411 | #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) |
Ville Syrjälä | 4b736ed | 2023-03-02 18:10:09 +0200 | [diff] [blame] | 1412 | /* HDMI/DP bits are g4x+ */ |
Ville Syrjälä | 0780cd3 | 2016-02-10 19:59:05 +0200 | [diff] [blame] | 1413 | #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) |
Todd Previte | 232a6ee | 2014-01-23 00:13:41 -0700 | [diff] [blame] | 1414 | #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) |
Ville Syrjälä | 0780cd3 | 2016-02-10 19:59:05 +0200 | [diff] [blame] | 1415 | #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) |
Daniel Vetter | 26739f1 | 2013-02-07 12:42:32 +0100 | [diff] [blame] | 1416 | #define PORTD_HOTPLUG_INT_STATUS (3 << 21) |
Daniel Vetter | a211b49 | 2014-06-05 09:36:23 +0200 | [diff] [blame] | 1417 | #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) |
| 1418 | #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) |
Daniel Vetter | 26739f1 | 2013-02-07 12:42:32 +0100 | [diff] [blame] | 1419 | #define PORTC_HOTPLUG_INT_STATUS (3 << 19) |
Daniel Vetter | a211b49 | 2014-06-05 09:36:23 +0200 | [diff] [blame] | 1420 | #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) |
| 1421 | #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) |
Daniel Vetter | 26739f1 | 2013-02-07 12:42:32 +0100 | [diff] [blame] | 1422 | #define PORTB_HOTPLUG_INT_STATUS (3 << 17) |
Daniel Vetter | a211b49 | 2014-06-05 09:36:23 +0200 | [diff] [blame] | 1423 | #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) |
| 1424 | #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) |
Chris Wilson | 084b612 | 2012-05-11 18:01:33 +0100 | [diff] [blame] | 1425 | /* CRT/TV common between gen3+ */ |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1426 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) |
| 1427 | #define TV_HOTPLUG_INT_STATUS (1 << 10) |
| 1428 | #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) |
| 1429 | #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) |
| 1430 | #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) |
| 1431 | #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) |
Daniel Vetter | 4aeebd7 | 2013-10-31 09:53:36 +0100 | [diff] [blame] | 1432 | #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) |
| 1433 | #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) |
| 1434 | #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) |
Imre Deak | bfbdb42 | 2014-01-16 19:56:53 +0200 | [diff] [blame] | 1435 | #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) |
| 1436 | |
Chris Wilson | 084b612 | 2012-05-11 18:01:33 +0100 | [diff] [blame] | 1437 | /* SDVO is different across gen3/4 */ |
| 1438 | #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) |
| 1439 | #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) |
Daniel Vetter | 4f7fd70 | 2013-06-24 21:33:28 +0200 | [diff] [blame] | 1440 | /* |
| 1441 | * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, |
| 1442 | * since reality corrobates that they're the same as on gen3. But keep these |
| 1443 | * bits here (and the comment!) to help any other lost wanderers back onto the |
| 1444 | * right tracks. |
| 1445 | */ |
Chris Wilson | 084b612 | 2012-05-11 18:01:33 +0100 | [diff] [blame] | 1446 | #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) |
| 1447 | #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) |
| 1448 | #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) |
| 1449 | #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 1450 | #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ |
| 1451 | SDVOB_HOTPLUG_INT_STATUS_G4X | \ |
| 1452 | SDVOC_HOTPLUG_INT_STATUS_G4X | \ |
| 1453 | PORTB_HOTPLUG_INT_STATUS | \ |
| 1454 | PORTC_HOTPLUG_INT_STATUS | \ |
| 1455 | PORTD_HOTPLUG_INT_STATUS) |
| 1456 | |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 1457 | #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ |
| 1458 | SDVOB_HOTPLUG_INT_STATUS_I915 | \ |
| 1459 | SDVOC_HOTPLUG_INT_STATUS_I915 | \ |
| 1460 | PORTB_HOTPLUG_INT_STATUS | \ |
| 1461 | PORTC_HOTPLUG_INT_STATUS | \ |
| 1462 | PORTD_HOTPLUG_INT_STATUS) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1463 | |
Paulo Zanoni | c20cd31 | 2013-02-19 16:21:45 -0300 | [diff] [blame] | 1464 | /* SDVO and HDMI port control. |
| 1465 | * The same register may be used for SDVO or HDMI */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1466 | #define _GEN3_SDVOB 0x61140 |
| 1467 | #define _GEN3_SDVOC 0x61160 |
| 1468 | #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) |
| 1469 | #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) |
Paulo Zanoni | c20cd31 | 2013-02-19 16:21:45 -0300 | [diff] [blame] | 1470 | #define GEN4_HDMIB GEN3_SDVOB |
| 1471 | #define GEN4_HDMIC GEN3_SDVOC |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1472 | #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) |
| 1473 | #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) |
| 1474 | #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) |
| 1475 | #define PCH_SDVOB _MMIO(0xe1140) |
Paulo Zanoni | c20cd31 | 2013-02-19 16:21:45 -0300 | [diff] [blame] | 1476 | #define PCH_HDMIB PCH_SDVOB |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1477 | #define PCH_HDMIC _MMIO(0xe1150) |
| 1478 | #define PCH_HDMID _MMIO(0xe1160) |
Paulo Zanoni | c20cd31 | 2013-02-19 16:21:45 -0300 | [diff] [blame] | 1479 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1480 | #define PORT_DFT_I9XX _MMIO(0x61150) |
Daniel Vetter | 84093603 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 1481 | #define DC_BALANCE_RESET (1 << 25) |
Jani Nikula | ed5eb1b | 2018-12-31 16:56:42 +0200 | [diff] [blame] | 1482 | #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) |
Daniel Vetter | 84093603 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 1483 | #define DC_BALANCE_RESET_VLV (1 << 31) |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 1484 | #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) |
Ville Syrjälä | 51707f2 | 2021-11-12 21:38:11 +0200 | [diff] [blame] | 1485 | #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */ |
| 1486 | #define PIPE_B_SCRAMBLE_RESET REG_BIT(1) |
| 1487 | #define PIPE_A_SCRAMBLE_RESET REG_BIT(0) |
Daniel Vetter | 84093603 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 1488 | |
Paulo Zanoni | c20cd31 | 2013-02-19 16:21:45 -0300 | [diff] [blame] | 1489 | /* Gen 3 SDVO bits: */ |
| 1490 | #define SDVO_ENABLE (1 << 31) |
Ville Syrjälä | 7620346 | 2018-05-14 20:24:21 +0300 | [diff] [blame] | 1491 | #define SDVO_PIPE_SEL_SHIFT 30 |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 1492 | #define SDVO_PIPE_SEL_MASK (1 << 30) |
Ville Syrjälä | 7620346 | 2018-05-14 20:24:21 +0300 | [diff] [blame] | 1493 | #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) |
Paulo Zanoni | c20cd31 | 2013-02-19 16:21:45 -0300 | [diff] [blame] | 1494 | #define SDVO_STALL_SELECT (1 << 29) |
| 1495 | #define SDVO_INTERRUPT_ENABLE (1 << 26) |
Ville Syrjälä | 646b426 | 2014-04-25 20:14:30 +0300 | [diff] [blame] | 1496 | /* |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1497 | * 915G/GM SDVO pixel multiplier. |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1498 | * Programmed value is multiplier - 1, up to 5x. |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1499 | * \sa DPLL_MD_UDI_MULTIPLIER_MASK |
| 1500 | */ |
Paulo Zanoni | c20cd31 | 2013-02-19 16:21:45 -0300 | [diff] [blame] | 1501 | #define SDVO_PORT_MULTIPLY_MASK (7 << 23) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1502 | #define SDVO_PORT_MULTIPLY_SHIFT 23 |
Paulo Zanoni | c20cd31 | 2013-02-19 16:21:45 -0300 | [diff] [blame] | 1503 | #define SDVO_PHASE_SELECT_MASK (15 << 19) |
| 1504 | #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) |
| 1505 | #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) |
| 1506 | #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ |
| 1507 | #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ |
| 1508 | #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ |
| 1509 | #define SDVO_DETECTED (1 << 2) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1510 | /* Bits to be preserved when writing */ |
Paulo Zanoni | c20cd31 | 2013-02-19 16:21:45 -0300 | [diff] [blame] | 1511 | #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ |
| 1512 | SDVO_INTERRUPT_ENABLE) |
| 1513 | #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) |
| 1514 | |
| 1515 | /* Gen 4 SDVO/HDMI bits: */ |
Paulo Zanoni | 4f3a8bc | 2013-02-19 16:21:47 -0300 | [diff] [blame] | 1516 | #define SDVO_COLOR_FORMAT_8bpc (0 << 26) |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 1517 | #define SDVO_COLOR_FORMAT_MASK (7 << 26) |
Paulo Zanoni | c20cd31 | 2013-02-19 16:21:45 -0300 | [diff] [blame] | 1518 | #define SDVO_ENCODING_SDVO (0 << 10) |
| 1519 | #define SDVO_ENCODING_HDMI (2 << 10) |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 1520 | #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ |
| 1521 | #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ |
Paulo Zanoni | 4f3a8bc | 2013-02-19 16:21:47 -0300 | [diff] [blame] | 1522 | #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ |
Ville Syrjälä | dd6090f | 2019-04-09 17:40:50 +0300 | [diff] [blame] | 1523 | #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */ |
Paulo Zanoni | c20cd31 | 2013-02-19 16:21:45 -0300 | [diff] [blame] | 1524 | /* VSYNC/HSYNC bits new with 965, default is to be set */ |
| 1525 | #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) |
| 1526 | #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) |
| 1527 | |
| 1528 | /* Gen 5 (IBX) SDVO/HDMI bits: */ |
Paulo Zanoni | 4f3a8bc | 2013-02-19 16:21:47 -0300 | [diff] [blame] | 1529 | #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ |
Paulo Zanoni | c20cd31 | 2013-02-19 16:21:45 -0300 | [diff] [blame] | 1530 | #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ |
| 1531 | |
| 1532 | /* Gen 6 (CPT) SDVO/HDMI bits: */ |
Ville Syrjälä | 7620346 | 2018-05-14 20:24:21 +0300 | [diff] [blame] | 1533 | #define SDVO_PIPE_SEL_SHIFT_CPT 29 |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 1534 | #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) |
Ville Syrjälä | 7620346 | 2018-05-14 20:24:21 +0300 | [diff] [blame] | 1535 | #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) |
Paulo Zanoni | c20cd31 | 2013-02-19 16:21:45 -0300 | [diff] [blame] | 1536 | |
Chon Ming Lee | 44f37d1 | 2014-04-09 13:28:21 +0300 | [diff] [blame] | 1537 | /* CHV SDVO/HDMI bits: */ |
Ville Syrjälä | 7620346 | 2018-05-14 20:24:21 +0300 | [diff] [blame] | 1538 | #define SDVO_PIPE_SEL_SHIFT_CHV 24 |
Chon Ming Lee | 44f37d1 | 2014-04-09 13:28:21 +0300 | [diff] [blame] | 1539 | #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) |
Ville Syrjälä | 7620346 | 2018-05-14 20:24:21 +0300 | [diff] [blame] | 1540 | #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) |
Chon Ming Lee | 44f37d1 | 2014-04-09 13:28:21 +0300 | [diff] [blame] | 1541 | |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 1542 | /* Video Data Island Packet control */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1543 | #define VIDEO_DIP_DATA _MMIO(0x61178) |
Yannick Guerrini | fd0753c | 2015-02-28 17:20:41 +0100 | [diff] [blame] | 1544 | /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC |
Paulo Zanoni | adf00b2 | 2012-09-25 13:23:34 -0300 | [diff] [blame] | 1545 | * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte |
| 1546 | * of the infoframe structure specified by CEA-861. */ |
| 1547 | #define VIDEO_DIP_DATA_SIZE 32 |
Mitul Golani | 12ea892 | 2024-03-22 08:41:52 +0530 | [diff] [blame] | 1548 | #define VIDEO_DIP_ASYNC_DATA_SIZE 36 |
Gwan-gyeong Mun | 922430d | 2019-09-19 22:53:09 +0300 | [diff] [blame] | 1549 | #define VIDEO_DIP_GMP_DATA_SIZE 36 |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1550 | #define VIDEO_DIP_VSC_DATA_SIZE 36 |
Manasi Navare | 4c61483 | 2018-11-28 12:26:20 -0800 | [diff] [blame] | 1551 | #define VIDEO_DIP_PPS_DATA_SIZE 132 |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1552 | #define VIDEO_DIP_CTL _MMIO(0x61170) |
Paulo Zanoni | 2da8af5 | 2012-05-14 17:12:51 -0300 | [diff] [blame] | 1553 | /* Pre HSW: */ |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 1554 | #define VIDEO_DIP_ENABLE (1 << 31) |
Ville Syrjälä | 822cdc5 | 2014-01-23 23:15:34 +0200 | [diff] [blame] | 1555 | #define VIDEO_DIP_PORT(port) ((port) << 29) |
Paulo Zanoni | 3e6e639 | 2012-05-04 17:18:19 -0300 | [diff] [blame] | 1556 | #define VIDEO_DIP_PORT_MASK (3 << 29) |
Ville Syrjälä | 5cb3c1a | 2019-02-25 19:40:58 +0200 | [diff] [blame] | 1557 | #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 1558 | #define VIDEO_DIP_ENABLE_AVI (1 << 21) |
| 1559 | #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) |
Ville Syrjälä | 5cb3c1a | 2019-02-25 19:40:58 +0200 | [diff] [blame] | 1560 | #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 1561 | #define VIDEO_DIP_ENABLE_SPD (8 << 21) |
| 1562 | #define VIDEO_DIP_SELECT_AVI (0 << 19) |
| 1563 | #define VIDEO_DIP_SELECT_VENDOR (1 << 19) |
Ville Syrjälä | 5cb3c1a | 2019-02-25 19:40:58 +0200 | [diff] [blame] | 1564 | #define VIDEO_DIP_SELECT_GAMUT (2 << 19) |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 1565 | #define VIDEO_DIP_SELECT_SPD (3 << 19) |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 1566 | #define VIDEO_DIP_SELECT_MASK (3 << 19) |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 1567 | #define VIDEO_DIP_FREQ_ONCE (0 << 16) |
| 1568 | #define VIDEO_DIP_FREQ_VSYNC (1 << 16) |
| 1569 | #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) |
Paulo Zanoni | 60c5ea2 | 2012-05-04 17:18:22 -0300 | [diff] [blame] | 1570 | #define VIDEO_DIP_FREQ_MASK (3 << 16) |
Paulo Zanoni | 2da8af5 | 2012-05-14 17:12:51 -0300 | [diff] [blame] | 1571 | /* HSW and later: */ |
Ville Syrjälä | 44b42eb | 2019-05-17 21:52:25 +0530 | [diff] [blame] | 1572 | #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) |
Dhinakaran Pandiyan | a670be3 | 2018-10-05 11:56:43 -0700 | [diff] [blame] | 1573 | #define PSR_VSC_BIT_7_SET (1 << 27) |
| 1574 | #define VSC_SELECT_MASK (0x3 << 25) |
| 1575 | #define VSC_SELECT_SHIFT 25 |
| 1576 | #define VSC_DIP_HW_HEA_DATA (0 << 25) |
| 1577 | #define VSC_DIP_HW_HEA_SW_DATA (1 << 25) |
| 1578 | #define VSC_DIP_HW_DATA_SW_HEA (2 << 25) |
| 1579 | #define VSC_DIP_SW_HEA_DATA (3 << 25) |
| 1580 | #define VDIP_ENABLE_PPS (1 << 24) |
Paulo Zanoni | 0dd87d2 | 2012-05-28 16:42:53 -0300 | [diff] [blame] | 1581 | #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) |
| 1582 | #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) |
Paulo Zanoni | 2da8af5 | 2012-05-14 17:12:51 -0300 | [diff] [blame] | 1583 | #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) |
Paulo Zanoni | 0dd87d2 | 2012-05-28 16:42:53 -0300 | [diff] [blame] | 1584 | #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) |
| 1585 | #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) |
Paulo Zanoni | 2da8af5 | 2012-05-14 17:12:51 -0300 | [diff] [blame] | 1586 | #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) |
Mitul Golani | 12ea892 | 2024-03-22 08:41:52 +0530 | [diff] [blame] | 1587 | /* ADL and later: */ |
| 1588 | #define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23) |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 1589 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1590 | /* Panel fitting */ |
Jani Nikula | ed5eb1b | 2018-12-31 16:56:42 +0200 | [diff] [blame] | 1591 | #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) |
Ville Syrjälä | 08df6d3 | 2023-04-18 20:55:18 +0300 | [diff] [blame] | 1592 | #define PFIT_ENABLE REG_BIT(31) |
| 1593 | #define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */ |
| 1594 | #define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe)) |
| 1595 | #define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */ |
| 1596 | #define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0) |
| 1597 | #define PFIT_SCALING_PROGRAMMED REG_FIELD_PREP(PFIT_SCALING_MASK, 1) |
| 1598 | #define PFIT_SCALING_PILLAR REG_FIELD_PREP(PFIT_SCALING_MASK, 2) |
| 1599 | #define PFIT_SCALING_LETTER REG_FIELD_PREP(PFIT_SCALING_MASK, 3) |
| 1600 | #define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */ |
| 1601 | #define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0) |
| 1602 | #define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1) |
| 1603 | #define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2) |
Ville Syrjälä | e27525c | 2023-04-18 20:55:19 +0300 | [diff] [blame] | 1604 | #define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */ |
| 1605 | #define PFIT_VERT_INTERP_BILINEAR REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1) |
| 1606 | #define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */ |
| 1607 | #define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */ |
| 1608 | #define PFIT_HORIZ_INTERP_BILINEAR REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1) |
| 1609 | #define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */ |
| 1610 | #define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */ |
Ville Syrjälä | 08df6d3 | 2023-04-18 20:55:18 +0300 | [diff] [blame] | 1611 | |
Jani Nikula | ed5eb1b | 2018-12-31 16:56:42 +0200 | [diff] [blame] | 1612 | #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) |
Ville Syrjälä | 08df6d3 | 2023-04-18 20:55:18 +0300 | [diff] [blame] | 1613 | #define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */ |
| 1614 | #define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x)) |
| 1615 | #define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */ |
| 1616 | #define PFIT_HORIZ_SCALE(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x)) |
| 1617 | #define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */ |
| 1618 | #define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */ |
Zhao Yakui | 3fbe18d | 2009-06-22 15:31:25 +0800 | [diff] [blame] | 1619 | |
Jani Nikula | ed5eb1b | 2018-12-31 16:56:42 +0200 | [diff] [blame] | 1620 | #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1621 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1622 | #define PCH_GTC_CTL _MMIO(0xe7000) |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 1623 | #define PCH_GTC_ENABLE (1 << 31) |
| 1624 | |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1625 | /* Display Port */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1626 | #define DP_A _MMIO(0x64000) /* eDP */ |
| 1627 | #define DP_B _MMIO(0x64100) |
| 1628 | #define DP_C _MMIO(0x64200) |
| 1629 | #define DP_D _MMIO(0x64300) |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1630 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1631 | #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) |
| 1632 | #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) |
| 1633 | #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) |
Ville Syrjälä | e66eb81 | 2015-09-18 20:03:34 +0300 | [diff] [blame] | 1634 | |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1635 | #define DP_PORT_EN (1 << 31) |
Ville Syrjälä | 59b74c4 | 2018-05-18 18:29:28 +0300 | [diff] [blame] | 1636 | #define DP_PIPE_SEL_SHIFT 30 |
| 1637 | #define DP_PIPE_SEL_MASK (1 << 30) |
| 1638 | #define DP_PIPE_SEL(pipe) ((pipe) << 30) |
| 1639 | #define DP_PIPE_SEL_SHIFT_IVB 29 |
| 1640 | #define DP_PIPE_SEL_MASK_IVB (3 << 29) |
| 1641 | #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29) |
| 1642 | #define DP_PIPE_SEL_SHIFT_CHV 16 |
| 1643 | #define DP_PIPE_SEL_MASK_CHV (3 << 16) |
| 1644 | #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16) |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1645 | |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1646 | /* Link training mode - select a suitable mode for each stage */ |
| 1647 | #define DP_LINK_TRAIN_PAT_1 (0 << 28) |
| 1648 | #define DP_LINK_TRAIN_PAT_2 (1 << 28) |
| 1649 | #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) |
| 1650 | #define DP_LINK_TRAIN_OFF (3 << 28) |
| 1651 | #define DP_LINK_TRAIN_MASK (3 << 28) |
| 1652 | #define DP_LINK_TRAIN_SHIFT 28 |
| 1653 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1654 | /* CPT Link training mode */ |
| 1655 | #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) |
| 1656 | #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) |
| 1657 | #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) |
| 1658 | #define DP_LINK_TRAIN_OFF_CPT (3 << 8) |
| 1659 | #define DP_LINK_TRAIN_MASK_CPT (7 << 8) |
| 1660 | #define DP_LINK_TRAIN_SHIFT_CPT 8 |
| 1661 | |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1662 | /* Signal voltages. These are mostly controlled by the other end */ |
| 1663 | #define DP_VOLTAGE_0_4 (0 << 25) |
| 1664 | #define DP_VOLTAGE_0_6 (1 << 25) |
| 1665 | #define DP_VOLTAGE_0_8 (2 << 25) |
| 1666 | #define DP_VOLTAGE_1_2 (3 << 25) |
| 1667 | #define DP_VOLTAGE_MASK (7 << 25) |
| 1668 | #define DP_VOLTAGE_SHIFT 25 |
| 1669 | |
| 1670 | /* Signal pre-emphasis levels, like voltages, the other end tells us what |
| 1671 | * they want |
| 1672 | */ |
| 1673 | #define DP_PRE_EMPHASIS_0 (0 << 22) |
| 1674 | #define DP_PRE_EMPHASIS_3_5 (1 << 22) |
| 1675 | #define DP_PRE_EMPHASIS_6 (2 << 22) |
| 1676 | #define DP_PRE_EMPHASIS_9_5 (3 << 22) |
| 1677 | #define DP_PRE_EMPHASIS_MASK (7 << 22) |
| 1678 | #define DP_PRE_EMPHASIS_SHIFT 22 |
| 1679 | |
| 1680 | /* How many wires to use. I guess 3 was too hard */ |
Daniel Vetter | 17aa6be | 2013-04-30 14:01:40 +0200 | [diff] [blame] | 1681 | #define DP_PORT_WIDTH(width) (((width) - 1) << 19) |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1682 | #define DP_PORT_WIDTH_MASK (7 << 19) |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 1683 | #define DP_PORT_WIDTH_SHIFT 19 |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1684 | |
| 1685 | /* Mystic DPCD version 1.1 special mode */ |
| 1686 | #define DP_ENHANCED_FRAMING (1 << 18) |
| 1687 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1688 | /* eDP */ |
| 1689 | #define DP_PLL_FREQ_270MHZ (0 << 16) |
Ville Syrjälä | b377e0d | 2015-10-29 21:25:59 +0200 | [diff] [blame] | 1690 | #define DP_PLL_FREQ_162MHZ (1 << 16) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1691 | #define DP_PLL_FREQ_MASK (3 << 16) |
| 1692 | |
Ville Syrjälä | 646b426 | 2014-04-25 20:14:30 +0300 | [diff] [blame] | 1693 | /* locked once port is enabled */ |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1694 | #define DP_PORT_REVERSAL (1 << 15) |
| 1695 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1696 | /* eDP */ |
| 1697 | #define DP_PLL_ENABLE (1 << 14) |
| 1698 | |
Ville Syrjälä | 646b426 | 2014-04-25 20:14:30 +0300 | [diff] [blame] | 1699 | /* sends the clock on lane 15 of the PEG for debug */ |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1700 | #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) |
| 1701 | |
| 1702 | #define DP_SCRAMBLING_DISABLE (1 << 12) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1703 | #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1704 | |
Ville Syrjälä | 646b426 | 2014-04-25 20:14:30 +0300 | [diff] [blame] | 1705 | /* limit RGB values to avoid confusing TVs */ |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1706 | #define DP_COLOR_RANGE_16_235 (1 << 8) |
| 1707 | |
Ville Syrjälä | 646b426 | 2014-04-25 20:14:30 +0300 | [diff] [blame] | 1708 | /* Turn on the audio link */ |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1709 | #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) |
| 1710 | |
Ville Syrjälä | 646b426 | 2014-04-25 20:14:30 +0300 | [diff] [blame] | 1711 | /* vs and hs sync polarity */ |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1712 | #define DP_SYNC_VS_HIGH (1 << 4) |
| 1713 | #define DP_SYNC_HS_HIGH (1 << 3) |
| 1714 | |
Ville Syrjälä | 646b426 | 2014-04-25 20:14:30 +0300 | [diff] [blame] | 1715 | /* A fantasy */ |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1716 | #define DP_DETECTED (1 << 2) |
| 1717 | |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1718 | /* |
| 1719 | * Computing GMCH M and N values for the Display Port link |
| 1720 | * |
| 1721 | * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes |
| 1722 | * |
| 1723 | * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) |
| 1724 | * |
| 1725 | * The GMCH value is used internally |
| 1726 | * |
| 1727 | * bytes_per_pixel is the number of bytes coming out of the plane, |
| 1728 | * which is after the LUTs, so we want the bytes for our color format. |
| 1729 | * For our current usage, this is always 3, one byte for R, G and B. |
| 1730 | */ |
Daniel Vetter | e3b95f1 | 2013-05-03 11:49:49 +0200 | [diff] [blame] | 1731 | #define _PIPEA_DATA_M_G4X 0x70050 |
| 1732 | #define _PIPEB_DATA_M_G4X 0x71050 |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1733 | |
| 1734 | /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ |
Ville Syrjälä | c65b3af | 2022-01-27 14:02:19 +0200 | [diff] [blame] | 1735 | #define TU_SIZE_MASK REG_GENMASK(30, 25) |
| 1736 | #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */ |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1737 | |
Ville Syrjälä | c65b3af | 2022-01-27 14:02:19 +0200 | [diff] [blame] | 1738 | #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0) |
Ville Syrjälä | a65851a | 2013-04-23 15:03:34 +0300 | [diff] [blame] | 1739 | #define DATA_LINK_N_MAX (0x800000) |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1740 | |
Daniel Vetter | e3b95f1 | 2013-05-03 11:49:49 +0200 | [diff] [blame] | 1741 | #define _PIPEA_DATA_N_G4X 0x70054 |
| 1742 | #define _PIPEB_DATA_N_G4X 0x71054 |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1743 | |
| 1744 | /* |
| 1745 | * Computing Link M and N values for the Display Port link |
| 1746 | * |
| 1747 | * Link M / N = pixel_clock / ls_clk |
| 1748 | * |
| 1749 | * (the DP spec calls pixel_clock the 'strm_clk') |
| 1750 | * |
| 1751 | * The Link value is transmitted in the Main Stream |
| 1752 | * Attributes and VB-ID. |
| 1753 | */ |
| 1754 | |
Daniel Vetter | e3b95f1 | 2013-05-03 11:49:49 +0200 | [diff] [blame] | 1755 | #define _PIPEA_LINK_M_G4X 0x70060 |
| 1756 | #define _PIPEB_LINK_M_G4X 0x71060 |
Daniel Vetter | e3b95f1 | 2013-05-03 11:49:49 +0200 | [diff] [blame] | 1757 | #define _PIPEA_LINK_N_G4X 0x70064 |
| 1758 | #define _PIPEB_LINK_N_G4X 0x71064 |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1759 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1760 | #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) |
| 1761 | #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) |
| 1762 | #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) |
| 1763 | #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1764 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1765 | /* Display & cursor control */ |
| 1766 | |
| 1767 | /* Pipe A */ |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 1768 | #define _PIPEADSL 0x70000 |
Ville Syrjälä | 96e4c3c | 2021-11-12 21:38:05 +0200 | [diff] [blame] | 1769 | #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */ |
| 1770 | #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0) |
Ville Syrjälä | 3eb08ea | 2023-02-14 00:52:50 +0200 | [diff] [blame] | 1771 | #define _TRANSACONF 0x70008 |
| 1772 | #define TRANSCONF_ENABLE REG_BIT(31) |
| 1773 | #define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */ |
| 1774 | #define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */ |
| 1775 | #define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */ |
| 1776 | #define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */ |
| 1777 | #define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */ |
| 1778 | #define TRANSCONF_PIPE_LOCKED REG_BIT(25) |
| 1779 | #define TRANSCONF_FORCE_BORDER REG_BIT(25) |
| 1780 | #define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */ |
| 1781 | #define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */ |
| 1782 | #define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0) |
| 1783 | #define TRANSCONF_GAMMA_MODE_10BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1) |
| 1784 | #define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */ |
| 1785 | #define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */ |
| 1786 | #define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */ |
| 1787 | #define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */ |
| 1788 | #define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0) |
| 1789 | #define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */ |
| 1790 | #define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */ |
| 1791 | #define TRANSCONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6) |
| 1792 | #define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */ |
Ville Syrjälä | 6a6d914 | 2021-11-12 21:38:08 +0200 | [diff] [blame] | 1793 | /* |
| 1794 | * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display, |
| 1795 | * DBL=power saving pixel doubling, PF-ID* requires panel fitter |
| 1796 | */ |
Ville Syrjälä | 3eb08ea | 2023-02-14 00:52:50 +0200 | [diff] [blame] | 1797 | #define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */ |
| 1798 | #define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */ |
| 1799 | #define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0) |
| 1800 | #define TRANSCONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1) |
| 1801 | #define TRANSCONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3) |
| 1802 | #define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */ |
| 1803 | #define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */ |
| 1804 | #define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20) |
| 1805 | #define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */ |
| 1806 | #define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x)) |
| 1807 | #define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16) |
Ville Syrjälä | 47d56ca | 2023-04-13 19:49:14 +0300 | [diff] [blame] | 1808 | #define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */ |
Ville Syrjälä | 3eb08ea | 2023-02-14 00:52:50 +0200 | [diff] [blame] | 1809 | #define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14) |
| 1810 | #define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13) |
| 1811 | #define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */ |
| 1812 | #define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */ |
| 1813 | #define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */ |
| 1814 | #define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */ |
| 1815 | #define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */ |
| 1816 | #define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */ |
| 1817 | #define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0) |
| 1818 | #define TRANSCONF_BPC_10 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1) |
| 1819 | #define TRANSCONF_BPC_6 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2) |
| 1820 | #define TRANSCONF_BPC_12 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3) |
| 1821 | #define TRANSCONF_DITHER_EN REG_BIT(4) |
| 1822 | #define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2) |
| 1823 | #define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0) |
| 1824 | #define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1) |
| 1825 | #define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2) |
| 1826 | #define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3) |
Imre Deak | 377cc98 | 2024-01-29 19:55:31 +0200 | [diff] [blame] | 1827 | #define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0) |
| 1828 | #define TRANSCONF_PIXEL_COUNT_SCALING_X4 1 |
| 1829 | |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 1830 | #define _PIPEASTAT 0x70024 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 1831 | #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) |
| 1832 | #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) |
| 1833 | #define PIPE_CRC_ERROR_ENABLE (1UL << 29) |
| 1834 | #define PIPE_CRC_DONE_ENABLE (1UL << 28) |
| 1835 | #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) |
| 1836 | #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) |
| 1837 | #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) |
| 1838 | #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) |
| 1839 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) |
| 1840 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) |
| 1841 | #define PIPE_DPST_EVENT_ENABLE (1UL << 23) |
| 1842 | #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) |
| 1843 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) |
| 1844 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) |
| 1845 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) |
| 1846 | #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) |
| 1847 | #define PERF_COUNTER_INTERRUPT_EN (1UL << 19) |
| 1848 | #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ |
| 1849 | #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ |
| 1850 | #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) |
| 1851 | #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) |
| 1852 | #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) |
| 1853 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) |
| 1854 | #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) |
| 1855 | #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) |
| 1856 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) |
| 1857 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) |
| 1858 | #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) |
| 1859 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) |
| 1860 | #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) |
| 1861 | #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) |
| 1862 | #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) |
| 1863 | #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) |
| 1864 | #define PIPE_DPST_EVENT_STATUS (1UL << 7) |
| 1865 | #define PIPE_A_PSR_STATUS_VLV (1UL << 6) |
| 1866 | #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) |
| 1867 | #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) |
| 1868 | #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) |
| 1869 | #define PIPE_B_PSR_STATUS_VLV (1UL << 3) |
| 1870 | #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) |
| 1871 | #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ |
| 1872 | #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ |
| 1873 | #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) |
| 1874 | #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) |
| 1875 | #define PIPE_HBLANK_INT_STATUS (1UL << 0) |
| 1876 | #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1877 | |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 1878 | #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 |
| 1879 | #define PIPESTAT_INT_STATUS_MASK 0x0000ffff |
| 1880 | |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 1881 | #define TRANSCONF(trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF) |
| 1882 | #define PIPEDSL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL) |
| 1883 | #define PIPEFRAME(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH) |
| 1884 | #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL) |
| 1885 | #define PIPESTAT(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1886 | |
Ville Syrjälä | e262568 | 2019-04-01 23:02:29 +0300 | [diff] [blame] | 1887 | #define _PIPEAGCMAX 0x70010 |
| 1888 | #define _PIPEBGCMAX 0x71010 |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 1889 | #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ |
Ville Syrjälä | e262568 | 2019-04-01 23:02:29 +0300 | [diff] [blame] | 1890 | |
Ville Syrjälä | 0b86952 | 2021-05-26 20:36:00 +0300 | [diff] [blame] | 1891 | #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 1892 | #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A) |
Ville Syrjälä | 0b86952 | 2021-05-26 20:36:00 +0300 | [diff] [blame] | 1893 | #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13) |
| 1894 | |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 1895 | #define _PIPE_MISC_A 0x70030 |
| 1896 | #define _PIPE_MISC_B 0x71030 |
Ville Syrjälä | c640f6c | 2023-03-14 15:02:48 +0200 | [diff] [blame] | 1897 | #define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */ |
| 1898 | #define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */ |
| 1899 | #define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */ |
Ville Syrjälä | 2590ef9 | 2023-04-11 22:14:26 +0300 | [diff] [blame] | 1900 | #define PIPE_MISC_PSR_MASK_PRIMARY_FLIP REG_BIT(23) /* bdw */ |
| 1901 | #define PIPE_MISC_PSR_MASK_SPRITE_ENABLE REG_BIT(22) /* bdw */ |
| 1902 | #define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE REG_BIT(21) /* skl+ */ |
| 1903 | #define PIPE_MISC_PSR_MASK_CURSOR_MOVE REG_BIT(21) /* bdw */ |
| 1904 | #define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT REG_BIT(20) |
Ville Syrjälä | c640f6c | 2023-03-14 15:02:48 +0200 | [diff] [blame] | 1905 | #define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11) |
Ville Syrjälä | 3d0d333 | 2023-04-11 22:14:22 +0300 | [diff] [blame] | 1906 | #define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ |
Ankit Nautiyal | 70418a6 | 2021-08-11 10:48:57 +0530 | [diff] [blame] | 1907 | /* |
| 1908 | * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with |
| 1909 | * valid values of: 6, 8, 10 BPC. |
| 1910 | * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of: |
| 1911 | * 6, 8, 10, 12 BPC. |
| 1912 | */ |
Ville Syrjälä | c640f6c | 2023-03-14 15:02:48 +0200 | [diff] [blame] | 1913 | #define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5) |
| 1914 | #define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0) |
| 1915 | #define PIPE_MISC_BPC_10 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1) |
| 1916 | #define PIPE_MISC_BPC_6 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2) |
| 1917 | #define PIPE_MISC_BPC_12_ADLP REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */ |
| 1918 | #define PIPE_MISC_DITHER_ENABLE REG_BIT(4) |
| 1919 | #define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2) |
| 1920 | #define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0) |
| 1921 | #define PIPE_MISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1) |
| 1922 | #define PIPE_MISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2) |
| 1923 | #define PIPE_MISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3) |
| 1924 | #define PIPE_MISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B) |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 1925 | |
Anusha Srivatsa | e2ca757 | 2021-05-18 17:06:24 -0700 | [diff] [blame] | 1926 | #define _PIPE_MISC2_A 0x7002C |
| 1927 | #define _PIPE_MISC2_B 0x7102C |
Ville Syrjälä | d083c23 | 2021-11-12 21:38:06 +0200 | [diff] [blame] | 1928 | #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24) |
| 1929 | #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80) |
| 1930 | #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20) |
Ville Syrjälä | 6e889b1 | 2023-03-14 15:02:49 +0200 | [diff] [blame] | 1931 | #define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */ |
| 1932 | #define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id)) |
Ville Syrjälä | 14c7b24 | 2023-03-14 15:02:47 +0200 | [diff] [blame] | 1933 | #define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B) |
Anusha Srivatsa | e2ca757 | 2021-05-18 17:06:24 -0700 | [diff] [blame] | 1934 | |
Matt Roper | 8bcc084 | 2021-05-25 17:06:54 -0700 | [diff] [blame] | 1935 | #define _ICL_PIPE_A_STATUS 0x70058 |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 1936 | #define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(dev_priv, pipe, _ICL_PIPE_A_STATUS) |
Matt Roper | 8bcc084 | 2021-05-25 17:06:54 -0700 | [diff] [blame] | 1937 | #define PIPE_STATUS_UNDERRUN REG_BIT(31) |
| 1938 | #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28) |
| 1939 | #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27) |
| 1940 | #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26) |
| 1941 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1942 | #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) |
Ville Syrjälä | 7d938bc | 2021-11-12 21:38:12 +0200 | [diff] [blame] | 1943 | #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29) |
| 1944 | #define PIPEB_HLINE_INT_EN REG_BIT(28) |
| 1945 | #define PIPEB_VBLANK_INT_EN REG_BIT(27) |
| 1946 | #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26) |
| 1947 | #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25) |
| 1948 | #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24) |
| 1949 | #define PIPE_PSR_INT_EN REG_BIT(22) |
| 1950 | #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21) |
| 1951 | #define PIPEA_HLINE_INT_EN REG_BIT(20) |
| 1952 | #define PIPEA_VBLANK_INT_EN REG_BIT(19) |
| 1953 | #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18) |
| 1954 | #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17) |
| 1955 | #define PLANEA_FLIPDONE_INT_EN REG_BIT(16) |
| 1956 | #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13) |
| 1957 | #define PIPEC_HLINE_INT_EN REG_BIT(12) |
| 1958 | #define PIPEC_VBLANK_INT_EN REG_BIT(11) |
| 1959 | #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10) |
| 1960 | #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9) |
| 1961 | #define PLANEC_FLIPDONE_INT_EN REG_BIT(8) |
Jesse Barnes | c46ce4d | 2012-03-28 13:39:24 -0700 | [diff] [blame] | 1962 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1963 | #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ |
Ville Syrjälä | 7d938bc | 2021-11-12 21:38:12 +0200 | [diff] [blame] | 1964 | #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16) |
| 1965 | #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16) |
| 1966 | #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27) |
| 1967 | #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26) |
| 1968 | #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25) |
| 1969 | #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24) |
| 1970 | #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23) |
| 1971 | #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22) |
| 1972 | #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21) |
| 1973 | #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20) |
| 1974 | #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19) |
| 1975 | #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18) |
| 1976 | #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17) |
| 1977 | #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16) |
| 1978 | #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0) |
| 1979 | #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0) |
| 1980 | #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11) |
| 1981 | #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10) |
| 1982 | #define PLANEC_INVALID_GTT_STATUS REG_BIT(9) |
| 1983 | #define CURSORC_INVALID_GTT_STATUS REG_BIT(8) |
| 1984 | #define CURSORB_INVALID_GTT_STATUS REG_BIT(7) |
| 1985 | #define CURSORA_INVALID_GTT_STATUS REG_BIT(6) |
| 1986 | #define SPRITED_INVALID_GTT_STATUS REG_BIT(5) |
| 1987 | #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4) |
| 1988 | #define PLANEB_INVALID_GTT_STATUS REG_BIT(3) |
| 1989 | #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2) |
| 1990 | #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1) |
| 1991 | #define PLANEA_INVALID_GTT_STATUS REG_BIT(0) |
Jesse Barnes | c46ce4d | 2012-03-28 13:39:24 -0700 | [diff] [blame] | 1992 | |
Jani Nikula | ed5eb1b | 2018-12-31 16:56:42 +0200 | [diff] [blame] | 1993 | #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1994 | #define DSPARB_CSTART_MASK (0x7f << 7) |
| 1995 | #define DSPARB_CSTART_SHIFT 7 |
| 1996 | #define DSPARB_BSTART_MASK (0x7f) |
| 1997 | #define DSPARB_BSTART_SHIFT 0 |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 1998 | #define DSPARB_BEND_SHIFT 9 /* on 855 */ |
| 1999 | #define DSPARB_AEND_SHIFT 0 |
Ville Syrjälä | 54f1b6e | 2015-06-24 22:00:05 +0300 | [diff] [blame] | 2000 | #define DSPARB_SPRITEA_SHIFT_VLV 0 |
| 2001 | #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) |
| 2002 | #define DSPARB_SPRITEB_SHIFT_VLV 8 |
| 2003 | #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) |
| 2004 | #define DSPARB_SPRITEC_SHIFT_VLV 16 |
| 2005 | #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) |
| 2006 | #define DSPARB_SPRITED_SHIFT_VLV 24 |
| 2007 | #define DSPARB_SPRITED_MASK_VLV (0xff << 24) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2008 | #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ |
Ville Syrjälä | 54f1b6e | 2015-06-24 22:00:05 +0300 | [diff] [blame] | 2009 | #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 |
| 2010 | #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) |
| 2011 | #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 |
| 2012 | #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) |
| 2013 | #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 |
| 2014 | #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) |
| 2015 | #define DSPARB_SPRITED_HI_SHIFT_VLV 12 |
| 2016 | #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) |
| 2017 | #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 |
| 2018 | #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) |
| 2019 | #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 |
| 2020 | #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2021 | #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ |
Ville Syrjälä | 54f1b6e | 2015-06-24 22:00:05 +0300 | [diff] [blame] | 2022 | #define DSPARB_SPRITEE_SHIFT_VLV 0 |
| 2023 | #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) |
| 2024 | #define DSPARB_SPRITEF_SHIFT_VLV 8 |
| 2025 | #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) |
Ville Syrjälä | b500472 | 2015-03-05 21:19:47 +0200 | [diff] [blame] | 2026 | |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2027 | /* pnv/gen4/g4x/vlv/chv */ |
Jani Nikula | ed5eb1b | 2018-12-31 16:56:42 +0200 | [diff] [blame] | 2028 | #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2029 | #define DSPFW_SR_SHIFT 23 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2030 | #define DSPFW_SR_MASK (0x1ff << 23) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2031 | #define DSPFW_CURSORB_SHIFT 16 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2032 | #define DSPFW_CURSORB_MASK (0x3f << 16) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2033 | #define DSPFW_PLANEB_SHIFT 8 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2034 | #define DSPFW_PLANEB_MASK (0x7f << 8) |
| 2035 | #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */ |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2036 | #define DSPFW_PLANEA_SHIFT 0 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2037 | #define DSPFW_PLANEA_MASK (0x7f << 0) |
| 2038 | #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ |
Jani Nikula | ed5eb1b | 2018-12-31 16:56:42 +0200 | [diff] [blame] | 2039 | #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2040 | #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2041 | #define DSPFW_FBC_SR_SHIFT 28 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2042 | #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2043 | #define DSPFW_FBC_HPLL_SR_SHIFT 24 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2044 | #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */ |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2045 | #define DSPFW_SPRITEB_SHIFT (16) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2046 | #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */ |
| 2047 | #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */ |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2048 | #define DSPFW_CURSORA_SHIFT 8 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2049 | #define DSPFW_CURSORA_MASK (0x3f << 8) |
Ville Syrjälä | f499896 | 2015-03-10 17:02:21 +0200 | [diff] [blame] | 2050 | #define DSPFW_PLANEC_OLD_SHIFT 0 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2051 | #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */ |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2052 | #define DSPFW_SPRITEA_SHIFT 0 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2053 | #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ |
| 2054 | #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ |
Jani Nikula | ed5eb1b | 2018-12-31 16:56:42 +0200 | [diff] [blame] | 2055 | #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2056 | #define DSPFW_HPLL_SR_EN (1 << 31) |
| 2057 | #define PINEVIEW_SELF_REFRESH_EN (1 << 30) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2058 | #define DSPFW_CURSOR_SR_SHIFT 24 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2059 | #define DSPFW_CURSOR_SR_MASK (0x3f << 24) |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 2060 | #define DSPFW_HPLL_CURSOR_SHIFT 16 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2061 | #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2062 | #define DSPFW_HPLL_SR_SHIFT 0 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2063 | #define DSPFW_HPLL_SR_MASK (0x1ff << 0) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2064 | |
| 2065 | /* vlv/chv */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2066 | #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2067 | #define DSPFW_SPRITEB_WM1_SHIFT 16 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2068 | #define DSPFW_SPRITEB_WM1_MASK (0xff << 16) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2069 | #define DSPFW_CURSORA_WM1_SHIFT 8 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2070 | #define DSPFW_CURSORA_WM1_MASK (0x3f << 8) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2071 | #define DSPFW_SPRITEA_WM1_SHIFT 0 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2072 | #define DSPFW_SPRITEA_WM1_MASK (0xff << 0) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2073 | #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2074 | #define DSPFW_PLANEB_WM1_SHIFT 24 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2075 | #define DSPFW_PLANEB_WM1_MASK (0xff << 24) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2076 | #define DSPFW_PLANEA_WM1_SHIFT 16 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2077 | #define DSPFW_PLANEA_WM1_MASK (0xff << 16) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2078 | #define DSPFW_CURSORB_WM1_SHIFT 8 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2079 | #define DSPFW_CURSORB_WM1_MASK (0x3f << 8) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2080 | #define DSPFW_CURSOR_SR_WM1_SHIFT 0 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2081 | #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2082 | #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2083 | #define DSPFW_SR_WM1_SHIFT 0 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2084 | #define DSPFW_SR_WM1_MASK (0x1ff << 0) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2085 | #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) |
| 2086 | #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2087 | #define DSPFW_SPRITED_WM1_SHIFT 24 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2088 | #define DSPFW_SPRITED_WM1_MASK (0xff << 24) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2089 | #define DSPFW_SPRITED_SHIFT 16 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2090 | #define DSPFW_SPRITED_MASK_VLV (0xff << 16) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2091 | #define DSPFW_SPRITEC_WM1_SHIFT 8 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2092 | #define DSPFW_SPRITEC_WM1_MASK (0xff << 8) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2093 | #define DSPFW_SPRITEC_SHIFT 0 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2094 | #define DSPFW_SPRITEC_MASK_VLV (0xff << 0) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2095 | #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2096 | #define DSPFW_SPRITEF_WM1_SHIFT 24 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2097 | #define DSPFW_SPRITEF_WM1_MASK (0xff << 24) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2098 | #define DSPFW_SPRITEF_SHIFT 16 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2099 | #define DSPFW_SPRITEF_MASK_VLV (0xff << 16) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2100 | #define DSPFW_SPRITEE_WM1_SHIFT 8 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2101 | #define DSPFW_SPRITEE_WM1_MASK (0xff << 8) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2102 | #define DSPFW_SPRITEE_SHIFT 0 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2103 | #define DSPFW_SPRITEE_MASK_VLV (0xff << 0) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2104 | #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2105 | #define DSPFW_PLANEC_WM1_SHIFT 24 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2106 | #define DSPFW_PLANEC_WM1_MASK (0xff << 24) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2107 | #define DSPFW_PLANEC_SHIFT 16 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2108 | #define DSPFW_PLANEC_MASK_VLV (0xff << 16) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2109 | #define DSPFW_CURSORC_WM1_SHIFT 8 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2110 | #define DSPFW_CURSORC_WM1_MASK (0x3f << 16) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2111 | #define DSPFW_CURSORC_SHIFT 0 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2112 | #define DSPFW_CURSORC_MASK (0x3f << 0) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2113 | |
| 2114 | /* vlv/chv high order bits */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2115 | #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2116 | #define DSPFW_SR_HI_SHIFT 24 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2117 | #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2118 | #define DSPFW_SPRITEF_HI_SHIFT 23 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2119 | #define DSPFW_SPRITEF_HI_MASK (1 << 23) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2120 | #define DSPFW_SPRITEE_HI_SHIFT 22 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2121 | #define DSPFW_SPRITEE_HI_MASK (1 << 22) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2122 | #define DSPFW_PLANEC_HI_SHIFT 21 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2123 | #define DSPFW_PLANEC_HI_MASK (1 << 21) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2124 | #define DSPFW_SPRITED_HI_SHIFT 20 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2125 | #define DSPFW_SPRITED_HI_MASK (1 << 20) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2126 | #define DSPFW_SPRITEC_HI_SHIFT 16 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2127 | #define DSPFW_SPRITEC_HI_MASK (1 << 16) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2128 | #define DSPFW_PLANEB_HI_SHIFT 12 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2129 | #define DSPFW_PLANEB_HI_MASK (1 << 12) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2130 | #define DSPFW_SPRITEB_HI_SHIFT 8 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2131 | #define DSPFW_SPRITEB_HI_MASK (1 << 8) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2132 | #define DSPFW_SPRITEA_HI_SHIFT 4 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2133 | #define DSPFW_SPRITEA_HI_MASK (1 << 4) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2134 | #define DSPFW_PLANEA_HI_SHIFT 0 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2135 | #define DSPFW_PLANEA_HI_MASK (1 << 0) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2136 | #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2137 | #define DSPFW_SR_WM1_HI_SHIFT 24 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2138 | #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2139 | #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2140 | #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2141 | #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2142 | #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2143 | #define DSPFW_PLANEC_WM1_HI_SHIFT 21 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2144 | #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2145 | #define DSPFW_SPRITED_WM1_HI_SHIFT 20 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2146 | #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2147 | #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2148 | #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2149 | #define DSPFW_PLANEB_WM1_HI_SHIFT 12 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2150 | #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2151 | #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2152 | #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2153 | #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2154 | #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4) |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 2155 | #define DSPFW_PLANEA_WM1_HI_SHIFT 0 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2156 | #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2157 | |
Gajanan Bhat | 12a3c05 | 2012-03-28 13:39:30 -0700 | [diff] [blame] | 2158 | /* drain latency register values*/ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2159 | #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) |
Ville Syrjälä | 1abc4dc | 2014-06-26 17:02:37 +0300 | [diff] [blame] | 2160 | #define DDL_CURSOR_SHIFT 24 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2161 | #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite)) |
Ville Syrjälä | 1abc4dc | 2014-06-26 17:02:37 +0300 | [diff] [blame] | 2162 | #define DDL_PLANE_SHIFT 0 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2163 | #define DDL_PRECISION_HIGH (1 << 7) |
| 2164 | #define DDL_PRECISION_LOW (0 << 7) |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 2165 | #define DRAIN_LATENCY_MASK 0x7f |
Gajanan Bhat | 12a3c05 | 2012-03-28 13:39:30 -0700 | [diff] [blame] | 2166 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2167 | #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2168 | #define CBR_PND_DEADLINE_DISABLE (1 << 31) |
| 2169 | #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) |
Ville Syrjälä | c6beb13 | 2015-03-05 21:19:48 +0200 | [diff] [blame] | 2170 | |
Ville Syrjälä | c231775 | 2016-03-15 16:39:56 +0200 | [diff] [blame] | 2171 | #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 2172 | #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ |
Ville Syrjälä | c231775 | 2016-03-15 16:39:56 +0200 | [diff] [blame] | 2173 | |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2174 | /* FIFO watermark sizes etc */ |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2175 | #define G4X_FIFO_LINE_SIZE 64 |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2176 | #define I915_FIFO_LINE_SIZE 64 |
| 2177 | #define I830_FIFO_LINE_SIZE 32 |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2178 | |
Jesse Barnes | ceb0424 | 2012-03-28 13:39:22 -0700 | [diff] [blame] | 2179 | #define VALLEYVIEW_FIFO_SIZE 255 |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2180 | #define G4X_FIFO_SIZE 127 |
Zhao Yakui | 1b07e04 | 2010-06-12 14:32:24 +0800 | [diff] [blame] | 2181 | #define I965_FIFO_SIZE 512 |
| 2182 | #define I945_FIFO_SIZE 127 |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2183 | #define I915_FIFO_SIZE 95 |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2184 | #define I855GM_FIFO_SIZE 127 /* In cachelines */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2185 | #define I830_FIFO_SIZE 95 |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2186 | |
Jesse Barnes | ceb0424 | 2012-03-28 13:39:22 -0700 | [diff] [blame] | 2187 | #define VALLEYVIEW_MAX_WM 0xff |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2188 | #define G4X_MAX_WM 0x3f |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2189 | #define I915_MAX_WM 0x3f |
| 2190 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2191 | #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ |
| 2192 | #define PINEVIEW_FIFO_LINE_SIZE 64 |
| 2193 | #define PINEVIEW_MAX_WM 0x1ff |
| 2194 | #define PINEVIEW_DFT_WM 0x3f |
| 2195 | #define PINEVIEW_DFT_HPLLOFF_WM 0 |
| 2196 | #define PINEVIEW_GUARD_WM 10 |
| 2197 | #define PINEVIEW_CURSOR_FIFO 64 |
| 2198 | #define PINEVIEW_CURSOR_MAX_WM 0x3f |
| 2199 | #define PINEVIEW_CURSOR_DFT_WM 0 |
| 2200 | #define PINEVIEW_CURSOR_GUARD_WM 5 |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2201 | |
Jesse Barnes | ceb0424 | 2012-03-28 13:39:22 -0700 | [diff] [blame] | 2202 | #define VALLEYVIEW_CURSOR_MAX_WM 64 |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 2203 | #define I965_CURSOR_FIFO 64 |
| 2204 | #define I965_CURSOR_MAX_WM 32 |
| 2205 | #define I965_CURSOR_DFT_WM 8 |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 2206 | |
| 2207 | /* define the Watermark register on Ironlake */ |
Ville Syrjälä | 96eaeb3d | 2018-12-12 23:17:38 +0200 | [diff] [blame] | 2208 | #define _WM0_PIPEA_ILK 0x45100 |
| 2209 | #define _WM0_PIPEB_ILK 0x45104 |
| 2210 | #define _WM0_PIPEC_IVB 0x45200 |
Jani Nikula | 7322aed | 2024-04-23 19:44:59 +0300 | [diff] [blame] | 2211 | #define WM0_PIPE_ILK(pipe) _MMIO_BASE_PIPE3(0, (pipe), _WM0_PIPEA_ILK, \ |
| 2212 | _WM0_PIPEB_ILK, _WM0_PIPEC_IVB) |
Ville Syrjälä | 7f088be | 2022-02-17 01:28:06 +0200 | [diff] [blame] | 2213 | #define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16) |
| 2214 | #define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8) |
| 2215 | #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0) |
| 2216 | #define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x)) |
| 2217 | #define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x)) |
| 2218 | #define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x)) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2219 | #define WM1_LP_ILK _MMIO(0x45108) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2220 | #define WM2_LP_ILK _MMIO(0x4510c) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2221 | #define WM3_LP_ILK _MMIO(0x45110) |
Ville Syrjälä | 7f088be | 2022-02-17 01:28:06 +0200 | [diff] [blame] | 2222 | #define WM_LP_ENABLE REG_BIT(31) |
| 2223 | #define WM_LP_LATENCY_MASK REG_GENMASK(30, 24) |
| 2224 | #define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19) |
| 2225 | #define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20) |
| 2226 | #define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8) |
| 2227 | #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0) |
| 2228 | #define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x)) |
| 2229 | #define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x)) |
| 2230 | #define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x)) |
| 2231 | #define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x)) |
| 2232 | #define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x)) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2233 | #define WM1S_LP_ILK _MMIO(0x45120) |
| 2234 | #define WM2S_LP_IVB _MMIO(0x45124) |
| 2235 | #define WM3S_LP_IVB _MMIO(0x45128) |
Ville Syrjälä | 7f088be | 2022-02-17 01:28:06 +0200 | [diff] [blame] | 2236 | #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */ |
| 2237 | #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0) |
| 2238 | #define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x)) |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2239 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2240 | /* |
| 2241 | * The two pipe frame counter registers are not synchronized, so |
| 2242 | * reading a stable value is somewhat tricky. The following code |
| 2243 | * should work: |
| 2244 | * |
| 2245 | * do { |
| 2246 | * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> |
| 2247 | * PIPE_FRAME_HIGH_SHIFT; |
| 2248 | * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> |
| 2249 | * PIPE_FRAME_LOW_SHIFT); |
| 2250 | * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> |
| 2251 | * PIPE_FRAME_HIGH_SHIFT); |
| 2252 | * } while (high1 != high2); |
| 2253 | * frame = (high1 << 8) | low1; |
| 2254 | */ |
Ville Syrjälä | 25a2e2d | 2013-10-11 22:24:41 +0300 | [diff] [blame] | 2255 | #define _PIPEAFRAMEHIGH 0x70040 |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2256 | #define PIPE_FRAME_HIGH_MASK 0x0000ffff |
| 2257 | #define PIPE_FRAME_HIGH_SHIFT 0 |
Ville Syrjälä | 25a2e2d | 2013-10-11 22:24:41 +0300 | [diff] [blame] | 2258 | #define _PIPEAFRAMEPIXEL 0x70044 |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2259 | #define PIPE_FRAME_LOW_MASK 0xff000000 |
| 2260 | #define PIPE_FRAME_LOW_SHIFT 24 |
| 2261 | #define PIPE_PIXEL_MASK 0x00ffffff |
| 2262 | #define PIPE_PIXEL_SHIFT 0 |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 2263 | /* GM45+ just has to be different */ |
Ville Syrjälä | fd8f507c | 2015-09-18 20:03:42 +0300 | [diff] [blame] | 2264 | #define _PIPEA_FRMCOUNT_G4X 0x70040 |
| 2265 | #define _PIPEA_FLIPCOUNT_G4X 0x70044 |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 2266 | #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X) |
| 2267 | #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2268 | |
| 2269 | /* Cursor A & B regs */ |
Ville Syrjälä | 5efb3e28 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 2270 | #define _CURACNTR 0x70080 |
Jesse Barnes | 14b60391 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 2271 | /* Old style CUR*CNTR flags (desktop 8xx) */ |
Ville Syrjälä | 348abd4 | 2021-12-01 17:25:49 +0200 | [diff] [blame] | 2272 | #define CURSOR_ENABLE REG_BIT(31) |
| 2273 | #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) |
| 2274 | #define CURSOR_STRIDE_MASK REG_GENMASK(29, 28) |
| 2275 | #define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */ |
| 2276 | #define CURSOR_FORMAT_MASK REG_GENMASK(26, 24) |
| 2277 | #define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0) |
| 2278 | #define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1) |
| 2279 | #define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2) |
| 2280 | #define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4) |
| 2281 | #define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5) |
Jesse Barnes | 14b60391 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 2282 | /* New style CUR*CNTR flags */ |
Ville Syrjälä | 0b86952 | 2021-05-26 20:36:00 +0300 | [diff] [blame] | 2283 | #define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ |
| 2284 | #define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */ |
Ville Syrjälä | 348abd4 | 2021-12-01 17:25:49 +0200 | [diff] [blame] | 2285 | #define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28) |
| 2286 | #define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe)) |
| 2287 | #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26) |
| 2288 | #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ |
| 2289 | #define MCURSOR_ROTATE_180 REG_BIT(15) |
| 2290 | #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14) |
| 2291 | #define MCURSOR_MODE_MASK 0x27 |
| 2292 | #define MCURSOR_MODE_DISABLE 0x00 |
| 2293 | #define MCURSOR_MODE_128_32B_AX 0x02 |
| 2294 | #define MCURSOR_MODE_256_32B_AX 0x03 |
Jouni Högander | b6cc0b9 | 2024-03-19 14:33:26 +0200 | [diff] [blame] | 2295 | #define MCURSOR_MODE_64_2B 0x04 |
Ville Syrjälä | 348abd4 | 2021-12-01 17:25:49 +0200 | [diff] [blame] | 2296 | #define MCURSOR_MODE_64_32B_AX 0x07 |
| 2297 | #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) |
| 2298 | #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) |
| 2299 | #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX) |
Ville Syrjälä | 5efb3e28 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 2300 | #define _CURABASE 0x70084 |
| 2301 | #define _CURAPOS 0x70088 |
Jouni Högander | 7f85883 | 2023-12-18 19:50:01 +0200 | [diff] [blame] | 2302 | #define _CURAPOS_ERLY_TPT 0x7008c |
Ville Syrjälä | 348abd4 | 2021-12-01 17:25:49 +0200 | [diff] [blame] | 2303 | #define CURSOR_POS_Y_SIGN REG_BIT(31) |
| 2304 | #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16) |
| 2305 | #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) |
| 2306 | #define CURSOR_POS_X_SIGN REG_BIT(15) |
| 2307 | #define CURSOR_POS_X_MASK REG_GENMASK(14, 0) |
| 2308 | #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) |
| 2309 | #define _CURASIZE 0x700a0 /* 845/865 */ |
| 2310 | #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) |
| 2311 | #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) |
| 2312 | #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0) |
| 2313 | #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) |
Ville Syrjälä | 024faac | 2017-03-27 21:55:42 +0300 | [diff] [blame] | 2314 | #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ |
Ville Syrjälä | 348abd4 | 2021-12-01 17:25:49 +0200 | [diff] [blame] | 2315 | #define CUR_FBC_EN REG_BIT(31) |
| 2316 | #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) |
| 2317 | #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) |
Ville Syrjälä | 1119f00 | 2023-03-29 22:04:45 +0300 | [diff] [blame] | 2318 | #define _CUR_CHICKEN_A 0x700a4 /* mtl+ */ |
Rodrigo Vivi | a8ada06 | 2018-03-12 14:05:28 -0700 | [diff] [blame] | 2319 | #define _CURASURFLIVE 0x700ac /* g4x+ */ |
Ville Syrjälä | 5efb3e28 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 2320 | #define _CURBCNTR 0x700c0 |
| 2321 | #define _CURBBASE 0x700c4 |
| 2322 | #define _CURBPOS 0x700c8 |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2323 | |
Jesse Barnes | 65a21cd | 2011-10-12 11:10:21 -0700 | [diff] [blame] | 2324 | #define _CURBCNTR_IVB 0x71080 |
| 2325 | #define _CURBBASE_IVB 0x71084 |
| 2326 | #define _CURBPOS_IVB 0x71088 |
| 2327 | |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 2328 | #define CURCNTR(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR) |
| 2329 | #define CURBASE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE) |
| 2330 | #define CURPOS(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS) |
| 2331 | #define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT) |
| 2332 | #define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) |
| 2333 | #define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A) |
| 2334 | #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A) |
| 2335 | #define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE) |
Ville Syrjälä | 5efb3e28 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 2336 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2337 | /* Display A control */ |
Ville Syrjälä | 6ede6b06 | 2021-01-11 18:37:11 +0200 | [diff] [blame] | 2338 | #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 2339 | #define _DSPACNTR 0x70180 |
Ville Syrjälä | 428cb15 | 2022-01-21 13:30:31 +0200 | [diff] [blame] | 2340 | #define DISP_ENABLE REG_BIT(31) |
| 2341 | #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) |
| 2342 | #define DISP_FORMAT_MASK REG_GENMASK(29, 26) |
| 2343 | #define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2) |
| 2344 | #define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3) |
| 2345 | #define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4) |
| 2346 | #define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5) |
| 2347 | #define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6) |
| 2348 | #define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7) |
| 2349 | #define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8) |
| 2350 | #define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9) |
| 2351 | #define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10) |
| 2352 | #define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11) |
| 2353 | #define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12) |
| 2354 | #define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14) |
| 2355 | #define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15) |
| 2356 | #define DISP_STEREO_ENABLE REG_BIT(25) |
| 2357 | #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ |
| 2358 | #define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24) |
| 2359 | #define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe)) |
| 2360 | #define DISP_SRC_KEY_ENABLE REG_BIT(22) |
| 2361 | #define DISP_LINE_DOUBLE REG_BIT(20) |
| 2362 | #define DISP_STEREO_POLARITY_SECOND REG_BIT(18) |
| 2363 | #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ |
| 2364 | #define DISP_ROTATE_180 REG_BIT(15) |
| 2365 | #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ |
| 2366 | #define DISP_TILED REG_BIT(10) |
| 2367 | #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ |
| 2368 | #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 2369 | #define _DSPAADDR 0x70184 |
| 2370 | #define _DSPASTRIDE 0x70188 |
| 2371 | #define _DSPAPOS 0x7018C /* reserved */ |
Hans de Goede | 681f8a5 | 2022-04-18 17:09:36 +0200 | [diff] [blame] | 2372 | #define DISP_POS_Y_MASK REG_GENMASK(31, 16) |
Ville Syrjälä | 428cb15 | 2022-01-21 13:30:31 +0200 | [diff] [blame] | 2373 | #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) |
| 2374 | #define DISP_POS_X_MASK REG_GENMASK(15, 0) |
| 2375 | #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 2376 | #define _DSPASIZE 0x70190 |
Hans de Goede | 681f8a5 | 2022-04-18 17:09:36 +0200 | [diff] [blame] | 2377 | #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) |
Ville Syrjälä | 428cb15 | 2022-01-21 13:30:31 +0200 | [diff] [blame] | 2378 | #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) |
| 2379 | #define DISP_WIDTH_MASK REG_GENMASK(15, 0) |
| 2380 | #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 2381 | #define _DSPASURF 0x7019C /* 965+ only */ |
Ville Syrjälä | 428cb15 | 2022-01-21 13:30:31 +0200 | [diff] [blame] | 2382 | #define DISP_ADDR_MASK REG_GENMASK(31, 12) |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 2383 | #define _DSPATILEOFF 0x701A4 /* 965+ only */ |
Ville Syrjälä | 428cb15 | 2022-01-21 13:30:31 +0200 | [diff] [blame] | 2384 | #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) |
| 2385 | #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) |
| 2386 | #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) |
| 2387 | #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 2388 | #define _DSPAOFFSET 0x701A4 /* HSW */ |
| 2389 | #define _DSPASURFLIVE 0x701AC |
Ville Syrjälä | 94e1572 | 2019-07-03 23:08:21 +0300 | [diff] [blame] | 2390 | #define _DSPAGAMC 0x701E0 |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2391 | |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 2392 | #define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) |
| 2393 | #define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) |
| 2394 | #define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) |
| 2395 | #define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) |
| 2396 | #define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) |
| 2397 | #define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) |
| 2398 | #define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) |
| 2399 | #define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2400 | #define DSPLINOFF(plane) DSPADDR(plane) |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 2401 | #define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) |
| 2402 | #define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) |
| 2403 | #define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2404 | |
Ville Syrjälä | c14b048 | 2014-10-16 20:52:34 +0300 | [diff] [blame] | 2405 | /* CHV pipe B blender and primary plane */ |
| 2406 | #define _CHV_BLEND_A 0x60a00 |
Ville Syrjälä | 428cb15 | 2022-01-21 13:30:31 +0200 | [diff] [blame] | 2407 | #define CHV_BLEND_MASK REG_GENMASK(31, 30) |
| 2408 | #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0) |
| 2409 | #define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1) |
| 2410 | #define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2) |
Ville Syrjälä | c14b048 | 2014-10-16 20:52:34 +0300 | [diff] [blame] | 2411 | #define _CHV_CANVAS_A 0x60a04 |
Ville Syrjälä | 428cb15 | 2022-01-21 13:30:31 +0200 | [diff] [blame] | 2412 | #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20) |
| 2413 | #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10) |
| 2414 | #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0) |
Ville Syrjälä | c14b048 | 2014-10-16 20:52:34 +0300 | [diff] [blame] | 2415 | #define _PRIMPOS_A 0x60a08 |
Ville Syrjälä | 428cb15 | 2022-01-21 13:30:31 +0200 | [diff] [blame] | 2416 | #define PRIM_POS_Y_MASK REG_GENMASK(31, 16) |
| 2417 | #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) |
| 2418 | #define PRIM_POS_X_MASK REG_GENMASK(15, 0) |
| 2419 | #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) |
Ville Syrjälä | c14b048 | 2014-10-16 20:52:34 +0300 | [diff] [blame] | 2420 | #define _PRIMSIZE_A 0x60a0c |
Ville Syrjälä | 428cb15 | 2022-01-21 13:30:31 +0200 | [diff] [blame] | 2421 | #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) |
| 2422 | #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) |
| 2423 | #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) |
| 2424 | #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w)) |
Ville Syrjälä | c14b048 | 2014-10-16 20:52:34 +0300 | [diff] [blame] | 2425 | #define _PRIMCNSTALPHA_A 0x60a10 |
Ville Syrjälä | 428cb15 | 2022-01-21 13:30:31 +0200 | [diff] [blame] | 2426 | #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31) |
| 2427 | #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0) |
| 2428 | #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha)) |
Ville Syrjälä | c14b048 | 2014-10-16 20:52:34 +0300 | [diff] [blame] | 2429 | |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 2430 | #define CHV_BLEND(pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A) |
| 2431 | #define CHV_CANVAS(pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A) |
| 2432 | #define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) |
| 2433 | #define PRIMSIZE(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A) |
| 2434 | #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A) |
Ville Syrjälä | c14b048 | 2014-10-16 20:52:34 +0300 | [diff] [blame] | 2435 | |
Armin Reese | 446f254 | 2012-03-30 16:20:16 -0700 | [diff] [blame] | 2436 | /* Display/Sprite base address macros */ |
| 2437 | #define DISP_BASEADDR_MASK (0xfffff000) |
Paulo Zanoni | 9e8789e | 2018-06-12 16:56:54 -0700 | [diff] [blame] | 2438 | #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) |
| 2439 | #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) |
Armin Reese | 446f254 | 2012-03-30 16:20:16 -0700 | [diff] [blame] | 2440 | |
Ville Syrjälä | 85fa792 | 2015-09-18 20:03:43 +0300 | [diff] [blame] | 2441 | /* |
| 2442 | * VBIOS flags |
| 2443 | * gen2: |
| 2444 | * [00:06] alm,mgm |
| 2445 | * [10:16] all |
| 2446 | * [30:32] alm,mgm |
| 2447 | * gen3+: |
| 2448 | * [00:0f] all |
| 2449 | * [10:1f] all |
| 2450 | * [30:32] all |
| 2451 | */ |
Jani Nikula | ed5eb1b | 2018-12-31 16:56:42 +0200 | [diff] [blame] | 2452 | #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) |
| 2453 | #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) |
| 2454 | #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2455 | #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2456 | |
| 2457 | /* Pipe B */ |
Jani Nikula | ed5eb1b | 2018-12-31 16:56:42 +0200 | [diff] [blame] | 2458 | #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) |
Ville Syrjälä | 3eb08ea | 2023-02-14 00:52:50 +0200 | [diff] [blame] | 2459 | #define _TRANSBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) |
Jani Nikula | ed5eb1b | 2018-12-31 16:56:42 +0200 | [diff] [blame] | 2460 | #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) |
Ville Syrjälä | 25a2e2d | 2013-10-11 22:24:41 +0300 | [diff] [blame] | 2461 | #define _PIPEBFRAMEHIGH 0x71040 |
| 2462 | #define _PIPEBFRAMEPIXEL 0x71044 |
Jani Nikula | ed5eb1b | 2018-12-31 16:56:42 +0200 | [diff] [blame] | 2463 | #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) |
| 2464 | #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 2465 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2466 | |
| 2467 | /* Display B control */ |
Jani Nikula | ed5eb1b | 2018-12-31 16:56:42 +0200 | [diff] [blame] | 2468 | #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) |
Ville Syrjälä | 428cb15 | 2022-01-21 13:30:31 +0200 | [diff] [blame] | 2469 | #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) |
| 2470 | #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) |
Jani Nikula | ed5eb1b | 2018-12-31 16:56:42 +0200 | [diff] [blame] | 2471 | #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) |
| 2472 | #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) |
| 2473 | #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) |
| 2474 | #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) |
| 2475 | #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) |
| 2476 | #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) |
| 2477 | #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) |
| 2478 | #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2479 | |
Madhav Chauhan | 372610f | 2018-10-15 17:28:04 +0300 | [diff] [blame] | 2480 | /* ICL DSI 0 and 1 */ |
| 2481 | #define _PIPEDSI0CONF 0x7b008 |
| 2482 | #define _PIPEDSI1CONF 0x7b808 |
| 2483 | |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 2484 | /* Skylake plane registers */ |
| 2485 | |
| 2486 | #define _PLANE_CTL_1_A 0x70180 |
| 2487 | #define _PLANE_CTL_2_A 0x70280 |
| 2488 | #define _PLANE_CTL_3_A 0x70380 |
Ville Syrjälä | 12d7d85 | 2021-12-01 17:25:44 +0200 | [diff] [blame] | 2489 | #define PLANE_CTL_ENABLE REG_BIT(31) |
Ville Syrjälä | 0b86952 | 2021-05-26 20:36:00 +0300 | [diff] [blame] | 2490 | #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ |
| 2491 | #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ |
Ville Syrjälä | 12d7d85 | 2021-12-01 17:25:44 +0200 | [diff] [blame] | 2492 | #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */ |
| 2493 | #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) |
James Ausmus | b597277 | 2018-01-30 11:49:16 -0200 | [diff] [blame] | 2494 | /* |
| 2495 | * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition |
| 2496 | * expanded to include bit 23 as well. However, the shift-24 based values |
| 2497 | * correctly map to the same formats in ICL, as long as bit 23 is set to 0 |
| 2498 | */ |
Ville Syrjälä | 12d7d85 | 2021-12-01 17:25:44 +0200 | [diff] [blame] | 2499 | #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */ |
| 2500 | #define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */ |
| 2501 | #define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0) |
| 2502 | #define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1) |
| 2503 | #define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2) |
| 2504 | #define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3) |
| 2505 | #define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4) |
| 2506 | #define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5) |
| 2507 | #define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6) |
| 2508 | #define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7) |
| 2509 | #define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8) |
| 2510 | #define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12) |
| 2511 | #define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14) |
| 2512 | #define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1) |
| 2513 | #define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3) |
| 2514 | #define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5) |
| 2515 | #define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7) |
| 2516 | #define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9) |
| 2517 | #define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11) |
| 2518 | #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */ |
| 2519 | #define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21) |
| 2520 | #define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1) |
| 2521 | #define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2) |
| 2522 | #define PLANE_CTL_ORDER_RGBX REG_BIT(20) |
| 2523 | #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19) |
| 2524 | #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) |
| 2525 | #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16) |
| 2526 | #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0) |
| 2527 | #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1) |
| 2528 | #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2) |
| 2529 | #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3) |
| 2530 | #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15) |
| 2531 | #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14) |
| 2532 | #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */ |
| 2533 | #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */ |
| 2534 | #define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10) |
| 2535 | #define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0) |
| 2536 | #define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1) |
| 2537 | #define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4) |
| 2538 | #define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) |
Stanislav Lisovskiy | 072ce41 | 2022-01-18 13:55:44 +0200 | [diff] [blame] | 2539 | #define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) |
Ville Syrjälä | 12d7d85 | 2021-12-01 17:25:44 +0200 | [diff] [blame] | 2540 | #define PLANE_CTL_ASYNC_FLIP REG_BIT(9) |
| 2541 | #define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8) |
| 2542 | #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */ |
| 2543 | #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */ |
| 2544 | #define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0) |
| 2545 | #define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2) |
| 2546 | #define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3) |
| 2547 | #define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0) |
| 2548 | #define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0) |
| 2549 | #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) |
| 2550 | #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) |
| 2551 | #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 2552 | #define _PLANE_STRIDE_1_A 0x70188 |
| 2553 | #define _PLANE_STRIDE_2_A 0x70288 |
| 2554 | #define _PLANE_STRIDE_3_A 0x70388 |
Ville Syrjälä | 12d7d85 | 2021-12-01 17:25:44 +0200 | [diff] [blame] | 2555 | #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) |
| 2556 | #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 2557 | #define _PLANE_POS_1_A 0x7018c |
| 2558 | #define _PLANE_POS_2_A 0x7028c |
| 2559 | #define _PLANE_POS_3_A 0x7038c |
Ville Syrjälä | 12d7d85 | 2021-12-01 17:25:44 +0200 | [diff] [blame] | 2560 | #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) |
| 2561 | #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) |
| 2562 | #define PLANE_POS_X_MASK REG_GENMASK(15, 0) |
| 2563 | #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 2564 | #define _PLANE_SIZE_1_A 0x70190 |
| 2565 | #define _PLANE_SIZE_2_A 0x70290 |
| 2566 | #define _PLANE_SIZE_3_A 0x70390 |
Ville Syrjälä | 12d7d85 | 2021-12-01 17:25:44 +0200 | [diff] [blame] | 2567 | #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) |
| 2568 | #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) |
| 2569 | #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) |
| 2570 | #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 2571 | #define _PLANE_SURF_1_A 0x7019c |
| 2572 | #define _PLANE_SURF_2_A 0x7029c |
| 2573 | #define _PLANE_SURF_3_A 0x7039c |
Ville Syrjälä | 12d7d85 | 2021-12-01 17:25:44 +0200 | [diff] [blame] | 2574 | #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) |
| 2575 | #define PLANE_SURF_DECRYPT REG_BIT(2) |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 2576 | #define _PLANE_OFFSET_1_A 0x701a4 |
| 2577 | #define _PLANE_OFFSET_2_A 0x702a4 |
| 2578 | #define _PLANE_OFFSET_3_A 0x703a4 |
Ville Syrjälä | 12d7d85 | 2021-12-01 17:25:44 +0200 | [diff] [blame] | 2579 | #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) |
| 2580 | #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) |
| 2581 | #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) |
| 2582 | #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x)) |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 2583 | #define _PLANE_KEYVAL_1_A 0x70194 |
| 2584 | #define _PLANE_KEYVAL_2_A 0x70294 |
| 2585 | #define _PLANE_KEYMSK_1_A 0x70198 |
| 2586 | #define _PLANE_KEYMSK_2_A 0x70298 |
Ville Syrjälä | 5747af7 | 2023-03-14 15:02:53 +0200 | [diff] [blame] | 2587 | #define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31) |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 2588 | #define _PLANE_KEYMAX_1_A 0x701a0 |
| 2589 | #define _PLANE_KEYMAX_2_A 0x702a0 |
Ville Syrjälä | 5747af7 | 2023-03-14 15:02:53 +0200 | [diff] [blame] | 2590 | #define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24) |
| 2591 | #define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a)) |
Ville Syrjälä | 3f3fdc9 | 2023-03-14 15:02:51 +0200 | [diff] [blame] | 2592 | #define _PLANE_SURFLIVE_1_A 0x701ac |
| 2593 | #define _PLANE_SURFLIVE_2_A 0x702ac |
Radhakrishna Sripada | d1e2775 | 2021-01-15 23:39:52 +0200 | [diff] [blame] | 2594 | #define _PLANE_CC_VAL_1_A 0x701b4 |
| 2595 | #define _PLANE_CC_VAL_2_A 0x702b4 |
Ville Syrjälä | 2e2adb0 | 2017-08-01 09:58:13 -0700 | [diff] [blame] | 2596 | #define _PLANE_AUX_DIST_1_A 0x701c0 |
Ville Syrjälä | 12d7d85 | 2021-12-01 17:25:44 +0200 | [diff] [blame] | 2597 | #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12) |
| 2598 | #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0) |
| 2599 | #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride)) |
Ville Syrjälä | 2e2adb0 | 2017-08-01 09:58:13 -0700 | [diff] [blame] | 2600 | #define _PLANE_AUX_DIST_2_A 0x702c0 |
| 2601 | #define _PLANE_AUX_OFFSET_1_A 0x701c4 |
| 2602 | #define _PLANE_AUX_OFFSET_2_A 0x702c4 |
Maarten Lankhorst | cb2458b | 2018-10-18 13:51:32 +0200 | [diff] [blame] | 2603 | #define _PLANE_CUS_CTL_1_A 0x701c8 |
| 2604 | #define _PLANE_CUS_CTL_2_A 0x702c8 |
Ville Syrjälä | 12d7d85 | 2021-12-01 17:25:44 +0200 | [diff] [blame] | 2605 | #define PLANE_CUS_ENABLE REG_BIT(31) |
| 2606 | #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) |
| 2607 | #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) |
| 2608 | #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) |
| 2609 | #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) |
| 2610 | #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) |
| 2611 | #define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) |
| 2612 | #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16) |
| 2613 | #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) |
| 2614 | #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) |
| 2615 | #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) |
| 2616 | #define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) |
| 2617 | #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12) |
| 2618 | #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) |
| 2619 | #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) |
| 2620 | #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2) |
Ander Conselvan de Oliveira | 47f9ea8 | 2017-01-26 13:24:22 +0200 | [diff] [blame] | 2621 | #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ |
| 2622 | #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ |
| 2623 | #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ |
Ville Syrjälä | 12d7d85 | 2021-12-01 17:25:44 +0200 | [diff] [blame] | 2624 | #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */ |
| 2625 | #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) |
| 2626 | #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ |
Anshuman Gupta | 6eba56f | 2021-09-24 12:14:49 -0700 | [diff] [blame] | 2627 | #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */ |
Ville Syrjälä | 12d7d85 | 2021-12-01 17:25:44 +0200 | [diff] [blame] | 2628 | #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */ |
| 2629 | #define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17) |
| 2630 | #define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0) |
| 2631 | #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1) |
| 2632 | #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2) |
| 2633 | #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3) |
| 2634 | #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4) |
| 2635 | #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13) |
| 2636 | #define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4) |
| 2637 | #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0) |
| 2638 | #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2) |
| 2639 | #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3) |
Ville Syrjälä | 7732e28 | 2023-03-29 22:04:44 +0300 | [diff] [blame] | 2640 | #define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */ |
| 2641 | #define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */ |
Ville Syrjälä | c5de248 | 2023-03-20 11:05:21 +0200 | [diff] [blame] | 2642 | #define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */ |
Damien Lespiau | 8211bd5 | 2014-11-04 17:06:44 +0000 | [diff] [blame] | 2643 | #define _PLANE_BUF_CFG_1_A 0x7027c |
| 2644 | #define _PLANE_BUF_CFG_2_A 0x7037c |
Ville Syrjälä | 2e4026a | 2023-03-20 11:05:22 +0200 | [diff] [blame] | 2645 | /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ |
| 2646 | #define PLANE_BUF_END_MASK REG_GENMASK(27, 16) |
| 2647 | #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) |
| 2648 | #define PLANE_BUF_START_MASK REG_GENMASK(11, 0) |
| 2649 | #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) |
Chandra Konduru | 2cd601c | 2015-04-27 15:47:37 -0700 | [diff] [blame] | 2650 | #define _PLANE_NV12_BUF_CFG_1_A 0x70278 |
| 2651 | #define _PLANE_NV12_BUF_CFG_2_A 0x70378 |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 2652 | |
Ville Syrjälä | f84b336 | 2021-12-01 17:25:39 +0200 | [diff] [blame] | 2653 | #define _PLANE_CC_VAL_1_B 0x711b4 |
| 2654 | #define _PLANE_CC_VAL_2_B 0x712b4 |
| 2655 | #define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4) |
| 2656 | #define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4) |
| 2657 | #define PLANE_CC_VAL(pipe, plane, dw) \ |
| 2658 | _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) |
Radhakrishna Sripada | d1e2775 | 2021-01-15 23:39:52 +0200 | [diff] [blame] | 2659 | |
Uma Shankar | 6a255da | 2018-11-02 00:40:19 +0530 | [diff] [blame] | 2660 | /* Input CSC Register Definitions */ |
| 2661 | #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 |
| 2662 | #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 |
| 2663 | |
| 2664 | #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 |
| 2665 | #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 |
| 2666 | |
| 2667 | #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ |
| 2668 | _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ |
| 2669 | _PLANE_INPUT_CSC_RY_GY_1_B) |
| 2670 | #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ |
| 2671 | _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ |
| 2672 | _PLANE_INPUT_CSC_RY_GY_2_B) |
| 2673 | |
| 2674 | #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ |
| 2675 | _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ |
| 2676 | _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) |
| 2677 | |
| 2678 | #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 |
| 2679 | #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 |
| 2680 | |
| 2681 | #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 |
| 2682 | #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 |
| 2683 | |
| 2684 | #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ |
| 2685 | _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ |
| 2686 | _PLANE_INPUT_CSC_PREOFF_HI_1_B) |
| 2687 | #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ |
| 2688 | _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ |
| 2689 | _PLANE_INPUT_CSC_PREOFF_HI_2_B) |
| 2690 | #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ |
| 2691 | _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ |
| 2692 | _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) |
| 2693 | |
| 2694 | #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 |
| 2695 | #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 |
| 2696 | |
| 2697 | #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 |
| 2698 | #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 |
| 2699 | |
| 2700 | #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ |
| 2701 | _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ |
| 2702 | _PLANE_INPUT_CSC_POSTOFF_HI_1_B) |
| 2703 | #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ |
| 2704 | _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ |
| 2705 | _PLANE_INPUT_CSC_POSTOFF_HI_2_B) |
| 2706 | #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ |
| 2707 | _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ |
| 2708 | _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) |
Ander Conselvan de Oliveira | 47f9ea8 | 2017-01-26 13:24:22 +0200 | [diff] [blame] | 2709 | |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 2710 | #define _PLANE_CTL_1_B 0x71180 |
| 2711 | #define _PLANE_CTL_2_B 0x71280 |
| 2712 | #define _PLANE_CTL_3_B 0x71380 |
| 2713 | #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) |
| 2714 | #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) |
| 2715 | #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) |
| 2716 | #define PLANE_CTL(pipe, plane) \ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2717 | _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 2718 | |
| 2719 | #define _PLANE_STRIDE_1_B 0x71188 |
| 2720 | #define _PLANE_STRIDE_2_B 0x71288 |
| 2721 | #define _PLANE_STRIDE_3_B 0x71388 |
| 2722 | #define _PLANE_STRIDE_1(pipe) \ |
| 2723 | _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) |
| 2724 | #define _PLANE_STRIDE_2(pipe) \ |
| 2725 | _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) |
| 2726 | #define _PLANE_STRIDE_3(pipe) \ |
| 2727 | _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) |
| 2728 | #define PLANE_STRIDE(pipe, plane) \ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2729 | _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 2730 | |
| 2731 | #define _PLANE_POS_1_B 0x7118c |
| 2732 | #define _PLANE_POS_2_B 0x7128c |
| 2733 | #define _PLANE_POS_3_B 0x7138c |
| 2734 | #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) |
| 2735 | #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) |
| 2736 | #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) |
| 2737 | #define PLANE_POS(pipe, plane) \ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2738 | _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 2739 | |
| 2740 | #define _PLANE_SIZE_1_B 0x71190 |
| 2741 | #define _PLANE_SIZE_2_B 0x71290 |
| 2742 | #define _PLANE_SIZE_3_B 0x71390 |
| 2743 | #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) |
| 2744 | #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) |
| 2745 | #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) |
| 2746 | #define PLANE_SIZE(pipe, plane) \ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2747 | _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 2748 | |
| 2749 | #define _PLANE_SURF_1_B 0x7119c |
| 2750 | #define _PLANE_SURF_2_B 0x7129c |
| 2751 | #define _PLANE_SURF_3_B 0x7139c |
| 2752 | #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) |
| 2753 | #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) |
| 2754 | #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) |
| 2755 | #define PLANE_SURF(pipe, plane) \ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2756 | _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 2757 | |
| 2758 | #define _PLANE_OFFSET_1_B 0x711a4 |
| 2759 | #define _PLANE_OFFSET_2_B 0x712a4 |
| 2760 | #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) |
| 2761 | #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) |
| 2762 | #define PLANE_OFFSET(pipe, plane) \ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2763 | _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 2764 | |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 2765 | #define _PLANE_KEYVAL_1_B 0x71194 |
| 2766 | #define _PLANE_KEYVAL_2_B 0x71294 |
| 2767 | #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) |
| 2768 | #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) |
| 2769 | #define PLANE_KEYVAL(pipe, plane) \ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2770 | _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 2771 | |
| 2772 | #define _PLANE_KEYMSK_1_B 0x71198 |
| 2773 | #define _PLANE_KEYMSK_2_B 0x71298 |
| 2774 | #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) |
| 2775 | #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) |
| 2776 | #define PLANE_KEYMSK(pipe, plane) \ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2777 | _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 2778 | |
| 2779 | #define _PLANE_KEYMAX_1_B 0x711a0 |
| 2780 | #define _PLANE_KEYMAX_2_B 0x712a0 |
| 2781 | #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) |
| 2782 | #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) |
| 2783 | #define PLANE_KEYMAX(pipe, plane) \ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2784 | _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 2785 | |
Ville Syrjälä | 3f3fdc9 | 2023-03-14 15:02:51 +0200 | [diff] [blame] | 2786 | #define _PLANE_SURFLIVE_1_B 0x711ac |
| 2787 | #define _PLANE_SURFLIVE_2_B 0x712ac |
| 2788 | #define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B) |
| 2789 | #define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B) |
| 2790 | #define PLANE_SURFLIVE(pipe, plane) \ |
| 2791 | _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe)) |
| 2792 | |
Ville Syrjälä | 5a08585 | 2023-03-20 11:05:20 +0200 | [diff] [blame] | 2793 | #define _PLANE_CHICKEN_1_B 0x7126c |
| 2794 | #define _PLANE_CHICKEN_2_B 0x7136c |
| 2795 | #define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B) |
| 2796 | #define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B) |
| 2797 | #define PLANE_CHICKEN(pipe, plane) \ |
| 2798 | _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe)) |
| 2799 | |
Ville Syrjälä | 2e2adb0 | 2017-08-01 09:58:13 -0700 | [diff] [blame] | 2800 | #define _PLANE_AUX_DIST_1_B 0x711c0 |
| 2801 | #define _PLANE_AUX_DIST_2_B 0x712c0 |
| 2802 | #define _PLANE_AUX_DIST_1(pipe) \ |
| 2803 | _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) |
| 2804 | #define _PLANE_AUX_DIST_2(pipe) \ |
| 2805 | _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) |
| 2806 | #define PLANE_AUX_DIST(pipe, plane) \ |
| 2807 | _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) |
| 2808 | |
| 2809 | #define _PLANE_AUX_OFFSET_1_B 0x711c4 |
| 2810 | #define _PLANE_AUX_OFFSET_2_B 0x712c4 |
| 2811 | #define _PLANE_AUX_OFFSET_1(pipe) \ |
| 2812 | _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) |
| 2813 | #define _PLANE_AUX_OFFSET_2(pipe) \ |
| 2814 | _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) |
| 2815 | #define PLANE_AUX_OFFSET(pipe, plane) \ |
| 2816 | _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) |
| 2817 | |
Maarten Lankhorst | cb2458b | 2018-10-18 13:51:32 +0200 | [diff] [blame] | 2818 | #define _PLANE_CUS_CTL_1_B 0x711c8 |
| 2819 | #define _PLANE_CUS_CTL_2_B 0x712c8 |
| 2820 | #define _PLANE_CUS_CTL_1(pipe) \ |
| 2821 | _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) |
| 2822 | #define _PLANE_CUS_CTL_2(pipe) \ |
| 2823 | _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) |
| 2824 | #define PLANE_CUS_CTL(pipe, plane) \ |
| 2825 | _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) |
| 2826 | |
Ander Conselvan de Oliveira | 47f9ea8 | 2017-01-26 13:24:22 +0200 | [diff] [blame] | 2827 | #define _PLANE_COLOR_CTL_1_B 0x711CC |
| 2828 | #define _PLANE_COLOR_CTL_2_B 0x712CC |
| 2829 | #define _PLANE_COLOR_CTL_3_B 0x713CC |
| 2830 | #define _PLANE_COLOR_CTL_1(pipe) \ |
| 2831 | _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) |
| 2832 | #define _PLANE_COLOR_CTL_2(pipe) \ |
| 2833 | _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) |
| 2834 | #define PLANE_COLOR_CTL(pipe, plane) \ |
| 2835 | _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) |
| 2836 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2837 | /* VBIOS regs */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2838 | #define VGACNTRL _MMIO(0x71400) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2839 | # define VGA_DISP_DISABLE (1 << 31) |
| 2840 | # define VGA_2X_MODE (1 << 30) |
| 2841 | # define VGA_PIPE_B_SELECT (1 << 29) |
| 2842 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2843 | #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) |
Ville Syrjälä | 766aa1c | 2013-01-25 21:44:46 +0200 | [diff] [blame] | 2844 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2845 | /* Ironlake */ |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2846 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2847 | #define CPU_VGACNTRL _MMIO(0x41000) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2848 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2849 | #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) |
Ville Syrjälä | 40bfd7a | 2015-08-27 23:55:56 +0300 | [diff] [blame] | 2850 | #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) |
| 2851 | #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ |
| 2852 | #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ |
| 2853 | #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ |
| 2854 | #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ |
| 2855 | #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ |
| 2856 | #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) |
| 2857 | #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) |
| 2858 | #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) |
| 2859 | #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2860 | |
| 2861 | /* refresh rate hardware control */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2862 | #define RR_HW_CTL _MMIO(0x45300) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2863 | #define RR_HW_LOW_POWER_FRAMES_MASK 0xff |
| 2864 | #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 |
| 2865 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2866 | #define PCH_3DCGDIS0 _MMIO(0x46020) |
Eric Anholt | 8956c8b | 2010-03-18 13:21:14 -0700 | [diff] [blame] | 2867 | # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) |
| 2868 | # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) |
| 2869 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2870 | #define PCH_3DCGDIS1 _MMIO(0x46024) |
Eric Anholt | 06f3775 | 2010-12-14 10:06:46 -0800 | [diff] [blame] | 2871 | # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) |
| 2872 | |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 2873 | #define _PIPEA_DATA_M1 0x60030 |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 2874 | #define _PIPEA_DATA_N1 0x60034 |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 2875 | #define _PIPEA_DATA_M2 0x60038 |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 2876 | #define _PIPEA_DATA_N2 0x6003c |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 2877 | #define _PIPEA_LINK_M1 0x60040 |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 2878 | #define _PIPEA_LINK_N1 0x60044 |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 2879 | #define _PIPEA_LINK_M2 0x60048 |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 2880 | #define _PIPEA_LINK_N2 0x6004c |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2881 | |
| 2882 | /* PIPEB timing regs are same start from 0x61000 */ |
| 2883 | |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 2884 | #define _PIPEB_DATA_M1 0x61030 |
| 2885 | #define _PIPEB_DATA_N1 0x61034 |
| 2886 | #define _PIPEB_DATA_M2 0x61038 |
| 2887 | #define _PIPEB_DATA_N2 0x6103c |
| 2888 | #define _PIPEB_LINK_M1 0x61040 |
| 2889 | #define _PIPEB_LINK_N1 0x61044 |
| 2890 | #define _PIPEB_LINK_M2 0x61048 |
| 2891 | #define _PIPEB_LINK_N2 0x6104c |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2892 | |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 2893 | #define PIPE_DATA_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1) |
| 2894 | #define PIPE_DATA_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1) |
| 2895 | #define PIPE_DATA_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2) |
| 2896 | #define PIPE_DATA_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2) |
| 2897 | #define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1) |
| 2898 | #define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) |
| 2899 | #define PIPE_LINK_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2) |
| 2900 | #define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2901 | |
| 2902 | /* CPU panel fitter */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2903 | /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ |
Ville Syrjälä | 75d020d | 2023-04-18 20:55:20 +0300 | [diff] [blame] | 2904 | #define _PFA_CTL_1 0x68080 |
| 2905 | #define _PFB_CTL_1 0x68880 |
| 2906 | #define PF_ENABLE REG_BIT(31) |
| 2907 | #define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */ |
| 2908 | #define PF_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe)) |
| 2909 | #define PF_FILTER_MASK REG_GENMASK(24, 23) |
| 2910 | #define PF_FILTER_PROGRAMMED REG_FIELD_PREP(PF_FILTER_MASK, 0) |
| 2911 | #define PF_FILTER_MED_3x3 REG_FIELD_PREP(PF_FILTER_MASK, 1) |
| 2912 | #define PF_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2) |
| 2913 | #define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2914 | #define _PFA_WIN_SZ 0x68074 |
| 2915 | #define _PFB_WIN_SZ 0x68874 |
Ville Syrjälä | 4883c80 | 2023-04-26 16:50:13 +0300 | [diff] [blame] | 2916 | #define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16) |
| 2917 | #define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w)) |
| 2918 | #define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0) |
| 2919 | #define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h)) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2920 | #define _PFA_WIN_POS 0x68070 |
| 2921 | #define _PFB_WIN_POS 0x68870 |
Ville Syrjälä | 4883c80 | 2023-04-26 16:50:13 +0300 | [diff] [blame] | 2922 | #define PF_WIN_XPOS_MASK REG_GENMASK(31, 16) |
| 2923 | #define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x)) |
| 2924 | #define PF_WIN_YPOS_MASK REG_GENMASK(15, 0) |
| 2925 | #define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y)) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2926 | #define _PFA_VSCALE 0x68084 |
| 2927 | #define _PFB_VSCALE 0x68884 |
| 2928 | #define _PFA_HSCALE 0x68090 |
| 2929 | #define _PFB_HSCALE 0x68890 |
| 2930 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2931 | #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) |
| 2932 | #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) |
| 2933 | #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) |
| 2934 | #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) |
| 2935 | #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2936 | |
Chandra Konduru | 1c9a2d4a | 2015-04-07 15:28:35 -0700 | [diff] [blame] | 2937 | /* |
| 2938 | * Skylake scalers |
| 2939 | */ |
| 2940 | #define _PS_1A_CTRL 0x68180 |
| 2941 | #define _PS_2A_CTRL 0x68280 |
| 2942 | #define _PS_1B_CTRL 0x68980 |
| 2943 | #define _PS_2B_CTRL 0x68A80 |
| 2944 | #define _PS_1C_CTRL 0x69180 |
Ville Syrjälä | e622066 | 2023-04-26 16:50:18 +0300 | [diff] [blame] | 2945 | #define PS_SCALER_EN REG_BIT(31) |
Ville Syrjälä | 9f8c1fe | 2023-04-26 16:50:19 +0300 | [diff] [blame] | 2946 | #define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */ |
| 2947 | #define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0) |
| 2948 | #define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1) |
Ville Syrjälä | e622066 | 2023-04-26 16:50:18 +0300 | [diff] [blame] | 2949 | #define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */ |
| 2950 | #define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0) |
| 2951 | #define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1) |
| 2952 | #define SKL_PS_SCALER_MODE_NV12 REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2) |
| 2953 | #define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */ |
| 2954 | #define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0) |
| 2955 | #define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1) |
Ville Syrjälä | 9f8c1fe | 2023-04-26 16:50:19 +0300 | [diff] [blame] | 2956 | #define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */ |
Ville Syrjälä | e622066 | 2023-04-26 16:50:18 +0300 | [diff] [blame] | 2957 | #define PS_BINDING_MASK REG_GENMASK(27, 25) |
| 2958 | #define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0) |
| 2959 | #define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1) |
| 2960 | #define PS_FILTER_MASK REG_GENMASK(24, 23) |
| 2961 | #define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0) |
| 2962 | #define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1) |
| 2963 | #define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2) |
| 2964 | #define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3) |
Ville Syrjälä | 9f8c1fe | 2023-04-26 16:50:19 +0300 | [diff] [blame] | 2965 | #define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */ |
| 2966 | #define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0) |
| 2967 | #define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1) |
| 2968 | #define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */ |
| 2969 | #define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */ |
| 2970 | #define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */ |
Ville Syrjälä | e622066 | 2023-04-26 16:50:18 +0300 | [diff] [blame] | 2971 | #define PS_VERT3TAP REG_BIT(21) /* skl/bxt */ |
| 2972 | #define PS_VERT_INT_INVERT_FIELD REG_BIT(20) |
Ville Syrjälä | 9f8c1fe | 2023-04-26 16:50:19 +0300 | [diff] [blame] | 2973 | #define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */ |
Ville Syrjälä | e622066 | 2023-04-26 16:50:18 +0300 | [diff] [blame] | 2974 | #define PS_PWRUP_PROGRESS REG_BIT(17) |
| 2975 | #define PS_V_FILTER_BYPASS REG_BIT(8) |
| 2976 | #define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */ |
| 2977 | #define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */ |
| 2978 | #define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0) |
| 2979 | #define PS_VADAPT_MODE_MOD_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1) |
| 2980 | #define PS_VADAPT_MODE_MOST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3) |
| 2981 | #define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */ |
| 2982 | #define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1) |
| 2983 | #define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */ |
| 2984 | #define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set)) |
| 2985 | #define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */ |
| 2986 | #define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set)) |
| 2987 | #define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */ |
| 2988 | #define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set)) |
| 2989 | #define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */ |
| 2990 | #define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set)) |
Chandra Konduru | 1c9a2d4a | 2015-04-07 15:28:35 -0700 | [diff] [blame] | 2991 | |
| 2992 | #define _PS_PWR_GATE_1A 0x68160 |
| 2993 | #define _PS_PWR_GATE_2A 0x68260 |
| 2994 | #define _PS_PWR_GATE_1B 0x68960 |
| 2995 | #define _PS_PWR_GATE_2B 0x68A60 |
| 2996 | #define _PS_PWR_GATE_1C 0x69160 |
Ville Syrjälä | e622066 | 2023-04-26 16:50:18 +0300 | [diff] [blame] | 2997 | #define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31) |
| 2998 | #define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3) |
| 2999 | #define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0) |
| 3000 | #define PS_PWR_GATE_SETTLING_TIME_64 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1) |
| 3001 | #define PS_PWR_GATE_SETTLING_TIME_96 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2) |
| 3002 | #define PS_PWR_GATE_SETTLING_TIME_128 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3) |
| 3003 | #define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0) |
| 3004 | #define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0) |
| 3005 | #define PS_PWR_GATE_SLPEN_16 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1) |
| 3006 | #define PS_PWR_GATE_SLPEN_24 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2) |
| 3007 | #define PS_PWR_GATE_SLPEN_32 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3) |
Chandra Konduru | 1c9a2d4a | 2015-04-07 15:28:35 -0700 | [diff] [blame] | 3008 | |
| 3009 | #define _PS_WIN_POS_1A 0x68170 |
| 3010 | #define _PS_WIN_POS_2A 0x68270 |
| 3011 | #define _PS_WIN_POS_1B 0x68970 |
| 3012 | #define _PS_WIN_POS_2B 0x68A70 |
| 3013 | #define _PS_WIN_POS_1C 0x69170 |
Ville Syrjälä | 6ec9179 | 2023-04-26 16:50:17 +0300 | [diff] [blame] | 3014 | #define PS_WIN_XPOS_MASK REG_GENMASK(31, 16) |
| 3015 | #define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x)) |
| 3016 | #define PS_WIN_YPOS_MASK REG_GENMASK(15, 0) |
| 3017 | #define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y)) |
Chandra Konduru | 1c9a2d4a | 2015-04-07 15:28:35 -0700 | [diff] [blame] | 3018 | |
| 3019 | #define _PS_WIN_SZ_1A 0x68174 |
| 3020 | #define _PS_WIN_SZ_2A 0x68274 |
| 3021 | #define _PS_WIN_SZ_1B 0x68974 |
| 3022 | #define _PS_WIN_SZ_2B 0x68A74 |
| 3023 | #define _PS_WIN_SZ_1C 0x69174 |
Ville Syrjälä | 6ec9179 | 2023-04-26 16:50:17 +0300 | [diff] [blame] | 3024 | #define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16) |
| 3025 | #define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w)) |
| 3026 | #define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0) |
| 3027 | #define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h)) |
Chandra Konduru | 1c9a2d4a | 2015-04-07 15:28:35 -0700 | [diff] [blame] | 3028 | |
| 3029 | #define _PS_VSCALE_1A 0x68184 |
| 3030 | #define _PS_VSCALE_2A 0x68284 |
| 3031 | #define _PS_VSCALE_1B 0x68984 |
| 3032 | #define _PS_VSCALE_2B 0x68A84 |
| 3033 | #define _PS_VSCALE_1C 0x69184 |
| 3034 | |
| 3035 | #define _PS_HSCALE_1A 0x68190 |
| 3036 | #define _PS_HSCALE_2A 0x68290 |
| 3037 | #define _PS_HSCALE_1B 0x68990 |
| 3038 | #define _PS_HSCALE_2B 0x68A90 |
| 3039 | #define _PS_HSCALE_1C 0x69190 |
| 3040 | |
| 3041 | #define _PS_VPHASE_1A 0x68188 |
| 3042 | #define _PS_VPHASE_2A 0x68288 |
| 3043 | #define _PS_VPHASE_1B 0x68988 |
| 3044 | #define _PS_VPHASE_2B 0x68A88 |
| 3045 | #define _PS_VPHASE_1C 0x69188 |
Ville Syrjälä | e622066 | 2023-04-26 16:50:18 +0300 | [diff] [blame] | 3046 | #define PS_Y_PHASE_MASK REG_GENMASK(31, 16) |
| 3047 | #define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x)) |
| 3048 | #define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0) |
| 3049 | #define PS_UV_RGB_PHASE(x) REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x)) |
| 3050 | #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ |
| 3051 | #define PS_PHASE_TRIP (1 << 0) |
Chandra Konduru | 1c9a2d4a | 2015-04-07 15:28:35 -0700 | [diff] [blame] | 3052 | |
| 3053 | #define _PS_HPHASE_1A 0x68194 |
| 3054 | #define _PS_HPHASE_2A 0x68294 |
| 3055 | #define _PS_HPHASE_1B 0x68994 |
| 3056 | #define _PS_HPHASE_2B 0x68A94 |
| 3057 | #define _PS_HPHASE_1C 0x69194 |
| 3058 | |
| 3059 | #define _PS_ECC_STAT_1A 0x681D0 |
| 3060 | #define _PS_ECC_STAT_2A 0x682D0 |
| 3061 | #define _PS_ECC_STAT_1B 0x689D0 |
| 3062 | #define _PS_ECC_STAT_2B 0x68AD0 |
| 3063 | #define _PS_ECC_STAT_1C 0x691D0 |
| 3064 | |
Pankaj Bharadiya | 105c9e1 | 2020-10-20 21:44:24 +0530 | [diff] [blame] | 3065 | #define _PS_COEF_SET0_INDEX_1A 0x68198 |
| 3066 | #define _PS_COEF_SET0_INDEX_2A 0x68298 |
| 3067 | #define _PS_COEF_SET0_INDEX_1B 0x68998 |
| 3068 | #define _PS_COEF_SET0_INDEX_2B 0x68A98 |
Ville Syrjälä | e622066 | 2023-04-26 16:50:18 +0300 | [diff] [blame] | 3069 | #define PS_COEF_INDEX_AUTO_INC REG_BIT(10) |
Pankaj Bharadiya | 105c9e1 | 2020-10-20 21:44:24 +0530 | [diff] [blame] | 3070 | |
| 3071 | #define _PS_COEF_SET0_DATA_1A 0x6819C |
| 3072 | #define _PS_COEF_SET0_DATA_2A 0x6829C |
| 3073 | #define _PS_COEF_SET0_DATA_1B 0x6899C |
| 3074 | #define _PS_COEF_SET0_DATA_2B 0x68A9C |
| 3075 | |
Jani Nikula | e67005e | 2018-06-29 13:20:39 +0300 | [diff] [blame] | 3076 | #define _ID(id, a, b) _PICK_EVEN(id, a, b) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3077 | #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ |
Chandra Konduru | 1c9a2d4a | 2015-04-07 15:28:35 -0700 | [diff] [blame] | 3078 | _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ |
| 3079 | _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3080 | #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ |
Chandra Konduru | 1c9a2d4a | 2015-04-07 15:28:35 -0700 | [diff] [blame] | 3081 | _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ |
| 3082 | _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3083 | #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ |
Chandra Konduru | 1c9a2d4a | 2015-04-07 15:28:35 -0700 | [diff] [blame] | 3084 | _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ |
| 3085 | _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3086 | #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ |
Chandra Konduru | 1c9a2d4a | 2015-04-07 15:28:35 -0700 | [diff] [blame] | 3087 | _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ |
| 3088 | _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3089 | #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ |
Chandra Konduru | 1c9a2d4a | 2015-04-07 15:28:35 -0700 | [diff] [blame] | 3090 | _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ |
| 3091 | _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3092 | #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ |
Chandra Konduru | 1c9a2d4a | 2015-04-07 15:28:35 -0700 | [diff] [blame] | 3093 | _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ |
| 3094 | _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3095 | #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ |
Chandra Konduru | 1c9a2d4a | 2015-04-07 15:28:35 -0700 | [diff] [blame] | 3096 | _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ |
| 3097 | _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3098 | #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ |
Chandra Konduru | 1c9a2d4a | 2015-04-07 15:28:35 -0700 | [diff] [blame] | 3099 | _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ |
| 3100 | _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3101 | #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ |
Chandra Konduru | 1c9a2d4a | 2015-04-07 15:28:35 -0700 | [diff] [blame] | 3102 | _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ |
Ville Syrjälä | 9bca5d0 | 2015-11-04 23:20:16 +0200 | [diff] [blame] | 3103 | _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) |
Lucas De Marchi | 4a8b03a | 2021-07-28 14:59:36 -0700 | [diff] [blame] | 3104 | #define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \ |
Pankaj Bharadiya | 105c9e1 | 2020-10-20 21:44:24 +0530 | [diff] [blame] | 3105 | _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \ |
| 3106 | _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8) |
Chandra Konduru | 1c9a2d4a | 2015-04-07 15:28:35 -0700 | [diff] [blame] | 3107 | |
Lucas De Marchi | 4a8b03a | 2021-07-28 14:59:36 -0700 | [diff] [blame] | 3108 | #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \ |
Pankaj Bharadiya | 105c9e1 | 2020-10-20 21:44:24 +0530 | [diff] [blame] | 3109 | _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \ |
| 3110 | _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8) |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 3111 | |
Uma Shankar | 1d85a29 | 2018-08-07 21:15:35 +0530 | [diff] [blame] | 3112 | /* Display Internal Timeout Register */ |
| 3113 | #define RM_TIMEOUT _MMIO(0x42060) |
| 3114 | #define MMIO_TIMEOUT_US(us) ((us) << 0) |
| 3115 | |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3116 | /* interrupts */ |
| 3117 | #define DE_MASTER_IRQ_CONTROL (1 << 31) |
| 3118 | #define DE_SPRITEB_FLIP_DONE (1 << 29) |
| 3119 | #define DE_SPRITEA_FLIP_DONE (1 << 28) |
| 3120 | #define DE_PLANEB_FLIP_DONE (1 << 27) |
| 3121 | #define DE_PLANEA_FLIP_DONE (1 << 26) |
Daniel Vetter | 40da17c2 | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 3122 | #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3123 | #define DE_PCU_EVENT (1 << 25) |
| 3124 | #define DE_GTT_FAULT (1 << 24) |
| 3125 | #define DE_POISON (1 << 23) |
| 3126 | #define DE_PERFORM_COUNTER (1 << 22) |
| 3127 | #define DE_PCH_EVENT (1 << 21) |
| 3128 | #define DE_AUX_CHANNEL_A (1 << 20) |
| 3129 | #define DE_DP_A_HOTPLUG (1 << 19) |
| 3130 | #define DE_GSE (1 << 18) |
| 3131 | #define DE_PIPEB_VBLANK (1 << 15) |
| 3132 | #define DE_PIPEB_EVEN_FIELD (1 << 14) |
| 3133 | #define DE_PIPEB_ODD_FIELD (1 << 13) |
| 3134 | #define DE_PIPEB_LINE_COMPARE (1 << 12) |
| 3135 | #define DE_PIPEB_VSYNC (1 << 11) |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3136 | #define DE_PIPEB_CRC_DONE (1 << 10) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3137 | #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) |
| 3138 | #define DE_PIPEA_VBLANK (1 << 7) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 3139 | #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3140 | #define DE_PIPEA_EVEN_FIELD (1 << 6) |
| 3141 | #define DE_PIPEA_ODD_FIELD (1 << 5) |
| 3142 | #define DE_PIPEA_LINE_COMPARE (1 << 4) |
| 3143 | #define DE_PIPEA_VSYNC (1 << 3) |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3144 | #define DE_PIPEA_CRC_DONE (1 << 2) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 3145 | #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3146 | #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 3147 | #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3148 | |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 3149 | /* More Ivybridge lolz */ |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 3150 | #define DE_ERR_INT_IVB (1 << 30) |
| 3151 | #define DE_GSE_IVB (1 << 29) |
| 3152 | #define DE_PCH_EVENT_IVB (1 << 28) |
| 3153 | #define DE_DP_A_HOTPLUG_IVB (1 << 27) |
| 3154 | #define DE_AUX_CHANNEL_A_IVB (1 << 26) |
| 3155 | #define DE_EDP_PSR_INT_HSW (1 << 19) |
| 3156 | #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) |
| 3157 | #define DE_PLANEC_FLIP_DONE_IVB (1 << 13) |
| 3158 | #define DE_PIPEC_VBLANK_IVB (1 << 10) |
| 3159 | #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) |
| 3160 | #define DE_PLANEB_FLIP_DONE_IVB (1 << 8) |
| 3161 | #define DE_PIPEB_VBLANK_IVB (1 << 5) |
| 3162 | #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) |
| 3163 | #define DE_PLANEA_FLIP_DONE_IVB (1 << 3) |
| 3164 | #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) |
| 3165 | #define DE_PIPEA_VBLANK_IVB (1 << 0) |
Ville Syrjälä | 68d9753 | 2015-09-18 20:03:39 +0300 | [diff] [blame] | 3166 | #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 3167 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3168 | #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 3169 | #define MASTER_INTERRUPT_ENABLE (1 << 31) |
Jesse Barnes | 7eea1dd | 2012-03-22 14:38:44 -0700 | [diff] [blame] | 3170 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3171 | #define DEISR _MMIO(0x44000) |
| 3172 | #define DEIMR _MMIO(0x44004) |
| 3173 | #define DEIIR _MMIO(0x44008) |
| 3174 | #define DEIER _MMIO(0x4400c) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3175 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3176 | #define GTISR _MMIO(0x44010) |
| 3177 | #define GTIMR _MMIO(0x44014) |
| 3178 | #define GTIIR _MMIO(0x44018) |
| 3179 | #define GTIER _MMIO(0x4401c) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3180 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3181 | #define GEN8_MASTER_IRQ _MMIO(0x44200) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 3182 | #define GEN8_MASTER_IRQ_CONTROL (1 << 31) |
| 3183 | #define GEN8_PCU_IRQ (1 << 30) |
| 3184 | #define GEN8_DE_PCH_IRQ (1 << 23) |
| 3185 | #define GEN8_DE_MISC_IRQ (1 << 22) |
| 3186 | #define GEN8_DE_PORT_IRQ (1 << 20) |
| 3187 | #define GEN8_DE_PIPE_C_IRQ (1 << 18) |
| 3188 | #define GEN8_DE_PIPE_B_IRQ (1 << 17) |
| 3189 | #define GEN8_DE_PIPE_A_IRQ (1 << 16) |
| 3190 | #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) |
| 3191 | #define GEN8_GT_VECS_IRQ (1 << 6) |
| 3192 | #define GEN8_GT_GUC_IRQ (1 << 5) |
| 3193 | #define GEN8_GT_PM_IRQ (1 << 4) |
Chris Wilson | 8a68d46 | 2019-03-05 18:03:30 +0000 | [diff] [blame] | 3194 | #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ |
| 3195 | #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 3196 | #define GEN8_GT_BCS_IRQ (1 << 1) |
| 3197 | #define GEN8_GT_RCS_IRQ (1 << 0) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3198 | |
Matt Roper | 0e53fb8 | 2021-05-11 21:21:42 -0700 | [diff] [blame] | 3199 | #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c) |
| 3200 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3201 | #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) |
| 3202 | #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) |
| 3203 | #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) |
| 3204 | #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3205 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3206 | #define GEN8_RCS_IRQ_SHIFT 0 |
Dave Gordon | 4df001d | 2015-08-12 15:43:42 +0100 | [diff] [blame] | 3207 | #define GEN8_BCS_IRQ_SHIFT 16 |
Chris Wilson | 8a68d46 | 2019-03-05 18:03:30 +0000 | [diff] [blame] | 3208 | #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */ |
| 3209 | #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */ |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3210 | #define GEN8_VECS_IRQ_SHIFT 0 |
Dave Gordon | 4df001d | 2015-08-12 15:43:42 +0100 | [diff] [blame] | 3211 | #define GEN8_WD_IRQ_SHIFT 16 |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3212 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3213 | #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) |
| 3214 | #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) |
| 3215 | #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) |
| 3216 | #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) |
Daniel Vetter | 38d83c96 | 2013-11-07 11:05:46 +0100 | [diff] [blame] | 3217 | #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3218 | #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) |
| 3219 | #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) |
Matt Roper | 8bcc084 | 2021-05-25 17:06:54 -0700 | [diff] [blame] | 3220 | #define XELPD_PIPE_SOFT_UNDERRUN (1 << 22) |
| 3221 | #define XELPD_PIPE_HARD_UNDERRUN (1 << 21) |
Ville Syrjälä | 1d9ce1c | 2023-02-14 00:52:52 +0200 | [diff] [blame] | 3222 | #define GEN12_PIPE_VBLANK_UNMOD (1 << 19) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3223 | #define GEN8_PIPE_CURSOR_FAULT (1 << 10) |
| 3224 | #define GEN8_PIPE_SPRITE_FAULT (1 << 9) |
| 3225 | #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) |
| 3226 | #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) |
Damien Lespiau | d0e1f1c | 2014-04-08 01:22:44 +0100 | [diff] [blame] | 3227 | #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3228 | #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) |
| 3229 | #define GEN8_PIPE_VSYNC (1 << 1) |
| 3230 | #define GEN8_PIPE_VBLANK (1 << 0) |
Damien Lespiau | 770de83d | 2014-03-20 20:45:01 +0000 | [diff] [blame] | 3231 | #define GEN9_PIPE_CURSOR_FAULT (1 << 11) |
Matt Roper | d506a65 | 2019-10-08 14:17:16 -0700 | [diff] [blame] | 3232 | #define GEN11_PIPE_PLANE7_FAULT (1 << 22) |
| 3233 | #define GEN11_PIPE_PLANE6_FAULT (1 << 21) |
| 3234 | #define GEN11_PIPE_PLANE5_FAULT (1 << 20) |
Damien Lespiau | b21249c | 2015-03-17 11:39:33 +0200 | [diff] [blame] | 3235 | #define GEN9_PIPE_PLANE4_FAULT (1 << 10) |
Damien Lespiau | 770de83d | 2014-03-20 20:45:01 +0000 | [diff] [blame] | 3236 | #define GEN9_PIPE_PLANE3_FAULT (1 << 9) |
| 3237 | #define GEN9_PIPE_PLANE2_FAULT (1 << 8) |
| 3238 | #define GEN9_PIPE_PLANE1_FAULT (1 << 7) |
Damien Lespiau | b21249c | 2015-03-17 11:39:33 +0200 | [diff] [blame] | 3239 | #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) |
Damien Lespiau | 770de83d | 2014-03-20 20:45:01 +0000 | [diff] [blame] | 3240 | #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) |
| 3241 | #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) |
| 3242 | #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) |
Ville Syrjälä | 68d9753 | 2015-09-18 20:03:39 +0300 | [diff] [blame] | 3243 | #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) |
Daniel Vetter | 30100f2 | 2013-11-07 14:49:24 +0100 | [diff] [blame] | 3244 | #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ |
| 3245 | (GEN8_PIPE_CURSOR_FAULT | \ |
| 3246 | GEN8_PIPE_SPRITE_FAULT | \ |
| 3247 | GEN8_PIPE_PRIMARY_FAULT) |
Damien Lespiau | 770de83d | 2014-03-20 20:45:01 +0000 | [diff] [blame] | 3248 | #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ |
| 3249 | (GEN9_PIPE_CURSOR_FAULT | \ |
Damien Lespiau | b21249c | 2015-03-17 11:39:33 +0200 | [diff] [blame] | 3250 | GEN9_PIPE_PLANE4_FAULT | \ |
Damien Lespiau | 770de83d | 2014-03-20 20:45:01 +0000 | [diff] [blame] | 3251 | GEN9_PIPE_PLANE3_FAULT | \ |
| 3252 | GEN9_PIPE_PLANE2_FAULT | \ |
| 3253 | GEN9_PIPE_PLANE1_FAULT) |
Matt Roper | d506a65 | 2019-10-08 14:17:16 -0700 | [diff] [blame] | 3254 | #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \ |
| 3255 | (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ |
| 3256 | GEN11_PIPE_PLANE7_FAULT | \ |
| 3257 | GEN11_PIPE_PLANE6_FAULT | \ |
| 3258 | GEN11_PIPE_PLANE5_FAULT) |
Matt Roper | 99e2d8b | 2020-05-04 15:52:12 -0700 | [diff] [blame] | 3259 | #define RKL_DE_PIPE_IRQ_FAULT_ERRORS \ |
| 3260 | (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ |
| 3261 | GEN11_PIPE_PLANE5_FAULT) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3262 | |
Ville Syrjälä | 8625b22 | 2020-10-28 23:33:11 +0200 | [diff] [blame] | 3263 | #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) |
Ville Syrjälä | 5b76e86 | 2020-10-28 23:33:14 +0200 | [diff] [blame] | 3264 | #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1) |
Ville Syrjälä | 8625b22 | 2020-10-28 23:33:11 +0200 | [diff] [blame] | 3265 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3266 | #define GEN8_DE_PORT_ISR _MMIO(0x44440) |
| 3267 | #define GEN8_DE_PORT_IMR _MMIO(0x44444) |
| 3268 | #define GEN8_DE_PORT_IIR _MMIO(0x44448) |
| 3269 | #define GEN8_DE_PORT_IER _MMIO(0x4444c) |
Vandita Kulkarni | 64ad532 | 2019-11-11 16:40:21 +0530 | [diff] [blame] | 3270 | #define DSI1_NON_TE (1 << 31) |
| 3271 | #define DSI0_NON_TE (1 << 30) |
James Ausmus | bb187e9 | 2018-06-11 17:25:12 -0700 | [diff] [blame] | 3272 | #define ICL_AUX_CHANNEL_E (1 << 29) |
Lucas De Marchi | 938a8a9 | 2021-07-28 14:59:37 -0700 | [diff] [blame] | 3273 | #define ICL_AUX_CHANNEL_F (1 << 28) |
Jesse Barnes | 88e0470 | 2014-11-13 17:51:48 +0000 | [diff] [blame] | 3274 | #define GEN9_AUX_CHANNEL_D (1 << 27) |
| 3275 | #define GEN9_AUX_CHANNEL_C (1 << 26) |
| 3276 | #define GEN9_AUX_CHANNEL_B (1 << 25) |
Vandita Kulkarni | 64ad532 | 2019-11-11 16:40:21 +0530 | [diff] [blame] | 3277 | #define DSI1_TE (1 << 24) |
| 3278 | #define DSI0_TE (1 << 23) |
Ville Syrjälä | e5abaab | 2020-10-28 23:33:12 +0200 | [diff] [blame] | 3279 | #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) |
| 3280 | #define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \ |
| 3281 | GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \ |
| 3282 | GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) |
| 3283 | #define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) |
Shashank Sharma | 9e63743 | 2014-08-22 17:40:43 +0530 | [diff] [blame] | 3284 | #define BXT_DE_PORT_GMBUS (1 << 1) |
Daniel Vetter | 6d766f0 | 2013-11-07 14:49:55 +0100 | [diff] [blame] | 3285 | #define GEN8_AUX_CHANNEL_A (1 << 0) |
Matt Roper | 20fe778 | 2021-05-11 21:21:38 -0700 | [diff] [blame] | 3286 | #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13) |
| 3287 | #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13) |
| 3288 | #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12) |
| 3289 | #define XELPD_DE_PORT_AUX_DDID REG_BIT(12) |
| 3290 | #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11) |
| 3291 | #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10) |
| 3292 | #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9) |
| 3293 | #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8) |
| 3294 | #define TGL_DE_PORT_AUX_DDIC REG_BIT(2) |
| 3295 | #define TGL_DE_PORT_AUX_DDIB REG_BIT(1) |
| 3296 | #define TGL_DE_PORT_AUX_DDIA REG_BIT(0) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3297 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3298 | #define GEN8_DE_MISC_ISR _MMIO(0x44460) |
| 3299 | #define GEN8_DE_MISC_IMR _MMIO(0x44464) |
| 3300 | #define GEN8_DE_MISC_IIR _MMIO(0x44468) |
| 3301 | #define GEN8_DE_MISC_IER _MMIO(0x4446c) |
Mika Kahola | 4c4cc7a | 2023-06-06 23:10:32 +0300 | [diff] [blame] | 3302 | #define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27) |
| 3303 | #define GEN8_DE_MISC_GSE REG_BIT(27) |
| 3304 | #define GEN8_DE_EDP_PSR REG_BIT(19) |
| 3305 | #define XELPDP_PMDEMAND_RSP REG_BIT(3) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3306 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3307 | #define GEN8_PCU_ISR _MMIO(0x444e0) |
| 3308 | #define GEN8_PCU_IMR _MMIO(0x444e4) |
| 3309 | #define GEN8_PCU_IIR _MMIO(0x444e8) |
| 3310 | #define GEN8_PCU_IER _MMIO(0x444ec) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3311 | |
Dhinakaran Pandiyan | df0d28c | 2018-06-15 17:05:28 -0700 | [diff] [blame] | 3312 | #define GEN11_GU_MISC_ISR _MMIO(0x444f0) |
| 3313 | #define GEN11_GU_MISC_IMR _MMIO(0x444f4) |
| 3314 | #define GEN11_GU_MISC_IIR _MMIO(0x444f8) |
| 3315 | #define GEN11_GU_MISC_IER _MMIO(0x444fc) |
| 3316 | #define GEN11_GU_MISC_GSE (1 << 27) |
| 3317 | |
Tvrtko Ursulin | a6358dd | 2018-01-09 21:23:13 -0200 | [diff] [blame] | 3318 | #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) |
| 3319 | #define GEN11_MASTER_IRQ (1 << 31) |
| 3320 | #define GEN11_PCU_IRQ (1 << 30) |
Dhinakaran Pandiyan | df0d28c | 2018-06-15 17:05:28 -0700 | [diff] [blame] | 3321 | #define GEN11_GU_MISC_IRQ (1 << 29) |
Tvrtko Ursulin | a6358dd | 2018-01-09 21:23:13 -0200 | [diff] [blame] | 3322 | #define GEN11_DISPLAY_IRQ (1 << 16) |
| 3323 | #define GEN11_GT_DW_IRQ(x) (1 << (x)) |
| 3324 | #define GEN11_GT_DW1_IRQ (1 << 1) |
| 3325 | #define GEN11_GT_DW0_IRQ (1 << 0) |
| 3326 | |
Paulo Zanoni | 22e26af | 2021-07-21 15:30:29 -0700 | [diff] [blame] | 3327 | #define DG1_MSTR_TILE_INTR _MMIO(0x190008) |
Lucas De Marchi | 97b492f | 2020-07-13 11:23:19 -0700 | [diff] [blame] | 3328 | #define DG1_MSTR_IRQ REG_BIT(31) |
Paulo Zanoni | 22e26af | 2021-07-21 15:30:29 -0700 | [diff] [blame] | 3329 | #define DG1_MSTR_TILE(t) REG_BIT(t) |
Lucas De Marchi | 97b492f | 2020-07-13 11:23:19 -0700 | [diff] [blame] | 3330 | |
Tvrtko Ursulin | a6358dd | 2018-01-09 21:23:13 -0200 | [diff] [blame] | 3331 | #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) |
| 3332 | #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) |
| 3333 | #define GEN11_AUDIO_CODEC_IRQ (1 << 24) |
| 3334 | #define GEN11_DE_PCH_IRQ (1 << 23) |
| 3335 | #define GEN11_DE_MISC_IRQ (1 << 22) |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 3336 | #define GEN11_DE_HPD_IRQ (1 << 21) |
Tvrtko Ursulin | a6358dd | 2018-01-09 21:23:13 -0200 | [diff] [blame] | 3337 | #define GEN11_DE_PORT_IRQ (1 << 20) |
| 3338 | #define GEN11_DE_PIPE_C (1 << 18) |
| 3339 | #define GEN11_DE_PIPE_B (1 << 17) |
| 3340 | #define GEN11_DE_PIPE_A (1 << 16) |
| 3341 | |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 3342 | #define GEN11_DE_HPD_ISR _MMIO(0x44470) |
| 3343 | #define GEN11_DE_HPD_IMR _MMIO(0x44474) |
| 3344 | #define GEN11_DE_HPD_IIR _MMIO(0x44478) |
| 3345 | #define GEN11_DE_HPD_IER _MMIO(0x4447c) |
Ville Syrjälä | 5b76e86 | 2020-10-28 23:33:14 +0200 | [diff] [blame] | 3346 | #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) |
| 3347 | #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \ |
| 3348 | GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \ |
| 3349 | GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \ |
| 3350 | GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \ |
| 3351 | GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \ |
| 3352 | GEN11_TC_HOTPLUG(HPD_PORT_TC1)) |
| 3353 | #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) |
| 3354 | #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \ |
| 3355 | GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \ |
| 3356 | GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \ |
| 3357 | GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \ |
| 3358 | GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \ |
| 3359 | GEN11_TBT_HOTPLUG(HPD_PORT_TC1)) |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 3360 | |
Dhinakaran Pandiyan | b796b97 | 2018-06-15 17:05:30 -0700 | [diff] [blame] | 3361 | #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 3362 | #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) |
Ville Syrjälä | 5b76e86 | 2020-10-28 23:33:14 +0200 | [diff] [blame] | 3363 | #define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) |
| 3364 | #define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) |
| 3365 | #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) |
| 3366 | #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4)) |
Dhinakaran Pandiyan | 121e758 | 2018-06-15 17:05:29 -0700 | [diff] [blame] | 3367 | |
Mika Kahola | babde06 | 2023-04-13 14:24:39 -0700 | [diff] [blame] | 3368 | #define PICAINTERRUPT_ISR _MMIO(0x16FE50) |
| 3369 | #define PICAINTERRUPT_IMR _MMIO(0x16FE54) |
| 3370 | #define PICAINTERRUPT_IIR _MMIO(0x16FE58) |
| 3371 | #define PICAINTERRUPT_IER _MMIO(0x16FE5C) |
Mika Kahola | babde06 | 2023-04-13 14:24:39 -0700 | [diff] [blame] | 3372 | #define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) |
| 3373 | #define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16) |
Mika Kahola | babde06 | 2023-04-13 14:24:39 -0700 | [diff] [blame] | 3374 | #define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin)) |
| 3375 | #define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8) |
Gustavo Sousa | 925163b | 2023-09-19 12:21:19 -0700 | [diff] [blame] | 3376 | #define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin)) |
| 3377 | #define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6) |
Mika Kahola | babde06 | 2023-04-13 14:24:39 -0700 | [diff] [blame] | 3378 | #define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) |
| 3379 | #define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0) |
| 3380 | |
| 3381 | #define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200)) |
| 3382 | #define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6) |
| 3383 | #define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5) |
| 3384 | #define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4) |
| 3385 | #define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2) |
| 3386 | #define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1) |
| 3387 | #define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0) |
| 3388 | |
Mika Kahola | 4c4cc7a | 2023-06-06 23:10:32 +0300 | [diff] [blame] | 3389 | #define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword)) |
| 3390 | #define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16) |
| 3391 | #define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12) |
| 3392 | #define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8) |
| 3393 | #define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6) |
| 3394 | #define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4) |
| 3395 | #define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0) |
| 3396 | |
| 3397 | #define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31) |
| 3398 | #define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20) |
| 3399 | #define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8) |
| 3400 | #define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4) |
| 3401 | #define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0) |
| 3402 | |
| 3403 | #define GEN12_DCPR_STATUS_1 _MMIO(0x46440) |
| 3404 | #define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26) |
| 3405 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3406 | #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) |
Eric Anholt | 67e92af | 2010-11-06 14:53:33 -0700 | [diff] [blame] | 3407 | /* Required on all Ironlake and Sandybridge according to the B-Spec. */ |
Ville Syrjälä | 3df3c589 | 2023-04-11 22:14:23 +0300 | [diff] [blame] | 3408 | #define ILK_ELPIN_409_SELECT REG_BIT(25) |
| 3409 | #define ILK_DPARB_GATE REG_BIT(22) |
| 3410 | #define ILK_VSDPFD_FULL REG_BIT(21) |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 3411 | |
Ville Syrjälä | 3df3c589 | 2023-04-11 22:14:23 +0300 | [diff] [blame] | 3412 | #define FUSE_STRAP _MMIO(0x42014) |
| 3413 | #define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31) |
| 3414 | #define ILK_INTERNAL_DISPLAY_DISABLE REG_BIT(30) |
| 3415 | #define ILK_DISPLAY_DEBUG_DISABLE REG_BIT(29) |
| 3416 | #define IVB_PIPE_C_DISABLE REG_BIT(28) |
| 3417 | #define ILK_HDCP_DISABLE REG_BIT(25) |
| 3418 | #define ILK_eDP_A_DISABLE REG_BIT(24) |
| 3419 | #define HSW_CDCLK_LIMIT REG_BIT(24) |
| 3420 | #define ILK_DESKTOP REG_BIT(23) |
| 3421 | #define HSW_CPU_SSC_ENABLE REG_BIT(21) |
Ville Syrjälä | 8676178 | 2019-06-04 23:09:33 +0300 | [diff] [blame] | 3422 | |
Ville Syrjälä | 3df3c589 | 2023-04-11 22:14:23 +0300 | [diff] [blame] | 3423 | #define FUSE_STRAP3 _MMIO(0x42020) |
| 3424 | #define HSW_REF_CLK_SELECT REG_BIT(1) |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3425 | |
Ville Syrjälä | 3df3c589 | 2023-04-11 22:14:23 +0300 | [diff] [blame] | 3426 | #define ILK_DSPCLK_GATE_D _MMIO(0x42020) |
| 3427 | #define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28) |
| 3428 | #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9) |
| 3429 | #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE REG_BIT(8) |
| 3430 | #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE REG_BIT(7) |
| 3431 | #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE REG_BIT(5) |
Eric Anholt | 116ac8d | 2011-12-21 10:31:09 -0800 | [diff] [blame] | 3432 | |
Ville Syrjälä | 3df3c589 | 2023-04-11 22:14:23 +0300 | [diff] [blame] | 3433 | #define IVB_CHICKEN3 _MMIO(0x4200c) |
| 3434 | #define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5) |
| 3435 | #define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2) |
| 3436 | |
| 3437 | #define CHICKEN_PAR1_1 _MMIO(0x42080) |
Ville Syrjälä | 3d0d333 | 2023-04-11 22:14:22 +0300 | [diff] [blame] | 3438 | #define IGNORE_KVMR_PIPE_A REG_BIT(23) |
| 3439 | #define KBL_ARB_FILL_SPARE_22 REG_BIT(22) |
Ville Syrjälä | 3df3c589 | 2023-04-11 22:14:23 +0300 | [diff] [blame] | 3440 | #define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16) |
| 3441 | #define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15) |
Ville Syrjälä | 2590ef9 | 2023-04-11 22:14:26 +0300 | [diff] [blame] | 3442 | #define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */ |
Ville Syrjälä | 3df3c589 | 2023-04-11 22:14:23 +0300 | [diff] [blame] | 3443 | #define FORCE_ARB_IDLE_PLANES REG_BIT(14) |
| 3444 | #define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3) |
| 3445 | #define IGNORE_PSR2_HW_TRACKING REG_BIT(1) |
Paulo Zanoni | 90a8864 | 2013-05-03 17:23:45 -0300 | [diff] [blame] | 3446 | |
Mika Kuoppala | 17e0adf | 2016-06-07 17:19:02 +0300 | [diff] [blame] | 3447 | #define CHICKEN_PAR2_1 _MMIO(0x42090) |
Ville Syrjälä | 3df3c589 | 2023-04-11 22:14:23 +0300 | [diff] [blame] | 3448 | #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14) |
Mika Kuoppala | 17e0adf | 2016-06-07 17:19:02 +0300 | [diff] [blame] | 3449 | |
Ander Conselvan de Oliveira | f4f4b59 | 2017-02-22 08:34:29 +0200 | [diff] [blame] | 3450 | #define CHICKEN_MISC_2 _MMIO(0x42084) |
Ville Syrjälä | 3d0d333 | 2023-04-11 22:14:22 +0300 | [diff] [blame] | 3451 | #define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */ |
| 3452 | #define KBL_ARB_FILL_SPARE_14 REG_BIT(14) |
| 3453 | #define KBL_ARB_FILL_SPARE_13 REG_BIT(13) |
Ville Syrjälä | 3df3c589 | 2023-04-11 22:14:23 +0300 | [diff] [blame] | 3454 | #define GLK_CL2_PWR_DOWN REG_BIT(12) |
| 3455 | #define GLK_CL1_PWR_DOWN REG_BIT(11) |
| 3456 | #define GLK_CL0_PWR_DOWN REG_BIT(10) |
Ville Syrjälä | d8d4a51 | 2017-06-09 15:26:00 -0700 | [diff] [blame] | 3457 | |
Imre Deak | 9655a9a | 2024-01-29 19:55:28 +0200 | [diff] [blame] | 3458 | #define CHICKEN_MISC_3 _MMIO(0x42088) |
Imre Deak | d4e745b | 2024-01-29 19:55:30 +0200 | [diff] [blame] | 3459 | #define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A) |
Imre Deak | 1af52d0 | 2024-01-29 19:55:29 +0200 | [diff] [blame] | 3460 | #define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A) |
Imre Deak | 9655a9a | 2024-01-29 19:55:28 +0200 | [diff] [blame] | 3461 | #define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A) |
| 3462 | |
Praveen Paneri | 5654a16 | 2017-08-11 00:00:33 +0530 | [diff] [blame] | 3463 | #define CHICKEN_MISC_4 _MMIO(0x4208c) |
Ville Syrjälä | 2670ff5 | 2021-07-02 23:45:59 +0300 | [diff] [blame] | 3464 | #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13) |
| 3465 | #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0) |
| 3466 | #define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x)) |
Praveen Paneri | 5654a16 | 2017-08-11 00:00:33 +0530 | [diff] [blame] | 3467 | |
Ben Widawsky | fe4ab3c | 2013-11-02 21:07:54 -0700 | [diff] [blame] | 3468 | #define _CHICKEN_PIPESL_1_A 0x420b0 |
| 3469 | #define _CHICKEN_PIPESL_1_B 0x420b4 |
Ville Syrjälä | 3d0d333 | 2023-04-11 22:14:22 +0300 | [diff] [blame] | 3470 | #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) |
| 3471 | #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27) |
| 3472 | #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0) |
| 3473 | #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1) |
| 3474 | #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2) |
| 3475 | #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3) |
| 3476 | #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25) |
| 3477 | #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0) |
| 3478 | #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1) |
| 3479 | #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2) |
| 3480 | #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3) |
Ville Syrjälä | 3df3c589 | 2023-04-11 22:14:23 +0300 | [diff] [blame] | 3481 | #define HSW_FBCQ_DIS REG_BIT(22) |
Ville Syrjälä | 2590ef9 | 2023-04-11 22:14:26 +0300 | [diff] [blame] | 3482 | #define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */ |
| 3483 | #define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */ |
Ville Syrjälä | 3d0d333 | 2023-04-11 22:14:22 +0300 | [diff] [blame] | 3484 | #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0) |
| 3485 | #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0) |
| 3486 | #define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1) |
| 3487 | #define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2) |
| 3488 | #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) |
Ville Syrjälä | 2590ef9 | 2023-04-11 22:14:26 +0300 | [diff] [blame] | 3489 | #define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */ |
Ben Widawsky | fe4ab3c | 2013-11-02 21:07:54 -0700 | [diff] [blame] | 3490 | |
Ville Syrjälä | 12c4d4c | 2019-10-24 15:21:36 +0300 | [diff] [blame] | 3491 | #define _CHICKEN_TRANS_A 0x420c0 |
| 3492 | #define _CHICKEN_TRANS_B 0x420c4 |
| 3493 | #define _CHICKEN_TRANS_C 0x420c8 |
| 3494 | #define _CHICKEN_TRANS_EDP 0x420cc |
Ville Syrjälä | 1d581dc | 2019-10-24 15:21:37 +0300 | [diff] [blame] | 3495 | #define _CHICKEN_TRANS_D 0x420d8 |
Ville Syrjälä | 12c4d4c | 2019-10-24 15:21:36 +0300 | [diff] [blame] | 3496 | #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ |
| 3497 | [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ |
| 3498 | [TRANSCODER_A] = _CHICKEN_TRANS_A, \ |
| 3499 | [TRANSCODER_B] = _CHICKEN_TRANS_B, \ |
Ville Syrjälä | 1d581dc | 2019-10-24 15:21:37 +0300 | [diff] [blame] | 3500 | [TRANSCODER_C] = _CHICKEN_TRANS_C, \ |
| 3501 | [TRANSCODER_D] = _CHICKEN_TRANS_D)) |
Madhumitha Tolakanahalli Pradeep | 4aaa1a9 | 2022-09-13 11:33:41 -0700 | [diff] [blame] | 3502 | #define _MTL_CHICKEN_TRANS_A 0x604e0 |
| 3503 | #define _MTL_CHICKEN_TRANS_B 0x614e0 |
| 3504 | #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \ |
| 3505 | _MTL_CHICKEN_TRANS_A, \ |
| 3506 | _MTL_CHICKEN_TRANS_B) |
Ville Syrjälä | 810e451 | 2024-03-06 06:08:04 +0200 | [diff] [blame] | 3507 | #define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */ |
Ville Syrjälä | 2590ef9 | 2023-04-11 22:14:26 +0300 | [diff] [blame] | 3508 | #define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */ |
Ville Syrjälä | 3d0d333 | 2023-04-11 22:14:22 +0300 | [diff] [blame] | 3509 | #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) |
| 3510 | #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x) |
| 3511 | #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */ |
| 3512 | #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23) |
| 3513 | #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19) |
| 3514 | #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18) |
| 3515 | #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18) |
| 3516 | #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */ |
| 3517 | #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */ |
| 3518 | #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) |
Imre Deak | 8f6372a | 2024-01-29 19:55:33 +0200 | [diff] [blame] | 3519 | #define DP_FEC_BS_JITTER_WA REG_BIT(15) |
Ville Syrjälä | 3d0d333 | 2023-04-11 22:14:22 +0300 | [diff] [blame] | 3520 | #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) |
Imre Deak | 7e3025c | 2024-01-29 19:55:32 +0200 | [diff] [blame] | 3521 | #define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4) |
Nagaraju, Vathsala | d86f048 | 2017-01-13 00:31:31 +0530 | [diff] [blame] | 3522 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3523 | #define DISP_ARB_CTL _MMIO(0x45000) |
Ville Syrjälä | 3df3c589 | 2023-04-11 22:14:23 +0300 | [diff] [blame] | 3524 | #define DISP_FBC_MEMORY_WAKE REG_BIT(31) |
| 3525 | #define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13) |
| 3526 | #define DISP_FBC_WM_DIS REG_BIT(15) |
| 3527 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3528 | #define DISP_ARB_CTL2 _MMIO(0x45004) |
Ville Syrjälä | 3df3c589 | 2023-04-11 22:14:23 +0300 | [diff] [blame] | 3529 | #define DISP_DATA_PARTITION_5_6 REG_BIT(6) |
| 3530 | #define DISP_IPC_ENABLE REG_BIT(3) |
José Roberto de Souza | 359d0ef | 2020-10-19 10:39:06 -0700 | [diff] [blame] | 3531 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3532 | #define GEN7_MSG_CTL _MMIO(0x45010) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 3533 | #define WAIT_FOR_PCH_RESET_ACK (1 << 1) |
| 3534 | #define WAIT_FOR_PCH_FLR_ACK (1 << 0) |
Matt Roper | 3fa01d6 | 2019-12-05 14:48:48 -0800 | [diff] [blame] | 3535 | |
Matt Roper | 62afef2 | 2020-06-05 19:57:34 -0700 | [diff] [blame] | 3536 | #define _BW_BUDDY0_CTL 0x45130 |
| 3537 | #define _BW_BUDDY1_CTL 0x45140 |
| 3538 | #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ |
| 3539 | _BW_BUDDY0_CTL, \ |
| 3540 | _BW_BUDDY1_CTL)) |
Matt Roper | 3fa01d6 | 2019-12-05 14:48:48 -0800 | [diff] [blame] | 3541 | #define BW_BUDDY_DISABLE REG_BIT(31) |
Matt Roper | 87e04f7 | 2020-02-19 13:56:55 -0800 | [diff] [blame] | 3542 | #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) |
Matt Roper | 62afef2 | 2020-06-05 19:57:34 -0700 | [diff] [blame] | 3543 | #define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) |
Matt Roper | 3fa01d6 | 2019-12-05 14:48:48 -0800 | [diff] [blame] | 3544 | |
Matt Roper | 62afef2 | 2020-06-05 19:57:34 -0700 | [diff] [blame] | 3545 | #define _BW_BUDDY0_PAGE_MASK 0x45134 |
| 3546 | #define _BW_BUDDY1_PAGE_MASK 0x45144 |
| 3547 | #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ |
| 3548 | _BW_BUDDY0_PAGE_MASK, \ |
| 3549 | _BW_BUDDY1_PAGE_MASK)) |
Matt Roper | 3fa01d6 | 2019-12-05 14:48:48 -0800 | [diff] [blame] | 3550 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3551 | #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) |
Radhakrishna Sripada | 61c8657 | 2022-08-18 16:41:50 -0700 | [diff] [blame] | 3552 | #define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6) |
| 3553 | #define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4) |
Zhenyu Wang | 553bd14 | 2009-09-02 10:57:52 +0800 | [diff] [blame] | 3554 | |
José Roberto de Souza | 79af240 | 2022-02-10 10:52:23 -0800 | [diff] [blame] | 3555 | #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) |
Jouni Högander | af9f44d | 2023-01-05 08:56:37 +0200 | [diff] [blame] | 3556 | #define LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31) |
José Roberto de Souza | 79af240 | 2022-02-10 10:52:23 -0800 | [diff] [blame] | 3557 | #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) |
| 3558 | #define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25) |
| 3559 | #define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24) |
| 3560 | #define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23) |
| 3561 | #define ICL_DELAY_PMRSP REG_BIT(22) |
| 3562 | #define DISABLE_FLR_SRC REG_BIT(15) |
| 3563 | #define MASK_WAKEMEM REG_BIT(13) |
Imre Deak | 59207e6 | 2022-03-23 22:17:49 +0200 | [diff] [blame] | 3564 | #define DDI_CLOCK_REG_ACCESS REG_BIT(7) |
Mika Kuoppala | 590e8ff | 2016-06-07 17:19:13 +0300 | [diff] [blame] | 3565 | |
Matt Atwood | af9e103 | 2020-06-24 14:57:23 -0700 | [diff] [blame] | 3566 | #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) |
| 3567 | #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) |
| 3568 | #define DCPR_MASK_LPMODE REG_BIT(26) |
| 3569 | #define DCPR_SEND_RESP_IMM REG_BIT(25) |
| 3570 | #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24) |
| 3571 | |
Mika Kahola | 4c4cc7a | 2023-06-06 23:10:32 +0300 | [diff] [blame] | 3572 | #define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438) |
| 3573 | #define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19) |
| 3574 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3575 | #define SKL_DFSM _MMIO(0x51000) |
José Roberto de Souza | 7a40aac | 2019-10-25 17:13:21 -0700 | [diff] [blame] | 3576 | #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) |
José Roberto de Souza | 7439310 | 2019-10-25 17:13:20 -0700 | [diff] [blame] | 3577 | #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) |
José Roberto de Souza | a20e26d | 2019-10-25 17:13:19 -0700 | [diff] [blame] | 3578 | #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) |
| 3579 | #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) |
| 3580 | #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) |
| 3581 | #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) |
| 3582 | #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) |
José Roberto de Souza | ee59588 | 2019-10-25 17:13:22 -0700 | [diff] [blame] | 3583 | #define ICL_DFSM_DMC_DISABLE (1 << 23) |
José Roberto de Souza | a20e26d | 2019-10-25 17:13:19 -0700 | [diff] [blame] | 3584 | #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) |
| 3585 | #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) |
| 3586 | #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) |
| 3587 | #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) |
Lucas De Marchi | a4d082f | 2021-07-28 14:59:45 -0700 | [diff] [blame] | 3588 | #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7) |
Damien Lespiau | a9419e8 | 2015-06-04 18:21:30 +0100 | [diff] [blame] | 3589 | |
Vinod Govindapillai | 9a3acd8 | 2023-10-01 14:31:53 +0300 | [diff] [blame] | 3590 | #define XE2LPD_DE_CAP _MMIO(0x41100) |
| 3591 | #define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30) |
| 3592 | #define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28) |
| 3593 | #define XE2LPD_DE_CAP_DSC_REMOVED 1 |
| 3594 | #define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26) |
| 3595 | #define XE2LPD_DE_CAP_SCALER_SINGLE 1 |
| 3596 | |
Paulo Zanoni | 186a277 | 2018-02-06 17:33:46 -0200 | [diff] [blame] | 3597 | #define SKL_DSSM _MMIO(0x51004) |
Paulo Zanoni | 186a277 | 2018-02-06 17:33:46 -0200 | [diff] [blame] | 3598 | #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) |
| 3599 | #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) |
| 3600 | #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) |
| 3601 | #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) |
Ville Syrjälä | 945f267 | 2017-06-09 15:25:58 -0700 | [diff] [blame] | 3602 | |
Matt Roper | c2c7075 | 2022-09-15 18:46:46 -0700 | [diff] [blame] | 3603 | #define GMD_ID_DISPLAY _MMIO(0x510a0) |
| 3604 | #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) |
| 3605 | #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) |
| 3606 | #define GMD_ID_STEP REG_GENMASK(5, 0) |
| 3607 | |
Vandita Kulkarni | e16a375 | 2018-06-21 20:43:56 +0530 | [diff] [blame] | 3608 | /*GEN11 chicken */ |
Aditya Swarup | 26eeea1 | 2019-03-06 18:14:12 -0800 | [diff] [blame] | 3609 | #define _PIPEA_CHICKEN 0x70038 |
| 3610 | #define _PIPEB_CHICKEN 0x71038 |
| 3611 | #define _PIPEC_CHICKEN 0x72038 |
| 3612 | #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ |
| 3613 | _PIPEB_CHICKEN) |
Matt Roper | ba3b049 | 2021-07-27 07:50:56 -0700 | [diff] [blame] | 3614 | #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) |
| 3615 | #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) |
Matt Roper | 7cbea1b | 2021-11-16 09:48:15 -0800 | [diff] [blame] | 3616 | #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15) |
| 3617 | #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12) |
| 3618 | #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7) |
Vandita Kulkarni | e16a375 | 2018-06-21 20:43:56 +0530 | [diff] [blame] | 3619 | |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3620 | /* PCH */ |
| 3621 | |
Lucas De Marchi | dce8887 | 2018-07-27 12:36:47 -0700 | [diff] [blame] | 3622 | #define PCH_DISPLAY_BASE 0xc0000u |
| 3623 | |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 3624 | /* south display engine interrupt: IBX */ |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 3625 | #define SDE_AUDIO_POWER_D (1 << 27) |
| 3626 | #define SDE_AUDIO_POWER_C (1 << 26) |
| 3627 | #define SDE_AUDIO_POWER_B (1 << 25) |
| 3628 | #define SDE_AUDIO_POWER_SHIFT (25) |
| 3629 | #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) |
| 3630 | #define SDE_GMBUS (1 << 24) |
| 3631 | #define SDE_AUDIO_HDCP_TRANSB (1 << 23) |
| 3632 | #define SDE_AUDIO_HDCP_TRANSA (1 << 22) |
| 3633 | #define SDE_AUDIO_HDCP_MASK (3 << 22) |
| 3634 | #define SDE_AUDIO_TRANSB (1 << 21) |
| 3635 | #define SDE_AUDIO_TRANSA (1 << 20) |
| 3636 | #define SDE_AUDIO_TRANS_MASK (3 << 20) |
| 3637 | #define SDE_POISON (1 << 19) |
| 3638 | /* 18 reserved */ |
| 3639 | #define SDE_FDI_RXB (1 << 17) |
| 3640 | #define SDE_FDI_RXA (1 << 16) |
| 3641 | #define SDE_FDI_MASK (3 << 16) |
| 3642 | #define SDE_AUXD (1 << 15) |
| 3643 | #define SDE_AUXC (1 << 14) |
| 3644 | #define SDE_AUXB (1 << 13) |
| 3645 | #define SDE_AUX_MASK (7 << 13) |
| 3646 | /* 12 reserved */ |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3647 | #define SDE_CRT_HOTPLUG (1 << 11) |
| 3648 | #define SDE_PORTD_HOTPLUG (1 << 10) |
| 3649 | #define SDE_PORTC_HOTPLUG (1 << 9) |
| 3650 | #define SDE_PORTB_HOTPLUG (1 << 8) |
| 3651 | #define SDE_SDVOB_HOTPLUG (1 << 6) |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 3652 | #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ |
| 3653 | SDE_SDVOB_HOTPLUG | \ |
| 3654 | SDE_PORTB_HOTPLUG | \ |
| 3655 | SDE_PORTC_HOTPLUG | \ |
| 3656 | SDE_PORTD_HOTPLUG) |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 3657 | #define SDE_TRANSB_CRC_DONE (1 << 5) |
| 3658 | #define SDE_TRANSB_CRC_ERR (1 << 4) |
| 3659 | #define SDE_TRANSB_FIFO_UNDER (1 << 3) |
| 3660 | #define SDE_TRANSA_CRC_DONE (1 << 2) |
| 3661 | #define SDE_TRANSA_CRC_ERR (1 << 1) |
| 3662 | #define SDE_TRANSA_FIFO_UNDER (1 << 0) |
| 3663 | #define SDE_TRANS_MASK (0x3f) |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 3664 | |
Anusha Srivatsa | 3160422 | 2018-06-26 13:52:23 -0700 | [diff] [blame] | 3665 | /* south display engine interrupt: CPT - CNP */ |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 3666 | #define SDE_AUDIO_POWER_D_CPT (1 << 31) |
| 3667 | #define SDE_AUDIO_POWER_C_CPT (1 << 30) |
| 3668 | #define SDE_AUDIO_POWER_B_CPT (1 << 29) |
| 3669 | #define SDE_AUDIO_POWER_SHIFT_CPT 29 |
| 3670 | #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) |
| 3671 | #define SDE_AUXD_CPT (1 << 27) |
| 3672 | #define SDE_AUXC_CPT (1 << 26) |
| 3673 | #define SDE_AUXB_CPT (1 << 25) |
| 3674 | #define SDE_AUX_MASK_CPT (7 << 25) |
Xiong Zhang | 26951ca | 2015-08-17 15:55:50 +0800 | [diff] [blame] | 3675 | #define SDE_PORTE_HOTPLUG_SPT (1 << 25) |
Ville Syrjälä | 74c0b39 | 2015-08-27 23:56:07 +0300 | [diff] [blame] | 3676 | #define SDE_PORTA_HOTPLUG_SPT (1 << 24) |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3677 | #define SDE_PORTD_HOTPLUG_CPT (1 << 23) |
| 3678 | #define SDE_PORTC_HOTPLUG_CPT (1 << 22) |
| 3679 | #define SDE_PORTB_HOTPLUG_CPT (1 << 21) |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 3680 | #define SDE_CRT_HOTPLUG_CPT (1 << 19) |
Daniel Vetter | 73c352a | 2013-03-26 22:38:43 +0100 | [diff] [blame] | 3681 | #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 3682 | #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ |
Daniel Vetter | 73c352a | 2013-03-26 22:38:43 +0100 | [diff] [blame] | 3683 | SDE_SDVOB_HOTPLUG_CPT | \ |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 3684 | SDE_PORTD_HOTPLUG_CPT | \ |
| 3685 | SDE_PORTC_HOTPLUG_CPT | \ |
| 3686 | SDE_PORTB_HOTPLUG_CPT) |
Xiong Zhang | 26951ca | 2015-08-17 15:55:50 +0800 | [diff] [blame] | 3687 | #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ |
| 3688 | SDE_PORTD_HOTPLUG_CPT | \ |
| 3689 | SDE_PORTC_HOTPLUG_CPT | \ |
Ville Syrjälä | 74c0b39 | 2015-08-27 23:56:07 +0300 | [diff] [blame] | 3690 | SDE_PORTB_HOTPLUG_CPT | \ |
| 3691 | SDE_PORTA_HOTPLUG_SPT) |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 3692 | #define SDE_GMBUS_CPT (1 << 17) |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 3693 | #define SDE_ERROR_CPT (1 << 16) |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 3694 | #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) |
| 3695 | #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) |
| 3696 | #define SDE_FDI_RXC_CPT (1 << 8) |
| 3697 | #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) |
| 3698 | #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) |
| 3699 | #define SDE_FDI_RXB_CPT (1 << 4) |
| 3700 | #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) |
| 3701 | #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) |
| 3702 | #define SDE_FDI_RXA_CPT (1 << 0) |
| 3703 | #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ |
| 3704 | SDE_AUDIO_CP_REQ_B_CPT | \ |
| 3705 | SDE_AUDIO_CP_REQ_A_CPT) |
| 3706 | #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ |
| 3707 | SDE_AUDIO_CP_CHG_B_CPT | \ |
| 3708 | SDE_AUDIO_CP_CHG_A_CPT) |
| 3709 | #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ |
| 3710 | SDE_FDI_RXB_CPT | \ |
| 3711 | SDE_FDI_RXA_CPT) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3712 | |
Mika Kahola | babde06 | 2023-04-13 14:24:39 -0700 | [diff] [blame] | 3713 | /* south display engine interrupt: ICP/TGP/MTP */ |
| 3714 | #define SDE_PICAINTERRUPT REG_BIT(31) |
Anusha Srivatsa | 3160422 | 2018-06-26 13:52:23 -0700 | [diff] [blame] | 3715 | #define SDE_GMBUS_ICP (1 << 23) |
Ville Syrjälä | 9701135 | 2020-10-28 23:33:15 +0200 | [diff] [blame] | 3716 | #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin)) |
Matt Roper | 2f8a669 | 2022-02-17 17:03:28 -0800 | [diff] [blame] | 3717 | #define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */ |
Ville Syrjälä | 5f371a8 | 2020-10-28 23:33:13 +0200 | [diff] [blame] | 3718 | #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin)) |
Ville Syrjälä | e76ab2c | 2020-10-28 23:33:20 +0200 | [diff] [blame] | 3719 | #define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \ |
| 3720 | SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \ |
Ville Syrjälä | 5f371a8 | 2020-10-28 23:33:13 +0200 | [diff] [blame] | 3721 | SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ |
| 3722 | SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) |
Ville Syrjälä | e76ab2c | 2020-10-28 23:33:20 +0200 | [diff] [blame] | 3723 | #define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \ |
Ville Syrjälä | 9701135 | 2020-10-28 23:33:15 +0200 | [diff] [blame] | 3724 | SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \ |
| 3725 | SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \ |
| 3726 | SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ |
| 3727 | SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ |
| 3728 | SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) |
Anusha Srivatsa | 3160422 | 2018-06-26 13:52:23 -0700 | [diff] [blame] | 3729 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3730 | #define SDEISR _MMIO(0xc4000) |
| 3731 | #define SDEIMR _MMIO(0xc4004) |
| 3732 | #define SDEIIR _MMIO(0xc4008) |
| 3733 | #define SDEIER _MMIO(0xc400c) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3734 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3735 | #define SERR_INT _MMIO(0xc4040) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 3736 | #define SERR_INT_POISON (1 << 31) |
| 3737 | #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 3738 | |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3739 | /* digital port hotplug */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3740 | #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ |
Ville Syrjälä | 195baa0 | 2015-08-27 23:56:00 +0300 | [diff] [blame] | 3741 | #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ |
Shubhangi Shrivastava | d252bf6 | 2016-03-31 16:11:47 +0530 | [diff] [blame] | 3742 | #define BXT_DDIA_HPD_INVERT (1 << 27) |
Ville Syrjälä | 195baa0 | 2015-08-27 23:56:00 +0300 | [diff] [blame] | 3743 | #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ |
| 3744 | #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ |
| 3745 | #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ |
| 3746 | #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ |
Ville Syrjälä | 40bfd7a | 2015-08-27 23:55:56 +0300 | [diff] [blame] | 3747 | #define PORTD_HOTPLUG_ENABLE (1 << 20) |
| 3748 | #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ |
| 3749 | #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ |
| 3750 | #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ |
| 3751 | #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ |
| 3752 | #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ |
| 3753 | #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) |
Damien Lespiau | b696519 | 2012-12-13 16:08:59 +0000 | [diff] [blame] | 3754 | #define PORTD_HOTPLUG_NO_DETECT (0 << 16) |
| 3755 | #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) |
| 3756 | #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) |
Ville Syrjälä | 40bfd7a | 2015-08-27 23:55:56 +0300 | [diff] [blame] | 3757 | #define PORTC_HOTPLUG_ENABLE (1 << 12) |
Shubhangi Shrivastava | d252bf6 | 2016-03-31 16:11:47 +0530 | [diff] [blame] | 3758 | #define BXT_DDIC_HPD_INVERT (1 << 11) |
Ville Syrjälä | 40bfd7a | 2015-08-27 23:55:56 +0300 | [diff] [blame] | 3759 | #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ |
| 3760 | #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ |
| 3761 | #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ |
| 3762 | #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ |
| 3763 | #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ |
| 3764 | #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) |
Damien Lespiau | b696519 | 2012-12-13 16:08:59 +0000 | [diff] [blame] | 3765 | #define PORTC_HOTPLUG_NO_DETECT (0 << 8) |
| 3766 | #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) |
| 3767 | #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) |
Ville Syrjälä | 40bfd7a | 2015-08-27 23:55:56 +0300 | [diff] [blame] | 3768 | #define PORTB_HOTPLUG_ENABLE (1 << 4) |
Shubhangi Shrivastava | d252bf6 | 2016-03-31 16:11:47 +0530 | [diff] [blame] | 3769 | #define BXT_DDIB_HPD_INVERT (1 << 3) |
Ville Syrjälä | 40bfd7a | 2015-08-27 23:55:56 +0300 | [diff] [blame] | 3770 | #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ |
| 3771 | #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ |
| 3772 | #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ |
| 3773 | #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ |
| 3774 | #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ |
| 3775 | #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) |
Damien Lespiau | b696519 | 2012-12-13 16:08:59 +0000 | [diff] [blame] | 3776 | #define PORTB_HOTPLUG_NO_DETECT (0 << 0) |
| 3777 | #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) |
| 3778 | #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) |
Shubhangi Shrivastava | d252bf6 | 2016-03-31 16:11:47 +0530 | [diff] [blame] | 3779 | #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ |
| 3780 | BXT_DDIB_HPD_INVERT | \ |
| 3781 | BXT_DDIC_HPD_INVERT) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3782 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3783 | #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ |
Ville Syrjälä | 40bfd7a | 2015-08-27 23:55:56 +0300 | [diff] [blame] | 3784 | #define PORTE_HOTPLUG_ENABLE (1 << 4) |
| 3785 | #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) |
Xiong Zhang | 26951ca | 2015-08-17 15:55:50 +0800 | [diff] [blame] | 3786 | #define PORTE_HOTPLUG_NO_DETECT (0 << 0) |
| 3787 | #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) |
| 3788 | #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) |
| 3789 | |
Anusha Srivatsa | 3160422 | 2018-06-26 13:52:23 -0700 | [diff] [blame] | 3790 | /* This register is a reuse of PCH_PORT_HOTPLUG register. The |
| 3791 | * functionality covered in PCH_PORT_HOTPLUG is split into |
| 3792 | * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. |
| 3793 | */ |
| 3794 | |
Lucas De Marchi | ed3126f | 2019-08-29 14:15:23 -0700 | [diff] [blame] | 3795 | #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) |
Ville Syrjälä | 5f371a8 | 2020-10-28 23:33:13 +0200 | [diff] [blame] | 3796 | #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4)) |
Jani Nikula | f087cfe | 2022-12-19 12:59:55 +0200 | [diff] [blame] | 3797 | #define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4)) |
Ville Syrjälä | 5f371a8 | 2020-10-28 23:33:13 +0200 | [diff] [blame] | 3798 | #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) |
| 3799 | #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4)) |
| 3800 | #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4)) |
| 3801 | #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4)) |
| 3802 | #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) |
Anusha Srivatsa | 3160422 | 2018-06-26 13:52:23 -0700 | [diff] [blame] | 3803 | |
| 3804 | #define SHOTPLUG_CTL_TC _MMIO(0xc4034) |
Ville Syrjälä | 9701135 | 2020-10-28 23:33:15 +0200 | [diff] [blame] | 3805 | #define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) |
| 3806 | #define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) |
| 3807 | #define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) |
Matt Roper | f49108d | 2019-11-27 14:13:14 -0800 | [diff] [blame] | 3808 | |
| 3809 | #define SHPD_FILTER_CNT _MMIO(0xc4038) |
| 3810 | #define SHPD_FILTER_CNT_500_ADJ 0x001D9 |
Suraj Kandpal | 4948738 | 2023-07-20 16:16:24 +0530 | [diff] [blame] | 3811 | #define SHPD_FILTER_CNT_250 0x000F8 |
Matt Roper | f49108d | 2019-11-27 14:13:14 -0800 | [diff] [blame] | 3812 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 3813 | #define _PCH_DPLL_A 0xc6014 |
| 3814 | #define _PCH_DPLL_B 0xc6018 |
Paulo Zanoni | 9e8789e | 2018-06-12 16:56:54 -0700 | [diff] [blame] | 3815 | #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3816 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 3817 | #define _PCH_FPA0 0xc6040 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 3818 | #define FP_CB_TUNE (0x3 << 22) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 3819 | #define _PCH_FPA1 0xc6044 |
| 3820 | #define _PCH_FPB0 0xc6048 |
| 3821 | #define _PCH_FPB1 0xc604c |
Paulo Zanoni | 9e8789e | 2018-06-12 16:56:54 -0700 | [diff] [blame] | 3822 | #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) |
| 3823 | #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3824 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3825 | #define PCH_DPLL_TEST _MMIO(0xc606c) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3826 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3827 | #define PCH_DREF_CONTROL _MMIO(0xC6200) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3828 | #define DREF_CONTROL_MASK 0x7fc3 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 3829 | #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) |
| 3830 | #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) |
| 3831 | #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) |
| 3832 | #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) |
| 3833 | #define DREF_SSC_SOURCE_DISABLE (0 << 11) |
| 3834 | #define DREF_SSC_SOURCE_ENABLE (2 << 11) |
| 3835 | #define DREF_SSC_SOURCE_MASK (3 << 11) |
| 3836 | #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) |
| 3837 | #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) |
| 3838 | #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) |
| 3839 | #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) |
| 3840 | #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) |
| 3841 | #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) |
| 3842 | #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) |
| 3843 | #define DREF_SSC4_DOWNSPREAD (0 << 6) |
| 3844 | #define DREF_SSC4_CENTERSPREAD (1 << 6) |
| 3845 | #define DREF_SSC1_DISABLE (0 << 1) |
| 3846 | #define DREF_SSC1_ENABLE (1 << 1) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3847 | #define DREF_SSC4_DISABLE (0) |
| 3848 | #define DREF_SSC4_ENABLE (1) |
| 3849 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3850 | #define PCH_RAWCLK_FREQ _MMIO(0xc6204) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3851 | #define FDL_TP1_TIMER_SHIFT 12 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 3852 | #define FDL_TP1_TIMER_MASK (3 << 12) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3853 | #define FDL_TP2_TIMER_SHIFT 10 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 3854 | #define FDL_TP2_TIMER_MASK (3 << 10) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3855 | #define RAWCLK_FREQ_MASK 0x3ff |
Rodrigo Vivi | 9d81a99 | 2017-06-02 13:06:41 -0700 | [diff] [blame] | 3856 | #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) |
| 3857 | #define CNP_RAWCLK_DIV(div) ((div) << 16) |
| 3858 | #define CNP_RAWCLK_FRAC_MASK (0xf << 26) |
Paulo Zanoni | 228a5cf | 2018-11-12 15:23:12 -0800 | [diff] [blame] | 3859 | #define CNP_RAWCLK_DEN(den) ((den) << 26) |
Anusha Srivatsa | 4ef99ab | 2018-01-11 16:00:06 -0200 | [diff] [blame] | 3860 | #define ICP_RAWCLK_NUM(num) ((num) << 11) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3861 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3862 | #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3863 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3864 | #define PCH_SSC4_PARMS _MMIO(0xc6210) |
| 3865 | #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3866 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3867 | #define PCH_DPLL_SEL _MMIO(0xc7000) |
Ville Syrjälä | 68d9753 | 2015-09-18 20:03:39 +0300 | [diff] [blame] | 3868 | #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) |
Daniel Vetter | 1188739 | 2013-06-05 13:34:09 +0200 | [diff] [blame] | 3869 | #define TRANS_DPLLA_SEL(pipe) 0 |
Ville Syrjälä | 68d9753 | 2015-09-18 20:03:39 +0300 | [diff] [blame] | 3870 | #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3871 | |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3872 | /* transcoder */ |
| 3873 | |
Daniel Vetter | 275f01b2 | 2013-05-03 11:49:47 +0200 | [diff] [blame] | 3874 | #define _PCH_TRANS_HTOTAL_A 0xe0000 |
| 3875 | #define TRANS_HTOTAL_SHIFT 16 |
| 3876 | #define TRANS_HACTIVE_SHIFT 0 |
| 3877 | #define _PCH_TRANS_HBLANK_A 0xe0004 |
| 3878 | #define TRANS_HBLANK_END_SHIFT 16 |
| 3879 | #define TRANS_HBLANK_START_SHIFT 0 |
| 3880 | #define _PCH_TRANS_HSYNC_A 0xe0008 |
| 3881 | #define TRANS_HSYNC_END_SHIFT 16 |
| 3882 | #define TRANS_HSYNC_START_SHIFT 0 |
| 3883 | #define _PCH_TRANS_VTOTAL_A 0xe000c |
| 3884 | #define TRANS_VTOTAL_SHIFT 16 |
| 3885 | #define TRANS_VACTIVE_SHIFT 0 |
| 3886 | #define _PCH_TRANS_VBLANK_A 0xe0010 |
| 3887 | #define TRANS_VBLANK_END_SHIFT 16 |
| 3888 | #define TRANS_VBLANK_START_SHIFT 0 |
| 3889 | #define _PCH_TRANS_VSYNC_A 0xe0014 |
Paulo Zanoni | af7187b | 2018-06-12 16:56:53 -0700 | [diff] [blame] | 3890 | #define TRANS_VSYNC_END_SHIFT 16 |
Daniel Vetter | 275f01b2 | 2013-05-03 11:49:47 +0200 | [diff] [blame] | 3891 | #define TRANS_VSYNC_START_SHIFT 0 |
| 3892 | #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3893 | |
Daniel Vetter | e3b95f1 | 2013-05-03 11:49:49 +0200 | [diff] [blame] | 3894 | #define _PCH_TRANSA_DATA_M1 0xe0030 |
| 3895 | #define _PCH_TRANSA_DATA_N1 0xe0034 |
| 3896 | #define _PCH_TRANSA_DATA_M2 0xe0038 |
| 3897 | #define _PCH_TRANSA_DATA_N2 0xe003c |
| 3898 | #define _PCH_TRANSA_LINK_M1 0xe0040 |
| 3899 | #define _PCH_TRANSA_LINK_N1 0xe0044 |
| 3900 | #define _PCH_TRANSA_LINK_M2 0xe0048 |
| 3901 | #define _PCH_TRANSA_LINK_N2 0xe004c |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 3902 | |
Ville Syrjälä | 2dcbc34 | 2014-04-09 13:29:09 +0300 | [diff] [blame] | 3903 | /* Per-transcoder DIP controls (PCH) */ |
Jesse Barnes | b055c8f | 2011-07-08 11:31:57 -0700 | [diff] [blame] | 3904 | #define _VIDEO_DIP_CTL_A 0xe0200 |
| 3905 | #define _VIDEO_DIP_DATA_A 0xe0208 |
| 3906 | #define _VIDEO_DIP_GCP_A 0xe0210 |
Ville Syrjälä | 6d67415 | 2015-05-05 17:06:20 +0300 | [diff] [blame] | 3907 | #define GCP_COLOR_INDICATION (1 << 2) |
| 3908 | #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) |
| 3909 | #define GCP_AV_MUTE (1 << 0) |
Jesse Barnes | b055c8f | 2011-07-08 11:31:57 -0700 | [diff] [blame] | 3910 | |
| 3911 | #define _VIDEO_DIP_CTL_B 0xe1200 |
| 3912 | #define _VIDEO_DIP_DATA_B 0xe1208 |
| 3913 | #define _VIDEO_DIP_GCP_B 0xe1210 |
| 3914 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3915 | #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) |
| 3916 | #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) |
| 3917 | #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) |
Jesse Barnes | b055c8f | 2011-07-08 11:31:57 -0700 | [diff] [blame] | 3918 | |
Ville Syrjälä | 2dcbc34 | 2014-04-09 13:29:09 +0300 | [diff] [blame] | 3919 | /* Per-transcoder DIP controls (VLV) */ |
Jani Nikula | 7322aed | 2024-04-23 19:44:59 +0300 | [diff] [blame] | 3920 | #define _VLV_VIDEO_DIP_CTL_A 0x60200 |
| 3921 | #define _VLV_VIDEO_DIP_CTL_B 0x61170 |
| 3922 | #define _CHV_VIDEO_DIP_CTL_C 0x611f0 |
| 3923 | #define VLV_TVIDEO_DIP_CTL(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \ |
| 3924 | _VLV_VIDEO_DIP_CTL_A, \ |
| 3925 | _VLV_VIDEO_DIP_CTL_B, \ |
| 3926 | _CHV_VIDEO_DIP_CTL_C) |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 3927 | |
Jani Nikula | 7322aed | 2024-04-23 19:44:59 +0300 | [diff] [blame] | 3928 | #define _VLV_VIDEO_DIP_DATA_A 0x60208 |
| 3929 | #define _VLV_VIDEO_DIP_DATA_B 0x61174 |
| 3930 | #define _CHV_VIDEO_DIP_DATA_C 0x611f4 |
| 3931 | #define VLV_TVIDEO_DIP_DATA(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \ |
| 3932 | _VLV_VIDEO_DIP_DATA_A, \ |
| 3933 | _VLV_VIDEO_DIP_DATA_B, \ |
| 3934 | _CHV_VIDEO_DIP_DATA_C) |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 3935 | |
Jani Nikula | 7322aed | 2024-04-23 19:44:59 +0300 | [diff] [blame] | 3936 | #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210 |
| 3937 | #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178 |
| 3938 | #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C 0x611f8 |
| 3939 | #define VLV_TVIDEO_DIP_GCP(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \ |
| 3940 | _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ |
| 3941 | _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, \ |
| 3942 | _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 3943 | |
Eugeni Dodonov | 8c5f5f7 | 2012-05-10 10:18:02 -0300 | [diff] [blame] | 3944 | /* Haswell DIP controls */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3945 | |
Ville Syrjälä | 086f8e8 | 2015-11-04 23:20:01 +0200 | [diff] [blame] | 3946 | #define _HSW_VIDEO_DIP_CTL_A 0x60200 |
| 3947 | #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 |
| 3948 | #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 |
| 3949 | #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 |
| 3950 | #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 |
| 3951 | #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 |
Mitul Golani | 12ea892 | 2024-03-22 08:41:52 +0530 | [diff] [blame] | 3952 | #define _ADL_VIDEO_DIP_AS_DATA_A 0x60484 |
Ville Syrjälä | 44b42eb | 2019-05-17 21:52:25 +0530 | [diff] [blame] | 3953 | #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 |
Ville Syrjälä | 086f8e8 | 2015-11-04 23:20:01 +0200 | [diff] [blame] | 3954 | #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 |
| 3955 | #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 |
| 3956 | #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 |
| 3957 | #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 |
| 3958 | #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 |
| 3959 | #define _HSW_VIDEO_DIP_GCP_A 0x60210 |
Eugeni Dodonov | 8c5f5f7 | 2012-05-10 10:18:02 -0300 | [diff] [blame] | 3960 | |
Ville Syrjälä | 086f8e8 | 2015-11-04 23:20:01 +0200 | [diff] [blame] | 3961 | #define _HSW_VIDEO_DIP_CTL_B 0x61200 |
| 3962 | #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 |
| 3963 | #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 |
| 3964 | #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 |
| 3965 | #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 |
| 3966 | #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 |
Mitul Golani | 12ea892 | 2024-03-22 08:41:52 +0530 | [diff] [blame] | 3967 | #define _ADL_VIDEO_DIP_AS_DATA_B 0x61484 |
Ville Syrjälä | 44b42eb | 2019-05-17 21:52:25 +0530 | [diff] [blame] | 3968 | #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 |
Ville Syrjälä | 086f8e8 | 2015-11-04 23:20:01 +0200 | [diff] [blame] | 3969 | #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 |
| 3970 | #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 |
| 3971 | #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 |
| 3972 | #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 |
| 3973 | #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 |
| 3974 | #define _HSW_VIDEO_DIP_GCP_B 0x61210 |
Eugeni Dodonov | 8c5f5f7 | 2012-05-10 10:18:02 -0300 | [diff] [blame] | 3975 | |
Anusha Srivatsa | 7af2be6 | 2018-07-17 14:10:58 -0700 | [diff] [blame] | 3976 | /* Icelake PPS_DATA and _ECC DIP Registers. |
| 3977 | * These are available for transcoders B,C and eDP. |
| 3978 | * Adding the _A so as to reuse the _MMIO_TRANS2 |
| 3979 | * definition, with which it offsets to the right location. |
| 3980 | */ |
| 3981 | |
| 3982 | #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350 |
| 3983 | #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350 |
| 3984 | #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 |
| 3985 | #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 |
| 3986 | |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 3987 | #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A) |
| 3988 | #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A) |
| 3989 | #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) |
| 3990 | #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) |
| 3991 | #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) |
| 3992 | #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) |
| 3993 | #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) |
| 3994 | #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) |
| 3995 | #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) |
| 3996 | #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) |
Mitul Golani | 12ea892 | 2024-03-22 08:41:52 +0530 | [diff] [blame] | 3997 | /*ADLP and later: */ |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 3998 | #define ADL_TVIDEO_DIP_AS_SDP_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans,\ |
Mitul Golani | 12ea892 | 2024-03-22 08:41:52 +0530 | [diff] [blame] | 3999 | _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4) |
Eugeni Dodonov | 8c5f5f7 | 2012-05-10 10:18:02 -0300 | [diff] [blame] | 4000 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4001 | #define _HSW_STEREO_3D_CTL_A 0x70020 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4002 | #define S3D_ENABLE (1 << 31) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4003 | #define _HSW_STEREO_3D_CTL_B 0x71020 |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 4004 | |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 4005 | #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A) |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 4006 | |
Daniel Vetter | 275f01b2 | 2013-05-03 11:49:47 +0200 | [diff] [blame] | 4007 | #define _PCH_TRANS_HTOTAL_B 0xe1000 |
| 4008 | #define _PCH_TRANS_HBLANK_B 0xe1004 |
| 4009 | #define _PCH_TRANS_HSYNC_B 0xe1008 |
| 4010 | #define _PCH_TRANS_VTOTAL_B 0xe100c |
| 4011 | #define _PCH_TRANS_VBLANK_B 0xe1010 |
| 4012 | #define _PCH_TRANS_VSYNC_B 0xe1014 |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4013 | #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 4014 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4015 | #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) |
| 4016 | #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) |
| 4017 | #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) |
| 4018 | #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) |
| 4019 | #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) |
| 4020 | #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) |
| 4021 | #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4022 | |
Daniel Vetter | e3b95f1 | 2013-05-03 11:49:49 +0200 | [diff] [blame] | 4023 | #define _PCH_TRANSB_DATA_M1 0xe1030 |
| 4024 | #define _PCH_TRANSB_DATA_N1 0xe1034 |
| 4025 | #define _PCH_TRANSB_DATA_M2 0xe1038 |
| 4026 | #define _PCH_TRANSB_DATA_N2 0xe103c |
| 4027 | #define _PCH_TRANSB_LINK_M1 0xe1040 |
| 4028 | #define _PCH_TRANSB_LINK_N1 0xe1044 |
| 4029 | #define _PCH_TRANSB_LINK_M2 0xe1048 |
| 4030 | #define _PCH_TRANSB_LINK_N2 0xe104c |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 4031 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4032 | #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) |
| 4033 | #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) |
| 4034 | #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) |
| 4035 | #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) |
| 4036 | #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) |
| 4037 | #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) |
| 4038 | #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) |
| 4039 | #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 4040 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 4041 | #define _PCH_TRANSACONF 0xf0008 |
| 4042 | #define _PCH_TRANSBCONF 0xf1008 |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4043 | #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) |
| 4044 | #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ |
Ville Syrjälä | e93a590 | 2021-11-12 21:38:09 +0200 | [diff] [blame] | 4045 | #define TRANS_ENABLE REG_BIT(31) |
| 4046 | #define TRANS_STATE_ENABLE REG_BIT(30) |
| 4047 | #define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */ |
| 4048 | #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */ |
| 4049 | #define TRANS_INTERLACE_MASK REG_GENMASK(23, 21) |
| 4050 | #define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0) |
| 4051 | #define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */ |
| 4052 | #define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3) |
| 4053 | #define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */ |
| 4054 | #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0) |
| 4055 | #define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1) |
| 4056 | #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2) |
| 4057 | #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3) |
Ville Syrjälä | 3df3c589 | 2023-04-11 22:14:23 +0300 | [diff] [blame] | 4058 | |
Daniel Vetter | ce40141 | 2012-10-31 22:52:30 +0100 | [diff] [blame] | 4059 | #define _TRANSA_CHICKEN1 0xf0060 |
| 4060 | #define _TRANSB_CHICKEN1 0xf1060 |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4061 | #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) |
Ville Syrjälä | 3df3c589 | 2023-04-11 22:14:23 +0300 | [diff] [blame] | 4062 | #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10) |
| 4063 | #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4) |
| 4064 | |
Jesse Barnes | 3bcf603 | 2011-07-27 11:51:40 -0700 | [diff] [blame] | 4065 | #define _TRANSA_CHICKEN2 0xf0064 |
| 4066 | #define _TRANSB_CHICKEN2 0xf1064 |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4067 | #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) |
Ville Syrjälä | 3df3c589 | 2023-04-11 22:14:23 +0300 | [diff] [blame] | 4068 | #define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31) |
| 4069 | #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29) |
| 4070 | #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) |
| 4071 | #define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */ |
| 4072 | #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26) |
| 4073 | #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25) |
Jesse Barnes | 3bcf603 | 2011-07-27 11:51:40 -0700 | [diff] [blame] | 4074 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4075 | #define SOUTH_CHICKEN1 _MMIO(0xc2000) |
Jesse Barnes | 291427f | 2011-07-29 12:42:37 -0700 | [diff] [blame] | 4076 | #define FDIA_PHASE_SYNC_SHIFT_OVR 19 |
| 4077 | #define FDIA_PHASE_SYNC_SHIFT_EN 18 |
Mika Kahola | babde06 | 2023-04-13 14:24:39 -0700 | [diff] [blame] | 4078 | #define INVERT_DDIE_HPD REG_BIT(28) |
| 4079 | #define INVERT_DDID_HPD_MTP REG_BIT(27) |
| 4080 | #define INVERT_TC4_HPD REG_BIT(26) |
| 4081 | #define INVERT_TC3_HPD REG_BIT(25) |
| 4082 | #define INVERT_TC2_HPD REG_BIT(24) |
| 4083 | #define INVERT_TC1_HPD REG_BIT(23) |
Clinton A Taylor | b18c1eb | 2020-10-21 01:20:30 -0700 | [diff] [blame] | 4084 | #define INVERT_DDID_HPD (1 << 18) |
| 4085 | #define INVERT_DDIC_HPD (1 << 17) |
| 4086 | #define INVERT_DDIB_HPD (1 << 16) |
| 4087 | #define INVERT_DDIA_HPD (1 << 15) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4088 | #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) |
| 4089 | #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) |
Daniel Vetter | 01a415f | 2012-10-27 15:58:40 +0200 | [diff] [blame] | 4090 | #define FDI_BC_BIFURCATION_SELECT (1 << 12) |
Rodrigo Vivi | 3b92e26 | 2017-09-19 14:57:03 -0700 | [diff] [blame] | 4091 | #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) |
| 4092 | #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) |
Matt Roper | 9b2383a | 2020-05-01 14:37:01 -0700 | [diff] [blame] | 4093 | #define SBCLK_RUN_REFCLK_DIS (1 << 7) |
Ville Syrjälä | ba21bb2 | 2022-11-25 19:31:53 +0200 | [diff] [blame] | 4094 | #define ICP_SECOND_PPS_IO_SELECT REG_BIT(2) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4095 | #define SPT_PWM_GRANULARITY (1 << 0) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4096 | #define SOUTH_CHICKEN2 _MMIO(0xc2004) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4097 | #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) |
| 4098 | #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) |
| 4099 | #define LPT_PWM_GRANULARITY (1 << 5) |
| 4100 | #define DPLS_EDP_PPS_FIX_DIS (1 << 0) |
Jesse Barnes | 645c62a | 2011-05-11 09:49:31 -0700 | [diff] [blame] | 4101 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4102 | #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4103 | #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) |
| 4104 | #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) |
| 4105 | #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) |
José Roberto de Souza | c746063 | 2020-07-27 09:47:29 -0700 | [diff] [blame] | 4106 | #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4107 | #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) |
| 4108 | #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) |
| 4109 | #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) |
Jesse Barnes | 382b093 | 2010-10-07 16:01:25 -0700 | [diff] [blame] | 4110 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4111 | #define _PCH_DP_B 0xe4100 |
| 4112 | #define PCH_DP_B _MMIO(_PCH_DP_B) |
Ville Syrjälä | 750a951 | 2015-11-11 20:34:12 +0200 | [diff] [blame] | 4113 | #define _PCH_DPB_AUX_CH_CTL 0xe4110 |
| 4114 | #define _PCH_DPB_AUX_CH_DATA1 0xe4114 |
| 4115 | #define _PCH_DPB_AUX_CH_DATA2 0xe4118 |
| 4116 | #define _PCH_DPB_AUX_CH_DATA3 0xe411c |
| 4117 | #define _PCH_DPB_AUX_CH_DATA4 0xe4120 |
| 4118 | #define _PCH_DPB_AUX_CH_DATA5 0xe4124 |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4119 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4120 | #define _PCH_DP_C 0xe4200 |
| 4121 | #define PCH_DP_C _MMIO(_PCH_DP_C) |
Ville Syrjälä | 750a951 | 2015-11-11 20:34:12 +0200 | [diff] [blame] | 4122 | #define _PCH_DPC_AUX_CH_CTL 0xe4210 |
| 4123 | #define _PCH_DPC_AUX_CH_DATA1 0xe4214 |
| 4124 | #define _PCH_DPC_AUX_CH_DATA2 0xe4218 |
| 4125 | #define _PCH_DPC_AUX_CH_DATA3 0xe421c |
| 4126 | #define _PCH_DPC_AUX_CH_DATA4 0xe4220 |
| 4127 | #define _PCH_DPC_AUX_CH_DATA5 0xe4224 |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4128 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4129 | #define _PCH_DP_D 0xe4300 |
| 4130 | #define PCH_DP_D _MMIO(_PCH_DP_D) |
Ville Syrjälä | 750a951 | 2015-11-11 20:34:12 +0200 | [diff] [blame] | 4131 | #define _PCH_DPD_AUX_CH_CTL 0xe4310 |
| 4132 | #define _PCH_DPD_AUX_CH_DATA1 0xe4314 |
| 4133 | #define _PCH_DPD_AUX_CH_DATA2 0xe4318 |
| 4134 | #define _PCH_DPD_AUX_CH_DATA3 0xe431c |
| 4135 | #define _PCH_DPD_AUX_CH_DATA4 0xe4320 |
| 4136 | #define _PCH_DPD_AUX_CH_DATA5 0xe4324 |
| 4137 | |
Ville Syrjälä | bdabdb6 | 2018-02-22 20:10:30 +0200 | [diff] [blame] | 4138 | #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) |
| 4139 | #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4140 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 4141 | /* CPT */ |
Ville Syrjälä | 086f8e8 | 2015-11-04 23:20:01 +0200 | [diff] [blame] | 4142 | #define _TRANS_DP_CTL_A 0xe0300 |
| 4143 | #define _TRANS_DP_CTL_B 0xe1300 |
| 4144 | #define _TRANS_DP_CTL_C 0xe2300 |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4145 | #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) |
Ville Syrjälä | e93a590 | 2021-11-12 21:38:09 +0200 | [diff] [blame] | 4146 | #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31) |
| 4147 | #define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29) |
| 4148 | #define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3) |
| 4149 | #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B) |
| 4150 | #define TRANS_DP_AUDIO_ONLY REG_BIT(26) |
| 4151 | #define TRANS_DP_ENH_FRAMING REG_BIT(18) |
| 4152 | #define TRANS_DP_BPC_MASK REG_GENMASK(10, 9) |
| 4153 | #define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0) |
| 4154 | #define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1) |
| 4155 | #define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2) |
| 4156 | #define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3) |
| 4157 | #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4) |
| 4158 | #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3) |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 4159 | |
Jani Nikula | 59821ed | 2021-08-23 19:18:08 +0300 | [diff] [blame] | 4160 | #define _TRANS_DP2_CTL_A 0x600a0 |
| 4161 | #define _TRANS_DP2_CTL_B 0x610a0 |
| 4162 | #define _TRANS_DP2_CTL_C 0x620a0 |
| 4163 | #define _TRANS_DP2_CTL_D 0x630a0 |
| 4164 | #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B) |
| 4165 | #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31) |
| 4166 | #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30) |
| 4167 | #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23) |
| 4168 | |
Jani Nikula | 1db1826 | 2021-08-23 19:18:10 +0300 | [diff] [blame] | 4169 | #define _TRANS_DP2_VFREQHIGH_A 0x600a4 |
| 4170 | #define _TRANS_DP2_VFREQHIGH_B 0x610a4 |
| 4171 | #define _TRANS_DP2_VFREQHIGH_C 0x620a4 |
| 4172 | #define _TRANS_DP2_VFREQHIGH_D 0x630a4 |
| 4173 | #define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B) |
| 4174 | #define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8) |
| 4175 | #define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz)) |
| 4176 | |
| 4177 | #define _TRANS_DP2_VFREQLOW_A 0x600a8 |
| 4178 | #define _TRANS_DP2_VFREQLOW_B 0x610a8 |
| 4179 | #define _TRANS_DP2_VFREQLOW_C 0x620a8 |
| 4180 | #define _TRANS_DP2_VFREQLOW_D 0x630a8 |
| 4181 | #define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B) |
| 4182 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 4183 | /* SNB eDP training params */ |
| 4184 | /* SNB A-stepping */ |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4185 | #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) |
| 4186 | #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) |
| 4187 | #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) |
| 4188 | #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 4189 | /* SNB B-stepping */ |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4190 | #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) |
| 4191 | #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) |
| 4192 | #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) |
| 4193 | #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) |
| 4194 | #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) |
| 4195 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 4196 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 4197 | /* IVB */ |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4198 | #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) |
| 4199 | #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) |
| 4200 | #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) |
| 4201 | #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) |
| 4202 | #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) |
| 4203 | #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) |
| 4204 | #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 4205 | |
| 4206 | /* legacy values */ |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4207 | #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) |
| 4208 | #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) |
| 4209 | #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) |
| 4210 | #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) |
| 4211 | #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 4212 | |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4213 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 4214 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4215 | #define VLV_PMWGICZ _MMIO(0x1300a4) |
Imre Deak | 9e72b46 | 2014-05-05 15:13:55 +0300 | [diff] [blame] | 4216 | |
Mika Kuoppala | 3accaf7 | 2016-04-13 17:26:43 +0300 | [diff] [blame] | 4217 | #define HSW_EDRAM_CAP _MMIO(0x120010) |
Damien Lespiau | 2db59d5 | 2015-02-03 14:25:14 +0000 | [diff] [blame] | 4218 | #define EDRAM_ENABLED 0x1 |
Mika Kuoppala | c02e85a | 2016-04-13 17:26:44 +0300 | [diff] [blame] | 4219 | #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) |
| 4220 | #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) |
| 4221 | #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) |
Ben Widawsky | 05e21cc | 2013-07-04 11:02:04 -0700 | [diff] [blame] | 4222 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4223 | #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) |
Gaurav K Singh | a9da9bc | 2014-12-05 14:13:41 +0530 | [diff] [blame] | 4224 | #define PIXEL_OVERLAP_CNT_MASK (3 << 30) |
| 4225 | #define PIXEL_OVERLAP_CNT_SHIFT 30 |
| 4226 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4227 | #define GEN6_PCODE_MAILBOX _MMIO(0x138124) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4228 | #define GEN6_PCODE_READY (1 << 31) |
Dale B Stimson | 5f38c3f | 2022-05-19 09:57:32 +0100 | [diff] [blame] | 4229 | #define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16) |
| 4230 | #define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8) |
| 4231 | #define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0) |
Lyude | 8766050 | 2016-08-17 15:55:53 -0400 | [diff] [blame] | 4232 | #define GEN6_PCODE_ERROR_MASK 0xFF |
| 4233 | #define GEN6_PCODE_SUCCESS 0x0 |
| 4234 | #define GEN6_PCODE_ILLEGAL_CMD 0x1 |
| 4235 | #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 |
| 4236 | #define GEN6_PCODE_TIMEOUT 0x3 |
| 4237 | #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF |
| 4238 | #define GEN7_PCODE_TIMEOUT 0x2 |
| 4239 | #define GEN7_PCODE_ILLEGAL_DATA 0x3 |
Matt Roper | f22fd33 | 2020-01-10 17:45:11 -0800 | [diff] [blame] | 4240 | #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4 |
| 4241 | #define GEN11_PCODE_LOCKED 0x6 |
Stanislav Lisovskiy | f136c58 | 2020-05-05 13:22:45 +0300 | [diff] [blame] | 4242 | #define GEN11_PCODE_REJECTED 0x11 |
Lyude | 8766050 | 2016-08-17 15:55:53 -0400 | [diff] [blame] | 4243 | #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 |
Ville Syrjälä | 3e8ddd9 | 2017-09-12 18:34:10 +0300 | [diff] [blame] | 4244 | #define GEN6_PCODE_WRITE_RC6VIDS 0x4 |
| 4245 | #define GEN6_PCODE_READ_RC6VIDS 0x5 |
Damien Lespiau | 9043ae0 | 2015-04-30 16:39:18 +0100 | [diff] [blame] | 4246 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) |
| 4247 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 4248 | #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 |
Damien Lespiau | 57520bc | 2015-04-30 16:39:19 +0100 | [diff] [blame] | 4249 | #define GEN9_PCODE_READ_MEM_LATENCY 0x6 |
Ville Syrjälä | 3fecf93 | 2022-09-08 22:16:46 +0300 | [diff] [blame] | 4250 | #define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24) |
| 4251 | #define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16) |
| 4252 | #define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8) |
| 4253 | #define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0) |
Sean Paul | ee5e5e7 | 2018-01-08 14:55:39 -0500 | [diff] [blame] | 4254 | #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 4255 | #define SKL_PCODE_CDCLK_CONTROL 0x7 |
| 4256 | #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 |
| 4257 | #define SKL_CDCLK_READY_FOR_CHANGE 0x1 |
Damien Lespiau | 9043ae0 | 2015-04-30 16:39:18 +0100 | [diff] [blame] | 4258 | #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 |
| 4259 | #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 |
| 4260 | #define GEN6_READ_OC_PARAMS 0xc |
Ville Syrjälä | c457d9c | 2019-05-24 18:36:14 +0300 | [diff] [blame] | 4261 | #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd |
| 4262 | #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) |
| 4263 | #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) |
Stanislav Lisovskiy | 192fbfb | 2021-05-31 09:48:45 +0300 | [diff] [blame] | 4264 | #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8)) |
Stanislav Lisovskiy | ceb0cc3 | 2023-05-04 12:39:59 +0300 | [diff] [blame] | 4265 | #define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D |
| 4266 | #define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0) |
| 4267 | #define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK |
| 4268 | #define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27) |
| 4269 | #define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31) |
| 4270 | #define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16) |
| 4271 | #define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28) |
| 4272 | #define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x)) |
| 4273 | #define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x)) |
| 4274 | #define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x)) |
| 4275 | #define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \ |
| 4276 | ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \ |
| 4277 | (DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \ |
| 4278 | (DISPLAY_TO_PCODE_VOLTAGE(voltage_level))) |
Stanislav Lisovskiy | f136c58 | 2020-05-05 13:22:45 +0300 | [diff] [blame] | 4279 | #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe |
Ville Syrjälä | 4bdba4f | 2022-03-09 18:49:48 +0200 | [diff] [blame] | 4280 | #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0) |
| 4281 | #define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0) |
| 4282 | #define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1) |
| 4283 | #define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2) |
| 4284 | #define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2) |
| 4285 | #define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0) |
| 4286 | #define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1) |
| 4287 | #define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2) |
| 4288 | #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0) |
| 4289 | #define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x)) |
| 4290 | #define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8) |
| 4291 | #define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x)) |
Paulo Zanoni | 515b239 | 2013-09-10 19:36:37 -0300 | [diff] [blame] | 4292 | #define GEN6_PCODE_READ_D_COMP 0x10 |
| 4293 | #define GEN6_PCODE_WRITE_D_COMP 0x11 |
José Roberto de Souza | feb7e0e | 2020-04-14 12:49:52 -0700 | [diff] [blame] | 4294 | #define ICL_PCODE_EXIT_TCCOLD 0x12 |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 4295 | #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 4296 | #define DISPLAY_IPS_CONTROL 0x19 |
José Roberto de Souza | 3c02934 | 2020-04-14 12:49:54 -0700 | [diff] [blame] | 4297 | #define TGL_PCODE_TCCOLD 0x26 |
| 4298 | #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0) |
Imre Deak | 05e31dd | 2020-08-05 18:00:56 +0300 | [diff] [blame] | 4299 | #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0 |
| 4300 | #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0) |
Ville Syrjälä | 61843f0 | 2017-09-12 18:34:11 +0300 | [diff] [blame] | 4301 | /* See also IPS_CTL */ |
| 4302 | #define IPS_PCODE_CONTROL (1 << 30) |
Ville Syrjälä | 3e8ddd9 | 2017-09-12 18:34:10 +0300 | [diff] [blame] | 4303 | #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A |
Lyude | 656d1b8 | 2016-08-17 15:55:54 -0400 | [diff] [blame] | 4304 | #define GEN9_PCODE_SAGV_CONTROL 0x21 |
| 4305 | #define GEN9_SAGV_DISABLE 0x0 |
| 4306 | #define GEN9_SAGV_IS_DISABLED 0x1 |
| 4307 | #define GEN9_SAGV_ENABLE 0x3 |
Matt Roper | f9c730ed | 2020-09-30 23:39:17 -0700 | [diff] [blame] | 4308 | #define DG1_PCODE_STATUS 0x7E |
| 4309 | #define DG1_UNCORE_GET_INIT_STATUS 0x0 |
| 4310 | #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 |
Ashutosh Dixit | c8939848 | 2022-10-13 08:45:24 -0700 | [diff] [blame] | 4311 | #define PCODE_POWER_SETUP 0x7C |
| 4312 | #define POWER_SETUP_SUBCOMMAND_READ_I1 0x4 |
| 4313 | #define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5 |
| 4314 | #define POWER_SETUP_I1_WATTS REG_BIT(31) |
| 4315 | #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */ |
| 4316 | #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0) |
James Ausmus | da80f04 | 2019-10-09 10:23:15 -0700 | [diff] [blame] | 4317 | #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 |
Lucas De Marchi | cb4046d | 2024-03-19 23:02:58 -0700 | [diff] [blame] | 4318 | #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */ |
Matt Roper | 7d80970 | 2022-06-24 14:03:28 -0700 | [diff] [blame] | 4319 | /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */ |
Dale B Stimson | 9d15dd1 | 2022-05-25 06:19:19 -0700 | [diff] [blame] | 4320 | #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0 |
| 4321 | #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1 |
| 4322 | /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */ |
Matt Roper | 7d80970 | 2022-06-24 14:03:28 -0700 | [diff] [blame] | 4323 | /* XEHP_PCODE_FREQUENCY_CONFIG param2 */ |
Dale B Stimson | 9d15dd1 | 2022-05-25 06:19:19 -0700 | [diff] [blame] | 4324 | #define PCODE_MBOX_DOMAIN_NONE 0x0 |
| 4325 | #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3 |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4326 | #define GEN6_PCODE_DATA _MMIO(0x138128) |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 4327 | #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 4328 | #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4329 | #define GEN6_PCODE_DATA1 _MMIO(0x13812C) |
Chris Wilson | 8fd2685 | 2010-12-08 18:40:43 +0000 | [diff] [blame] | 4330 | |
Ville Syrjälä | c08c3641 | 2024-02-03 00:43:28 +0200 | [diff] [blame] | 4331 | #define MTL_PCODE_STOLEN_ACCESS _MMIO(0x138914) |
| 4332 | #define STOLEN_ACCESS_ALLOWED 0x1 |
| 4333 | |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 4334 | /* IVYBRIDGE DPF */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4335 | #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4336 | #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) |
| 4337 | #define GEN7_PARITY_ERROR_VALID (1 << 13) |
| 4338 | #define GEN7_L3CDERRST1_BANK_MASK (3 << 11) |
| 4339 | #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 4340 | #define GEN7_PARITY_ERROR_ROW(reg) \ |
Paulo Zanoni | 9e8789e | 2018-06-12 16:56:54 -0700 | [diff] [blame] | 4341 | (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 4342 | #define GEN7_PARITY_ERROR_BANK(reg) \ |
Paulo Zanoni | 9e8789e | 2018-06-12 16:56:54 -0700 | [diff] [blame] | 4343 | (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 4344 | #define GEN7_PARITY_ERROR_SUBBANK(reg) \ |
Paulo Zanoni | 9e8789e | 2018-06-12 16:56:54 -0700 | [diff] [blame] | 4345 | (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4346 | #define GEN7_L3CDERRST1_ENABLE (1 << 7) |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 4347 | |
Eric Anholt | ae662d3 | 2012-01-03 09:23:29 -0800 | [diff] [blame] | 4348 | /* These are the 4 32-bit write offset registers for each stream |
| 4349 | * output buffer. It determines the offset from the |
| 4350 | * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. |
| 4351 | */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4352 | #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) |
Eric Anholt | ae662d3 | 2012-01-03 09:23:29 -0800 | [diff] [blame] | 4353 | |
Imre Deak | 9c3a16c | 2017-08-14 18:15:30 +0300 | [diff] [blame] | 4354 | /* |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4355 | * HSW - ICL power wells |
| 4356 | * |
| 4357 | * Platforms have up to 3 power well control register sets, each set |
| 4358 | * controlling up to 16 power wells via a request/status HW flag tuple: |
| 4359 | * - main (HSW_PWR_WELL_CTL[1-4]) |
| 4360 | * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) |
| 4361 | * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) |
| 4362 | * Each control register set consists of up to 4 registers used by different |
| 4363 | * sources that can request a power well to be enabled: |
| 4364 | * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) |
| 4365 | * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) |
| 4366 | * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) |
| 4367 | * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) |
Imre Deak | 9c3a16c | 2017-08-14 18:15:30 +0300 | [diff] [blame] | 4368 | */ |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4369 | #define HSW_PWR_WELL_CTL1 _MMIO(0x45400) |
| 4370 | #define HSW_PWR_WELL_CTL2 _MMIO(0x45404) |
| 4371 | #define HSW_PWR_WELL_CTL3 _MMIO(0x45408) |
| 4372 | #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) |
| 4373 | #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) |
| 4374 | #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) |
Imre Deak | 9c3a16c | 2017-08-14 18:15:30 +0300 | [diff] [blame] | 4375 | |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4376 | /* HSW/BDW power well */ |
| 4377 | #define HSW_PW_CTL_IDX_GLOBAL 15 |
| 4378 | |
Lucas De Marchi | a4d082f | 2021-07-28 14:59:45 -0700 | [diff] [blame] | 4379 | /* SKL/BXT/GLK power wells */ |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4380 | #define SKL_PW_CTL_IDX_PW_2 15 |
| 4381 | #define SKL_PW_CTL_IDX_PW_1 14 |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4382 | #define GLK_PW_CTL_IDX_AUX_C 10 |
| 4383 | #define GLK_PW_CTL_IDX_AUX_B 9 |
| 4384 | #define GLK_PW_CTL_IDX_AUX_A 8 |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4385 | #define SKL_PW_CTL_IDX_DDI_D 4 |
| 4386 | #define SKL_PW_CTL_IDX_DDI_C 3 |
| 4387 | #define SKL_PW_CTL_IDX_DDI_B 2 |
| 4388 | #define SKL_PW_CTL_IDX_DDI_A_E 1 |
| 4389 | #define GLK_PW_CTL_IDX_DDI_A 1 |
| 4390 | #define SKL_PW_CTL_IDX_MISC_IO 0 |
| 4391 | |
Imre Deak | 656409b | 2019-07-11 10:31:02 -0700 | [diff] [blame] | 4392 | /* ICL/TGL - power wells */ |
Mika Kahola | 1db27a7 | 2019-07-11 10:31:03 -0700 | [diff] [blame] | 4393 | #define TGL_PW_CTL_IDX_PW_5 4 |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4394 | #define ICL_PW_CTL_IDX_PW_4 3 |
| 4395 | #define ICL_PW_CTL_IDX_PW_3 2 |
| 4396 | #define ICL_PW_CTL_IDX_PW_2 1 |
| 4397 | #define ICL_PW_CTL_IDX_PW_1 0 |
| 4398 | |
Matt Roper | a6922f4 | 2021-05-11 21:21:40 -0700 | [diff] [blame] | 4399 | /* XE_LPD - power wells */ |
| 4400 | #define XELPD_PW_CTL_IDX_PW_D 8 |
| 4401 | #define XELPD_PW_CTL_IDX_PW_C 7 |
| 4402 | #define XELPD_PW_CTL_IDX_PW_B 6 |
| 4403 | #define XELPD_PW_CTL_IDX_PW_A 5 |
| 4404 | |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4405 | #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) |
| 4406 | #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) |
| 4407 | #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) |
Imre Deak | 656409b | 2019-07-11 10:31:02 -0700 | [diff] [blame] | 4408 | #define TGL_PW_CTL_IDX_AUX_TBT6 14 |
| 4409 | #define TGL_PW_CTL_IDX_AUX_TBT5 13 |
| 4410 | #define TGL_PW_CTL_IDX_AUX_TBT4 12 |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4411 | #define ICL_PW_CTL_IDX_AUX_TBT4 11 |
Imre Deak | 656409b | 2019-07-11 10:31:02 -0700 | [diff] [blame] | 4412 | #define TGL_PW_CTL_IDX_AUX_TBT3 11 |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4413 | #define ICL_PW_CTL_IDX_AUX_TBT3 10 |
Imre Deak | 656409b | 2019-07-11 10:31:02 -0700 | [diff] [blame] | 4414 | #define TGL_PW_CTL_IDX_AUX_TBT2 10 |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4415 | #define ICL_PW_CTL_IDX_AUX_TBT2 9 |
Imre Deak | 656409b | 2019-07-11 10:31:02 -0700 | [diff] [blame] | 4416 | #define TGL_PW_CTL_IDX_AUX_TBT1 9 |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4417 | #define ICL_PW_CTL_IDX_AUX_TBT1 8 |
Imre Deak | 656409b | 2019-07-11 10:31:02 -0700 | [diff] [blame] | 4418 | #define TGL_PW_CTL_IDX_AUX_TC6 8 |
Matt Roper | a6922f4 | 2021-05-11 21:21:40 -0700 | [diff] [blame] | 4419 | #define XELPD_PW_CTL_IDX_AUX_E 8 |
Imre Deak | 656409b | 2019-07-11 10:31:02 -0700 | [diff] [blame] | 4420 | #define TGL_PW_CTL_IDX_AUX_TC5 7 |
Matt Roper | a6922f4 | 2021-05-11 21:21:40 -0700 | [diff] [blame] | 4421 | #define XELPD_PW_CTL_IDX_AUX_D 7 |
Imre Deak | 656409b | 2019-07-11 10:31:02 -0700 | [diff] [blame] | 4422 | #define TGL_PW_CTL_IDX_AUX_TC4 6 |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4423 | #define ICL_PW_CTL_IDX_AUX_F 5 |
Imre Deak | 656409b | 2019-07-11 10:31:02 -0700 | [diff] [blame] | 4424 | #define TGL_PW_CTL_IDX_AUX_TC3 5 |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4425 | #define ICL_PW_CTL_IDX_AUX_E 4 |
Imre Deak | 656409b | 2019-07-11 10:31:02 -0700 | [diff] [blame] | 4426 | #define TGL_PW_CTL_IDX_AUX_TC2 4 |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4427 | #define ICL_PW_CTL_IDX_AUX_D 3 |
Imre Deak | 656409b | 2019-07-11 10:31:02 -0700 | [diff] [blame] | 4428 | #define TGL_PW_CTL_IDX_AUX_TC1 3 |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4429 | #define ICL_PW_CTL_IDX_AUX_C 2 |
| 4430 | #define ICL_PW_CTL_IDX_AUX_B 1 |
| 4431 | #define ICL_PW_CTL_IDX_AUX_A 0 |
| 4432 | |
| 4433 | #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) |
| 4434 | #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) |
| 4435 | #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) |
Matt Roper | a6922f4 | 2021-05-11 21:21:40 -0700 | [diff] [blame] | 4436 | #define XELPD_PW_CTL_IDX_DDI_E 8 |
Imre Deak | 656409b | 2019-07-11 10:31:02 -0700 | [diff] [blame] | 4437 | #define TGL_PW_CTL_IDX_DDI_TC6 8 |
Matt Roper | a6922f4 | 2021-05-11 21:21:40 -0700 | [diff] [blame] | 4438 | #define XELPD_PW_CTL_IDX_DDI_D 7 |
Imre Deak | 656409b | 2019-07-11 10:31:02 -0700 | [diff] [blame] | 4439 | #define TGL_PW_CTL_IDX_DDI_TC5 7 |
| 4440 | #define TGL_PW_CTL_IDX_DDI_TC4 6 |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4441 | #define ICL_PW_CTL_IDX_DDI_F 5 |
Imre Deak | 656409b | 2019-07-11 10:31:02 -0700 | [diff] [blame] | 4442 | #define TGL_PW_CTL_IDX_DDI_TC3 5 |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4443 | #define ICL_PW_CTL_IDX_DDI_E 4 |
Imre Deak | 656409b | 2019-07-11 10:31:02 -0700 | [diff] [blame] | 4444 | #define TGL_PW_CTL_IDX_DDI_TC2 4 |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4445 | #define ICL_PW_CTL_IDX_DDI_D 3 |
Imre Deak | 656409b | 2019-07-11 10:31:02 -0700 | [diff] [blame] | 4446 | #define TGL_PW_CTL_IDX_DDI_TC1 3 |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4447 | #define ICL_PW_CTL_IDX_DDI_C 2 |
| 4448 | #define ICL_PW_CTL_IDX_DDI_B 1 |
| 4449 | #define ICL_PW_CTL_IDX_DDI_A 0 |
| 4450 | |
| 4451 | /* HSW - power well misc debug registers */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4452 | #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4453 | #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) |
| 4454 | #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) |
| 4455 | #define HSW_PWR_WELL_FORCE_ON (1 << 19) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4456 | #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) |
Eugeni Dodonov | 9eb3a75 | 2012-03-29 12:32:21 -0300 | [diff] [blame] | 4457 | |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 4458 | /* SKL Fuse Status */ |
Imre Deak | b2891eb | 2017-07-11 23:42:35 +0300 | [diff] [blame] | 4459 | enum skl_power_gate { |
| 4460 | SKL_PG0, |
| 4461 | SKL_PG1, |
| 4462 | SKL_PG2, |
Imre Deak | 1a260e1 | 2018-08-06 12:58:43 +0300 | [diff] [blame] | 4463 | ICL_PG3, |
| 4464 | ICL_PG4, |
Imre Deak | b2891eb | 2017-07-11 23:42:35 +0300 | [diff] [blame] | 4465 | }; |
| 4466 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4467 | #define SKL_FUSE_STATUS _MMIO(0x42000) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4468 | #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) |
Imre Deak | 75e3968 | 2018-08-06 12:58:39 +0300 | [diff] [blame] | 4469 | /* |
| 4470 | * PG0 is HW controlled, so doesn't have a corresponding power well control knob |
| 4471 | * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 |
| 4472 | */ |
| 4473 | #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ |
| 4474 | ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) |
| 4475 | /* |
| 4476 | * PG0 is HW controlled, so doesn't have a corresponding power well control knob |
| 4477 | * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 |
| 4478 | */ |
| 4479 | #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ |
| 4480 | ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) |
Imre Deak | b2891eb | 2017-07-11 23:42:35 +0300 | [diff] [blame] | 4481 | #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 4482 | |
Eugeni Dodonov | e7e104c | 2012-03-29 12:32:23 -0300 | [diff] [blame] | 4483 | /* Per-pipe DDI Function Control */ |
Ville Syrjälä | 086f8e8 | 2015-11-04 23:20:01 +0200 | [diff] [blame] | 4484 | #define _TRANS_DDI_FUNC_CTL_A 0x60400 |
| 4485 | #define _TRANS_DDI_FUNC_CTL_B 0x61400 |
| 4486 | #define _TRANS_DDI_FUNC_CTL_C 0x62400 |
Lucas De Marchi | f1f1d4f | 2019-07-11 10:30:55 -0700 | [diff] [blame] | 4487 | #define _TRANS_DDI_FUNC_CTL_D 0x63400 |
Ville Syrjälä | 086f8e8 | 2015-11-04 23:20:01 +0200 | [diff] [blame] | 4488 | #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 |
Madhav Chauhan | 49edbd4 | 2018-10-15 17:28:00 +0300 | [diff] [blame] | 4489 | #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 |
| 4490 | #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 4491 | #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A) |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 4492 | |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4493 | #define TRANS_DDI_FUNC_ENABLE (1 << 31) |
Eugeni Dodonov | e7e104c | 2012-03-29 12:32:23 -0300 | [diff] [blame] | 4494 | /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ |
Daniel Vetter | 26804af | 2014-06-25 22:01:55 +0300 | [diff] [blame] | 4495 | #define TRANS_DDI_PORT_SHIFT 28 |
Mahesh Kumar | df16b63 | 2019-07-12 18:09:20 -0700 | [diff] [blame] | 4496 | #define TGL_TRANS_DDI_PORT_SHIFT 27 |
| 4497 | #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT) |
| 4498 | #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT) |
| 4499 | #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) |
| 4500 | #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4501 | #define TRANS_DDI_MODE_SELECT_MASK (7 << 24) |
| 4502 | #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) |
| 4503 | #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) |
| 4504 | #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) |
| 4505 | #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) |
Jani Nikula | 7bb97db | 2021-09-09 15:51:57 +0300 | [diff] [blame] | 4506 | #define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4507 | #define TRANS_DDI_BPC_MASK (7 << 20) |
| 4508 | #define TRANS_DDI_BPC_8 (0 << 20) |
| 4509 | #define TRANS_DDI_BPC_10 (1 << 20) |
| 4510 | #define TRANS_DDI_BPC_6 (2 << 20) |
| 4511 | #define TRANS_DDI_BPC_12 (3 << 20) |
Lucas De Marchi | a4d082f | 2021-07-28 14:59:45 -0700 | [diff] [blame] | 4512 | #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) |
Ville Syrjälä | dc5b8ed | 2020-03-13 18:48:26 +0200 | [diff] [blame] | 4513 | #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x)) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4514 | #define TRANS_DDI_PVSYNC (1 << 17) |
| 4515 | #define TRANS_DDI_PHSYNC (1 << 16) |
Lucas De Marchi | a4d082f | 2021-07-28 14:59:45 -0700 | [diff] [blame] | 4516 | #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4517 | #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) |
| 4518 | #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) |
| 4519 | #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) |
| 4520 | #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) |
| 4521 | #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) |
José Roberto de Souza | 4d89adc | 2019-11-07 13:45:58 -0800 | [diff] [blame] | 4522 | #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) |
José Roberto de Souza | bb747fa | 2019-11-07 13:45:57 -0800 | [diff] [blame] | 4523 | #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) |
Lucas De Marchi | b3545e0 | 2019-10-28 20:50:49 -0700 | [diff] [blame] | 4524 | #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ |
| 4525 | REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4526 | #define TRANS_DDI_HDCP_SIGNALLING (1 << 9) |
| 4527 | #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) |
| 4528 | #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) |
| 4529 | #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) |
Anshuman Gupta | 1a67a16 | 2021-01-11 13:41:08 +0530 | [diff] [blame] | 4530 | #define TRANS_DDI_HDCP_SELECT REG_BIT(5) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4531 | #define TRANS_DDI_BFI_ENABLE (1 << 4) |
| 4532 | #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) |
Ankit Nautiyal | b66a8ab | 2023-04-13 14:24:42 -0700 | [diff] [blame] | 4533 | #define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1) |
| 4534 | #define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4535 | #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) |
Shashank Sharma | 1595363 | 2017-03-13 16:54:03 +0530 | [diff] [blame] | 4536 | #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ |
| 4537 | | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ |
| 4538 | | TRANS_DDI_HDMI_SCRAMBLING) |
Eugeni Dodonov | e7e104c | 2012-03-29 12:32:23 -0300 | [diff] [blame] | 4539 | |
Madhav Chauhan | 49edbd4 | 2018-10-15 17:28:00 +0300 | [diff] [blame] | 4540 | #define _TRANS_DDI_FUNC_CTL2_A 0x60404 |
| 4541 | #define _TRANS_DDI_FUNC_CTL2_B 0x61404 |
| 4542 | #define _TRANS_DDI_FUNC_CTL2_C 0x62404 |
| 4543 | #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 |
| 4544 | #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 |
| 4545 | #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 4546 | #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A) |
Ville Syrjälä | d4d7d9c | 2020-03-13 18:48:23 +0200 | [diff] [blame] | 4547 | #define PORT_SYNC_MODE_ENABLE REG_BIT(4) |
| 4548 | #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) |
| 4549 | #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) |
Madhav Chauhan | 49edbd4 | 2018-10-15 17:28:00 +0300 | [diff] [blame] | 4550 | |
Imre Deak | 573d7ce | 2021-07-27 16:44:00 +0300 | [diff] [blame] | 4551 | #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90) |
| 4552 | #define DISABLE_DPT_CLK_GATING REG_BIT(1) |
| 4553 | |
Eugeni Dodonov | 0e87f66 | 2012-03-29 12:32:24 -0300 | [diff] [blame] | 4554 | /* DisplayPort Transport Control */ |
Ville Syrjälä | 086f8e8 | 2015-11-04 23:20:01 +0200 | [diff] [blame] | 4555 | #define _DP_TP_CTL_A 0x64040 |
| 4556 | #define _DP_TP_CTL_B 0x64140 |
Lucas De Marchi | 4444df6 | 2019-09-04 14:34:17 -0700 | [diff] [blame] | 4557 | #define _TGL_DP_TP_CTL_A 0x60540 |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4558 | #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 4559 | #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4560 | #define DP_TP_CTL_ENABLE (1 << 31) |
Anusha Srivatsa | 5c44b93 | 2018-11-28 12:26:27 -0800 | [diff] [blame] | 4561 | #define DP_TP_CTL_FEC_ENABLE (1 << 30) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4562 | #define DP_TP_CTL_MODE_SST (0 << 27) |
| 4563 | #define DP_TP_CTL_MODE_MST (1 << 27) |
| 4564 | #define DP_TP_CTL_FORCE_ACT (1 << 25) |
Khaled Almahallawy | 6c7ffa7 | 2023-12-13 13:15:41 -0800 | [diff] [blame] | 4565 | #define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) |
| 4566 | #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A (0 << 19) |
| 4567 | #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B (1 << 19) |
| 4568 | #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C (2 << 19) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4569 | #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) |
| 4570 | #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) |
| 4571 | #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) |
| 4572 | #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) |
| 4573 | #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) |
| 4574 | #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) |
| 4575 | #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) |
| 4576 | #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) |
| 4577 | #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) |
| 4578 | #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) |
Eugeni Dodonov | 0e87f66 | 2012-03-29 12:32:24 -0300 | [diff] [blame] | 4579 | |
Eugeni Dodonov | e411b2c | 2012-03-29 12:32:25 -0300 | [diff] [blame] | 4580 | /* DisplayPort Transport Status */ |
Ville Syrjälä | 086f8e8 | 2015-11-04 23:20:01 +0200 | [diff] [blame] | 4581 | #define _DP_TP_STATUS_A 0x64044 |
| 4582 | #define _DP_TP_STATUS_B 0x64144 |
Lucas De Marchi | 4444df6 | 2019-09-04 14:34:17 -0700 | [diff] [blame] | 4583 | #define _TGL_DP_TP_STATUS_A 0x60544 |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4584 | #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 4585 | #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A) |
Anusha Srivatsa | 5c44b93 | 2018-11-28 12:26:27 -0800 | [diff] [blame] | 4586 | #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4587 | #define DP_TP_STATUS_IDLE_DONE (1 << 25) |
| 4588 | #define DP_TP_STATUS_ACT_SENT (1 << 24) |
| 4589 | #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) |
| 4590 | #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12) |
Dave Airlie | 01b887c | 2014-05-02 11:17:41 +1000 | [diff] [blame] | 4591 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) |
| 4592 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) |
| 4593 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) |
Eugeni Dodonov | e411b2c | 2012-03-29 12:32:25 -0300 | [diff] [blame] | 4594 | |
Eugeni Dodonov | 03f896a | 2012-03-29 12:32:26 -0300 | [diff] [blame] | 4595 | /* DDI Buffer Control */ |
Ville Syrjälä | 086f8e8 | 2015-11-04 23:20:01 +0200 | [diff] [blame] | 4596 | #define _DDI_BUF_CTL_A 0x64000 |
| 4597 | #define _DDI_BUF_CTL_B 0x64100 |
José Roberto de Souza | 23ef619 | 2023-04-13 14:24:40 -0700 | [diff] [blame] | 4598 | /* Known as DDI_CTL_DE in MTL+ */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4599 | #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4600 | #define DDI_BUF_CTL_ENABLE (1 << 31) |
Lucas De Marchi | d5c7854 | 2024-01-26 14:46:36 -0800 | [diff] [blame] | 4601 | #define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29) |
| 4602 | #define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28) |
Sonika Jindal | c5fe6a0 | 2014-08-11 08:57:36 +0530 | [diff] [blame] | 4603 | #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4604 | #define DDI_BUF_EMP_MASK (0xf << 24) |
Imre Deak | 414002f | 2021-05-18 17:06:23 -0700 | [diff] [blame] | 4605 | #define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20) |
José Roberto de Souza | 23ef619 | 2023-04-13 14:24:40 -0700 | [diff] [blame] | 4606 | #define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18) |
| 4607 | #define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0) |
| 4608 | #define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1) |
| 4609 | #define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4610 | #define DDI_BUF_PORT_REVERSAL (1 << 16) |
| 4611 | #define DDI_BUF_IS_IDLE (1 << 7) |
José Roberto de Souza | 55ce306 | 2021-05-18 17:06:13 -0700 | [diff] [blame] | 4612 | #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4613 | #define DDI_A_4_LANES (1 << 4) |
Daniel Vetter | 17aa6be | 2013-04-30 14:01:40 +0200 | [diff] [blame] | 4614 | #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 4615 | #define DDI_PORT_WIDTH_MASK (7 << 1) |
| 4616 | #define DDI_PORT_WIDTH_SHIFT 1 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4617 | #define DDI_INIT_DISPLAY_DETECTED (1 << 0) |
Eugeni Dodonov | 03f896a | 2012-03-29 12:32:26 -0300 | [diff] [blame] | 4618 | |
Eugeni Dodonov | bb879a4 | 2012-03-29 12:32:27 -0300 | [diff] [blame] | 4619 | /* DDI Buffer Translations */ |
Ville Syrjälä | 086f8e8 | 2015-11-04 23:20:01 +0200 | [diff] [blame] | 4620 | #define _DDI_BUF_TRANS_A 0x64E00 |
| 4621 | #define _DDI_BUF_TRANS_B 0x64E60 |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4622 | #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) |
Ville Syrjälä | c110ae6 | 2016-07-12 15:59:29 +0300 | [diff] [blame] | 4623 | #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4624 | #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) |
Eugeni Dodonov | bb879a4 | 2012-03-29 12:32:27 -0300 | [diff] [blame] | 4625 | |
Animesh Manna | fce214a | 2020-03-24 10:41:11 +0530 | [diff] [blame] | 4626 | /* DDI DP Compliance Control */ |
| 4627 | #define _DDI_DP_COMP_CTL_A 0x605F0 |
| 4628 | #define _DDI_DP_COMP_CTL_B 0x615F0 |
| 4629 | #define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) |
| 4630 | #define DDI_DP_COMP_CTL_ENABLE (1 << 31) |
| 4631 | #define DDI_DP_COMP_CTL_D10_2 (0 << 28) |
| 4632 | #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) |
| 4633 | #define DDI_DP_COMP_CTL_PRBS7 (2 << 28) |
| 4634 | #define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28) |
| 4635 | #define DDI_DP_COMP_CTL_HBR2 (4 << 28) |
| 4636 | #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) |
| 4637 | #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) |
| 4638 | |
| 4639 | /* DDI DP Compliance Pattern */ |
| 4640 | #define _DDI_DP_COMP_PAT_A 0x605F4 |
| 4641 | #define _DDI_DP_COMP_PAT_B 0x615F4 |
| 4642 | #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4) |
| 4643 | |
Eugeni Dodonov | 7501a4d | 2012-03-29 12:32:29 -0300 | [diff] [blame] | 4644 | /* Sideband Interface (SBI) is programmed indirectly, via |
| 4645 | * SBI_ADDR, which contains the register offset; and SBI_DATA, |
| 4646 | * which contains the payload */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4647 | #define SBI_ADDR _MMIO(0xC6000) |
| 4648 | #define SBI_DATA _MMIO(0xC6004) |
| 4649 | #define SBI_CTL_STAT _MMIO(0xC6008) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4650 | #define SBI_CTL_DEST_ICLK (0x0 << 16) |
| 4651 | #define SBI_CTL_DEST_MPHY (0x1 << 16) |
| 4652 | #define SBI_CTL_OP_IORD (0x2 << 8) |
| 4653 | #define SBI_CTL_OP_IOWR (0x3 << 8) |
| 4654 | #define SBI_CTL_OP_CRRD (0x6 << 8) |
| 4655 | #define SBI_CTL_OP_CRWR (0x7 << 8) |
| 4656 | #define SBI_RESPONSE_FAIL (0x1 << 1) |
| 4657 | #define SBI_RESPONSE_SUCCESS (0x0 << 1) |
| 4658 | #define SBI_BUSY (0x1 << 0) |
| 4659 | #define SBI_READY (0x0 << 0) |
Eugeni Dodonov | 52f025e | 2012-03-29 12:32:31 -0300 | [diff] [blame] | 4660 | |
Eugeni Dodonov | ccf1c86 | 2012-03-29 12:32:34 -0300 | [diff] [blame] | 4661 | /* SBI offsets */ |
Ville Syrjälä | f7be2c2 | 2015-12-04 22:19:39 +0200 | [diff] [blame] | 4662 | #define SBI_SSCDIVINTPHASE 0x0200 |
Paulo Zanoni | 5e49cea | 2012-08-08 14:15:31 -0300 | [diff] [blame] | 4663 | #define SBI_SSCDIVINTPHASE6 0x0600 |
Ville Syrjälä | 8802e5b | 2016-02-17 21:41:12 +0200 | [diff] [blame] | 4664 | #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4665 | #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) |
| 4666 | #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) |
Ville Syrjälä | 8802e5b | 2016-02-17 21:41:12 +0200 | [diff] [blame] | 4667 | #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4668 | #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) |
| 4669 | #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) |
| 4670 | #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) |
| 4671 | #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) |
Ville Syrjälä | f7be2c2 | 2015-12-04 22:19:39 +0200 | [diff] [blame] | 4672 | #define SBI_SSCDITHPHASE 0x0204 |
Paulo Zanoni | 5e49cea | 2012-08-08 14:15:31 -0300 | [diff] [blame] | 4673 | #define SBI_SSCCTL 0x020c |
Eugeni Dodonov | ccf1c86 | 2012-03-29 12:32:34 -0300 | [diff] [blame] | 4674 | #define SBI_SSCCTL6 0x060C |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4675 | #define SBI_SSCCTL_PATHALT (1 << 3) |
| 4676 | #define SBI_SSCCTL_DISABLE (1 << 0) |
Eugeni Dodonov | ccf1c86 | 2012-03-29 12:32:34 -0300 | [diff] [blame] | 4677 | #define SBI_SSCAUXDIV6 0x0610 |
Ville Syrjälä | 8802e5b | 2016-02-17 21:41:12 +0200 | [diff] [blame] | 4678 | #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4679 | #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) |
| 4680 | #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) |
Paulo Zanoni | 5e49cea | 2012-08-08 14:15:31 -0300 | [diff] [blame] | 4681 | #define SBI_DBUFF0 0x2a00 |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 4682 | #define SBI_GEN0 0x1f00 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4683 | #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) |
Eugeni Dodonov | ccf1c86 | 2012-03-29 12:32:34 -0300 | [diff] [blame] | 4684 | |
Eugeni Dodonov | 52f025e | 2012-03-29 12:32:31 -0300 | [diff] [blame] | 4685 | /* LPT PIXCLK_GATE */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4686 | #define PIXCLK_GATE _MMIO(0xC6020) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4687 | #define PIXCLK_GATE_UNGATE (1 << 0) |
| 4688 | #define PIXCLK_GATE_GATE (0 << 0) |
Eugeni Dodonov | 52f025e | 2012-03-29 12:32:31 -0300 | [diff] [blame] | 4689 | |
Eugeni Dodonov | e93ea06 | 2012-03-29 12:32:32 -0300 | [diff] [blame] | 4690 | /* SPLL */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4691 | #define SPLL_CTL _MMIO(0x46020) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4692 | #define SPLL_PLL_ENABLE (1 << 31) |
Ville Syrjälä | 4a95e36 | 2019-06-10 16:36:09 +0300 | [diff] [blame] | 4693 | #define SPLL_REF_BCLK (0 << 28) |
| 4694 | #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ |
| 4695 | #define SPLL_REF_NON_SSC_HSW (2 << 28) |
| 4696 | #define SPLL_REF_PCH_SSC_BDW (2 << 28) |
| 4697 | #define SPLL_REF_LCPLL (3 << 28) |
| 4698 | #define SPLL_REF_MASK (3 << 28) |
| 4699 | #define SPLL_FREQ_810MHz (0 << 26) |
| 4700 | #define SPLL_FREQ_1350MHz (1 << 26) |
| 4701 | #define SPLL_FREQ_2700MHz (2 << 26) |
| 4702 | #define SPLL_FREQ_MASK (3 << 26) |
Eugeni Dodonov | e93ea06 | 2012-03-29 12:32:32 -0300 | [diff] [blame] | 4703 | |
Eugeni Dodonov | 4dffc40 | 2012-03-29 12:32:36 -0300 | [diff] [blame] | 4704 | /* WRPLL */ |
Ville Syrjälä | 086f8e8 | 2015-11-04 23:20:01 +0200 | [diff] [blame] | 4705 | #define _WRPLL_CTL1 0x46040 |
| 4706 | #define _WRPLL_CTL2 0x46060 |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4707 | #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4708 | #define WRPLL_PLL_ENABLE (1 << 31) |
Ville Syrjälä | 4a95e36 | 2019-06-10 16:36:09 +0300 | [diff] [blame] | 4709 | #define WRPLL_REF_BCLK (0 << 28) |
| 4710 | #define WRPLL_REF_PCH_SSC (1 << 28) |
| 4711 | #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ |
| 4712 | #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */ |
| 4713 | #define WRPLL_REF_LCPLL (3 << 28) |
| 4714 | #define WRPLL_REF_MASK (3 << 28) |
Eugeni Dodonov | ef4d084 | 2012-04-13 17:08:38 -0300 | [diff] [blame] | 4715 | /* WRPLL divider programming */ |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4716 | #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) |
Jesse Barnes | 1157855 | 2014-01-21 12:42:10 -0800 | [diff] [blame] | 4717 | #define WRPLL_DIVIDER_REF_MASK (0xff) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4718 | #define WRPLL_DIVIDER_POST(x) ((x) << 8) |
| 4719 | #define WRPLL_DIVIDER_POST_MASK (0x3f << 8) |
Jesse Barnes | 1157855 | 2014-01-21 12:42:10 -0800 | [diff] [blame] | 4720 | #define WRPLL_DIVIDER_POST_SHIFT 8 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4721 | #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) |
Jesse Barnes | 1157855 | 2014-01-21 12:42:10 -0800 | [diff] [blame] | 4722 | #define WRPLL_DIVIDER_FB_SHIFT 16 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4723 | #define WRPLL_DIVIDER_FB_MASK (0xff << 16) |
Eugeni Dodonov | 4dffc40 | 2012-03-29 12:32:36 -0300 | [diff] [blame] | 4724 | |
Eugeni Dodonov | fec9181 | 2012-03-29 12:32:33 -0300 | [diff] [blame] | 4725 | /* Port clock selection */ |
Ville Syrjälä | 086f8e8 | 2015-11-04 23:20:01 +0200 | [diff] [blame] | 4726 | #define _PORT_CLK_SEL_A 0x46100 |
| 4727 | #define _PORT_CLK_SEL_B 0x46104 |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4728 | #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) |
Jani Nikula | 230fb39 | 2022-05-18 14:33:14 +0300 | [diff] [blame] | 4729 | #define PORT_CLK_SEL_MASK REG_GENMASK(31, 29) |
| 4730 | #define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0) |
| 4731 | #define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1) |
| 4732 | #define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2) |
| 4733 | #define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3) |
| 4734 | #define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll)) |
| 4735 | #define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4) |
| 4736 | #define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5) |
| 4737 | #define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7) |
Eugeni Dodonov | fec9181 | 2012-03-29 12:32:33 -0300 | [diff] [blame] | 4738 | |
Paulo Zanoni | 78b60ce | 2018-03-28 14:57:57 -0700 | [diff] [blame] | 4739 | /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ |
| 4740 | #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) |
Jani Nikula | 230fb39 | 2022-05-18 14:33:14 +0300 | [diff] [blame] | 4741 | #define DDI_CLK_SEL_MASK REG_GENMASK(31, 28) |
| 4742 | #define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0) |
| 4743 | #define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8) |
| 4744 | #define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC) |
| 4745 | #define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD) |
| 4746 | #define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE) |
| 4747 | #define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF) |
Paulo Zanoni | 78b60ce | 2018-03-28 14:57:57 -0700 | [diff] [blame] | 4748 | |
Paulo Zanoni | bb523fc | 2012-10-23 18:29:56 -0200 | [diff] [blame] | 4749 | /* Transcoder clock selection */ |
Ville Syrjälä | 086f8e8 | 2015-11-04 23:20:01 +0200 | [diff] [blame] | 4750 | #define _TRANS_CLK_SEL_A 0x46140 |
| 4751 | #define _TRANS_CLK_SEL_B 0x46144 |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4752 | #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) |
Paulo Zanoni | bb523fc | 2012-10-23 18:29:56 -0200 | [diff] [blame] | 4753 | /* For each transcoder, we need to select the corresponding port clock */ |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4754 | #define TRANS_CLK_SEL_DISABLED (0x0 << 29) |
| 4755 | #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) |
Mahesh Kumar | df16b63 | 2019-07-12 18:09:20 -0700 | [diff] [blame] | 4756 | #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28) |
| 4757 | #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28) |
| 4758 | |
Eugeni Dodonov | fec9181 | 2012-03-29 12:32:33 -0300 | [diff] [blame] | 4759 | |
Ville Syrjälä | 7f1052a | 2016-04-26 19:46:32 +0300 | [diff] [blame] | 4760 | #define CDCLK_FREQ _MMIO(0x46200) |
| 4761 | |
Ville Syrjälä | 086f8e8 | 2015-11-04 23:20:01 +0200 | [diff] [blame] | 4762 | #define _TRANSA_MSA_MISC 0x60410 |
| 4763 | #define _TRANSB_MSA_MISC 0x61410 |
| 4764 | #define _TRANSC_MSA_MISC 0x62410 |
| 4765 | #define _TRANS_EDP_MSA_MISC 0x6f410 |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 4766 | #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC) |
Ville Syrjälä | 3e706df | 2019-07-18 17:50:47 +0300 | [diff] [blame] | 4767 | /* See DP_MSA_MISC_* for the bit definitions */ |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 4768 | |
José Roberto de Souza | 1d53ccd | 2021-06-16 13:31:55 -0700 | [diff] [blame] | 4769 | #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C |
| 4770 | #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C |
| 4771 | #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C |
| 4772 | #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 4773 | #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY) |
José Roberto de Souza | 1d53ccd | 2021-06-16 13:31:55 -0700 | [diff] [blame] | 4774 | #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0) |
| 4775 | #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x)) |
| 4776 | |
Eugeni Dodonov | 90e8d31 | 2012-03-29 12:32:35 -0300 | [diff] [blame] | 4777 | /* LCPLL Control */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4778 | #define LCPLL_CTL _MMIO(0x130040) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4779 | #define LCPLL_PLL_DISABLE (1 << 31) |
| 4780 | #define LCPLL_PLL_LOCK (1 << 30) |
Ville Syrjälä | 4a95e36 | 2019-06-10 16:36:09 +0300 | [diff] [blame] | 4781 | #define LCPLL_REF_NON_SSC (0 << 28) |
| 4782 | #define LCPLL_REF_BCLK (2 << 28) |
| 4783 | #define LCPLL_REF_PCH_SSC (3 << 28) |
| 4784 | #define LCPLL_REF_MASK (3 << 28) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4785 | #define LCPLL_CLK_FREQ_MASK (3 << 26) |
| 4786 | #define LCPLL_CLK_FREQ_450 (0 << 26) |
| 4787 | #define LCPLL_CLK_FREQ_54O_BDW (1 << 26) |
| 4788 | #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) |
| 4789 | #define LCPLL_CLK_FREQ_675_BDW (3 << 26) |
| 4790 | #define LCPLL_CD_CLOCK_DISABLE (1 << 25) |
| 4791 | #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) |
| 4792 | #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) |
| 4793 | #define LCPLL_POWER_DOWN_ALLOW (1 << 22) |
| 4794 | #define LCPLL_CD_SOURCE_FCLK (1 << 21) |
| 4795 | #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 4796 | |
Satheeshakrishna M | 326ac39b | 2014-11-13 14:55:13 +0000 | [diff] [blame] | 4797 | /* |
| 4798 | * SKL Clocks |
| 4799 | */ |
| 4800 | |
| 4801 | /* CDCLK_CTL */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4802 | #define CDCLK_CTL _MMIO(0x46000) |
Stanislav Lisovskiy | f9feb882 | 2022-08-23 11:25:14 +0300 | [diff] [blame] | 4803 | #define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26) |
| 4804 | #define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0) |
| 4805 | #define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1) |
| 4806 | #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2) |
| 4807 | #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3) |
Gustavo Sousa | 5372a54 | 2024-03-12 13:36:33 -0300 | [diff] [blame] | 4808 | #define MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25) |
| 4809 | #define MDCLK_SOURCE_SEL_CD2XCLK REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0) |
| 4810 | #define MDCLK_SOURCE_SEL_CDCLK_PLL REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1) |
Stanislav Lisovskiy | f9feb882 | 2022-08-23 11:25:14 +0300 | [diff] [blame] | 4811 | #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22) |
| 4812 | #define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0) |
| 4813 | #define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1) |
| 4814 | #define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2) |
| 4815 | #define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3) |
Paulo Zanoni | 186a277 | 2018-02-06 17:33:46 -0200 | [diff] [blame] | 4816 | #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) |
| 4817 | #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) |
Ville Syrjälä | 7fe6275 | 2016-05-11 22:44:51 +0300 | [diff] [blame] | 4818 | #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) |
Matt Roper | 385ba62 | 2019-08-29 17:48:28 -0700 | [diff] [blame] | 4819 | #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19) |
Paulo Zanoni | 186a277 | 2018-02-06 17:33:46 -0200 | [diff] [blame] | 4820 | #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) |
Matt Roper | 385ba62 | 2019-08-29 17:48:28 -0700 | [diff] [blame] | 4821 | #define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe) |
| 4822 | #define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE |
Paulo Zanoni | 186a277 | 2018-02-06 17:33:46 -0200 | [diff] [blame] | 4823 | #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) |
Ville Syrjälä | 7fe6275 | 2016-05-11 22:44:51 +0300 | [diff] [blame] | 4824 | #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 4825 | |
Mika Kahola | 2060a68 | 2021-11-19 15:13:46 +0200 | [diff] [blame] | 4826 | /* CDCLK_SQUASH_CTL */ |
| 4827 | #define CDCLK_SQUASH_CTL _MMIO(0x46008) |
| 4828 | #define CDCLK_SQUASH_ENABLE REG_BIT(31) |
| 4829 | #define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24) |
| 4830 | #define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x)) |
| 4831 | #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0) |
| 4832 | #define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x)) |
| 4833 | |
Satheeshakrishna M | 326ac39b | 2014-11-13 14:55:13 +0000 | [diff] [blame] | 4834 | /* LCPLL_CTL */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4835 | #define LCPLL1_CTL _MMIO(0x46010) |
| 4836 | #define LCPLL2_CTL _MMIO(0x46014) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4837 | #define LCPLL_PLL_ENABLE (1 << 31) |
Satheeshakrishna M | 326ac39b | 2014-11-13 14:55:13 +0000 | [diff] [blame] | 4838 | |
| 4839 | /* DPLL control1 */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4840 | #define DPLL_CTRL1 _MMIO(0x6C058) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4841 | #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) |
| 4842 | #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) |
| 4843 | #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) |
| 4844 | #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) |
| 4845 | #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) |
| 4846 | #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) |
Damien Lespiau | 71cd842 | 2015-04-30 16:39:17 +0100 | [diff] [blame] | 4847 | #define DPLL_CTRL1_LINK_RATE_2700 0 |
| 4848 | #define DPLL_CTRL1_LINK_RATE_1350 1 |
| 4849 | #define DPLL_CTRL1_LINK_RATE_810 2 |
| 4850 | #define DPLL_CTRL1_LINK_RATE_1620 3 |
| 4851 | #define DPLL_CTRL1_LINK_RATE_1080 4 |
| 4852 | #define DPLL_CTRL1_LINK_RATE_2160 5 |
Satheeshakrishna M | 326ac39b | 2014-11-13 14:55:13 +0000 | [diff] [blame] | 4853 | |
| 4854 | /* DPLL control2 */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4855 | #define DPLL_CTRL2 _MMIO(0x6C05C) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4856 | #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) |
| 4857 | #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) |
| 4858 | #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) |
| 4859 | #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) |
| 4860 | #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) |
Satheeshakrishna M | 326ac39b | 2014-11-13 14:55:13 +0000 | [diff] [blame] | 4861 | |
| 4862 | /* DPLL Status */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4863 | #define DPLL_STATUS _MMIO(0x6C060) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4864 | #define DPLL_LOCK(id) (1 << ((id) * 8)) |
Satheeshakrishna M | 326ac39b | 2014-11-13 14:55:13 +0000 | [diff] [blame] | 4865 | |
| 4866 | /* DPLL cfg */ |
Ville Syrjälä | 086f8e8 | 2015-11-04 23:20:01 +0200 | [diff] [blame] | 4867 | #define _DPLL1_CFGCR1 0x6C040 |
| 4868 | #define _DPLL2_CFGCR1 0x6C048 |
| 4869 | #define _DPLL3_CFGCR1 0x6C050 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4870 | #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) |
| 4871 | #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) |
| 4872 | #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) |
Satheeshakrishna M | 326ac39b | 2014-11-13 14:55:13 +0000 | [diff] [blame] | 4873 | #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) |
| 4874 | |
Ville Syrjälä | 086f8e8 | 2015-11-04 23:20:01 +0200 | [diff] [blame] | 4875 | #define _DPLL1_CFGCR2 0x6C044 |
| 4876 | #define _DPLL2_CFGCR2 0x6C04C |
| 4877 | #define _DPLL3_CFGCR2 0x6C054 |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 4878 | #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) |
| 4879 | #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) |
| 4880 | #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) |
| 4881 | #define DPLL_CFGCR2_KDIV_MASK (3 << 5) |
| 4882 | #define DPLL_CFGCR2_KDIV(x) ((x) << 5) |
| 4883 | #define DPLL_CFGCR2_KDIV_5 (0 << 5) |
| 4884 | #define DPLL_CFGCR2_KDIV_2 (1 << 5) |
| 4885 | #define DPLL_CFGCR2_KDIV_3 (2 << 5) |
| 4886 | #define DPLL_CFGCR2_KDIV_1 (3 << 5) |
| 4887 | #define DPLL_CFGCR2_PDIV_MASK (7 << 2) |
| 4888 | #define DPLL_CFGCR2_PDIV(x) ((x) << 2) |
| 4889 | #define DPLL_CFGCR2_PDIV_1 (0 << 2) |
| 4890 | #define DPLL_CFGCR2_PDIV_2 (1 << 2) |
| 4891 | #define DPLL_CFGCR2_PDIV_3 (2 << 2) |
| 4892 | #define DPLL_CFGCR2_PDIV_7 (4 << 2) |
Imre Deak | 7a8a95f | 2020-10-06 04:35:55 +0300 | [diff] [blame] | 4893 | #define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2) |
Satheeshakrishna M | 326ac39b | 2014-11-13 14:55:13 +0000 | [diff] [blame] | 4894 | #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) |
| 4895 | |
Lyude | da3b891 | 2016-02-04 10:43:21 -0500 | [diff] [blame] | 4896 | #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4897 | #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) |
Satheeshakrishna M | 540e732 | 2014-11-13 14:55:16 +0000 | [diff] [blame] | 4898 | |
Lucas De Marchi | 11ffe97 | 2020-11-06 13:00:06 -0800 | [diff] [blame] | 4899 | /* ICL Clocks */ |
Matt Roper | befa372 | 2019-07-09 11:39:31 -0700 | [diff] [blame] | 4900 | #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) |
Aditya Swarup | d6d2bc9 | 2021-01-25 06:07:49 -0800 | [diff] [blame] | 4901 | #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5)) |
Matt Roper | cd803bb | 2020-07-16 15:05:47 -0700 | [diff] [blame] | 4902 | #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) |
Ville Syrjälä | 320c670 | 2020-10-28 23:33:05 +0200 | [diff] [blame] | 4903 | #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ |
Mahesh Kumar | aaf70b9 | 2019-07-12 18:09:21 -0700 | [diff] [blame] | 4904 | (tc_port) + 12 : \ |
Ville Syrjälä | 320c670 | 2020-10-28 23:33:05 +0200 | [diff] [blame] | 4905 | (tc_port) - TC_PORT_4 + 21)) |
Matt Roper | befa372 | 2019-07-09 11:39:31 -0700 | [diff] [blame] | 4906 | #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) |
| 4907 | #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) |
| 4908 | #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) |
Matt Roper | cd803bb | 2020-07-16 15:05:47 -0700 | [diff] [blame] | 4909 | #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) |
| 4910 | #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ |
| 4911 | (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) |
| 4912 | #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ |
| 4913 | ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) |
Matt Roper | befa372 | 2019-07-09 11:39:31 -0700 | [diff] [blame] | 4914 | |
Lucas De Marchi | 11ffe97 | 2020-11-06 13:00:06 -0800 | [diff] [blame] | 4915 | /* |
| 4916 | * DG1 Clocks |
| 4917 | * First registers controls the first A and B, while the second register |
| 4918 | * controls the phy C and D. The bits on these registers are the |
| 4919 | * same, but refer to different phys |
| 4920 | */ |
| 4921 | #define _DG1_DPCLKA_CFGCR0 0x164280 |
| 4922 | #define _DG1_DPCLKA1_CFGCR0 0x16C280 |
| 4923 | #define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2) |
| 4924 | #define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2) |
Lucas De Marchi | 11ffe97 | 2020-11-06 13:00:06 -0800 | [diff] [blame] | 4925 | #define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \ |
| 4926 | _DG1_DPCLKA_CFGCR0, \ |
| 4927 | _DG1_DPCLKA1_CFGCR0) |
| 4928 | #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10) |
| 4929 | #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2) |
| 4930 | #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) |
| 4931 | #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) |
Lucas De Marchi | 11ffe97 | 2020-11-06 13:00:06 -0800 | [diff] [blame] | 4932 | |
Aditya Swarup | d6d2bc9 | 2021-01-25 06:07:49 -0800 | [diff] [blame] | 4933 | /* ADLS Clocks */ |
| 4934 | #define _ADLS_DPCLKA_CFGCR0 0x164280 |
| 4935 | #define _ADLS_DPCLKA_CFGCR1 0x1642BC |
| 4936 | #define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \ |
| 4937 | _ADLS_DPCLKA_CFGCR0, \ |
| 4938 | _ADLS_DPCLKA_CFGCR1) |
| 4939 | #define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2) |
| 4940 | /* ADLS DPCLKA_CFGCR0 DDI mask */ |
| 4941 | #define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4) |
| 4942 | #define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2) |
| 4943 | #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0) |
| 4944 | /* ADLS DPCLKA_CFGCR1 DDI mask */ |
| 4945 | #define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2) |
| 4946 | #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0) |
| 4947 | #define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \ |
| 4948 | ADLS_DPCLKA_DDIA_SEL_MASK, \ |
| 4949 | ADLS_DPCLKA_DDIB_SEL_MASK, \ |
| 4950 | ADLS_DPCLKA_DDII_SEL_MASK, \ |
| 4951 | ADLS_DPCLKA_DDIJ_SEL_MASK, \ |
| 4952 | ADLS_DPCLKA_DDIK_SEL_MASK) |
| 4953 | |
Lucas De Marchi | 8de358c | 2021-07-29 16:39:35 -0700 | [diff] [blame] | 4954 | /* ICL PLL */ |
Lucas De Marchi | 6d8d5c6 | 2023-01-20 11:34:51 -0800 | [diff] [blame] | 4955 | #define _DPLL0_ENABLE 0x46010 |
| 4956 | #define _DPLL1_ENABLE 0x46014 |
Aditya Swarup | 80d0f765 | 2021-01-25 06:07:48 -0800 | [diff] [blame] | 4957 | #define _ADLS_DPLL2_ENABLE 0x46018 |
| 4958 | #define _ADLS_DPLL3_ENABLE 0x46030 |
Lucas De Marchi | 6d8d5c6 | 2023-01-20 11:34:51 -0800 | [diff] [blame] | 4959 | #define PLL_ENABLE REG_BIT(31) |
| 4960 | #define PLL_LOCK REG_BIT(30) |
| 4961 | #define PLL_POWER_ENABLE REG_BIT(27) |
| 4962 | #define PLL_POWER_STATE REG_BIT(26) |
Lucas De Marchi | 680d0c7 | 2023-01-20 11:34:52 -0800 | [diff] [blame] | 4963 | #define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ |
| 4964 | _DPLL0_ENABLE, _DPLL1_ENABLE, \ |
| 4965 | _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE)) |
Rodrigo Vivi | a927c92 | 2017-06-09 15:26:04 -0700 | [diff] [blame] | 4966 | |
Matt Roper | 2908100 | 2021-07-23 10:42:32 -0700 | [diff] [blame] | 4967 | #define _DG2_PLL3_ENABLE 0x4601C |
| 4968 | |
Lucas De Marchi | 680d0c7 | 2023-01-20 11:34:52 -0800 | [diff] [blame] | 4969 | #define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ |
| 4970 | _DPLL0_ENABLE, _DPLL1_ENABLE, \ |
| 4971 | _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE)) |
Matt Roper | 2908100 | 2021-07-23 10:42:32 -0700 | [diff] [blame] | 4972 | |
Paulo Zanoni | 1fa11ee | 2018-05-21 17:25:48 -0700 | [diff] [blame] | 4973 | #define TBT_PLL_ENABLE _MMIO(0x46020) |
| 4974 | |
Paulo Zanoni | 78b60ce | 2018-03-28 14:57:57 -0700 | [diff] [blame] | 4975 | #define _MG_PLL1_ENABLE 0x46030 |
| 4976 | #define _MG_PLL2_ENABLE 0x46034 |
| 4977 | #define _MG_PLL3_ENABLE 0x46038 |
| 4978 | #define _MG_PLL4_ENABLE 0x4603C |
Lucas De Marchi | 6d8d5c6 | 2023-01-20 11:34:51 -0800 | [diff] [blame] | 4979 | /* Bits are the same as _DPLL0_ENABLE */ |
Lucas De Marchi | 584fca1 | 2019-01-25 14:24:41 -0800 | [diff] [blame] | 4980 | #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ |
Paulo Zanoni | 78b60ce | 2018-03-28 14:57:57 -0700 | [diff] [blame] | 4981 | _MG_PLL2_ENABLE) |
| 4982 | |
Lucas De Marchi | 0dac17a | 2020-10-14 12:19:32 -0700 | [diff] [blame] | 4983 | /* DG1 PLL */ |
Lucas De Marchi | 680d0c7 | 2023-01-20 11:34:52 -0800 | [diff] [blame] | 4984 | #define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ |
| 4985 | _DPLL0_ENABLE, _DPLL1_ENABLE, \ |
| 4986 | _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)) |
Lucas De Marchi | 0dac17a | 2020-10-14 12:19:32 -0700 | [diff] [blame] | 4987 | |
Anusha Srivatsa | 226c832 | 2021-05-18 17:06:22 -0700 | [diff] [blame] | 4988 | /* ADL-P Type C PLL */ |
| 4989 | #define PORTTC1_PLL_ENABLE 0x46038 |
| 4990 | #define PORTTC2_PLL_ENABLE 0x46040 |
| 4991 | |
| 4992 | #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ |
| 4993 | PORTTC1_PLL_ENABLE, \ |
| 4994 | PORTTC2_PLL_ENABLE) |
| 4995 | |
Paulo Zanoni | 78b60ce | 2018-03-28 14:57:57 -0700 | [diff] [blame] | 4996 | #define _ICL_DPLL0_CFGCR0 0x164000 |
| 4997 | #define _ICL_DPLL1_CFGCR0 0x164080 |
| 4998 | #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ |
| 4999 | _ICL_DPLL1_CFGCR0) |
Lucas De Marchi | a4d082f | 2021-07-28 14:59:45 -0700 | [diff] [blame] | 5000 | #define DPLL_CFGCR0_HDMI_MODE (1 << 30) |
| 5001 | #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) |
| 5002 | #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) |
| 5003 | #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) |
| 5004 | #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) |
| 5005 | #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) |
| 5006 | #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) |
| 5007 | #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) |
| 5008 | #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) |
| 5009 | #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) |
| 5010 | #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) |
| 5011 | #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) |
| 5012 | #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) |
| 5013 | #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) |
| 5014 | #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) |
| 5015 | #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) |
Paulo Zanoni | 78b60ce | 2018-03-28 14:57:57 -0700 | [diff] [blame] | 5016 | |
| 5017 | #define _ICL_DPLL0_CFGCR1 0x164004 |
| 5018 | #define _ICL_DPLL1_CFGCR1 0x164084 |
| 5019 | #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ |
| 5020 | _ICL_DPLL1_CFGCR1) |
Lucas De Marchi | a4d082f | 2021-07-28 14:59:45 -0700 | [diff] [blame] | 5021 | #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) |
| 5022 | #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) |
| 5023 | #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) |
| 5024 | #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) |
| 5025 | #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) |
| 5026 | #define DPLL_CFGCR1_KDIV_MASK (7 << 6) |
| 5027 | #define DPLL_CFGCR1_KDIV_SHIFT (6) |
| 5028 | #define DPLL_CFGCR1_KDIV(x) ((x) << 6) |
| 5029 | #define DPLL_CFGCR1_KDIV_1 (1 << 6) |
| 5030 | #define DPLL_CFGCR1_KDIV_2 (2 << 6) |
| 5031 | #define DPLL_CFGCR1_KDIV_3 (4 << 6) |
| 5032 | #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) |
| 5033 | #define DPLL_CFGCR1_PDIV_SHIFT (2) |
| 5034 | #define DPLL_CFGCR1_PDIV(x) ((x) << 2) |
| 5035 | #define DPLL_CFGCR1_PDIV_2 (1 << 2) |
| 5036 | #define DPLL_CFGCR1_PDIV_3 (2 << 2) |
| 5037 | #define DPLL_CFGCR1_PDIV_5 (4 << 2) |
| 5038 | #define DPLL_CFGCR1_PDIV_7 (8 << 2) |
| 5039 | #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) |
| 5040 | #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) |
| 5041 | #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0) |
Paulo Zanoni | 78b60ce | 2018-03-28 14:57:57 -0700 | [diff] [blame] | 5042 | |
Lucas De Marchi | 36ca533 | 2019-07-11 10:31:14 -0700 | [diff] [blame] | 5043 | #define _TGL_DPLL0_CFGCR0 0x164284 |
| 5044 | #define _TGL_DPLL1_CFGCR0 0x16428C |
Lucas De Marchi | 36ca533 | 2019-07-11 10:31:14 -0700 | [diff] [blame] | 5045 | #define _TGL_TBTPLL_CFGCR0 0x16429C |
Lucas De Marchi | 680d0c7 | 2023-01-20 11:34:52 -0800 | [diff] [blame] | 5046 | #define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ |
| 5047 | _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ |
| 5048 | _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0)) |
Matt Roper | e66f609 | 2020-07-16 15:05:49 -0700 | [diff] [blame] | 5049 | #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ |
| 5050 | _TGL_DPLL1_CFGCR0) |
Lucas De Marchi | 36ca533 | 2019-07-11 10:31:14 -0700 | [diff] [blame] | 5051 | |
José Roberto de Souza | b70ad01 | 2022-02-16 05:40:59 -0800 | [diff] [blame] | 5052 | #define _TGL_DPLL0_DIV0 0x164B00 |
| 5053 | #define _TGL_DPLL1_DIV0 0x164C00 |
| 5054 | #define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0) |
| 5055 | #define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) |
| 5056 | #define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val)) |
| 5057 | |
Lucas De Marchi | 36ca533 | 2019-07-11 10:31:14 -0700 | [diff] [blame] | 5058 | #define _TGL_DPLL0_CFGCR1 0x164288 |
| 5059 | #define _TGL_DPLL1_CFGCR1 0x164290 |
Lucas De Marchi | 36ca533 | 2019-07-11 10:31:14 -0700 | [diff] [blame] | 5060 | #define _TGL_TBTPLL_CFGCR1 0x1642A0 |
Lucas De Marchi | 680d0c7 | 2023-01-20 11:34:52 -0800 | [diff] [blame] | 5061 | #define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ |
| 5062 | _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ |
| 5063 | _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1)) |
Matt Roper | e66f609 | 2020-07-16 15:05:49 -0700 | [diff] [blame] | 5064 | #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ |
| 5065 | _TGL_DPLL1_CFGCR1) |
Lucas De Marchi | 36ca533 | 2019-07-11 10:31:14 -0700 | [diff] [blame] | 5066 | |
Aditya Swarup | 049c651 | 2020-10-14 12:19:30 -0700 | [diff] [blame] | 5067 | #define _DG1_DPLL2_CFGCR0 0x16C284 |
| 5068 | #define _DG1_DPLL3_CFGCR0 0x16C28C |
Lucas De Marchi | 680d0c7 | 2023-01-20 11:34:52 -0800 | [diff] [blame] | 5069 | #define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ |
| 5070 | _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ |
| 5071 | _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0)) |
Aditya Swarup | 049c651 | 2020-10-14 12:19:30 -0700 | [diff] [blame] | 5072 | |
| 5073 | #define _DG1_DPLL2_CFGCR1 0x16C288 |
| 5074 | #define _DG1_DPLL3_CFGCR1 0x16C290 |
Lucas De Marchi | 680d0c7 | 2023-01-20 11:34:52 -0800 | [diff] [blame] | 5075 | #define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ |
| 5076 | _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ |
| 5077 | _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1)) |
Aditya Swarup | 049c651 | 2020-10-14 12:19:30 -0700 | [diff] [blame] | 5078 | |
Aditya Swarup | 80d0f765 | 2021-01-25 06:07:48 -0800 | [diff] [blame] | 5079 | /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ |
Aditya Swarup | 80d0f765 | 2021-01-25 06:07:48 -0800 | [diff] [blame] | 5080 | #define _ADLS_DPLL4_CFGCR0 0x164294 |
Lucas De Marchi | 680d0c7 | 2023-01-20 11:34:52 -0800 | [diff] [blame] | 5081 | #define _ADLS_DPLL3_CFGCR0 0x1642C0 |
| 5082 | #define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ |
| 5083 | _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ |
| 5084 | _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0)) |
Aditya Swarup | 80d0f765 | 2021-01-25 06:07:48 -0800 | [diff] [blame] | 5085 | |
Aditya Swarup | 80d0f765 | 2021-01-25 06:07:48 -0800 | [diff] [blame] | 5086 | #define _ADLS_DPLL4_CFGCR1 0x164298 |
Lucas De Marchi | 680d0c7 | 2023-01-20 11:34:52 -0800 | [diff] [blame] | 5087 | #define _ADLS_DPLL3_CFGCR1 0x1642C4 |
| 5088 | #define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ |
| 5089 | _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ |
| 5090 | _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1)) |
Aditya Swarup | 80d0f765 | 2021-01-25 06:07:48 -0800 | [diff] [blame] | 5091 | |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 5092 | /* BXT display engine PLL */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 5093 | #define BXT_DE_PLL_CTL _MMIO(0x6d000) |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 5094 | #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ |
| 5095 | #define BXT_DE_PLL_RATIO_MASK 0xff |
| 5096 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 5097 | #define BXT_DE_PLL_ENABLE _MMIO(0x46070) |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 5098 | #define BXT_DE_PLL_PLL_ENABLE (1 << 31) |
| 5099 | #define BXT_DE_PLL_LOCK (1 << 30) |
Stanislav Lisovskiy | d62686b | 2021-06-03 09:50:38 +0300 | [diff] [blame] | 5100 | #define BXT_DE_PLL_FREQ_REQ (1 << 23) |
| 5101 | #define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22) |
Lucas De Marchi | 1d89509 | 2021-07-28 14:59:23 -0700 | [diff] [blame] | 5102 | #define ICL_CDCLK_PLL_RATIO(x) (x) |
| 5103 | #define ICL_CDCLK_PLL_RATIO_MASK 0xff |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 5104 | |
A.Sunil Kamath | 664326f | 2014-11-24 13:37:44 +0530 | [diff] [blame] | 5105 | /* GEN9 DC */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 5106 | #define DC_STATE_EN _MMIO(0x45504) |
Imre Deak | 13ae3a0 | 2015-11-04 19:24:16 +0200 | [diff] [blame] | 5107 | #define DC_STATE_DISABLE 0 |
Anshuman Gupta | e45e0003 | 2019-10-07 15:16:07 +0530 | [diff] [blame] | 5108 | #define DC_STATE_EN_DC3CO REG_BIT(30) |
| 5109 | #define DC_STATE_DC3CO_STATUS REG_BIT(29) |
José Roberto de Souza | c4298d1 | 2023-03-01 12:10:53 -0800 | [diff] [blame] | 5110 | #define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21) |
| 5111 | #define HOLD_PHY_PG1_LATCH REG_BIT(20) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 5112 | #define DC_STATE_EN_UPTO_DC5 (1 << 0) |
| 5113 | #define DC_STATE_EN_DC9 (1 << 3) |
| 5114 | #define DC_STATE_EN_UPTO_DC6 (2 << 0) |
A.Sunil Kamath | 6b457d3 | 2015-04-16 14:22:09 +0530 | [diff] [blame] | 5115 | #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 |
| 5116 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 5117 | #define DC_STATE_DEBUG _MMIO(0x45520) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 5118 | #define DC_STATE_DEBUG_MASK_CORES (1 << 0) |
| 5119 | #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) |
A.Sunil Kamath | 6b457d3 | 2015-04-16 14:22:09 +0530 | [diff] [blame] | 5120 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 5121 | #define D_COMP_BDW _MMIO(0x138144) |
Eugeni Dodonov | 90e8d31 | 2012-03-29 12:32:35 -0300 | [diff] [blame] | 5122 | |
Eugeni Dodonov | 69e94b7 | 2012-03-29 12:32:37 -0300 | [diff] [blame] | 5123 | /* Pipe WM_LINETIME - watermark line time */ |
Ville Syrjälä | 0560b0c | 2020-01-20 19:47:11 +0200 | [diff] [blame] | 5124 | #define _WM_LINETIME_A 0x45270 |
| 5125 | #define _WM_LINETIME_B 0x45274 |
| 5126 | #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B) |
| 5127 | #define HSW_LINETIME_MASK REG_GENMASK(8, 0) |
| 5128 | #define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x)) |
| 5129 | #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16) |
| 5130 | #define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x)) |
Eugeni Dodonov | 96d6e35 | 2012-03-29 12:32:38 -0300 | [diff] [blame] | 5131 | |
| 5132 | /* SFUSE_STRAP */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 5133 | #define SFUSE_STRAP _MMIO(0xc2014) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 5134 | #define SFUSE_STRAP_FUSE_LOCK (1 << 13) |
| 5135 | #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) |
| 5136 | #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) |
| 5137 | #define SFUSE_STRAP_CRT_DISABLED (1 << 6) |
| 5138 | #define SFUSE_STRAP_DDIF_DETECTED (1 << 3) |
| 5139 | #define SFUSE_STRAP_DDIB_DETECTED (1 << 2) |
| 5140 | #define SFUSE_STRAP_DDIC_DETECTED (1 << 1) |
| 5141 | #define SFUSE_STRAP_DDID_DETECTED (1 << 0) |
Eugeni Dodonov | 96d6e35 | 2012-03-29 12:32:38 -0300 | [diff] [blame] | 5142 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 5143 | #define WM_MISC _MMIO(0x45260) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 5144 | #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) |
| 5145 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 5146 | #define WM_DBG _MMIO(0x45280) |
Paulo Zanoni | 5ee8ee8 | 2018-06-18 11:09:43 -0700 | [diff] [blame] | 5147 | #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0) |
| 5148 | #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) |
| 5149 | #define WM_DBG_DISALLOW_SPRITE (1 << 2) |
Eugeni Dodonov | 1544d9d | 2012-07-02 11:51:10 -0300 | [diff] [blame] | 5150 | |
Anshuman Gupta | 6eba56f | 2021-09-24 12:14:49 -0700 | [diff] [blame] | 5151 | #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) |
| 5152 | |
| 5153 | /* Plane CSC Registers */ |
| 5154 | #define _PLANE_CSC_RY_GY_1_A 0x70210 |
| 5155 | #define _PLANE_CSC_RY_GY_2_A 0x70310 |
| 5156 | |
| 5157 | #define _PLANE_CSC_RY_GY_1_B 0x71210 |
| 5158 | #define _PLANE_CSC_RY_GY_2_B 0x71310 |
| 5159 | |
| 5160 | #define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \ |
| 5161 | _PLANE_CSC_RY_GY_1_B) |
Chaitanya Kumar Borah | e39c76b | 2023-03-30 20:31:04 +0530 | [diff] [blame] | 5162 | #define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, \ |
| 5163 | _PLANE_CSC_RY_GY_2_B) |
Anshuman Gupta | 6eba56f | 2021-09-24 12:14:49 -0700 | [diff] [blame] | 5164 | #define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \ |
| 5165 | _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ |
| 5166 | _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) |
| 5167 | |
| 5168 | #define _PLANE_CSC_PREOFF_HI_1_A 0x70228 |
| 5169 | #define _PLANE_CSC_PREOFF_HI_2_A 0x70328 |
| 5170 | |
| 5171 | #define _PLANE_CSC_PREOFF_HI_1_B 0x71228 |
| 5172 | #define _PLANE_CSC_PREOFF_HI_2_B 0x71328 |
| 5173 | |
| 5174 | #define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \ |
| 5175 | _PLANE_CSC_PREOFF_HI_1_B) |
| 5176 | #define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \ |
| 5177 | _PLANE_CSC_PREOFF_HI_2_B) |
| 5178 | #define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \ |
| 5179 | (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \ |
| 5180 | (index) * 4) |
| 5181 | |
| 5182 | #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 |
| 5183 | #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 |
| 5184 | |
| 5185 | #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 |
| 5186 | #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 |
| 5187 | |
| 5188 | #define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \ |
| 5189 | _PLANE_CSC_POSTOFF_HI_1_B) |
| 5190 | #define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \ |
| 5191 | _PLANE_CSC_POSTOFF_HI_2_B) |
| 5192 | #define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \ |
| 5193 | (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ |
| 5194 | (index) * 4) |
| 5195 | |
Uma Shankar | aec0246 | 2017-09-25 19:26:01 +0530 | [diff] [blame] | 5196 | /* Gen4+ Timestamp and Pipe Frame time stamp registers */ |
| 5197 | #define GEN4_TIMESTAMP _MMIO(0x2358) |
| 5198 | #define ILK_TIMESTAMP_HI _MMIO(0x70070) |
| 5199 | #define IVB_TIMESTAMP_CTR _MMIO(0x44070) |
| 5200 | |
Lionel Landwerlin | dab9178 | 2017-11-10 19:08:44 +0000 | [diff] [blame] | 5201 | #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) |
| 5202 | #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 |
| 5203 | #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff |
| 5204 | #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 |
| 5205 | #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) |
| 5206 | |
Ville Syrjälä | 6e889b1 | 2023-03-14 15:02:49 +0200 | [diff] [blame] | 5207 | /* g4x+, except vlv/chv! */ |
Uma Shankar | aec0246 | 2017-09-25 19:26:01 +0530 | [diff] [blame] | 5208 | #define _PIPE_FRMTMSTMP_A 0x70048 |
Ville Syrjälä | 6e889b1 | 2023-03-14 15:02:49 +0200 | [diff] [blame] | 5209 | #define _PIPE_FRMTMSTMP_B 0x71048 |
Uma Shankar | aec0246 | 2017-09-25 19:26:01 +0530 | [diff] [blame] | 5210 | #define PIPE_FRMTMSTMP(pipe) \ |
Ville Syrjälä | 6e889b1 | 2023-03-14 15:02:49 +0200 | [diff] [blame] | 5211 | _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B) |
| 5212 | |
| 5213 | /* g4x+, except vlv/chv! */ |
| 5214 | #define _PIPE_FLIPTMSTMP_A 0x7004C |
| 5215 | #define _PIPE_FLIPTMSTMP_B 0x7104C |
| 5216 | #define PIPE_FLIPTMSTMP(pipe) \ |
| 5217 | _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B) |
| 5218 | |
| 5219 | /* tgl+ */ |
| 5220 | #define _PIPE_FLIPDONETMSTMP_A 0x70054 |
| 5221 | #define _PIPE_FLIPDONETMSTMP_B 0x71054 |
| 5222 | #define PIPE_FLIPDONETIMSTMP(pipe) \ |
| 5223 | _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B) |
Uma Shankar | aec0246 | 2017-09-25 19:26:01 +0530 | [diff] [blame] | 5224 | |
Ville Syrjälä | c931ef0 | 2023-03-14 15:02:50 +0200 | [diff] [blame] | 5225 | #define _VLV_PIPE_MSA_MISC_A 0x70048 |
| 5226 | #define VLV_PIPE_MSA_MISC(pipe) \ |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 5227 | _MMIO_PIPE2(dev_priv, pipe, _VLV_PIPE_MSA_MISC_A) |
Ville Syrjälä | c931ef0 | 2023-03-14 15:02:50 +0200 | [diff] [blame] | 5228 | #define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31) |
| 5229 | #define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */ |
| 5230 | |
Aravind Iddamsetty | dbb2ffb | 2022-09-29 17:16:58 +0530 | [diff] [blame] | 5231 | #define GGC _MMIO(0x108040) |
| 5232 | #define GMS_MASK REG_GENMASK(15, 8) |
| 5233 | #define GGMS_MASK REG_GENMASK(7, 6) |
| 5234 | |
Ville Syrjälä | f8ae1d5 | 2024-02-03 00:43:30 +0200 | [diff] [blame] | 5235 | #define GEN6_GSMBASE _MMIO(0x108100) |
| 5236 | #define GEN6_DSMBASE _MMIO(0x1080C0) |
| 5237 | #define GEN6_BDSM_MASK REG_GENMASK64(31, 20) |
| 5238 | #define GEN11_BDSM_MASK REG_GENMASK64(63, 20) |
CQ Tang | 7f2aa5b | 2021-01-27 13:14:12 +0000 | [diff] [blame] | 5239 | |
Stuart Summers | d73dd1f | 2021-11-02 15:25:09 -0700 | [diff] [blame] | 5240 | #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014) |
Matt Roper | 645cc0b | 2021-11-02 15:25:10 -0700 | [diff] [blame] | 5241 | #define SGSI_SIDECLK_DIS REG_BIT(17) |
| 5242 | #define SGGI_DIS REG_BIT(15) |
Stuart Summers | d73dd1f | 2021-11-02 15:25:09 -0700 | [diff] [blame] | 5243 | #define SGR_DIS REG_BIT(13) |
| 5244 | |
Paulo Zanoni | ad186f3 | 2018-02-05 13:40:43 -0200 | [diff] [blame] | 5245 | #define _ICL_PHY_MISC_A 0x64C00 |
| 5246 | #define _ICL_PHY_MISC_B 0x64C04 |
Jouni Högander | d1af7b6 | 2022-02-17 17:03:26 -0800 | [diff] [blame] | 5247 | #define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */ |
| 5248 | #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B) |
| 5249 | #define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \ |
| 5250 | ICL_PHY_MISC(port)) |
Matt Roper | bdeb18d | 2019-06-18 10:51:31 -0700 | [diff] [blame] | 5251 | #define ICL_PHY_MISC_MUX_DDID (1 << 28) |
Paulo Zanoni | ad186f3 | 2018-02-05 13:40:43 -0200 | [diff] [blame] | 5252 | #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) |
Matt Roper | a6a1281 | 2021-07-23 10:42:36 -0700 | [diff] [blame] | 5253 | #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20) |
Paulo Zanoni | ad186f3 | 2018-02-05 13:40:43 -0200 | [diff] [blame] | 5254 | |
Anusha Srivatsa | 0caf625 | 2019-07-11 22:57:05 -0700 | [diff] [blame] | 5255 | #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0) |
| 5256 | #define MODULAR_FIA_MASK (1 << 4) |
José Roberto de Souza | 31d9ae9 | 2019-09-20 13:58:06 -0700 | [diff] [blame] | 5257 | #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6)) |
| 5258 | #define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5)) |
| 5259 | #define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8) |
| 5260 | #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8)) |
| 5261 | #define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8)) |
Paulo Zanoni | b9fcdda | 2018-07-25 12:59:27 -0700 | [diff] [blame] | 5262 | |
Anusha Srivatsa | 0caf625 | 2019-07-11 22:57:05 -0700 | [diff] [blame] | 5263 | #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890) |
José Roberto de Souza | 31d9ae9 | 2019-09-20 13:58:06 -0700 | [diff] [blame] | 5264 | #define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx)) |
Paulo Zanoni | 39d1e234 | 2018-08-01 10:34:41 -0700 | [diff] [blame] | 5265 | |
Anusha Srivatsa | 0caf625 | 2019-07-11 22:57:05 -0700 | [diff] [blame] | 5266 | #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894) |
José Roberto de Souza | 31d9ae9 | 2019-09-20 13:58:06 -0700 | [diff] [blame] | 5267 | #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx)) |
Paulo Zanoni | 39d1e234 | 2018-08-01 10:34:41 -0700 | [diff] [blame] | 5268 | |
Clinton A Taylor | 3b51be4 | 2019-09-26 14:06:56 -0700 | [diff] [blame] | 5269 | #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880) |
| 5270 | #define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4) |
| 5271 | #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4)) |
| 5272 | #define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4)) |
| 5273 | |
José Roberto de Souza | 55ce306 | 2021-05-18 17:06:13 -0700 | [diff] [blame] | 5274 | #define _TCSS_DDI_STATUS_1 0x161500 |
| 5275 | #define _TCSS_DDI_STATUS_2 0x161504 |
| 5276 | #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \ |
| 5277 | _TCSS_DDI_STATUS_1, \ |
| 5278 | _TCSS_DDI_STATUS_2)) |
Luca Coelho | 6f35a04 | 2023-09-19 12:21:20 -0700 | [diff] [blame] | 5279 | #define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25) |
José Roberto de Souza | 55ce306 | 2021-05-18 17:06:13 -0700 | [diff] [blame] | 5280 | #define TCSS_DDI_STATUS_READY REG_BIT(2) |
| 5281 | #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1) |
| 5282 | #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0) |
| 5283 | |
Clint Taylor | a36e7dc | 2021-12-15 22:26:45 -0800 | [diff] [blame] | 5284 | #define PRIMARY_SPI_TRIGGER _MMIO(0x102040) |
| 5285 | #define PRIMARY_SPI_ADDRESS _MMIO(0x102080) |
| 5286 | #define PRIMARY_SPI_REGIONID _MMIO(0x102084) |
| 5287 | #define SPI_STATIC_REGIONS _MMIO(0x102090) |
| 5288 | #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0) |
| 5289 | #define OROM_OFFSET _MMIO(0x1020c0) |
| 5290 | #define OROM_OFFSET_MASK REG_GENMASK(20, 16) |
| 5291 | |
José Roberto de Souza | 41c70d2b | 2021-04-08 13:49:16 -0700 | [diff] [blame] | 5292 | #define CLKREQ_POLICY _MMIO(0x101038) |
| 5293 | #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) |
| 5294 | |
José Roberto de Souza | 641dd82 | 2021-09-14 14:25:07 -0700 | [diff] [blame] | 5295 | #define CLKGATE_DIS_MISC _MMIO(0x46534) |
| 5296 | #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21) |
| 5297 | |
José Roberto de Souza | 47d4ae2 | 2022-09-07 11:15:43 +0300 | [diff] [blame] | 5298 | #define _MTL_CLKGATE_DIS_TRANS_A 0x604E8 |
| 5299 | #define _MTL_CLKGATE_DIS_TRANS_B 0x614E8 |
Jani Nikula | 407569f | 2024-04-23 19:45:00 +0300 | [diff] [blame] | 5300 | #define MTL_CLKGATE_DIS_TRANS(trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A) |
José Roberto de Souza | 47d4ae2 | 2022-09-07 11:15:43 +0300 | [diff] [blame] | 5301 | #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7) |
| 5302 | |
Radhakrishna Sripada | 825477e | 2022-09-01 23:03:39 -0700 | [diff] [blame] | 5303 | #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) |
| 5304 | #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8) |
| 5305 | #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4) |
| 5306 | #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0) |
| 5307 | |
Vinod Govindapillai | ff168b3 | 2023-03-23 13:44:25 +0200 | [diff] [blame] | 5308 | #define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710 |
| 5309 | #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8) |
Radhakrishna Sripada | 825477e | 2022-09-01 23:03:39 -0700 | [diff] [blame] | 5310 | #define MTL_TRCD_MASK REG_GENMASK(31, 24) |
| 5311 | #define MTL_TRP_MASK REG_GENMASK(23, 16) |
| 5312 | #define MTL_DCLK_MASK REG_GENMASK(15, 0) |
| 5313 | |
Vinod Govindapillai | ff168b3 | 2023-03-23 13:44:25 +0200 | [diff] [blame] | 5314 | #define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4) |
Radhakrishna Sripada | 825477e | 2022-09-01 23:03:39 -0700 | [diff] [blame] | 5315 | #define MTL_TRAS_MASK REG_GENMASK(16, 8) |
| 5316 | #define MTL_TRDPRE_MASK REG_GENMASK(7, 0) |
| 5317 | |
Matt Roper | c2c7075 | 2022-09-15 18:46:46 -0700 | [diff] [blame] | 5318 | #define MTL_MEDIA_GSI_BASE 0x380000 |
| 5319 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 5320 | #endif /* _I915_REG_H_ */ |